1/* 2 This is part of rtl818x pci OpenSource driver - v 0.1 3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> 4 Released under the terms of GPL (General Public License) 5 6 Parts of this driver are based on the GPL part of the official 7 Realtek driver. 8 9 Parts of this driver are based on the rtl8180 driver skeleton 10 from Patric Schenke & Andres Salomon. 11 12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. 13 14 Parts of BB/RF code are derived from David Young rtl8180 netbsd driver. 15 16 RSSI calc function from 'The Deuce' 17 18 Some ideas borrowed from the 8139too.c driver included in linux kernel. 19 20 We (I?) want to thanks the Authors of those projecs and also the 21 Ndiswrapper's project Authors. 22 23 A big big thanks goes also to Realtek corp. for their help in my attempt to 24 add RTL8185 and RTL8225 support, and to David Young also. 25 26 Power management interface routines. 27 Written by Mariusz Matuszek. 28*/ 29 30#undef RX_DONT_PASS_UL 31#undef DUMMY_RX 32 33#include <linux/slab.h> 34#include <linux/syscalls.h> 35#include <linux/eeprom_93cx6.h> 36 37#include "r8180_hw.h" 38#include "r8180.h" 39#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */ 40#include "r8180_93cx6.h" /* Card EEPROM */ 41#include "r8180_wx.h" 42#include "r8180_dm.h" 43 44#include "ieee80211/dot11d.h" 45 46static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = { 47 { 48 .vendor = PCI_VENDOR_ID_REALTEK, 49 .device = 0x8199, 50 .subvendor = PCI_ANY_ID, 51 .subdevice = PCI_ANY_ID, 52 .driver_data = 0, 53 }, 54 { 55 .vendor = 0, 56 .device = 0, 57 .subvendor = 0, 58 .subdevice = 0, 59 .driver_data = 0, 60 } 61}; 62 63 64static char ifname[IFNAMSIZ] = "wlan%d"; 65static int hwseqnum = 0; 66static int hwwep = 0; 67static int channels = 0x3fff; 68 69MODULE_LICENSE("GPL"); 70MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl); 71MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); 72MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards"); 73 74 75module_param_string(ifname, ifname, sizeof(ifname), S_IRUGO|S_IWUSR); 76module_param(hwseqnum, int, S_IRUGO|S_IWUSR); 77module_param(hwwep, int, S_IRUGO|S_IWUSR); 78module_param(channels, int, S_IRUGO|S_IWUSR); 79 80MODULE_PARM_DESC(devname, " Net interface name, wlan%d=default"); 81MODULE_PARM_DESC(hwseqnum, " Try to use hardware 802.11 header sequence numbers. Zero=default"); 82MODULE_PARM_DESC(hwwep, " Try to use hardware WEP support. Still broken and not available on all cards"); 83MODULE_PARM_DESC(channels, " Channel bitmask for specific locales. NYI"); 84 85 86static int __devinit rtl8180_pci_probe(struct pci_dev *pdev, 87 const struct pci_device_id *id); 88 89static void __devexit rtl8180_pci_remove(struct pci_dev *pdev); 90 91static void rtl8180_shutdown(struct pci_dev *pdev) 92{ 93 struct net_device *dev = pci_get_drvdata(pdev); 94 if (dev->netdev_ops->ndo_stop) 95 dev->netdev_ops->ndo_stop(dev); 96 pci_disable_device(pdev); 97} 98 99static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state) 100{ 101 struct net_device *dev = pci_get_drvdata(pdev); 102 103 if (!netif_running(dev)) 104 goto out_pci_suspend; 105 106 if (dev->netdev_ops->ndo_stop) 107 dev->netdev_ops->ndo_stop(dev); 108 109 netif_device_detach(dev); 110 111out_pci_suspend: 112 pci_save_state(pdev); 113 pci_disable_device(pdev); 114 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 115 return 0; 116} 117 118static int rtl8180_resume(struct pci_dev *pdev) 119{ 120 struct net_device *dev = pci_get_drvdata(pdev); 121 int err; 122 u32 val; 123 124 pci_set_power_state(pdev, PCI_D0); 125 126 err = pci_enable_device(pdev); 127 if (err) { 128 printk(KERN_ERR "%s: pci_enable_device failed on resume\n", 129 dev->name); 130 131 return err; 132 } 133 134 pci_restore_state(pdev); 135 136 /* 137 * Suspend/Resume resets the PCI configuration space, so we have to 138 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 139 * from interfering with C3 CPU state. pci_restore_state won't help 140 * here since it only restores the first 64 bytes pci config header. 141 */ 142 pci_read_config_dword(pdev, 0x40, &val); 143 if ((val & 0x0000ff00) != 0) 144 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 145 146 if (!netif_running(dev)) 147 goto out; 148 149 if (dev->netdev_ops->ndo_open) 150 dev->netdev_ops->ndo_open(dev); 151 152 netif_device_attach(dev); 153out: 154 return 0; 155} 156 157static struct pci_driver rtl8180_pci_driver = { 158 .name = RTL8180_MODULE_NAME, 159 .id_table = rtl8180_pci_id_tbl, 160 .probe = rtl8180_pci_probe, 161 .remove = __devexit_p(rtl8180_pci_remove), 162 .suspend = rtl8180_suspend, 163 .resume = rtl8180_resume, 164 .shutdown = rtl8180_shutdown, 165}; 166 167u8 read_nic_byte(struct net_device *dev, int x) 168{ 169 return 0xff&readb((u8 *)dev->mem_start + x); 170} 171 172u32 read_nic_dword(struct net_device *dev, int x) 173{ 174 return readl((u8 *)dev->mem_start + x); 175} 176 177u16 read_nic_word(struct net_device *dev, int x) 178{ 179 return readw((u8 *)dev->mem_start + x); 180} 181 182void write_nic_byte(struct net_device *dev, int x, u8 y) 183{ 184 writeb(y, (u8 *)dev->mem_start + x); 185 udelay(20); 186} 187 188void write_nic_dword(struct net_device *dev, int x, u32 y) 189{ 190 writel(y, (u8 *)dev->mem_start + x); 191 udelay(20); 192} 193 194void write_nic_word(struct net_device *dev, int x, u16 y) 195{ 196 writew(y, (u8 *)dev->mem_start + x); 197 udelay(20); 198} 199 200inline void force_pci_posting(struct net_device *dev) 201{ 202 read_nic_byte(dev, EPROM_CMD); 203 mb(); 204} 205 206irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs); 207void set_nic_rxring(struct net_device *dev); 208void set_nic_txring(struct net_device *dev); 209static struct net_device_stats *rtl8180_stats(struct net_device *dev); 210void rtl8180_commit(struct net_device *dev); 211void rtl8180_start_tx_beacon(struct net_device *dev); 212 213static struct proc_dir_entry *rtl8180_proc = NULL; 214 215static int proc_get_registers(char *page, char **start, 216 off_t offset, int count, 217 int *eof, void *data) 218{ 219 struct net_device *dev = data; 220 int len = 0; 221 int i, n; 222 int max = 0xff; 223 224 /* This dump the current register page */ 225 for (n = 0; n <= max;) { 226 len += snprintf(page + len, count - len, "\nD: %2x > ", n); 227 228 for (i = 0; i < 16 && n <= max; i++, n++) 229 len += snprintf(page + len, count - len, "%2x ", 230 read_nic_byte(dev, n)); 231 } 232 len += snprintf(page + len, count - len, "\n"); 233 234 *eof = 1; 235 return len; 236} 237 238int get_curr_tx_free_desc(struct net_device *dev, int priority); 239 240static int proc_get_stats_hw(char *page, char **start, 241 off_t offset, int count, 242 int *eof, void *data) 243{ 244 int len = 0; 245 246 *eof = 1; 247 return len; 248} 249 250static int proc_get_stats_rx(char *page, char **start, 251 off_t offset, int count, 252 int *eof, void *data) 253{ 254 struct net_device *dev = data; 255 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 256 257 int len = 0; 258 259 len += snprintf(page + len, count - len, 260 "RX OK: %lu\n" 261 "RX Retry: %lu\n" 262 "RX CRC Error(0-500): %lu\n" 263 "RX CRC Error(500-1000): %lu\n" 264 "RX CRC Error(>1000): %lu\n" 265 "RX ICV Error: %lu\n", 266 priv->stats.rxint, 267 priv->stats.rxerr, 268 priv->stats.rxcrcerrmin, 269 priv->stats.rxcrcerrmid, 270 priv->stats.rxcrcerrmax, 271 priv->stats.rxicverr 272 ); 273 274 *eof = 1; 275 return len; 276} 277 278static int proc_get_stats_tx(char *page, char **start, 279 off_t offset, int count, 280 int *eof, void *data) 281{ 282 struct net_device *dev = data; 283 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 284 285 int len = 0; 286 unsigned long totalOK; 287 288 totalOK = priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint; 289 len += snprintf(page + len, count - len, 290 "TX OK: %lu\n" 291 "TX Error: %lu\n" 292 "TX Retry: %lu\n" 293 "TX beacon OK: %lu\n" 294 "TX beacon error: %lu\n", 295 totalOK, 296 priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr, 297 priv->stats.txretry, 298 priv->stats.txbeacon, 299 priv->stats.txbeaconerr 300 ); 301 302 *eof = 1; 303 return len; 304} 305 306void rtl8180_proc_module_init(void) 307{ 308 DMESG("Initializing proc filesystem"); 309 rtl8180_proc = create_proc_entry(RTL8180_MODULE_NAME, S_IFDIR, init_net.proc_net); 310} 311 312void rtl8180_proc_module_remove(void) 313{ 314 remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net); 315} 316 317void rtl8180_proc_remove_one(struct net_device *dev) 318{ 319 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 320 if (priv->dir_dev) { 321 remove_proc_entry("stats-hw", priv->dir_dev); 322 remove_proc_entry("stats-tx", priv->dir_dev); 323 remove_proc_entry("stats-rx", priv->dir_dev); 324 remove_proc_entry("registers", priv->dir_dev); 325 remove_proc_entry(dev->name, rtl8180_proc); 326 priv->dir_dev = NULL; 327 } 328} 329 330void rtl8180_proc_init_one(struct net_device *dev) 331{ 332 struct proc_dir_entry *e; 333 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 334 335 priv->dir_dev = rtl8180_proc; 336 if (!priv->dir_dev) { 337 DMESGE("Unable to initialize /proc/net/r8180/%s\n", 338 dev->name); 339 return; 340 } 341 342 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO, 343 priv->dir_dev, proc_get_stats_hw, dev); 344 if (!e) { 345 DMESGE("Unable to initialize " 346 "/proc/net/r8180/%s/stats-hw\n", 347 dev->name); 348 } 349 350 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO, 351 priv->dir_dev, proc_get_stats_rx, dev); 352 if (!e) { 353 DMESGE("Unable to initialize " 354 "/proc/net/r8180/%s/stats-rx\n", 355 dev->name); 356 } 357 358 359 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO, 360 priv->dir_dev, proc_get_stats_tx, dev); 361 if (!e) { 362 DMESGE("Unable to initialize " 363 "/proc/net/r8180/%s/stats-tx\n", 364 dev->name); 365 } 366 367 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO, 368 priv->dir_dev, proc_get_registers, dev); 369 if (!e) { 370 DMESGE("Unable to initialize " 371 "/proc/net/r8180/%s/registers\n", 372 dev->name); 373 } 374} 375 376 377short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma, 378 struct buffer **bufferhead) 379{ 380 struct buffer *tmp; 381 382 if (!*buffer) { 383 384 *buffer = kmalloc(sizeof(struct buffer), GFP_KERNEL); 385 386 if (*buffer == NULL) { 387 DMESGE("Failed to kmalloc head of TX/RX struct"); 388 return -1; 389 } 390 (*buffer)->next = *buffer; 391 (*buffer)->buf = buf; 392 (*buffer)->dma = dma; 393 if (bufferhead != NULL) 394 (*bufferhead) = (*buffer); 395 return 0; 396 } 397 tmp = *buffer; 398 399 while (tmp->next != (*buffer)) 400 tmp = tmp->next; 401 tmp->next = kmalloc(sizeof(struct buffer), GFP_KERNEL); 402 if (tmp->next == NULL) { 403 DMESGE("Failed to kmalloc TX/RX struct"); 404 return -1; 405 } 406 tmp->next->buf = buf; 407 tmp->next->dma = dma; 408 tmp->next->next = *buffer; 409 410 return 0; 411} 412 413void buffer_free(struct net_device *dev, struct buffer **buffer, int len, short consistent) 414{ 415 416 struct buffer *tmp, *next; 417 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 418 struct pci_dev *pdev = priv->pdev; 419 420 if (!*buffer) 421 return; 422 423 tmp = *buffer; 424 425 do { 426 next = tmp->next; 427 if (consistent) { 428 pci_free_consistent(pdev, len, 429 tmp->buf, tmp->dma); 430 } else { 431 pci_unmap_single(pdev, tmp->dma, 432 len, PCI_DMA_FROMDEVICE); 433 kfree(tmp->buf); 434 } 435 kfree(tmp); 436 tmp = next; 437 } 438 while (next != *buffer); 439 440 *buffer = NULL; 441} 442 443void print_buffer(u32 *buffer, int len) 444{ 445 int i; 446 u8 *buf = (u8 *)buffer; 447 448 printk("ASCII BUFFER DUMP (len: %x):\n", len); 449 450 for (i = 0; i < len; i++) 451 printk("%c", buf[i]); 452 453 printk("\nBINARY BUFFER DUMP (len: %x):\n", len); 454 455 for (i = 0; i < len; i++) 456 printk("%02x", buf[i]); 457 458 printk("\n"); 459} 460 461int get_curr_tx_free_desc(struct net_device *dev, int priority) 462{ 463 struct r8180_priv *priv = ieee80211_priv(dev); 464 u32 *tail; 465 u32 *head; 466 int ret; 467 468 switch (priority) { 469 case MANAGE_PRIORITY: 470 head = priv->txmapringhead; 471 tail = priv->txmapringtail; 472 break; 473 case BK_PRIORITY: 474 head = priv->txbkpringhead; 475 tail = priv->txbkpringtail; 476 break; 477 case BE_PRIORITY: 478 head = priv->txbepringhead; 479 tail = priv->txbepringtail; 480 break; 481 case VI_PRIORITY: 482 head = priv->txvipringhead; 483 tail = priv->txvipringtail; 484 break; 485 case VO_PRIORITY: 486 head = priv->txvopringhead; 487 tail = priv->txvopringtail; 488 break; 489 case HI_PRIORITY: 490 head = priv->txhpringhead; 491 tail = priv->txhpringtail; 492 break; 493 default: 494 return -1; 495 } 496 497 if (head <= tail) 498 ret = priv->txringcount - (tail - head)/8; 499 else 500 ret = (head - tail)/8; 501 502 if (ret > priv->txringcount) 503 DMESG("BUG"); 504 505 return ret; 506} 507 508short check_nic_enought_desc(struct net_device *dev, int priority) 509{ 510 struct r8180_priv *priv = ieee80211_priv(dev); 511 struct ieee80211_device *ieee = netdev_priv(dev); 512 int requiredbyte, required; 513 514 requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data); 515 516 if (ieee->current_network.QoS_Enable) 517 requiredbyte += 2; 518 519 required = requiredbyte / (priv->txbuffsize-4); 520 521 if (requiredbyte % priv->txbuffsize) 522 required++; 523 524 /* for now we keep two free descriptor as a safety boundary 525 * between the tail and the head 526 */ 527 528 return (required+2 < get_curr_tx_free_desc(dev, priority)); 529} 530 531void fix_tx_fifo(struct net_device *dev) 532{ 533 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 534 u32 *tmp; 535 int i; 536 537 for (tmp = priv->txmapring, i = 0; 538 i < priv->txringcount; 539 tmp += 8, i++) { 540 *tmp = *tmp & ~(1<<31); 541 } 542 543 for (tmp = priv->txbkpring, i = 0; 544 i < priv->txringcount; 545 tmp += 8, i++) { 546 *tmp = *tmp & ~(1<<31); 547 } 548 549 for (tmp = priv->txbepring, i = 0; 550 i < priv->txringcount; 551 tmp += 8, i++) { 552 *tmp = *tmp & ~(1<<31); 553 } 554 for (tmp = priv->txvipring, i = 0; 555 i < priv->txringcount; 556 tmp += 8, i++) { 557 *tmp = *tmp & ~(1<<31); 558 } 559 560 for (tmp = priv->txvopring, i = 0; 561 i < priv->txringcount; 562 tmp += 8, i++) { 563 *tmp = *tmp & ~(1<<31); 564 } 565 566 for (tmp = priv->txhpring, i = 0; 567 i < priv->txringcount; 568 tmp += 8, i++) { 569 *tmp = *tmp & ~(1<<31); 570 } 571 572 for (tmp = priv->txbeaconring, i = 0; 573 i < priv->txbeaconcount; 574 tmp += 8, i++) { 575 *tmp = *tmp & ~(1<<31); 576 } 577 578 priv->txmapringtail = priv->txmapring; 579 priv->txmapringhead = priv->txmapring; 580 priv->txmapbufstail = priv->txmapbufs; 581 582 priv->txbkpringtail = priv->txbkpring; 583 priv->txbkpringhead = priv->txbkpring; 584 priv->txbkpbufstail = priv->txbkpbufs; 585 586 priv->txbepringtail = priv->txbepring; 587 priv->txbepringhead = priv->txbepring; 588 priv->txbepbufstail = priv->txbepbufs; 589 590 priv->txvipringtail = priv->txvipring; 591 priv->txvipringhead = priv->txvipring; 592 priv->txvipbufstail = priv->txvipbufs; 593 594 priv->txvopringtail = priv->txvopring; 595 priv->txvopringhead = priv->txvopring; 596 priv->txvopbufstail = priv->txvopbufs; 597 598 priv->txhpringtail = priv->txhpring; 599 priv->txhpringhead = priv->txhpring; 600 priv->txhpbufstail = priv->txhpbufs; 601 602 priv->txbeaconringtail = priv->txbeaconring; 603 priv->txbeaconbufstail = priv->txbeaconbufs; 604 set_nic_txring(dev); 605 606 ieee80211_reset_queue(priv->ieee80211); 607 priv->ack_tx_to_ieee = 0; 608} 609 610void fix_rx_fifo(struct net_device *dev) 611{ 612 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 613 u32 *tmp; 614 struct buffer *rxbuf; 615 u8 rx_desc_size; 616 617 rx_desc_size = 8; /* 4*8 = 32 bytes */ 618 619 for (tmp = priv->rxring, rxbuf = priv->rxbufferhead; 620 (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size); 621 tmp += rx_desc_size, rxbuf = rxbuf->next) { 622 *(tmp+2) = rxbuf->dma; 623 *tmp = *tmp & ~0xfff; 624 *tmp = *tmp | priv->rxbuffersize; 625 *tmp |= (1<<31); 626 } 627 628 priv->rxringtail = priv->rxring; 629 priv->rxbuffer = priv->rxbufferhead; 630 priv->rx_skb_complete = 1; 631 set_nic_rxring(dev); 632} 633 634unsigned char QUALITY_MAP[] = { 635 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61, 636 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c, 637 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f, 638 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29, 639 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 640 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20, 641 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e, 642 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19, 643 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f, 644 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00 645}; 646 647unsigned char STRENGTH_MAP[] = { 648 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e, 649 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50, 650 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f, 651 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b, 652 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17, 653 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13, 654 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f, 655 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b, 656 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07, 657 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00 658}; 659 660void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual) 661{ 662 u32 temp; 663 u32 temp2; 664 u32 q; 665 u32 orig_qual; 666 u8 _rssi; 667 668 q = *qual; 669 orig_qual = *qual; 670 _rssi = 0; /* avoid gcc complains.. */ 671 672 if (q <= 0x4e) { 673 temp = QUALITY_MAP[q]; 674 } else { 675 if (q & 0x80) 676 temp = 0x32; 677 else 678 temp = 1; 679 } 680 681 *qual = temp; 682 temp2 = *rssi; 683 684 if (_rssi < 0x64) { 685 if (_rssi == 0) 686 *rssi = 1; 687 } else { 688 *rssi = 0x64; 689 } 690 691 return; 692} 693 694void rtl8180_irq_enable(struct net_device *dev) 695{ 696 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 697 698 priv->irq_enabled = 1; 699 write_nic_word(dev, INTA_MASK, priv->irq_mask); 700} 701 702void rtl8180_irq_disable(struct net_device *dev) 703{ 704 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 705 706 write_nic_dword(dev, IMR, 0); 707 force_pci_posting(dev); 708 priv->irq_enabled = 0; 709} 710 711void rtl8180_set_mode(struct net_device *dev, int mode) 712{ 713 u8 ecmd; 714 715 ecmd = read_nic_byte(dev, EPROM_CMD); 716 ecmd = ecmd & ~EPROM_CMD_OPERATING_MODE_MASK; 717 ecmd = ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT); 718 ecmd = ecmd & ~(1<<EPROM_CS_SHIFT); 719 ecmd = ecmd & ~(1<<EPROM_CK_SHIFT); 720 write_nic_byte(dev, EPROM_CMD, ecmd); 721} 722 723void rtl8180_adapter_start(struct net_device *dev); 724void rtl8180_beacon_tx_enable(struct net_device *dev); 725 726void rtl8180_update_msr(struct net_device *dev) 727{ 728 struct r8180_priv *priv = ieee80211_priv(dev); 729 u8 msr; 730 u32 rxconf; 731 732 msr = read_nic_byte(dev, MSR); 733 msr &= ~MSR_LINK_MASK; 734 735 rxconf = read_nic_dword(dev, RX_CONF); 736 737 if (priv->ieee80211->state == IEEE80211_LINKED) { 738 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) 739 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT); 740 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER) 741 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT); 742 else if (priv->ieee80211->iw_mode == IW_MODE_INFRA) 743 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT); 744 else 745 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); 746 rxconf |= (1<<RX_CHECK_BSSID_SHIFT); 747 748 } else { 749 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); 750 rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT); 751 } 752 753 write_nic_byte(dev, MSR, msr); 754 write_nic_dword(dev, RX_CONF, rxconf); 755} 756 757void rtl8180_set_chan(struct net_device *dev, short ch) 758{ 759 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 760 761 if ((ch > 14) || (ch < 1)) { 762 printk("In %s: Invalid chnanel %d\n", __func__, ch); 763 return; 764 } 765 766 priv->chan = ch; 767 priv->rf_set_chan(dev, priv->chan); 768} 769 770void rtl8180_rx_enable(struct net_device *dev) 771{ 772 u8 cmd; 773 u32 rxconf; 774 /* for now we accept data, management & ctl frame*/ 775 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 776 777 rxconf = read_nic_dword(dev, RX_CONF); 778 rxconf = rxconf & ~MAC_FILTER_MASK; 779 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT); 780 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT); 781 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT); 782 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT); 783 if (dev->flags & IFF_PROMISC) 784 DMESG("NIC in promisc mode"); 785 786 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || \ 787 dev->flags & IFF_PROMISC) { 788 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT); 789 } else { 790 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT); 791 } 792 793 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR) { 794 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT); 795 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT); 796 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT); 797 } 798 799 if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR) 800 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT); 801 802 rxconf = rxconf & ~RX_FIFO_THRESHOLD_MASK; 803 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE << RX_FIFO_THRESHOLD_SHIFT); 804 805 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT); 806 rxconf = rxconf & ~MAX_RX_DMA_MASK; 807 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT); 808 809 rxconf = rxconf | RCR_ONLYERLPKT; 810 811 rxconf = rxconf & ~RCR_CS_MASK; 812 813 write_nic_dword(dev, RX_CONF, rxconf); 814 815 fix_rx_fifo(dev); 816 817 cmd = read_nic_byte(dev, CMD); 818 write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT)); 819} 820 821void set_nic_txring(struct net_device *dev) 822{ 823 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 824 825 write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma); 826 write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma); 827 write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma); 828 write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma); 829 write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma); 830 write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma); 831 write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma); 832} 833 834void rtl8180_conttx_enable(struct net_device *dev) 835{ 836 u32 txconf; 837 838 txconf = read_nic_dword(dev, TX_CONF); 839 txconf = txconf & ~TX_LOOPBACK_MASK; 840 txconf = txconf | (TX_LOOPBACK_CONTINUE<<TX_LOOPBACK_SHIFT); 841 write_nic_dword(dev, TX_CONF, txconf); 842} 843 844void rtl8180_conttx_disable(struct net_device *dev) 845{ 846 u32 txconf; 847 848 txconf = read_nic_dword(dev, TX_CONF); 849 txconf = txconf & ~TX_LOOPBACK_MASK; 850 txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT); 851 write_nic_dword(dev, TX_CONF, txconf); 852} 853 854void rtl8180_tx_enable(struct net_device *dev) 855{ 856 u8 cmd; 857 u8 tx_agc_ctl; 858 u8 byte; 859 u32 txconf; 860 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 861 862 txconf = read_nic_dword(dev, TX_CONF); 863 864 byte = read_nic_byte(dev, CW_CONF); 865 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT); 866 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT); 867 write_nic_byte(dev, CW_CONF, byte); 868 869 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL); 870 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT); 871 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT); 872 tx_agc_ctl |= (1<<TX_AGC_CTL_FEEDBACK_ANT); 873 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl); 874 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */ 875 876 txconf = txconf & ~(1<<TCR_PROBE_NOTIMESTAMP_SHIFT); 877 878 txconf = txconf & ~TX_LOOPBACK_MASK; 879 txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT); 880 txconf = txconf & ~TCR_DPRETRY_MASK; 881 txconf = txconf & ~TCR_RTSRETRY_MASK; 882 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT); 883 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT); 884 txconf = txconf & ~(1<<TX_NOCRC_SHIFT); 885 886 if (priv->hw_plcp_len) 887 txconf = txconf & ~TCR_PLCP_LEN; 888 else 889 txconf = txconf | TCR_PLCP_LEN; 890 891 txconf = txconf & ~TCR_MXDMA_MASK; 892 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT); 893 txconf = txconf | TCR_CWMIN; 894 txconf = txconf | TCR_DISCW; 895 896 txconf = txconf | (1 << TX_NOICV_SHIFT); 897 898 write_nic_dword(dev, TX_CONF, txconf); 899 900 fix_tx_fifo(dev); 901 902 cmd = read_nic_byte(dev, CMD); 903 write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT)); 904 905 write_nic_dword(dev, TX_CONF, txconf); 906} 907 908void rtl8180_beacon_tx_enable(struct net_device *dev) 909{ 910 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 911 912 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 913 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ); 914 write_nic_byte(dev, TPPollStop, priv->dma_poll_mask); 915 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 916} 917 918void rtl8180_beacon_tx_disable(struct net_device *dev) 919{ 920 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 921 922 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 923 priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ; 924 write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask); 925 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 926 927} 928 929void rtl8180_rtx_disable(struct net_device *dev) 930{ 931 u8 cmd; 932 struct r8180_priv *priv = ieee80211_priv(dev); 933 934 cmd = read_nic_byte(dev, CMD); 935 write_nic_byte(dev, CMD, cmd & ~\ 936 ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT))); 937 force_pci_posting(dev); 938 mdelay(10); 939 940 if (!priv->rx_skb_complete) 941 dev_kfree_skb_any(priv->rx_skb); 942} 943 944short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count, 945 int addr) 946{ 947 int i; 948 u32 *desc; 949 u32 *tmp; 950 dma_addr_t dma_desc, dma_tmp; 951 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 952 struct pci_dev *pdev = priv->pdev; 953 void *buf; 954 955 if ((bufsize & 0xfff) != bufsize) { 956 DMESGE("TX buffer allocation too large"); 957 return 0; 958 } 959 desc = (u32 *)pci_alloc_consistent(pdev, 960 sizeof(u32)*8*count+256, &dma_desc); 961 if (desc == NULL) 962 return -1; 963 964 if (dma_desc & 0xff) 965 /* 966 * descriptor's buffer must be 256 byte aligned 967 * we shouldn't be here, since we set DMA mask ! 968 */ 969 WARN(1, "DMA buffer is not aligned\n"); 970 971 tmp = desc; 972 973 for (i = 0; i < count; i++) { 974 buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp); 975 if (buf == NULL) 976 return -ENOMEM; 977 978 switch (addr) { 979 case TX_MANAGEPRIORITY_RING_ADDR: 980 if (-1 == buffer_add(&(priv->txmapbufs), buf, dma_tmp, NULL)) { 981 DMESGE("Unable to allocate mem for buffer NP"); 982 return -ENOMEM; 983 } 984 break; 985 case TX_BKPRIORITY_RING_ADDR: 986 if (-1 == buffer_add(&(priv->txbkpbufs), buf, dma_tmp, NULL)) { 987 DMESGE("Unable to allocate mem for buffer LP"); 988 return -ENOMEM; 989 } 990 break; 991 case TX_BEPRIORITY_RING_ADDR: 992 if (-1 == buffer_add(&(priv->txbepbufs), buf, dma_tmp, NULL)) { 993 DMESGE("Unable to allocate mem for buffer NP"); 994 return -ENOMEM; 995 } 996 break; 997 case TX_VIPRIORITY_RING_ADDR: 998 if (-1 == buffer_add(&(priv->txvipbufs), buf, dma_tmp, NULL)) { 999 DMESGE("Unable to allocate mem for buffer LP"); 1000 return -ENOMEM; 1001 } 1002 break; 1003 case TX_VOPRIORITY_RING_ADDR: 1004 if (-1 == buffer_add(&(priv->txvopbufs), buf, dma_tmp, NULL)) { 1005 DMESGE("Unable to allocate mem for buffer NP"); 1006 return -ENOMEM; 1007 } 1008 break; 1009 case TX_HIGHPRIORITY_RING_ADDR: 1010 if (-1 == buffer_add(&(priv->txhpbufs), buf, dma_tmp, NULL)) { 1011 DMESGE("Unable to allocate mem for buffer HP"); 1012 return -ENOMEM; 1013 } 1014 break; 1015 case TX_BEACON_RING_ADDR: 1016 if (-1 == buffer_add(&(priv->txbeaconbufs), buf, dma_tmp, NULL)) { 1017 DMESGE("Unable to allocate mem for buffer BP"); 1018 return -ENOMEM; 1019 } 1020 break; 1021 } 1022 *tmp = *tmp & ~(1<<31); /* descriptor empty, owned by the drv */ 1023 *(tmp+2) = (u32)dma_tmp; 1024 *(tmp+3) = bufsize; 1025 1026 if (i+1 < count) 1027 *(tmp+4) = (u32)dma_desc+((i+1)*8*4); 1028 else 1029 *(tmp+4) = (u32)dma_desc; 1030 1031 tmp = tmp+8; 1032 } 1033 1034 switch (addr) { 1035 case TX_MANAGEPRIORITY_RING_ADDR: 1036 priv->txmapringdma = dma_desc; 1037 priv->txmapring = desc; 1038 break; 1039 case TX_BKPRIORITY_RING_ADDR: 1040 priv->txbkpringdma = dma_desc; 1041 priv->txbkpring = desc; 1042 break; 1043 case TX_BEPRIORITY_RING_ADDR: 1044 priv->txbepringdma = dma_desc; 1045 priv->txbepring = desc; 1046 break; 1047 case TX_VIPRIORITY_RING_ADDR: 1048 priv->txvipringdma = dma_desc; 1049 priv->txvipring = desc; 1050 break; 1051 case TX_VOPRIORITY_RING_ADDR: 1052 priv->txvopringdma = dma_desc; 1053 priv->txvopring = desc; 1054 break; 1055 case TX_HIGHPRIORITY_RING_ADDR: 1056 priv->txhpringdma = dma_desc; 1057 priv->txhpring = desc; 1058 break; 1059 case TX_BEACON_RING_ADDR: 1060 priv->txbeaconringdma = dma_desc; 1061 priv->txbeaconring = desc; 1062 break; 1063 1064 } 1065 1066 return 0; 1067} 1068 1069void free_tx_desc_rings(struct net_device *dev) 1070{ 1071 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1072 struct pci_dev *pdev = priv->pdev; 1073 int count = priv->txringcount; 1074 1075 pci_free_consistent(pdev, sizeof(u32)*8*count+256, 1076 priv->txmapring, priv->txmapringdma); 1077 buffer_free(dev, &(priv->txmapbufs), priv->txbuffsize, 1); 1078 1079 pci_free_consistent(pdev, sizeof(u32)*8*count+256, 1080 priv->txbkpring, priv->txbkpringdma); 1081 buffer_free(dev, &(priv->txbkpbufs), priv->txbuffsize, 1); 1082 1083 pci_free_consistent(pdev, sizeof(u32)*8*count+256, 1084 priv->txbepring, priv->txbepringdma); 1085 buffer_free(dev, &(priv->txbepbufs), priv->txbuffsize, 1); 1086 1087 pci_free_consistent(pdev, sizeof(u32)*8*count+256, 1088 priv->txvipring, priv->txvipringdma); 1089 buffer_free(dev, &(priv->txvipbufs), priv->txbuffsize, 1); 1090 1091 pci_free_consistent(pdev, sizeof(u32)*8*count+256, 1092 priv->txvopring, priv->txvopringdma); 1093 buffer_free(dev, &(priv->txvopbufs), priv->txbuffsize, 1); 1094 1095 pci_free_consistent(pdev, sizeof(u32)*8*count+256, 1096 priv->txhpring, priv->txhpringdma); 1097 buffer_free(dev, &(priv->txhpbufs), priv->txbuffsize, 1); 1098 1099 count = priv->txbeaconcount; 1100 pci_free_consistent(pdev, sizeof(u32)*8*count+256, 1101 priv->txbeaconring, priv->txbeaconringdma); 1102 buffer_free(dev, &(priv->txbeaconbufs), priv->txbuffsize, 1); 1103} 1104 1105void free_rx_desc_ring(struct net_device *dev) 1106{ 1107 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1108 struct pci_dev *pdev = priv->pdev; 1109 int count = priv->rxringcount; 1110 1111 pci_free_consistent(pdev, sizeof(u32)*8*count+256, 1112 priv->rxring, priv->rxringdma); 1113 1114 buffer_free(dev, &(priv->rxbuffer), priv->rxbuffersize, 0); 1115} 1116 1117short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count) 1118{ 1119 int i; 1120 u32 *desc; 1121 u32 *tmp; 1122 dma_addr_t dma_desc, dma_tmp; 1123 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1124 struct pci_dev *pdev = priv->pdev; 1125 void *buf; 1126 u8 rx_desc_size; 1127 1128 rx_desc_size = 8; /* 4*8 = 32 bytes */ 1129 1130 if ((bufsize & 0xfff) != bufsize) { 1131 DMESGE("RX buffer allocation too large"); 1132 return -1; 1133 } 1134 1135 desc = (u32 *)pci_alloc_consistent(pdev, sizeof(u32)*rx_desc_size*count+256, 1136 &dma_desc); 1137 1138 if (dma_desc & 0xff) 1139 /* 1140 * descriptor's buffer must be 256 byte aligned 1141 * should never happen since we specify the DMA mask 1142 */ 1143 WARN(1, "DMA buffer is not aligned\n"); 1144 1145 priv->rxring = desc; 1146 priv->rxringdma = dma_desc; 1147 tmp = desc; 1148 1149 for (i = 0; i < count; i++) { 1150 buf = kmalloc(bufsize * sizeof(u8), GFP_ATOMIC); 1151 if (buf == NULL) { 1152 DMESGE("Failed to kmalloc RX buffer"); 1153 return -1; 1154 } 1155 1156 dma_tmp = pci_map_single(pdev, buf, bufsize * sizeof(u8), 1157 PCI_DMA_FROMDEVICE); 1158 1159 if (-1 == buffer_add(&(priv->rxbuffer), buf, dma_tmp, 1160 &(priv->rxbufferhead))) { 1161 DMESGE("Unable to allocate mem RX buf"); 1162 return -1; 1163 } 1164 *tmp = 0; /* zero pads the header of the descriptor */ 1165 *tmp = *tmp | (bufsize&0xfff); 1166 *(tmp+2) = (u32)dma_tmp; 1167 *tmp = *tmp | (1<<31); /* descriptor void, owned by the NIC */ 1168 1169 tmp = tmp+rx_desc_size; 1170 } 1171 1172 *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); /* this is the last descriptor */ 1173 1174 return 0; 1175} 1176 1177 1178void set_nic_rxring(struct net_device *dev) 1179{ 1180 u8 pgreg; 1181 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1182 1183 pgreg = read_nic_byte(dev, PGSELECT); 1184 write_nic_byte(dev, PGSELECT, pgreg & ~(1<<PGSELECT_PG_SHIFT)); 1185 1186 write_nic_dword(dev, RXRING_ADDR, priv->rxringdma); 1187} 1188 1189void rtl8180_reset(struct net_device *dev) 1190{ 1191 u8 cr; 1192 1193 rtl8180_irq_disable(dev); 1194 1195 cr = read_nic_byte(dev, CMD); 1196 cr = cr & 2; 1197 cr = cr | (1<<CMD_RST_SHIFT); 1198 write_nic_byte(dev, CMD, cr); 1199 1200 force_pci_posting(dev); 1201 1202 mdelay(200); 1203 1204 if (read_nic_byte(dev, CMD) & (1<<CMD_RST_SHIFT)) 1205 DMESGW("Card reset timeout!"); 1206 else 1207 DMESG("Card successfully reset"); 1208 1209 rtl8180_set_mode(dev, EPROM_CMD_LOAD); 1210 force_pci_posting(dev); 1211 mdelay(200); 1212} 1213 1214inline u16 ieeerate2rtlrate(int rate) 1215{ 1216 switch (rate) { 1217 case 10: 1218 return 0; 1219 case 20: 1220 return 1; 1221 case 55: 1222 return 2; 1223 case 110: 1224 return 3; 1225 case 60: 1226 return 4; 1227 case 90: 1228 return 5; 1229 case 120: 1230 return 6; 1231 case 180: 1232 return 7; 1233 case 240: 1234 return 8; 1235 case 360: 1236 return 9; 1237 case 480: 1238 return 10; 1239 case 540: 1240 return 11; 1241 default: 1242 return 3; 1243 } 1244} 1245 1246static u16 rtl_rate[] = {10, 20, 55, 110, 60, 90, 120, 180, 240, 360, 480, 540, 720}; 1247 1248inline u16 rtl8180_rate2rate(short rate) 1249{ 1250 if (rate > 12) 1251 return 10; 1252 return rtl_rate[rate]; 1253} 1254 1255inline u8 rtl8180_IsWirelessBMode(u16 rate) 1256{ 1257 if (((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220)) 1258 return 1; 1259 else 1260 return 0; 1261} 1262 1263u16 N_DBPSOfRate(u16 DataRate); 1264 1265u16 ComputeTxTime(u16 FrameLength, u16 DataRate, u8 bManagementFrame, 1266 u8 bShortPreamble) 1267{ 1268 u16 FrameTime; 1269 u16 N_DBPS; 1270 u16 Ceiling; 1271 1272 if (rtl8180_IsWirelessBMode(DataRate)) { 1273 if (bManagementFrame || !bShortPreamble || DataRate == 10) 1274 /* long preamble */ 1275 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10))); 1276 else 1277 /* short preamble */ 1278 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10))); 1279 1280 if ((FrameLength*8 % (DataRate/10)) != 0) /* get the ceilling */ 1281 FrameTime++; 1282 } else { /* 802.11g DSSS-OFDM PLCP length field calculation. */ 1283 N_DBPS = N_DBPSOfRate(DataRate); 1284 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS 1285 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0); 1286 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6); 1287 } 1288 return FrameTime; 1289} 1290 1291u16 N_DBPSOfRate(u16 DataRate) 1292{ 1293 u16 N_DBPS = 24; 1294 1295 switch (DataRate) { 1296 case 60: 1297 N_DBPS = 24; 1298 break; 1299 case 90: 1300 N_DBPS = 36; 1301 break; 1302 case 120: 1303 N_DBPS = 48; 1304 break; 1305 case 180: 1306 N_DBPS = 72; 1307 break; 1308 case 240: 1309 N_DBPS = 96; 1310 break; 1311 case 360: 1312 N_DBPS = 144; 1313 break; 1314 case 480: 1315 N_DBPS = 192; 1316 break; 1317 case 540: 1318 N_DBPS = 216; 1319 break; 1320 default: 1321 break; 1322 } 1323 1324 return N_DBPS; 1325} 1326 1327/* 1328 * For Netgear case, they want good-looking singal strength. 1329 */ 1330long NetgearSignalStrengthTranslate(long LastSS, long CurrSS) 1331{ 1332 long RetSS; 1333 1334 /* Step 1. Scale mapping. */ 1335 if (CurrSS >= 71 && CurrSS <= 100) 1336 RetSS = 90 + ((CurrSS - 70) / 3); 1337 else if (CurrSS >= 41 && CurrSS <= 70) 1338 RetSS = 78 + ((CurrSS - 40) / 3); 1339 else if (CurrSS >= 31 && CurrSS <= 40) 1340 RetSS = 66 + (CurrSS - 30); 1341 else if (CurrSS >= 21 && CurrSS <= 30) 1342 RetSS = 54 + (CurrSS - 20); 1343 else if (CurrSS >= 5 && CurrSS <= 20) 1344 RetSS = 42 + (((CurrSS - 5) * 2) / 3); 1345 else if (CurrSS == 4) 1346 RetSS = 36; 1347 else if (CurrSS == 3) 1348 RetSS = 27; 1349 else if (CurrSS == 2) 1350 RetSS = 18; 1351 else if (CurrSS == 1) 1352 RetSS = 9; 1353 else 1354 RetSS = CurrSS; 1355 1356 /* Step 2. Smoothing. */ 1357 if (LastSS > 0) 1358 RetSS = ((LastSS * 5) + (RetSS) + 5) / 6; 1359 1360 return RetSS; 1361} 1362 1363/* 1364 * Translate 0-100 signal strength index into dBm. 1365 */ 1366long TranslateToDbm8185(u8 SignalStrengthIndex) 1367{ 1368 long SignalPower; 1369 1370 /* Translate to dBm (x=0.5y-95). */ 1371 SignalPower = (long)((SignalStrengthIndex + 1) >> 1); 1372 SignalPower -= 95; 1373 1374 return SignalPower; 1375} 1376 1377/* 1378 * Perform signal smoothing for dynamic mechanism. 1379 * This is different with PerformSignalSmoothing8185 in smoothing fomula. 1380 * No dramatic adjustion is apply because dynamic mechanism need some degree 1381 * of correctness. Ported from 8187B. 1382 */ 1383void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv, 1384 bool bCckRate) 1385{ 1386 /* Determin the current packet is CCK rate. */ 1387 priv->bCurCCKPkt = bCckRate; 1388 1389 if (priv->UndecoratedSmoothedSS >= 0) 1390 priv->UndecoratedSmoothedSS = ((priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10)) / 6; 1391 else 1392 priv->UndecoratedSmoothedSS = priv->SignalStrength * 10; 1393 1394 priv->UndercorateSmoothedRxPower = ((priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower * 11)) / 60; 1395 1396 if (bCckRate) 1397 priv->CurCCKRSSI = priv->RSSI; 1398 else 1399 priv->CurCCKRSSI = 0; 1400} 1401 1402 1403/* 1404 * This is rough RX isr handling routine 1405 */ 1406void rtl8180_rx(struct net_device *dev) 1407{ 1408 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1409 struct sk_buff *tmp_skb; 1410 short first, last; 1411 u32 len; 1412 int lastlen; 1413 unsigned char quality, signal; 1414 u8 rate; 1415 u32 *tmp, *tmp2; 1416 u8 rx_desc_size; 1417 u8 padding; 1418 char rxpower = 0; 1419 u32 RXAGC = 0; 1420 long RxAGC_dBm = 0; 1421 u8 LNA = 0, BB = 0; 1422 u8 LNA_gain[4] = {02, 17, 29, 39}; 1423 u8 Antenna = 0; 1424 struct ieee80211_hdr_4addr *hdr; 1425 u16 fc, type; 1426 u8 bHwError = 0, bCRC = 0, bICV = 0; 1427 bool bCckRate = false; 1428 u8 RSSI = 0; 1429 long SignalStrengthIndex = 0; 1430 struct ieee80211_rx_stats stats = { 1431 .signal = 0, 1432 .noise = -98, 1433 .rate = 0, 1434 .freq = IEEE80211_24GHZ_BAND, 1435 }; 1436 1437 stats.nic_type = NIC_8185B; 1438 rx_desc_size = 8; 1439 1440 if ((*(priv->rxringtail)) & (1<<31)) { 1441 /* we have got an RX int, but the descriptor 1442 * we are pointing is empty */ 1443 1444 priv->stats.rxnodata++; 1445 priv->ieee80211->stats.rx_errors++; 1446 1447 tmp2 = NULL; 1448 tmp = priv->rxringtail; 1449 do { 1450 if (tmp == priv->rxring) 1451 tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size; 1452 else 1453 tmp -= rx_desc_size; 1454 1455 if (!(*tmp & (1<<31))) 1456 tmp2 = tmp; 1457 } while (tmp != priv->rxring); 1458 1459 if (tmp2) 1460 priv->rxringtail = tmp2; 1461 } 1462 1463 /* while there are filled descriptors */ 1464 while (!(*(priv->rxringtail) & (1<<31))) { 1465 if (*(priv->rxringtail) & (1<<26)) 1466 DMESGW("RX buffer overflow"); 1467 if (*(priv->rxringtail) & (1<<12)) 1468 priv->stats.rxicverr++; 1469 1470 if (*(priv->rxringtail) & (1<<27)) { 1471 priv->stats.rxdmafail++; 1472 /* DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail); */ 1473 goto drop; 1474 } 1475 1476 pci_dma_sync_single_for_cpu(priv->pdev, 1477 priv->rxbuffer->dma, 1478 priv->rxbuffersize * \ 1479 sizeof(u8), 1480 PCI_DMA_FROMDEVICE); 1481 1482 first = *(priv->rxringtail) & (1<<29) ? 1 : 0; 1483 if (first) 1484 priv->rx_prevlen = 0; 1485 1486 last = *(priv->rxringtail) & (1<<28) ? 1 : 0; 1487 if (last) { 1488 lastlen = ((*priv->rxringtail) & 0xfff); 1489 1490 if (lastlen < priv->rx_prevlen) 1491 len = 0; 1492 else 1493 len = lastlen-priv->rx_prevlen; 1494 1495 if (*(priv->rxringtail) & (1<<13)) { 1496 if ((*(priv->rxringtail) & 0xfff) < 500) 1497 priv->stats.rxcrcerrmin++; 1498 else if ((*(priv->rxringtail) & 0x0fff) > 1000) 1499 priv->stats.rxcrcerrmax++; 1500 else 1501 priv->stats.rxcrcerrmid++; 1502 1503 } 1504 1505 } else { 1506 len = priv->rxbuffersize; 1507 } 1508 1509 if (first && last) { 1510 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26; 1511 } else if (first) { 1512 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26; 1513 if (padding) 1514 len -= 2; 1515 } else { 1516 padding = 0; 1517 } 1518 padding = 0; 1519 priv->rx_prevlen += len; 1520 1521 if (priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100) { 1522 /* HW is probably passing several buggy frames 1523 * without FD or LD flag set. 1524 * Throw this garbage away to prevent skb 1525 * memory exausting 1526 */ 1527 if (!priv->rx_skb_complete) 1528 dev_kfree_skb_any(priv->rx_skb); 1529 priv->rx_skb_complete = 1; 1530 } 1531 1532 signal = (unsigned char)(((*(priv->rxringtail+3)) & (0x00ff0000))>>16); 1533 signal = (signal & 0xfe) >> 1; 1534 1535 quality = (unsigned char)((*(priv->rxringtail+3)) & (0xff)); 1536 1537 stats.mac_time[0] = *(priv->rxringtail+1); 1538 stats.mac_time[1] = *(priv->rxringtail+2); 1539 rxpower = ((char)(((*(priv->rxringtail+4)) & (0x00ff0000))>>16))/2 - 42; 1540 RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>>8)) & (0x7f); 1541 1542 rate = ((*(priv->rxringtail)) & 1543 ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20; 1544 1545 stats.rate = rtl8180_rate2rate(rate); 1546 Antenna = (((*(priv->rxringtail+3)) & (0x00008000)) == 0) ? 0 : 1; 1547 if (!rtl8180_IsWirelessBMode(stats.rate)) { /* OFDM rate. */ 1548 RxAGC_dBm = rxpower+1; /* bias */ 1549 } else { /* CCK rate. */ 1550 RxAGC_dBm = signal; /* bit 0 discard */ 1551 1552 LNA = (u8) (RxAGC_dBm & 0x60) >> 5; /* bit 6~ bit 5 */ 1553 BB = (u8) (RxAGC_dBm & 0x1F); /* bit 4 ~ bit 0 */ 1554 1555 RxAGC_dBm = -(LNA_gain[LNA] + (BB*2)); /* Pin_11b=-(LNA_gain+BB_gain) (dBm) */ 1556 1557 RxAGC_dBm += 4; /* bias */ 1558 } 1559 1560 if (RxAGC_dBm & 0x80) /* absolute value */ 1561 RXAGC = ~(RxAGC_dBm)+1; 1562 bCckRate = rtl8180_IsWirelessBMode(stats.rate); 1563 /* Translate RXAGC into 1-100. */ 1564 if (!rtl8180_IsWirelessBMode(stats.rate)) { /* OFDM rate. */ 1565 if (RXAGC > 90) 1566 RXAGC = 90; 1567 else if (RXAGC < 25) 1568 RXAGC = 25; 1569 RXAGC = (90-RXAGC)*100/65; 1570 } else { /* CCK rate. */ 1571 if (RXAGC > 95) 1572 RXAGC = 95; 1573 else if (RXAGC < 30) 1574 RXAGC = 30; 1575 RXAGC = (95-RXAGC)*100/65; 1576 } 1577 priv->SignalStrength = (u8)RXAGC; 1578 priv->RecvSignalPower = RxAGC_dBm; 1579 priv->RxPower = rxpower; 1580 priv->RSSI = RSSI; 1581 /* SQ translation formula is provided by SD3 DZ. 2006.06.27 */ 1582 if (quality >= 127) 1583 quality = 1; /*0; */ /* 0 will cause epc to show signal zero , walk aroud now; */ 1584 else if (quality < 27) 1585 quality = 100; 1586 else 1587 quality = 127 - quality; 1588 priv->SignalQuality = quality; 1589 1590 stats.signal = (u8)quality; /*priv->wstats.qual.level = priv->SignalStrength; */ 1591 stats.signalstrength = RXAGC; 1592 if (stats.signalstrength > 100) 1593 stats.signalstrength = 100; 1594 stats.signalstrength = (stats.signalstrength * 70)/100 + 30; 1595 /* printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength); */ 1596 stats.rssi = priv->wstats.qual.qual = priv->SignalQuality; 1597 stats.noise = priv->wstats.qual.noise = 100 - priv->wstats.qual.qual; 1598 bHwError = (((*(priv->rxringtail)) & (0x00000fff)) == 4080) | (((*(priv->rxringtail)) & (0x04000000)) != 0) 1599 | (((*(priv->rxringtail)) & (0x08000000)) != 0) | (((~(*(priv->rxringtail))) & (0x10000000)) != 0) | (((~(*(priv->rxringtail))) & (0x20000000)) != 0); 1600 bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13; 1601 bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12; 1602 hdr = (struct ieee80211_hdr_4addr *)priv->rxbuffer->buf; 1603 fc = le16_to_cpu(hdr->frame_ctl); 1604 type = WLAN_FC_GET_TYPE(fc); 1605 1606 if ((IEEE80211_FTYPE_CTL != type) && 1607 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS) ? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : hdr->addr3)) 1608 && (!bHwError) && (!bCRC) && (!bICV)) { 1609 /* Perform signal smoothing for dynamic 1610 * mechanism on demand. This is different 1611 * with PerformSignalSmoothing8185 in smoothing 1612 * fomula. No dramatic adjustion is apply 1613 * because dynamic mechanism need some degree 1614 * of correctness. */ 1615 PerformUndecoratedSignalSmoothing8185(priv, bCckRate); 1616 1617 /* For good-looking singal strength. */ 1618 SignalStrengthIndex = NetgearSignalStrengthTranslate( 1619 priv->LastSignalStrengthInPercent, 1620 priv->SignalStrength); 1621 1622 priv->LastSignalStrengthInPercent = SignalStrengthIndex; 1623 priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex); 1624 /* 1625 * We need more correct power of received packets and the "SignalStrength" of RxStats is beautified, 1626 * so we record the correct power here. 1627 */ 1628 priv->Stats_SignalQuality = (long)(priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6; 1629 priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower - 1) / 6; 1630 1631 /* Figure out which antenna that received the lasted packet. */ 1632 priv->LastRxPktAntenna = Antenna ? 1 : 0; /* 0: aux, 1: main. */ 1633 SwAntennaDiversityRxOk8185(dev, priv->SignalStrength); 1634 } 1635 1636 if (first) { 1637 if (!priv->rx_skb_complete) { 1638 /* seems that HW sometimes fails to reiceve and 1639 doesn't provide the last descriptor */ 1640 dev_kfree_skb_any(priv->rx_skb); 1641 priv->stats.rxnolast++; 1642 } 1643 /* support for prism header has been originally added by Christian */ 1644 if (priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR) { 1645 1646 } else { 1647 priv->rx_skb = dev_alloc_skb(len+2); 1648 if (!priv->rx_skb) 1649 goto drop; 1650 } 1651 1652 priv->rx_skb_complete = 0; 1653 priv->rx_skb->dev = dev; 1654 } else { 1655 /* if we are here we should have already RXed 1656 * the first frame. 1657 * If we get here and the skb is not allocated then 1658 * we have just throw out garbage (skb not allocated) 1659 * and we are still rxing garbage.... 1660 */ 1661 if (!priv->rx_skb_complete) { 1662 1663 tmp_skb = dev_alloc_skb(priv->rx_skb->len+len+2); 1664 1665 if (!tmp_skb) 1666 goto drop; 1667 1668 tmp_skb->dev = dev; 1669 1670 memcpy(skb_put(tmp_skb, priv->rx_skb->len), 1671 priv->rx_skb->data, 1672 priv->rx_skb->len); 1673 1674 dev_kfree_skb_any(priv->rx_skb); 1675 1676 priv->rx_skb = tmp_skb; 1677 } 1678 } 1679 1680 if (!priv->rx_skb_complete) { 1681 if (padding) { 1682 memcpy(skb_put(priv->rx_skb, len), 1683 (((unsigned char *)priv->rxbuffer->buf) + 2), len); 1684 } else { 1685 memcpy(skb_put(priv->rx_skb, len), 1686 priv->rxbuffer->buf, len); 1687 } 1688 } 1689 1690 if (last && !priv->rx_skb_complete) { 1691 if (priv->rx_skb->len > 4) 1692 skb_trim(priv->rx_skb, priv->rx_skb->len-4); 1693 if (!ieee80211_rtl_rx(priv->ieee80211, 1694 priv->rx_skb, &stats)) 1695 dev_kfree_skb_any(priv->rx_skb); 1696 priv->rx_skb_complete = 1; 1697 } 1698 1699 pci_dma_sync_single_for_device(priv->pdev, 1700 priv->rxbuffer->dma, 1701 priv->rxbuffersize * \ 1702 sizeof(u8), 1703 PCI_DMA_FROMDEVICE); 1704 1705drop: /* this is used when we have not enough mem */ 1706 /* restore the descriptor */ 1707 *(priv->rxringtail+2) = priv->rxbuffer->dma; 1708 *(priv->rxringtail) = *(priv->rxringtail) & ~0xfff; 1709 *(priv->rxringtail) = 1710 *(priv->rxringtail) | priv->rxbuffersize; 1711 1712 *(priv->rxringtail) = 1713 *(priv->rxringtail) | (1<<31); 1714 1715 priv->rxringtail += rx_desc_size; 1716 if (priv->rxringtail >= 1717 (priv->rxring)+(priv->rxringcount)*rx_desc_size) 1718 priv->rxringtail = priv->rxring; 1719 1720 priv->rxbuffer = (priv->rxbuffer->next); 1721 } 1722} 1723 1724 1725void rtl8180_dma_kick(struct net_device *dev, int priority) 1726{ 1727 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1728 1729 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 1730 write_nic_byte(dev, TX_DMA_POLLING, 1731 (1 << (priority + 1)) | priv->dma_poll_mask); 1732 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 1733 1734 force_pci_posting(dev); 1735} 1736 1737void rtl8180_data_hard_stop(struct net_device *dev) 1738{ 1739 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1740 1741 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 1742 priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ; 1743 write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask); 1744 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 1745} 1746 1747void rtl8180_data_hard_resume(struct net_device *dev) 1748{ 1749 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1750 1751 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 1752 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ); 1753 write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask); 1754 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 1755} 1756 1757/* 1758 * This function TX data frames when the ieee80211 stack requires this. 1759 * It checks also if we need to stop the ieee tx queue, eventually do it 1760 */ 1761void rtl8180_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int 1762rate) { 1763 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1764 int mode; 1765 struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data; 1766 short morefrag = (h->frame_control) & IEEE80211_FCTL_MOREFRAGS; 1767 unsigned long flags; 1768 int priority; 1769 1770 mode = priv->ieee80211->iw_mode; 1771 1772 rate = ieeerate2rtlrate(rate); 1773 /* 1774 * This function doesn't require lock because we make 1775 * sure it's called with the tx_lock already acquired. 1776 * this come from the kernel's hard_xmit callback (through 1777 * the ieee stack, or from the try_wake_queue (again through 1778 * the ieee stack. 1779 */ 1780 priority = AC2Q(skb->priority); 1781 spin_lock_irqsave(&priv->tx_lock, flags); 1782 1783 if (priv->ieee80211->bHwRadioOff) { 1784 spin_unlock_irqrestore(&priv->tx_lock, flags); 1785 1786 return; 1787 } 1788 1789 if (!check_nic_enought_desc(dev, priority)) { 1790 DMESGW("Error: no descriptor left by previous TX (avail %d) ", 1791 get_curr_tx_free_desc(dev, priority)); 1792 ieee80211_rtl_stop_queue(priv->ieee80211); 1793 } 1794 rtl8180_tx(dev, skb->data, skb->len, priority, morefrag, 0, rate); 1795 if (!check_nic_enought_desc(dev, priority)) 1796 ieee80211_rtl_stop_queue(priv->ieee80211); 1797 1798 spin_unlock_irqrestore(&priv->tx_lock, flags); 1799} 1800 1801/* 1802 * This is a rough attempt to TX a frame 1803 * This is called by the ieee 80211 stack to TX management frames. 1804 * If the ring is full packet are dropped (for data frame the queue 1805 * is stopped before this can happen). For this reason it is better 1806 * if the descriptors are larger than the largest management frame 1807 * we intend to TX: i'm unsure what the HW does if it will not found 1808 * the last fragment of a frame because it has been dropped... 1809 * Since queues for Management and Data frames are different we 1810 * might use a different lock than tx_lock (for example mgmt_tx_lock) 1811 */ 1812/* these function may loops if invoked with 0 descriptors or 0 len buffer */ 1813int rtl8180_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) 1814{ 1815 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1816 unsigned long flags; 1817 int priority; 1818 1819 priority = MANAGE_PRIORITY; 1820 1821 spin_lock_irqsave(&priv->tx_lock, flags); 1822 1823 if (priv->ieee80211->bHwRadioOff) { 1824 spin_unlock_irqrestore(&priv->tx_lock, flags); 1825 dev_kfree_skb_any(skb); 1826 return NETDEV_TX_OK; 1827 } 1828 1829 rtl8180_tx(dev, skb->data, skb->len, priority, 1830 0, 0, ieeerate2rtlrate(priv->ieee80211->basic_rate)); 1831 1832 priv->ieee80211->stats.tx_bytes += skb->len; 1833 priv->ieee80211->stats.tx_packets++; 1834 spin_unlock_irqrestore(&priv->tx_lock, flags); 1835 1836 dev_kfree_skb_any(skb); 1837 return NETDEV_TX_OK; 1838} 1839 1840/* longpre 144+48 shortpre 72+24 */ 1841u16 rtl8180_len2duration(u32 len, short rate, short *ext) 1842{ 1843 u16 duration; 1844 u16 drift; 1845 *ext = 0; 1846 1847 switch (rate) { 1848 case 0: /* 1mbps */ 1849 *ext = 0; 1850 duration = ((len+4)<<4) / 0x2; 1851 drift = ((len+4)<<4) % 0x2; 1852 if (drift == 0) 1853 break; 1854 duration++; 1855 break; 1856 case 1: /* 2mbps */ 1857 *ext = 0; 1858 duration = ((len+4)<<4) / 0x4; 1859 drift = ((len+4)<<4) % 0x4; 1860 if (drift == 0) 1861 break; 1862 duration++; 1863 break; 1864 case 2: /* 5.5mbps */ 1865 *ext = 0; 1866 duration = ((len+4)<<4) / 0xb; 1867 drift = ((len+4)<<4) % 0xb; 1868 if (drift == 0) 1869 break; 1870 duration++; 1871 break; 1872 default: 1873 case 3: /* 11mbps */ 1874 *ext = 0; 1875 duration = ((len+4)<<4) / 0x16; 1876 drift = ((len+4)<<4) % 0x16; 1877 if (drift == 0) 1878 break; 1879 duration++; 1880 if (drift > 6) 1881 break; 1882 *ext = 1; 1883 break; 1884 } 1885 1886 return duration; 1887} 1888 1889void rtl8180_prepare_beacon(struct net_device *dev) 1890{ 1891 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1892 struct sk_buff *skb; 1893 1894 u16 word = read_nic_word(dev, BcnItv); 1895 word &= ~BcnItv_BcnItv; /* clear Bcn_Itv */ 1896 word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval); /* 0x64; */ 1897 write_nic_word(dev, BcnItv, word); 1898 1899 skb = ieee80211_get_beacon(priv->ieee80211); 1900 if (skb) { 1901 rtl8180_tx(dev, skb->data, skb->len, BEACON_PRIORITY, 1902 0, 0, ieeerate2rtlrate(priv->ieee80211->basic_rate)); 1903 dev_kfree_skb_any(skb); 1904 } 1905} 1906 1907/* 1908 * This function do the real dirty work: it enqueues a TX command 1909 * descriptor in the ring buffer, copyes the frame in a TX buffer 1910 * and kicks the NIC to ensure it does the DMA transfer. 1911 */ 1912short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority, 1913 short morefrag, short descfrag, int rate) 1914{ 1915 struct r8180_priv *priv = ieee80211_priv(dev); 1916 u32 *tail, *temp_tail; 1917 u32 *begin; 1918 u32 *buf; 1919 int i; 1920 int remain; 1921 int buflen; 1922 int count; 1923 u16 duration; 1924 short ext; 1925 struct buffer *buflist; 1926 struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf; 1927 u8 dest[ETH_ALEN]; 1928 u8 bUseShortPreamble = 0; 1929 u8 bCTSEnable = 0; 1930 u8 bRTSEnable = 0; 1931 u16 Duration = 0; 1932 u16 RtsDur = 0; 1933 u16 ThisFrameTime = 0; 1934 u16 TxDescDuration = 0; 1935 u8 ownbit_flag = false; 1936 1937 switch (priority) { 1938 case MANAGE_PRIORITY: 1939 tail = priv->txmapringtail; 1940 begin = priv->txmapring; 1941 buflist = priv->txmapbufstail; 1942 count = priv->txringcount; 1943 break; 1944 case BK_PRIORITY: 1945 tail = priv->txbkpringtail; 1946 begin = priv->txbkpring; 1947 buflist = priv->txbkpbufstail; 1948 count = priv->txringcount; 1949 break; 1950 case BE_PRIORITY: 1951 tail = priv->txbepringtail; 1952 begin = priv->txbepring; 1953 buflist = priv->txbepbufstail; 1954 count = priv->txringcount; 1955 break; 1956 case VI_PRIORITY: 1957 tail = priv->txvipringtail; 1958 begin = priv->txvipring; 1959 buflist = priv->txvipbufstail; 1960 count = priv->txringcount; 1961 break; 1962 case VO_PRIORITY: 1963 tail = priv->txvopringtail; 1964 begin = priv->txvopring; 1965 buflist = priv->txvopbufstail; 1966 count = priv->txringcount; 1967 break; 1968 case HI_PRIORITY: 1969 tail = priv->txhpringtail; 1970 begin = priv->txhpring; 1971 buflist = priv->txhpbufstail; 1972 count = priv->txringcount; 1973 break; 1974 case BEACON_PRIORITY: 1975 tail = priv->txbeaconringtail; 1976 begin = priv->txbeaconring; 1977 buflist = priv->txbeaconbufstail; 1978 count = priv->txbeaconcount; 1979 break; 1980 default: 1981 return -1; 1982 break; 1983 } 1984 1985 memcpy(&dest, frag_hdr->addr1, ETH_ALEN); 1986 if (is_multicast_ether_addr(dest) || 1987 is_broadcast_ether_addr(dest)) { 1988 Duration = 0; 1989 RtsDur = 0; 1990 bRTSEnable = 0; 1991 bCTSEnable = 0; 1992 1993 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble); 1994 TxDescDuration = ThisFrameTime; 1995 } else { /* Unicast packet */ 1996 u16 AckTime; 1997 1998 /* YJ,add,080828,for Keep alive */ 1999 priv->NumTxUnicast++; 2000 2001 /* Figure out ACK rate according to BSS basic rate 2002 * and Tx rate. */ 2003 AckTime = ComputeTxTime(14, 10, 0, 0); /* AckCTSLng = 14 use 1M bps send */ 2004 2005 if (((len + sCrcLng) > priv->rts) && priv->rts) { /* RTS/CTS. */ 2006 u16 RtsTime, CtsTime; 2007 /* u16 CtsRate; */ 2008 bRTSEnable = 1; 2009 bCTSEnable = 0; 2010 2011 /* Rate and time required for RTS. */ 2012 RtsTime = ComputeTxTime(sAckCtsLng/8, priv->ieee80211->basic_rate, 0, 0); 2013 /* Rate and time required for CTS. */ 2014 CtsTime = ComputeTxTime(14, 10, 0, 0); /* AckCTSLng = 14 use 1M bps send */ 2015 2016 /* Figure out time required to transmit this frame. */ 2017 ThisFrameTime = ComputeTxTime(len + sCrcLng, 2018 rtl8180_rate2rate(rate), 2019 0, 2020 bUseShortPreamble); 2021 2022 /* RTS-CTS-ThisFrame-ACK. */ 2023 RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime; 2024 2025 TxDescDuration = RtsTime + RtsDur; 2026 } else { /* Normal case. */ 2027 bCTSEnable = 0; 2028 bRTSEnable = 0; 2029 RtsDur = 0; 2030 2031 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble); 2032 TxDescDuration = ThisFrameTime + aSifsTime + AckTime; 2033 } 2034 2035 if (!(frag_hdr->frame_control & IEEE80211_FCTL_MOREFRAGS)) { 2036 /* ThisFrame-ACK. */ 2037 Duration = aSifsTime + AckTime; 2038 } else { /* One or more fragments remained. */ 2039 u16 NextFragTime; 2040 NextFragTime = ComputeTxTime(len + sCrcLng, /* pretend following packet length equal current packet */ 2041 rtl8180_rate2rate(rate), 2042 0, 2043 bUseShortPreamble); 2044 2045 /* ThisFrag-ACk-NextFrag-ACK. */ 2046 Duration = NextFragTime + 3*aSifsTime + 2*AckTime; 2047 } 2048 2049 } /* End of Unicast packet */ 2050 2051 frag_hdr->duration_id = Duration; 2052 2053 buflen = priv->txbuffsize; 2054 remain = len; 2055 temp_tail = tail; 2056 2057 while (remain != 0) { 2058 mb(); 2059 if (!buflist) { 2060 DMESGE("TX buffer error, cannot TX frames. pri %d.", priority); 2061 return -1; 2062 } 2063 buf = buflist->buf; 2064 2065 if ((*tail & (1 << 31)) && (priority != BEACON_PRIORITY)) { 2066 DMESGW("No more TX desc, returning %x of %x", 2067 remain, len); 2068 priv->stats.txrdu++; 2069 return remain; 2070 } 2071 2072 *tail = 0; /* zeroes header */ 2073 *(tail+1) = 0; 2074 *(tail+3) = 0; 2075 *(tail+5) = 0; 2076 *(tail+6) = 0; 2077 *(tail+7) = 0; 2078 2079 *tail |= (1<<15); /* no encrypt */ 2080 2081 if (remain == len && !descfrag) { 2082 ownbit_flag = false; 2083 *tail = *tail | (1<<29) ; /* fist segment of the packet */ 2084 *tail = *tail | (len); 2085 } else { 2086 ownbit_flag = true; 2087 } 2088 2089 for (i = 0; i < buflen && remain > 0; i++, remain--) { 2090 ((u8 *)buf)[i] = txbuf[i]; /* copy data into descriptor pointed DMAble buffer */ 2091 if (remain == 4 && i+4 >= buflen) 2092 break; 2093 /* ensure the last desc has at least 4 bytes payload */ 2094 2095 } 2096 txbuf = txbuf + i; 2097 *(tail+3) = *(tail+3) & ~0xfff; 2098 *(tail+3) = *(tail+3) | i; /* buffer length */ 2099 /* Use short preamble or not */ 2100 if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE) 2101 if (priv->plcp_preamble_mode == 1 && rate != 0) /* short mode now, not long! */ 2102 ; /* *tail |= (1<<16); */ /* enable short preamble mode. */ 2103 2104 if (bCTSEnable) 2105 *tail |= (1<<18); 2106 2107 if (bRTSEnable) { /* rts enable */ 2108 *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19); /* RTS RATE */ 2109 *tail |= (1<<23); /* rts enable */ 2110 *(tail+1) |= (RtsDur&0xffff); /* RTS Duration */ 2111 } 2112 *(tail+3) |= ((TxDescDuration&0xffff)<<16); /* DURATION */ 2113 /* *(tail+3) |= (0xe6<<16); */ 2114 *(tail+5) |= (11<<8); /* (priv->retry_data<<8); */ /* retry lim; */ 2115 2116 *tail = *tail | ((rate&0xf) << 24); 2117 2118 /* hw_plcp_len is not used for rtl8180 chip */ 2119 if (!priv->hw_plcp_len) { 2120 duration = rtl8180_len2duration(len, rate, &ext); 2121 *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16); 2122 if (ext) 2123 *(tail+1) = *(tail+1) | (1<<31); /* plcp length extension */ 2124 } 2125 2126 if (morefrag) 2127 *tail = (*tail) | (1<<17); /* more fragment */ 2128 if (!remain) 2129 *tail = (*tail) | (1<<28); /* last segment of frame */ 2130 2131 *(tail+5) = *(tail+5)|(2<<27); 2132 *(tail+7) = *(tail+7)|(1<<4); 2133 2134 wmb(); 2135 if (ownbit_flag) 2136 *tail = *tail | (1<<31); /* descriptor ready to be txed */ 2137 2138 if ((tail - begin)/8 == count-1) 2139 tail = begin; 2140 else 2141 tail = tail+8; 2142 2143 buflist = buflist->next; 2144 2145 mb(); 2146 2147 switch (priority) { 2148 case MANAGE_PRIORITY: 2149 priv->txmapringtail = tail; 2150 priv->txmapbufstail = buflist; 2151 break; 2152 case BK_PRIORITY: 2153 priv->txbkpringtail = tail; 2154 priv->txbkpbufstail = buflist; 2155 break; 2156 case BE_PRIORITY: 2157 priv->txbepringtail = tail; 2158 priv->txbepbufstail = buflist; 2159 break; 2160 case VI_PRIORITY: 2161 priv->txvipringtail = tail; 2162 priv->txvipbufstail = buflist; 2163 break; 2164 case VO_PRIORITY: 2165 priv->txvopringtail = tail; 2166 priv->txvopbufstail = buflist; 2167 break; 2168 case HI_PRIORITY: 2169 priv->txhpringtail = tail; 2170 priv->txhpbufstail = buflist; 2171 break; 2172 case BEACON_PRIORITY: 2173 /* 2174 * The HW seems to be happy with the 1st 2175 * descriptor filled and the 2nd empty... 2176 * So always update descriptor 1 and never 2177 * touch 2nd 2178 */ 2179 break; 2180 } 2181 } 2182 *temp_tail = *temp_tail | (1<<31); /* descriptor ready to be txed */ 2183 rtl8180_dma_kick(dev, priority); 2184 2185 return 0; 2186} 2187 2188void rtl8180_irq_rx_tasklet(struct r8180_priv *priv); 2189 2190void rtl8180_link_change(struct net_device *dev) 2191{ 2192 struct r8180_priv *priv = ieee80211_priv(dev); 2193 u16 beacon_interval; 2194 struct ieee80211_network *net = &priv->ieee80211->current_network; 2195 2196 rtl8180_update_msr(dev); 2197 2198 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 2199 2200 write_nic_dword(dev, BSSID, ((u32 *)net->bssid)[0]); 2201 write_nic_word(dev, BSSID+4, ((u16 *)net->bssid)[2]); 2202 2203 beacon_interval = read_nic_dword(dev, BEACON_INTERVAL); 2204 beacon_interval &= ~BEACON_INTERVAL_MASK; 2205 beacon_interval |= net->beacon_interval; 2206 write_nic_dword(dev, BEACON_INTERVAL, beacon_interval); 2207 2208 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 2209 2210 rtl8180_set_chan(dev, priv->chan); 2211} 2212 2213void rtl8180_rq_tx_ack(struct net_device *dev) 2214{ 2215 2216 struct r8180_priv *priv = ieee80211_priv(dev); 2217 2218 write_nic_byte(dev, CONFIG4, read_nic_byte(dev, CONFIG4) | CONFIG4_PWRMGT); 2219 priv->ack_tx_to_ieee = 1; 2220} 2221 2222short rtl8180_is_tx_queue_empty(struct net_device *dev) 2223{ 2224 2225 struct r8180_priv *priv = ieee80211_priv(dev); 2226 u32 *d; 2227 2228 for (d = priv->txmapring; 2229 d < priv->txmapring + priv->txringcount; d += 8) 2230 if (*d & (1<<31)) 2231 return 0; 2232 2233 for (d = priv->txbkpring; 2234 d < priv->txbkpring + priv->txringcount; d += 8) 2235 if (*d & (1<<31)) 2236 return 0; 2237 2238 for (d = priv->txbepring; 2239 d < priv->txbepring + priv->txringcount; d += 8) 2240 if (*d & (1<<31)) 2241 return 0; 2242 2243 for (d = priv->txvipring; 2244 d < priv->txvipring + priv->txringcount; d += 8) 2245 if (*d & (1<<31)) 2246 return 0; 2247 2248 for (d = priv->txvopring; 2249 d < priv->txvopring + priv->txringcount; d += 8) 2250 if (*d & (1<<31)) 2251 return 0; 2252 2253 for (d = priv->txhpring; 2254 d < priv->txhpring + priv->txringcount; d += 8) 2255 if (*d & (1<<31)) 2256 return 0; 2257 return 1; 2258} 2259#define HW_WAKE_DELAY 5 2260 2261void rtl8180_hw_wakeup(struct net_device *dev) 2262{ 2263 unsigned long flags; 2264 struct r8180_priv *priv = ieee80211_priv(dev); 2265 2266 spin_lock_irqsave(&priv->ps_lock, flags); 2267 write_nic_byte(dev, CONFIG4, read_nic_byte(dev, CONFIG4) & ~CONFIG4_PWRMGT); 2268 if (priv->rf_wakeup) 2269 priv->rf_wakeup(dev); 2270 spin_unlock_irqrestore(&priv->ps_lock, flags); 2271} 2272 2273void rtl8180_hw_sleep_down(struct net_device *dev) 2274{ 2275 unsigned long flags; 2276 struct r8180_priv *priv = ieee80211_priv(dev); 2277 2278 spin_lock_irqsave(&priv->ps_lock, flags); 2279 if (priv->rf_sleep) 2280 priv->rf_sleep(dev); 2281 spin_unlock_irqrestore(&priv->ps_lock, flags); 2282} 2283 2284void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl) 2285{ 2286 struct r8180_priv *priv = ieee80211_priv(dev); 2287 u32 rb = jiffies; 2288 unsigned long flags; 2289 2290 spin_lock_irqsave(&priv->ps_lock, flags); 2291 2292 /* 2293 * Writing HW register with 0 equals to disable 2294 * the timer, that is not really what we want 2295 */ 2296 tl -= MSECS(4+16+7); 2297 2298 /* 2299 * If the interval in witch we are requested to sleep is too 2300 * short then give up and remain awake 2301 */ 2302 if (((tl >= rb) && (tl-rb) <= MSECS(MIN_SLEEP_TIME)) 2303 || ((rb > tl) && (rb-tl) < MSECS(MIN_SLEEP_TIME))) { 2304 spin_unlock_irqrestore(&priv->ps_lock, flags); 2305 printk("too short to sleep\n"); 2306 return; 2307 } 2308 2309 { 2310 u32 tmp = (tl > rb) ? (tl-rb) : (rb-tl); 2311 2312 priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp); 2313 2314 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); /* as tl may be less than rb */ 2315 } 2316 /* 2317 * If we suspect the TimerInt is gone beyond tl 2318 * while setting it, then give up 2319 */ 2320 2321 if (((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME))) || 2322 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) { 2323 spin_unlock_irqrestore(&priv->ps_lock, flags); 2324 return; 2325 } 2326 2327 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq); 2328 spin_unlock_irqrestore(&priv->ps_lock, flags); 2329} 2330 2331void rtl8180_wmm_param_update(struct work_struct *work) 2332{ 2333 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, wmm_param_update_wq); 2334 struct net_device *dev = ieee->dev; 2335 u8 *ac_param = (u8 *)(ieee->current_network.wmm_param); 2336 u8 mode = ieee->current_network.mode; 2337 AC_CODING eACI; 2338 AC_PARAM AcParam; 2339 PAC_PARAM pAcParam; 2340 u8 i; 2341 2342 if (!ieee->current_network.QoS_Enable) { 2343 /* legacy ac_xx_param update */ 2344 AcParam.longData = 0; 2345 AcParam.f.AciAifsn.f.AIFSN = 2; /* Follow 802.11 DIFS. */ 2346 AcParam.f.AciAifsn.f.ACM = 0; 2347 AcParam.f.Ecw.f.ECWmin = 3; /* Follow 802.11 CWmin. */ 2348 AcParam.f.Ecw.f.ECWmax = 7; /* Follow 802.11 CWmax. */ 2349 AcParam.f.TXOPLimit = 0; 2350 for (eACI = 0; eACI < AC_MAX; eACI++) { 2351 AcParam.f.AciAifsn.f.ACI = (u8)eACI; 2352 { 2353 u8 u1bAIFS; 2354 u32 u4bAcParam; 2355 pAcParam = (PAC_PARAM)(&AcParam); 2356 /* Retrive paramters to udpate. */ 2357 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G) ? 9 : 20) + aSifsTime; 2358 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)| 2359 (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)| 2360 (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)| 2361 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET)); 2362 switch (eACI) { 2363 case AC1_BK: 2364 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); 2365 break; 2366 case AC0_BE: 2367 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam); 2368 break; 2369 case AC2_VI: 2370 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam); 2371 break; 2372 case AC3_VO: 2373 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam); 2374 break; 2375 default: 2376 printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI); 2377 break; 2378 } 2379 } 2380 } 2381 return; 2382 } 2383 2384 for (i = 0; i < AC_MAX; i++) { 2385 /* AcParam.longData = 0; */ 2386 pAcParam = (AC_PARAM *)ac_param; 2387 { 2388 AC_CODING eACI; 2389 u8 u1bAIFS; 2390 u32 u4bAcParam; 2391 2392 /* Retrive paramters to udpate. */ 2393 eACI = pAcParam->f.AciAifsn.f.ACI; 2394 /* Mode G/A: slotTimeTimer = 9; Mode B: 20 */ 2395 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G) ? 9 : 20) + aSifsTime; 2396 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) | 2397 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) | 2398 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) | 2399 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET)); 2400 2401 switch (eACI) { 2402 case AC1_BK: 2403 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); 2404 break; 2405 case AC0_BE: 2406 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam); 2407 break; 2408 case AC2_VI: 2409 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam); 2410 break; 2411 case AC3_VO: 2412 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam); 2413 break; 2414 default: 2415 printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI); 2416 break; 2417 } 2418 } 2419 ac_param += (sizeof(AC_PARAM)); 2420 } 2421} 2422 2423void rtl8180_tx_irq_wq(struct work_struct *work); 2424void rtl8180_restart_wq(struct work_struct *work); 2425/* void rtl8180_rq_tx_ack(struct work_struct *work); */ 2426void rtl8180_watch_dog_wq(struct work_struct *work); 2427void rtl8180_hw_wakeup_wq(struct work_struct *work); 2428void rtl8180_hw_sleep_wq(struct work_struct *work); 2429void rtl8180_sw_antenna_wq(struct work_struct *work); 2430void rtl8180_watch_dog(struct net_device *dev); 2431 2432void watch_dog_adaptive(unsigned long data) 2433{ 2434 struct r8180_priv* priv = ieee80211_priv((struct net_device *)data); 2435 2436 if (!priv->up) { 2437 DMESG("<----watch_dog_adaptive():driver is not up!\n"); 2438 return; 2439 } 2440 2441 /* Tx High Power Mechanism. */ 2442 if (CheckHighPower((struct net_device *)data)) 2443 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq); 2444 2445 /* Tx Power Tracking on 87SE. */ 2446 if (CheckTxPwrTracking((struct net_device *)data)) 2447 TxPwrTracking87SE((struct net_device *)data); 2448 2449 /* Perform DIG immediately. */ 2450 if (CheckDig((struct net_device *)data) == true) 2451 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq); 2452 rtl8180_watch_dog((struct net_device *)data); 2453 2454 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem); 2455 2456 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME); 2457 add_timer(&priv->watch_dog_timer); 2458} 2459 2460static CHANNEL_LIST ChannelPlan[] = { 2461 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, /* FCC */ 2462 {{1,2,3,4,5,6,7,8,9,10,11},11}, /* IC */ 2463 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, /* ETSI */ 2464 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, /* Spain. Change to ETSI. */ 2465 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, /* France. Change to ETSI. */ 2466 {{14,36,40,44,48,52,56,60,64},9}, /* MKK */ 2467 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},/* MKK1 */ 2468 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, /* Israel. */ 2469 {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, /* For 11a , TELEC */ 2470 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, /* For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626 */ 2471 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} /* world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826 */ 2472}; 2473 2474static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee) 2475{ 2476 int i; 2477 2478 /* lzm add 080826 */ 2479 ieee->MinPassiveChnlNum = MAX_CHANNEL_NUMBER+1; 2480 ieee->IbssStartChnl = 0; 2481 2482 switch (channel_plan) { 2483 case COUNTRY_CODE_FCC: 2484 case COUNTRY_CODE_IC: 2485 case COUNTRY_CODE_ETSI: 2486 case COUNTRY_CODE_SPAIN: 2487 case COUNTRY_CODE_FRANCE: 2488 case COUNTRY_CODE_MKK: 2489 case COUNTRY_CODE_MKK1: 2490 case COUNTRY_CODE_ISRAEL: 2491 case COUNTRY_CODE_TELEC: 2492 { 2493 Dot11d_Init(ieee); 2494 ieee->bGlobalDomain = false; 2495 if (ChannelPlan[channel_plan].Len != 0) { 2496 /* Clear old channel map */ 2497 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map)); 2498 /* Set new channel map */ 2499 for (i = 0; i < ChannelPlan[channel_plan].Len; i++) { 2500 if (ChannelPlan[channel_plan].Channel[i] <= 14) 2501 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1; 2502 } 2503 } 2504 break; 2505 } 2506 case COUNTRY_CODE_GLOBAL_DOMAIN: 2507 { 2508 GET_DOT11D_INFO(ieee)->bEnabled = 0; 2509 Dot11d_Reset(ieee); 2510 ieee->bGlobalDomain = true; 2511 break; 2512 } 2513 case COUNTRY_CODE_WORLD_WIDE_13_INDEX:/* lzm add 080826 */ 2514 { 2515 ieee->MinPassiveChnlNum = 12; 2516 ieee->IbssStartChnl = 10; 2517 break; 2518 } 2519 default: 2520 { 2521 Dot11d_Init(ieee); 2522 ieee->bGlobalDomain = false; 2523 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map)); 2524 for (i = 1; i <= 14; i++) 2525 GET_DOT11D_INFO(ieee)->channel_map[i] = 1; 2526 break; 2527 } 2528 } 2529} 2530 2531void GPIOChangeRFWorkItemCallBack(struct work_struct *work); 2532 2533/* YJ,add,080828 */ 2534static void rtl8180_statistics_init(struct Stats *pstats) 2535{ 2536 memset(pstats, 0, sizeof(struct Stats)); 2537} 2538 2539static void rtl8180_link_detect_init(plink_detect_t plink_detect) 2540{ 2541 memset(plink_detect, 0, sizeof(link_detect_t)); 2542 plink_detect->SlotNum = DEFAULT_SLOT_NUM; 2543} 2544 2545/* YJ,add,080828,end */ 2546static void rtl8187se_eeprom_register_read(struct eeprom_93cx6 *eeprom) 2547{ 2548 struct net_device *dev = eeprom->data; 2549 u8 reg = read_nic_byte(dev, EPROM_CMD); 2550 2551 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; 2552 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; 2553 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; 2554 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; 2555} 2556 2557static void rtl8187se_eeprom_register_write(struct eeprom_93cx6 *eeprom) 2558{ 2559 struct net_device *dev = eeprom->data; 2560 u8 reg = 2 << 6; 2561 2562 if (eeprom->reg_data_in) 2563 reg |= RTL818X_EEPROM_CMD_WRITE; 2564 if (eeprom->reg_data_out) 2565 reg |= RTL818X_EEPROM_CMD_READ; 2566 if (eeprom->reg_data_clock) 2567 reg |= RTL818X_EEPROM_CMD_CK; 2568 if (eeprom->reg_chip_select) 2569 reg |= RTL818X_EEPROM_CMD_CS; 2570 2571 write_nic_byte(dev, EPROM_CMD, reg); 2572 read_nic_byte(dev, EPROM_CMD); 2573 udelay(10); 2574} 2575 2576short rtl8180_init(struct net_device *dev) 2577{ 2578 struct r8180_priv *priv = ieee80211_priv(dev); 2579 u16 word; 2580 u16 version; 2581 u32 usValue; 2582 u16 tmpu16; 2583 int i, j; 2584 struct eeprom_93cx6 eeprom; 2585 u16 eeprom_val; 2586 2587 eeprom.data = dev; 2588 eeprom.register_read = rtl8187se_eeprom_register_read; 2589 eeprom.register_write = rtl8187se_eeprom_register_write; 2590 eeprom.width = PCI_EEPROM_WIDTH_93C46; 2591 2592 eeprom_93cx6_read(&eeprom, EEPROM_COUNTRY_CODE>>1, &eeprom_val); 2593 priv->channel_plan = eeprom_val & 0xFF; 2594 if (priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN) { 2595 printk("rtl8180_init:Error channel plan! Set to default.\n"); 2596 priv->channel_plan = 0; 2597 } 2598 2599 DMESG("Channel plan is %d\n", priv->channel_plan); 2600 rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211); 2601 2602 priv->txbuffsize = 2048; /* 1024; */ 2603 priv->txringcount = 32; /* 32; */ 2604 priv->rxbuffersize = 2048; /* 1024; */ 2605 priv->rxringcount = 64; /* 32; */ 2606 priv->txbeaconcount = 2; 2607 priv->rx_skb_complete = 1; 2608 2609 priv->RFChangeInProgress = false; 2610 priv->SetRFPowerStateInProgress = false; 2611 priv->RFProgType = 0; 2612 priv->bInHctTest = false; 2613 2614 priv->irq_enabled = 0; 2615 2616 rtl8180_statistics_init(&priv->stats); 2617 rtl8180_link_detect_init(&priv->link_detect); 2618 2619 priv->ack_tx_to_ieee = 0; 2620 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL; 2621 priv->ieee80211->iw_mode = IW_MODE_INFRA; 2622 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN | 2623 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ | 2624 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE; 2625 priv->ieee80211->active_scan = 1; 2626 priv->ieee80211->rate = 110; /* 11 mbps */ 2627 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION; 2628 priv->ieee80211->host_encrypt = 1; 2629 priv->ieee80211->host_decrypt = 1; 2630 priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup; 2631 priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack; 2632 priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep; 2633 priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty; 2634 2635 priv->hw_wep = hwwep; 2636 priv->prism_hdr = 0; 2637 priv->dev = dev; 2638 priv->retry_rts = DEFAULT_RETRY_RTS; 2639 priv->retry_data = DEFAULT_RETRY_DATA; 2640 priv->RFChangeInProgress = false; 2641 priv->SetRFPowerStateInProgress = false; 2642 priv->RFProgType = 0; 2643 priv->bInHctTest = false; 2644 priv->bInactivePs = true; /* false; */ 2645 priv->ieee80211->bInactivePs = priv->bInactivePs; 2646 priv->bSwRfProcessing = false; 2647 priv->eRFPowerState = eRfOff; 2648 priv->RfOffReason = 0; 2649 priv->LedStrategy = SW_LED_MODE0; 2650 priv->TxPollingTimes = 0; /* lzm add 080826 */ 2651 priv->bLeisurePs = true; 2652 priv->dot11PowerSaveMode = eActive; 2653 priv->AdMinCheckPeriod = 5; 2654 priv->AdMaxCheckPeriod = 10; 2655 priv->AdMaxRxSsThreshold = 30; /* 60->30 */ 2656 priv->AdRxSsThreshold = 20; /* 50->20 */ 2657 priv->AdCheckPeriod = priv->AdMinCheckPeriod; 2658 priv->AdTickCount = 0; 2659 priv->AdRxSignalStrength = -1; 2660 priv->RegSwAntennaDiversityMechanism = 0; 2661 priv->RegDefaultAntenna = 0; 2662 priv->SignalStrength = 0; 2663 priv->AdRxOkCnt = 0; 2664 priv->CurrAntennaIndex = 0; 2665 priv->AdRxSsBeforeSwitched = 0; 2666 init_timer(&priv->SwAntennaDiversityTimer); 2667 priv->SwAntennaDiversityTimer.data = (unsigned long)dev; 2668 priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback; 2669 priv->bDigMechanism = 1; 2670 priv->InitialGain = 6; 2671 priv->bXtalCalibration = false; 2672 priv->XtalCal_Xin = 0; 2673 priv->XtalCal_Xout = 0; 2674 priv->bTxPowerTrack = false; 2675 priv->ThermalMeter = 0; 2676 priv->FalseAlarmRegValue = 0; 2677 priv->RegDigOfdmFaUpTh = 0xc; /* Upper threhold of OFDM false alarm, which is used in DIG. */ 2678 priv->DIG_NumberFallbackVote = 0; 2679 priv->DIG_NumberUpgradeVote = 0; 2680 priv->LastSignalStrengthInPercent = 0; 2681 priv->Stats_SignalStrength = 0; 2682 priv->LastRxPktAntenna = 0; 2683 priv->SignalQuality = 0; /* in 0-100 index. */ 2684 priv->Stats_SignalQuality = 0; 2685 priv->RecvSignalPower = 0; /* in dBm. */ 2686 priv->Stats_RecvSignalPower = 0; 2687 priv->AdMainAntennaRxOkCnt = 0; 2688 priv->AdAuxAntennaRxOkCnt = 0; 2689 priv->bHWAdSwitched = false; 2690 priv->bRegHighPowerMechanism = true; 2691 priv->RegHiPwrUpperTh = 77; 2692 priv->RegHiPwrLowerTh = 75; 2693 priv->RegRSSIHiPwrUpperTh = 70; 2694 priv->RegRSSIHiPwrLowerTh = 20; 2695 priv->bCurCCKPkt = false; 2696 priv->UndecoratedSmoothedSS = -1; 2697 priv->bToUpdateTxPwr = false; 2698 priv->CurCCKRSSI = 0; 2699 priv->RxPower = 0; 2700 priv->RSSI = 0; 2701 priv->NumTxOkTotal = 0; 2702 priv->NumTxUnicast = 0; 2703 priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL; 2704 priv->PowerProfile = POWER_PROFILE_AC; 2705 priv->CurrRetryCnt = 0; 2706 priv->LastRetryCnt = 0; 2707 priv->LastTxokCnt = 0; 2708 priv->LastRxokCnt = 0; 2709 priv->LastRetryRate = 0; 2710 priv->bTryuping = 0; 2711 priv->CurrTxRate = 0; 2712 priv->CurrRetryRate = 0; 2713 priv->TryupingCount = 0; 2714 priv->TryupingCountNoData = 0; 2715 priv->TryDownCountLowData = 0; 2716 priv->LastTxOKBytes = 0; 2717 priv->LastFailTxRate = 0; 2718 priv->LastFailTxRateSS = 0; 2719 priv->FailTxRateCount = 0; 2720 priv->LastTxThroughput = 0; 2721 priv->NumTxOkBytesTotal = 0; 2722 priv->ForcedDataRate = 0; 2723 priv->RegBModeGainStage = 1; 2724 2725 priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0; 2726 spin_lock_init(&priv->irq_lock); 2727 spin_lock_init(&priv->irq_th_lock); 2728 spin_lock_init(&priv->tx_lock); 2729 spin_lock_init(&priv->ps_lock); 2730 spin_lock_init(&priv->rf_ps_lock); 2731 sema_init(&priv->wx_sem, 1); 2732 sema_init(&priv->rf_state, 1); 2733 INIT_WORK(&priv->reset_wq, (void *)rtl8180_restart_wq); 2734 INIT_WORK(&priv->tx_irq_wq, (void *)rtl8180_tx_irq_wq); 2735 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq, 2736 (void *)rtl8180_hw_wakeup_wq); 2737 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq, 2738 (void *)rtl8180_hw_sleep_wq); 2739 INIT_WORK(&priv->ieee80211->wmm_param_update_wq, 2740 (void *)rtl8180_wmm_param_update); 2741 INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq, 2742 (void *)rtl8180_rate_adapter); 2743 INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq, 2744 (void *)rtl8180_hw_dig_wq); 2745 INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq, 2746 (void *)rtl8180_tx_pw_wq); 2747 INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem, 2748 (void *) GPIOChangeRFWorkItemCallBack); 2749 tasklet_init(&priv->irq_rx_tasklet, 2750 (void(*)(unsigned long)) rtl8180_irq_rx_tasklet, 2751 (unsigned long)priv); 2752 2753 init_timer(&priv->watch_dog_timer); 2754 priv->watch_dog_timer.data = (unsigned long)dev; 2755 priv->watch_dog_timer.function = watch_dog_adaptive; 2756 2757 init_timer(&priv->rateadapter_timer); 2758 priv->rateadapter_timer.data = (unsigned long)dev; 2759 priv->rateadapter_timer.function = timer_rate_adaptive; 2760 priv->RateAdaptivePeriod = RATE_ADAPTIVE_TIMER_PERIOD; 2761 priv->bEnhanceTxPwr = false; 2762 2763 priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit; 2764 priv->ieee80211->set_chan = rtl8180_set_chan; 2765 priv->ieee80211->link_change = rtl8180_link_change; 2766 priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit; 2767 priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop; 2768 priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume; 2769 2770 priv->ieee80211->init_wmmparam_flag = 0; 2771 2772 priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon; 2773 priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable; 2774 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD; 2775 2776 priv->MWIEnable = 0; 2777 2778 priv->ShortRetryLimit = 7; 2779 priv->LongRetryLimit = 7; 2780 priv->EarlyRxThreshold = 7; 2781 2782 priv->CSMethod = (0x01 << 29); 2783 2784 priv->TransmitConfig = TCR_DurProcMode_OFFSET | 2785 (7<<TCR_MXDMA_OFFSET) | 2786 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | 2787 (priv->LongRetryLimit<<TCR_LRL_OFFSET) | 2788 (0 ? TCR_SAT : 0); 2789 2790 priv->ReceiveConfig = RCR_AMF | RCR_ADF | RCR_ACF | 2791 RCR_AB | RCR_AM | RCR_APM | 2792 (7<<RCR_MXDMA_OFFSET) | 2793 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | 2794 (priv->EarlyRxThreshold == 7 ? 2795 RCR_ONLYERLPKT : 0); 2796 2797 priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER | 2798 IMR_THPDER | IMR_THPDOK | 2799 IMR_TVODER | IMR_TVODOK | 2800 IMR_TVIDER | IMR_TVIDOK | 2801 IMR_TBEDER | IMR_TBEDOK | 2802 IMR_TBKDER | IMR_TBKDOK | 2803 IMR_RDU | 2804 IMR_RER | IMR_ROK | 2805 IMR_RQoSOK; 2806 2807 priv->InitialGain = 6; 2808 2809 DMESG("MAC controller is a RTL8187SE b/g"); 2810 priv->phy_ver = 2; 2811 2812 priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION; 2813 priv->ieee80211->short_slot = 1; 2814 2815 /* just for sync 85 */ 2816 priv->enable_gpio0 = 0; 2817 2818 eeprom_93cx6_read(&eeprom, EEPROM_SW_REVD_OFFSET, &eeprom_val); 2819 usValue = eeprom_val; 2820 DMESG("usValue is 0x%x\n", usValue); 2821 /* 3Read AntennaDiversity */ 2822 2823 /* SW Antenna Diversity. */ 2824 if ((usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE) 2825 priv->EEPROMSwAntennaDiversity = false; 2826 else 2827 priv->EEPROMSwAntennaDiversity = true; 2828 2829 /* Default Antenna to use. */ 2830 if ((usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1) 2831 priv->EEPROMDefaultAntenna1 = false; 2832 else 2833 priv->EEPROMDefaultAntenna1 = true; 2834 2835 if (priv->RegSwAntennaDiversityMechanism == 0) /* Auto */ 2836 /* 0: default from EEPROM. */ 2837 priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity; 2838 else 2839 /* 1:disable antenna diversity, 2: enable antenna diversity. */ 2840 priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1) ? false : true); 2841 2842 if (priv->RegDefaultAntenna == 0) 2843 /* 0: default from EEPROM. */ 2844 priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1; 2845 else 2846 /* 1: main, 2: aux. */ 2847 priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna == 2) ? true : false); 2848 2849 /* rtl8185 can calc plcp len in HW. */ 2850 priv->hw_plcp_len = 1; 2851 2852 priv->plcp_preamble_mode = 2; 2853 /* the eeprom type is stored in RCR register bit #6 */ 2854 if (RCR_9356SEL & read_nic_dword(dev, RCR)) 2855 priv->epromtype = EPROM_93c56; 2856 else 2857 priv->epromtype = EPROM_93c46; 2858 2859 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *) 2860 dev->dev_addr, 3); 2861 2862 for (i = 1, j = 0; i < 14; i += 2, j++) { 2863 eeprom_93cx6_read(&eeprom, EPROM_TXPW_CH1_2 + j, &word); 2864 priv->chtxpwr[i] = word & 0xff; 2865 priv->chtxpwr[i+1] = (word & 0xff00)>>8; 2866 } 2867 for (i = 1, j = 0; i < 14; i += 2, j++) { 2868 eeprom_93cx6_read(&eeprom, EPROM_TXPW_OFDM_CH1_2 + j, &word); 2869 priv->chtxpwr_ofdm[i] = word & 0xff; 2870 priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8; 2871 } 2872 2873 /* 3Read crystal calibtration and thermal meter indication on 87SE. */ 2874 eeprom_93cx6_read(&eeprom, EEPROM_RSV>>1, &tmpu16); 2875 2876 /* Crystal calibration for Xin and Xout resp. */ 2877 priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK; 2878 priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4; 2879 if ((tmpu16 & EEPROM_XTAL_CAL_ENABLE) >> 12) 2880 priv->bXtalCalibration = true; 2881 2882 /* Thermal meter reference indication. */ 2883 priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK) >> 8); 2884 if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13) 2885 priv->bTxPowerTrack = true; 2886 2887 eeprom_93cx6_read(&eeprom, EPROM_TXPW_BASE, &word); 2888 priv->cck_txpwr_base = word & 0xf; 2889 priv->ofdm_txpwr_base = (word>>4) & 0xf; 2890 2891 eeprom_93cx6_read(&eeprom, EPROM_VERSION, &version); 2892 DMESG("EEPROM version %x", version); 2893 priv->rcr_csense = 3; 2894 2895 eeprom_93cx6_read(&eeprom, ENERGY_TRESHOLD, &eeprom_val); 2896 priv->cs_treshold = (eeprom_val & 0xff00) >> 8; 2897 2898 eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val); 2899 priv->rf_sleep = rtl8225z4_rf_sleep; 2900 priv->rf_wakeup = rtl8225z4_rf_wakeup; 2901 DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!"); 2902 2903 priv->rf_close = rtl8225z2_rf_close; 2904 priv->rf_init = rtl8225z2_rf_init; 2905 priv->rf_set_chan = rtl8225z2_rf_set_chan; 2906 priv->rf_set_sens = NULL; 2907 2908 if (0 != alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount)) 2909 return -ENOMEM; 2910 2911 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, 2912 TX_MANAGEPRIORITY_RING_ADDR)) 2913 return -ENOMEM; 2914 2915 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, 2916 TX_BKPRIORITY_RING_ADDR)) 2917 return -ENOMEM; 2918 2919 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, 2920 TX_BEPRIORITY_RING_ADDR)) 2921 return -ENOMEM; 2922 2923 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, 2924 TX_VIPRIORITY_RING_ADDR)) 2925 return -ENOMEM; 2926 2927 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, 2928 TX_VOPRIORITY_RING_ADDR)) 2929 return -ENOMEM; 2930 2931 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount, 2932 TX_HIGHPRIORITY_RING_ADDR)) 2933 return -ENOMEM; 2934 2935 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount, 2936 TX_BEACON_RING_ADDR)) 2937 return -ENOMEM; 2938 2939 if (request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)) { 2940 DMESGE("Error allocating IRQ %d", dev->irq); 2941 return -1; 2942 } else { 2943 priv->irq = dev->irq; 2944 DMESG("IRQ %d", dev->irq); 2945 } 2946 2947 return 0; 2948} 2949 2950void rtl8180_no_hw_wep(struct net_device *dev) 2951{ 2952} 2953 2954void rtl8180_set_hw_wep(struct net_device *dev) 2955{ 2956 struct r8180_priv *priv = ieee80211_priv(dev); 2957 u8 pgreg; 2958 u8 security; 2959 u32 key0_word4; 2960 2961 pgreg = read_nic_byte(dev, PGSELECT); 2962 write_nic_byte(dev, PGSELECT, pgreg & ~(1<<PGSELECT_PG_SHIFT)); 2963 2964 key0_word4 = read_nic_dword(dev, KEY0+4+4+4); 2965 key0_word4 &= ~0xff; 2966 key0_word4 |= priv->key0[3] & 0xff; 2967 write_nic_dword(dev, KEY0, (priv->key0[0])); 2968 write_nic_dword(dev, KEY0+4, (priv->key0[1])); 2969 write_nic_dword(dev, KEY0+4+4, (priv->key0[2])); 2970 write_nic_dword(dev, KEY0+4+4+4, (key0_word4)); 2971 2972 security = read_nic_byte(dev, SECURITY); 2973 security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT); 2974 security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT); 2975 security &= ~SECURITY_ENCRYP_MASK; 2976 security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT); 2977 2978 write_nic_byte(dev, SECURITY, security); 2979 2980 DMESG("key %x %x %x %x", read_nic_dword(dev, KEY0+4+4+4), 2981 read_nic_dword(dev, KEY0+4+4), read_nic_dword(dev, KEY0+4), 2982 read_nic_dword(dev, KEY0)); 2983} 2984 2985 2986void rtl8185_rf_pins_enable(struct net_device *dev) 2987{ 2988 /* u16 tmp; */ 2989 /* tmp = read_nic_word(dev, RFPinsEnable); */ 2990 write_nic_word(dev, RFPinsEnable, 0x1fff); /* | tmp); */ 2991} 2992 2993void rtl8185_set_anaparam2(struct net_device *dev, u32 a) 2994{ 2995 u8 conf3; 2996 2997 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 2998 2999 conf3 = read_nic_byte(dev, CONFIG3); 3000 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT)); 3001 write_nic_dword(dev, ANAPARAM2, a); 3002 3003 conf3 = read_nic_byte(dev, CONFIG3); 3004 write_nic_byte(dev, CONFIG3, conf3 & ~(1<<CONFIG3_ANAPARAM_W_SHIFT)); 3005 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 3006} 3007 3008void rtl8180_set_anaparam(struct net_device *dev, u32 a) 3009{ 3010 u8 conf3; 3011 3012 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 3013 3014 conf3 = read_nic_byte(dev, CONFIG3); 3015 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT)); 3016 write_nic_dword(dev, ANAPARAM, a); 3017 3018 conf3 = read_nic_byte(dev, CONFIG3); 3019 write_nic_byte(dev, CONFIG3, conf3 & ~(1<<CONFIG3_ANAPARAM_W_SHIFT)); 3020 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 3021} 3022 3023void rtl8185_tx_antenna(struct net_device *dev, u8 ant) 3024{ 3025 write_nic_byte(dev, TX_ANTENNA, ant); 3026 force_pci_posting(dev); 3027 mdelay(1); 3028} 3029 3030void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data) 3031{ 3032 u32 phyw; 3033 3034 adr |= 0x80; 3035 3036 phyw = ((data<<8) | adr); 3037 3038 /* Note that, we must write 0xff7c after 0x7d-0x7f to write BB register. */ 3039 write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24)); 3040 write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16)); 3041 write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8)); 3042 write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff))); 3043 3044 /* this is ok to fail when we write AGC table. check for AGC table might be 3045 * done by masking with 0x7f instead of 0xff 3046 */ 3047 /* if (phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data, adr); */ 3048} 3049 3050inline void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data) 3051{ 3052 data = data & 0xff; 3053 rtl8185_write_phy(dev, adr, data); 3054} 3055 3056void write_phy_cck(struct net_device *dev, u8 adr, u32 data) 3057{ 3058 data = data & 0xff; 3059 rtl8185_write_phy(dev, adr, data | 0x10000); 3060} 3061 3062void rtl8185_set_rate(struct net_device *dev) 3063{ 3064 int i; 3065 u16 word; 3066 int basic_rate, min_rr_rate, max_rr_rate; 3067 3068 basic_rate = ieeerate2rtlrate(240); 3069 min_rr_rate = ieeerate2rtlrate(60); 3070 max_rr_rate = ieeerate2rtlrate(240); 3071 3072 write_nic_byte(dev, RESP_RATE, 3073 max_rr_rate<<MAX_RESP_RATE_SHIFT | min_rr_rate<<MIN_RESP_RATE_SHIFT); 3074 3075 word = read_nic_word(dev, BRSR); 3076 word &= ~BRSR_MBR_8185; 3077 3078 for (i = 0; i <= basic_rate; i++) 3079 word |= (1<<i); 3080 3081 write_nic_word(dev, BRSR, word); 3082} 3083 3084void rtl8180_adapter_start(struct net_device *dev) 3085{ 3086 struct r8180_priv *priv = ieee80211_priv(dev); 3087 3088 rtl8180_rtx_disable(dev); 3089 rtl8180_reset(dev); 3090 3091 /* enable beacon timeout, beacon TX ok and err 3092 * LP tx ok and err, HP TX ok and err, NP TX ok and err, 3093 * RX ok and ERR, and GP timer 3094 */ 3095 priv->irq_mask = 0x6fcf; 3096 3097 priv->dma_poll_mask = 0; 3098 3099 rtl8180_beacon_tx_disable(dev); 3100 3101 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 3102 write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]); 3103 write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff); 3104 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 3105 3106 rtl8180_update_msr(dev); 3107 3108 /* These might be unnecessary since we do in rx_enable / tx_enable */ 3109 fix_rx_fifo(dev); 3110 fix_tx_fifo(dev); 3111 3112 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 3113 3114 /* 3115 * The following is very strange. seems to be that 1 means test mode, 3116 * but we need to acknolwledges the nic when a packet is ready 3117 * although we set it to 0 3118 */ 3119 3120 write_nic_byte(dev, 3121 CONFIG2, read_nic_byte(dev, CONFIG2) & ~\ 3122 (1<<CONFIG2_DMA_POLLING_MODE_SHIFT)); 3123 /* ^the nic isn't in test mode */ 3124 write_nic_byte(dev, 3125 CONFIG2, read_nic_byte(dev, CONFIG2)|(1<<4)); 3126 3127 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 3128 3129 write_nic_dword(dev, INT_TIMEOUT, 0); 3130 3131 write_nic_byte(dev, WPA_CONFIG, 0); 3132 3133 rtl8180_no_hw_wep(dev); 3134 3135 rtl8185_set_rate(dev); 3136 write_nic_byte(dev, RATE_FALLBACK, 0x81); 3137 3138 write_nic_byte(dev, GP_ENABLE, read_nic_byte(dev, GP_ENABLE) & ~(1<<6)); 3139 3140 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); 3141 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) 3142 | (1 << CONFIG3_CLKRUN_SHIFT)); 3143 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 3144 3145 priv->rf_init(dev); 3146 3147 if (priv->rf_set_sens != NULL) 3148 priv->rf_set_sens(dev, priv->sens); 3149 rtl8180_irq_enable(dev); 3150 3151 netif_start_queue(dev); 3152} 3153 3154/* 3155 * This configures registers for beacon tx and enables it via 3156 * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might 3157 * be used to stop beacon transmission 3158 */ 3159void rtl8180_start_tx_beacon(struct net_device *dev) 3160{ 3161 u16 word; 3162 3163 DMESG("Enabling beacon TX"); 3164 rtl8180_prepare_beacon(dev); 3165 rtl8180_irq_disable(dev); 3166 rtl8180_beacon_tx_enable(dev); 3167 3168 word = read_nic_word(dev, AtimWnd) & ~AtimWnd_AtimWnd; 3169 write_nic_word(dev, AtimWnd, word); /* word |= */ 3170 3171 word = read_nic_word(dev, BintrItv); 3172 word &= ~BintrItv_BintrItv; 3173 word |= 1000; 3174 write_nic_word(dev, BintrItv, word); 3175 3176 rtl8180_set_mode(dev, EPROM_CMD_NORMAL); 3177 3178 rtl8185b_irq_enable(dev); 3179} 3180 3181static struct net_device_stats *rtl8180_stats(struct net_device *dev) 3182{ 3183 struct r8180_priv *priv = ieee80211_priv(dev); 3184 3185 return &priv->ieee80211->stats; 3186} 3187 3188/* 3189 * Change current and default preamble mode. 3190 */ 3191bool 3192MgntActSet_802_11_PowerSaveMode( 3193 struct r8180_priv *priv, 3194 RT_PS_MODE rtPsMode 3195) 3196{ 3197 /* Currently, we do not change power save mode on IBSS mode. */ 3198 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) 3199 return false; 3200 3201 priv->ieee80211->ps = rtPsMode; 3202 3203 return true; 3204} 3205 3206void LeisurePSEnter(struct r8180_priv *priv) 3207{ 3208 if (priv->bLeisurePs) { 3209 if (priv->ieee80211->ps == IEEE80211_PS_DISABLED) 3210 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST); /* IEEE80211_PS_ENABLE */ 3211 } 3212} 3213 3214void LeisurePSLeave(struct r8180_priv *priv) 3215{ 3216 if (priv->bLeisurePs) { 3217 if (priv->ieee80211->ps != IEEE80211_PS_DISABLED) 3218 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED); 3219 } 3220} 3221 3222void rtl8180_hw_wakeup_wq(struct work_struct *work) 3223{ 3224 struct delayed_work *dwork = to_delayed_work(work); 3225 struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, hw_wakeup_wq); 3226 struct net_device *dev = ieee->dev; 3227 3228 rtl8180_hw_wakeup(dev); 3229} 3230 3231void rtl8180_hw_sleep_wq(struct work_struct *work) 3232{ 3233 struct delayed_work *dwork = to_delayed_work(work); 3234 struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, hw_sleep_wq); 3235 struct net_device *dev = ieee->dev; 3236 3237 rtl8180_hw_sleep_down(dev); 3238} 3239 3240static void MgntLinkKeepAlive(struct r8180_priv *priv) 3241{ 3242 if (priv->keepAliveLevel == 0) 3243 return; 3244 3245 if (priv->ieee80211->state == IEEE80211_LINKED) { 3246 /* 3247 * Keep-Alive. 3248 */ 3249 3250 if ((priv->keepAliveLevel == 2) || 3251 (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast && 3252 priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast) 3253 ) { 3254 priv->link_detect.IdleCount++; 3255 3256 /* 3257 * Send a Keep-Alive packet packet to AP if we had been idle for a while. 3258 */ 3259 if (priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1)) { 3260 priv->link_detect.IdleCount = 0; 3261 ieee80211_sta_ps_send_null_frame(priv->ieee80211, false); 3262 } 3263 } else { 3264 priv->link_detect.IdleCount = 0; 3265 } 3266 priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast; 3267 priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast; 3268 } 3269} 3270 3271static u8 read_acadapter_file(char *filename); 3272 3273void rtl8180_watch_dog(struct net_device *dev) 3274{ 3275 struct r8180_priv *priv = ieee80211_priv(dev); 3276 bool bEnterPS = false; 3277 bool bBusyTraffic = false; 3278 u32 TotalRxNum = 0; 3279 u16 SlotIndex = 0; 3280 u16 i = 0; 3281 if (priv->ieee80211->actscanning == false) { 3282 if ((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn)) 3283 IPSEnter(dev); 3284 } 3285 /* YJ,add,080828,for link state check */ 3286 if ((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)) { 3287 SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum; 3288 priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod; 3289 for (i = 0; i < priv->link_detect.SlotNum; i++) 3290 TotalRxNum += priv->link_detect.RxFrameNum[i]; 3291 3292 if (TotalRxNum == 0) { 3293 priv->ieee80211->state = IEEE80211_ASSOCIATING; 3294 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq); 3295 } 3296 } 3297 3298 /* YJ,add,080828,for KeepAlive */ 3299 MgntLinkKeepAlive(priv); 3300 3301 /* YJ,add,080828,for LPS */ 3302 if (priv->PowerProfile == POWER_PROFILE_BATTERY) 3303 priv->bLeisurePs = true; 3304 else if (priv->PowerProfile == POWER_PROFILE_AC) { 3305 LeisurePSLeave(priv); 3306 priv->bLeisurePs = false; 3307 } 3308 3309 if (priv->ieee80211->state == IEEE80211_LINKED) { 3310 priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod; 3311 if (priv->link_detect.NumRxOkInPeriod > 666 || 3312 priv->link_detect.NumTxOkInPeriod > 666) { 3313 bBusyTraffic = true; 3314 } 3315 if (((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8) 3316 || (priv->link_detect.NumRxOkInPeriod > 2)) { 3317 bEnterPS = false; 3318 } else 3319 bEnterPS = true; 3320 3321 if (bEnterPS) 3322 LeisurePSEnter(priv); 3323 else 3324 LeisurePSLeave(priv); 3325 } else 3326 LeisurePSLeave(priv); 3327 priv->link_detect.bBusyTraffic = bBusyTraffic; 3328 priv->link_detect.NumRxOkInPeriod = 0; 3329 priv->link_detect.NumTxOkInPeriod = 0; 3330 priv->ieee80211->NumRxDataInPeriod = 0; 3331 priv->ieee80211->NumRxBcnInPeriod = 0; 3332} 3333 3334int _rtl8180_up(struct net_device *dev) 3335{ 3336 struct r8180_priv *priv = ieee80211_priv(dev); 3337 3338 priv->up = 1; 3339 3340 DMESG("Bringing up iface"); 3341 rtl8185b_adapter_start(dev); 3342 rtl8185b_rx_enable(dev); 3343 rtl8185b_tx_enable(dev); 3344 if (priv->bInactivePs) { 3345 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) 3346 IPSLeave(dev); 3347 } 3348 timer_rate_adaptive((unsigned long)dev); 3349 watch_dog_adaptive((unsigned long)dev); 3350 if (priv->bSwAntennaDiverity) 3351 SwAntennaDiversityTimerCallback(dev); 3352 ieee80211_softmac_start_protocol(priv->ieee80211); 3353 return 0; 3354} 3355 3356int rtl8180_open(struct net_device *dev) 3357{ 3358 struct r8180_priv *priv = ieee80211_priv(dev); 3359 int ret; 3360 3361 down(&priv->wx_sem); 3362 ret = rtl8180_up(dev); 3363 up(&priv->wx_sem); 3364 return ret; 3365} 3366 3367int rtl8180_up(struct net_device *dev) 3368{ 3369 struct r8180_priv *priv = ieee80211_priv(dev); 3370 3371 if (priv->up == 1) 3372 return -1; 3373 3374 return _rtl8180_up(dev); 3375} 3376 3377int rtl8180_close(struct net_device *dev) 3378{ 3379 struct r8180_priv *priv = ieee80211_priv(dev); 3380 int ret; 3381 3382 down(&priv->wx_sem); 3383 ret = rtl8180_down(dev); 3384 up(&priv->wx_sem); 3385 3386 return ret; 3387} 3388 3389int rtl8180_down(struct net_device *dev) 3390{ 3391 struct r8180_priv *priv = ieee80211_priv(dev); 3392 3393 if (priv->up == 0) 3394 return -1; 3395 3396 priv->up = 0; 3397 3398 ieee80211_softmac_stop_protocol(priv->ieee80211); 3399 if (!netif_queue_stopped(dev)) 3400 netif_stop_queue(dev); 3401 rtl8180_rtx_disable(dev); 3402 rtl8180_irq_disable(dev); 3403 del_timer_sync(&priv->watch_dog_timer); 3404 del_timer_sync(&priv->rateadapter_timer); 3405 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq); 3406 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); 3407 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); 3408 cancel_delayed_work(&priv->ieee80211->hw_dig_wq); 3409 cancel_delayed_work(&priv->ieee80211->tx_pw_wq); 3410 del_timer_sync(&priv->SwAntennaDiversityTimer); 3411 SetZebraRFPowerState8185(dev, eRfOff); 3412 memset(&(priv->ieee80211->current_network), 0, sizeof(struct ieee80211_network)); 3413 priv->ieee80211->state = IEEE80211_NOLINK; 3414 return 0; 3415} 3416 3417void rtl8180_restart_wq(struct work_struct *work) 3418{ 3419 struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq); 3420 struct net_device *dev = priv->dev; 3421 3422 down(&priv->wx_sem); 3423 3424 rtl8180_commit(dev); 3425 3426 up(&priv->wx_sem); 3427} 3428 3429void rtl8180_restart(struct net_device *dev) 3430{ 3431 struct r8180_priv *priv = ieee80211_priv(dev); 3432 3433 schedule_work(&priv->reset_wq); 3434} 3435 3436void rtl8180_commit(struct net_device *dev) 3437{ 3438 struct r8180_priv *priv = ieee80211_priv(dev); 3439 3440 if (priv->up == 0) 3441 return ; 3442 3443 del_timer_sync(&priv->watch_dog_timer); 3444 del_timer_sync(&priv->rateadapter_timer); 3445 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq); 3446 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); 3447 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); 3448 cancel_delayed_work(&priv->ieee80211->hw_dig_wq); 3449 cancel_delayed_work(&priv->ieee80211->tx_pw_wq); 3450 del_timer_sync(&priv->SwAntennaDiversityTimer); 3451 ieee80211_softmac_stop_protocol(priv->ieee80211); 3452 rtl8180_irq_disable(dev); 3453 rtl8180_rtx_disable(dev); 3454 _rtl8180_up(dev); 3455} 3456 3457static void r8180_set_multicast(struct net_device *dev) 3458{ 3459 struct r8180_priv *priv = ieee80211_priv(dev); 3460 short promisc; 3461 3462 promisc = (dev->flags & IFF_PROMISC) ? 1 : 0; 3463 3464 if (promisc != priv->promisc) 3465 rtl8180_restart(dev); 3466 3467 priv->promisc = promisc; 3468} 3469 3470int r8180_set_mac_adr(struct net_device *dev, void *mac) 3471{ 3472 struct r8180_priv *priv = ieee80211_priv(dev); 3473 struct sockaddr *addr = mac; 3474 3475 down(&priv->wx_sem); 3476 3477 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3478 3479 if (priv->ieee80211->iw_mode == IW_MODE_MASTER) 3480 memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN); 3481 3482 if (priv->up) { 3483 rtl8180_down(dev); 3484 rtl8180_up(dev); 3485 } 3486 3487 up(&priv->wx_sem); 3488 3489 return 0; 3490} 3491 3492/* based on ipw2200 driver */ 3493int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3494{ 3495 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 3496 struct iwreq *wrq = (struct iwreq *) rq; 3497 int ret = -1; 3498 3499 switch (cmd) { 3500 case RTL_IOCTL_WPA_SUPPLICANT: 3501 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data); 3502 return ret; 3503 default: 3504 return -EOPNOTSUPP; 3505 } 3506 3507 return -EOPNOTSUPP; 3508} 3509 3510static const struct net_device_ops rtl8180_netdev_ops = { 3511 .ndo_open = rtl8180_open, 3512 .ndo_stop = rtl8180_close, 3513 .ndo_get_stats = rtl8180_stats, 3514 .ndo_tx_timeout = rtl8180_restart, 3515 .ndo_do_ioctl = rtl8180_ioctl, 3516 .ndo_set_multicast_list = r8180_set_multicast, 3517 .ndo_set_mac_address = r8180_set_mac_adr, 3518 .ndo_validate_addr = eth_validate_addr, 3519 .ndo_change_mtu = eth_change_mtu, 3520 .ndo_start_xmit = ieee80211_rtl_xmit, 3521}; 3522 3523static int __devinit rtl8180_pci_probe(struct pci_dev *pdev, 3524 const struct pci_device_id *id) 3525{ 3526 unsigned long ioaddr = 0; 3527 struct net_device *dev = NULL; 3528 struct r8180_priv *priv = NULL; 3529 u8 unit = 0; 3530 3531 unsigned long pmem_start, pmem_len, pmem_flags; 3532 3533 DMESG("Configuring chip resources"); 3534 3535 if (pci_enable_device(pdev)) { 3536 DMESG("Failed to enable PCI device"); 3537 return -EIO; 3538 } 3539 3540 pci_set_master(pdev); 3541 pci_set_dma_mask(pdev, 0xffffff00ULL); 3542 pci_set_consistent_dma_mask(pdev, 0xffffff00ULL); 3543 dev = alloc_ieee80211(sizeof(struct r8180_priv)); 3544 if (!dev) 3545 return -ENOMEM; 3546 priv = ieee80211_priv(dev); 3547 priv->ieee80211 = netdev_priv(dev); 3548 3549 pci_set_drvdata(pdev, dev); 3550 SET_NETDEV_DEV(dev, &pdev->dev); 3551 3552 priv = ieee80211_priv(dev); 3553 priv->pdev = pdev; 3554 3555 pmem_start = pci_resource_start(pdev, 1); 3556 pmem_len = pci_resource_len(pdev, 1); 3557 pmem_flags = pci_resource_flags(pdev, 1); 3558 3559 if (!(pmem_flags & IORESOURCE_MEM)) { 3560 DMESG("region #1 not a MMIO resource, aborting"); 3561 goto fail; 3562 } 3563 3564 if (!request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) { 3565 DMESG("request_mem_region failed!"); 3566 goto fail; 3567 } 3568 3569 ioaddr = (unsigned long)ioremap_nocache(pmem_start, pmem_len); 3570 if (ioaddr == (unsigned long)NULL) { 3571 DMESG("ioremap failed!"); 3572 goto fail1; 3573 } 3574 3575 dev->mem_start = ioaddr; /* shared mem start */ 3576 dev->mem_end = ioaddr + pci_resource_len(pdev, 0); /* shared mem end */ 3577 3578 pci_read_config_byte(pdev, 0x05, &unit); 3579 pci_write_config_byte(pdev, 0x05, unit & (~0x04)); 3580 3581 dev->irq = pdev->irq; 3582 priv->irq = 0; 3583 3584 dev->netdev_ops = &rtl8180_netdev_ops; 3585 dev->wireless_handlers = &r8180_wx_handlers_def; 3586 3587 dev->type = ARPHRD_ETHER; 3588 dev->watchdog_timeo = HZ*3; 3589 3590 if (dev_alloc_name(dev, ifname) < 0) { 3591 DMESG("Oops: devname already taken! Trying wlan%%d...\n"); 3592 strcpy(ifname, "wlan%d"); 3593 dev_alloc_name(dev, ifname); 3594 } 3595 3596 if (rtl8180_init(dev) != 0) { 3597 DMESG("Initialization failed"); 3598 goto fail1; 3599 } 3600 3601 netif_carrier_off(dev); 3602 3603 register_netdev(dev); 3604 3605 rtl8180_proc_init_one(dev); 3606 3607 DMESG("Driver probe completed\n"); 3608 return 0; 3609fail1: 3610 if (dev->mem_start != (unsigned long)NULL) { 3611 iounmap((void *)dev->mem_start); 3612 release_mem_region(pci_resource_start(pdev, 1), 3613 pci_resource_len(pdev, 1)); 3614 } 3615fail: 3616 if (dev) { 3617 if (priv->irq) { 3618 free_irq(dev->irq, dev); 3619 dev->irq = 0; 3620 } 3621 free_ieee80211(dev); 3622 } 3623 3624 pci_disable_device(pdev); 3625 3626 DMESG("wlan driver load failed\n"); 3627 pci_set_drvdata(pdev, NULL); 3628 return -ENODEV; 3629} 3630 3631static void __devexit rtl8180_pci_remove(struct pci_dev *pdev) 3632{ 3633 struct r8180_priv *priv; 3634 struct net_device *dev = pci_get_drvdata(pdev); 3635 3636 if (dev) { 3637 unregister_netdev(dev); 3638 3639 priv = ieee80211_priv(dev); 3640 3641 rtl8180_proc_remove_one(dev); 3642 rtl8180_down(dev); 3643 priv->rf_close(dev); 3644 rtl8180_reset(dev); 3645 mdelay(10); 3646 3647 if (priv->irq) { 3648 DMESG("Freeing irq %d", dev->irq); 3649 free_irq(dev->irq, dev); 3650 priv->irq = 0; 3651 } 3652 3653 free_rx_desc_ring(dev); 3654 free_tx_desc_rings(dev); 3655 3656 if (dev->mem_start != (unsigned long)NULL) { 3657 iounmap((void *)dev->mem_start); 3658 release_mem_region(pci_resource_start(pdev, 1), 3659 pci_resource_len(pdev, 1)); 3660 } 3661 3662 free_ieee80211(dev); 3663 } 3664 pci_disable_device(pdev); 3665 3666 DMESG("wlan driver removed\n"); 3667} 3668 3669/* fun with the built-in ieee80211 stack... */ 3670extern int ieee80211_crypto_init(void); 3671extern void ieee80211_crypto_deinit(void); 3672extern int ieee80211_crypto_tkip_init(void); 3673extern void ieee80211_crypto_tkip_exit(void); 3674extern int ieee80211_crypto_ccmp_init(void); 3675extern void ieee80211_crypto_ccmp_exit(void); 3676extern int ieee80211_crypto_wep_init(void); 3677extern void ieee80211_crypto_wep_exit(void); 3678 3679static int __init rtl8180_pci_module_init(void) 3680{ 3681 int ret; 3682 3683 ret = ieee80211_crypto_init(); 3684 if (ret) { 3685 printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret); 3686 return ret; 3687 } 3688 ret = ieee80211_crypto_tkip_init(); 3689 if (ret) { 3690 printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret); 3691 return ret; 3692 } 3693 ret = ieee80211_crypto_ccmp_init(); 3694 if (ret) { 3695 printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret); 3696 return ret; 3697 } 3698 ret = ieee80211_crypto_wep_init(); 3699 if (ret) { 3700 printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret); 3701 return ret; 3702 } 3703 3704 printk(KERN_INFO "\nLinux kernel driver for RTL8180 / RTL8185 based WLAN cards\n"); 3705 printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n"); 3706 DMESG("Initializing module"); 3707 DMESG("Wireless extensions version %d", WIRELESS_EXT); 3708 rtl8180_proc_module_init(); 3709 3710 if (pci_register_driver(&rtl8180_pci_driver)) { 3711 DMESG("No device found"); 3712 return -ENODEV; 3713 } 3714 return 0; 3715} 3716 3717static void __exit rtl8180_pci_module_exit(void) 3718{ 3719 pci_unregister_driver(&rtl8180_pci_driver); 3720 rtl8180_proc_module_remove(); 3721 ieee80211_crypto_tkip_exit(); 3722 ieee80211_crypto_ccmp_exit(); 3723 ieee80211_crypto_wep_exit(); 3724 ieee80211_crypto_deinit(); 3725 DMESG("Exiting"); 3726} 3727 3728void rtl8180_try_wake_queue(struct net_device *dev, int pri) 3729{ 3730 unsigned long flags; 3731 short enough_desc; 3732 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 3733 3734 spin_lock_irqsave(&priv->tx_lock, flags); 3735 enough_desc = check_nic_enought_desc(dev, pri); 3736 spin_unlock_irqrestore(&priv->tx_lock, flags); 3737 3738 if (enough_desc) 3739 ieee80211_rtl_wake_queue(priv->ieee80211); 3740} 3741 3742void rtl8180_tx_isr(struct net_device *dev, int pri, short error) 3743{ 3744 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 3745 u32 *tail; /* tail virtual addr */ 3746 u32 *head; /* head virtual addr */ 3747 u32 *begin; /* start of ring virtual addr */ 3748 u32 *nicv; /* nic pointer virtual addr */ 3749 u32 nic; /* nic pointer physical addr */ 3750 u32 nicbegin; /* start of ring physical addr */ 3751 unsigned long flag; 3752 /* physical addr are ok on 32 bits since we set DMA mask */ 3753 int offs; 3754 int j, i; 3755 int hd; 3756 if (error) 3757 priv->stats.txretry++; /* tony 20060601 */ 3758 spin_lock_irqsave(&priv->tx_lock, flag); 3759 switch (pri) { 3760 case MANAGE_PRIORITY: 3761 tail = priv->txmapringtail; 3762 begin = priv->txmapring; 3763 head = priv->txmapringhead; 3764 nic = read_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR); 3765 nicbegin = priv->txmapringdma; 3766 break; 3767 case BK_PRIORITY: 3768 tail = priv->txbkpringtail; 3769 begin = priv->txbkpring; 3770 head = priv->txbkpringhead; 3771 nic = read_nic_dword(dev, TX_BKPRIORITY_RING_ADDR); 3772 nicbegin = priv->txbkpringdma; 3773 break; 3774 case BE_PRIORITY: 3775 tail = priv->txbepringtail; 3776 begin = priv->txbepring; 3777 head = priv->txbepringhead; 3778 nic = read_nic_dword(dev, TX_BEPRIORITY_RING_ADDR); 3779 nicbegin = priv->txbepringdma; 3780 break; 3781 case VI_PRIORITY: 3782 tail = priv->txvipringtail; 3783 begin = priv->txvipring; 3784 head = priv->txvipringhead; 3785 nic = read_nic_dword(dev, TX_VIPRIORITY_RING_ADDR); 3786 nicbegin = priv->txvipringdma; 3787 break; 3788 case VO_PRIORITY: 3789 tail = priv->txvopringtail; 3790 begin = priv->txvopring; 3791 head = priv->txvopringhead; 3792 nic = read_nic_dword(dev, TX_VOPRIORITY_RING_ADDR); 3793 nicbegin = priv->txvopringdma; 3794 break; 3795 case HI_PRIORITY: 3796 tail = priv->txhpringtail; 3797 begin = priv->txhpring; 3798 head = priv->txhpringhead; 3799 nic = read_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR); 3800 nicbegin = priv->txhpringdma; 3801 break; 3802 3803 default: 3804 spin_unlock_irqrestore(&priv->tx_lock, flag); 3805 return ; 3806 } 3807 3808 nicv = (u32 *)((nic - nicbegin) + (u8*)begin); 3809 if ((head <= tail && (nicv > tail || nicv < head)) || 3810 (head > tail && (nicv > tail && nicv < head))) { 3811 DMESGW("nic has lost pointer"); 3812 spin_unlock_irqrestore(&priv->tx_lock, flag); 3813 rtl8180_restart(dev); 3814 return; 3815 } 3816 3817 /* 3818 * We check all the descriptors between the head and the nic, 3819 * but not the currently pointed by the nic (the next to be txed) 3820 * and the previous of the pointed (might be in process ??) 3821 */ 3822 offs = (nic - nicbegin); 3823 offs = offs / 8 / 4; 3824 hd = (head - begin) / 8; 3825 3826 if (offs >= hd) 3827 j = offs - hd; 3828 else 3829 j = offs + (priv->txringcount-1-hd); 3830 3831 j -= 2; 3832 if (j < 0) 3833 j = 0; 3834 3835 for (i = 0; i < j; i++) { 3836 if ((*head) & (1<<31)) 3837 break; 3838 if (((*head)&(0x10000000)) != 0) { 3839 priv->CurrRetryCnt += (u16)((*head) & (0x000000ff)); 3840 if (!error) 3841 priv->NumTxOkTotal++; 3842 } 3843 3844 if (!error) 3845 priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff); 3846 3847 *head = *head & ~(1<<31); 3848 3849 if ((head - begin)/8 == priv->txringcount-1) 3850 head = begin; 3851 else 3852 head += 8; 3853 } 3854 3855 /* 3856 * The head has been moved to the last certainly TXed 3857 * (or at least processed by the nic) packet. 3858 * The driver take forcefully owning of all these packets 3859 * If the packet previous of the nic pointer has been 3860 * processed this doesn't matter: it will be checked 3861 * here at the next round. Anyway if no more packet are 3862 * TXed no memory leak occour at all. 3863 */ 3864 3865 switch (pri) { 3866 case MANAGE_PRIORITY: 3867 priv->txmapringhead = head; 3868 3869 if (priv->ack_tx_to_ieee) { 3870 if (rtl8180_is_tx_queue_empty(dev)) { 3871 priv->ack_tx_to_ieee = 0; 3872 ieee80211_ps_tx_ack(priv->ieee80211, !error); 3873 } 3874 } 3875 break; 3876 case BK_PRIORITY: 3877 priv->txbkpringhead = head; 3878 break; 3879 case BE_PRIORITY: 3880 priv->txbepringhead = head; 3881 break; 3882 case VI_PRIORITY: 3883 priv->txvipringhead = head; 3884 break; 3885 case VO_PRIORITY: 3886 priv->txvopringhead = head; 3887 break; 3888 case HI_PRIORITY: 3889 priv->txhpringhead = head; 3890 break; 3891 } 3892 3893 spin_unlock_irqrestore(&priv->tx_lock, flag); 3894} 3895 3896void rtl8180_tx_irq_wq(struct work_struct *work) 3897{ 3898 struct delayed_work *dwork = to_delayed_work(work); 3899 struct ieee80211_device * ieee = (struct ieee80211_device *) 3900 container_of(dwork, struct ieee80211_device, watch_dog_wq); 3901 struct net_device *dev = ieee->dev; 3902 3903 rtl8180_tx_isr(dev, MANAGE_PRIORITY, 0); 3904} 3905irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs) 3906{ 3907 struct net_device *dev = (struct net_device *) netdev; 3908 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 3909 unsigned long flags; 3910 u32 inta; 3911 3912 /* We should return IRQ_NONE, but for now let me keep this */ 3913 if (priv->irq_enabled == 0) 3914 return IRQ_HANDLED; 3915 3916 spin_lock_irqsave(&priv->irq_th_lock, flags); 3917 3918 /* ISR: 4bytes */ 3919 inta = read_nic_dword(dev, ISR); /* & priv->IntrMask; */ 3920 write_nic_dword(dev, ISR, inta); /* reset int situation */ 3921 3922 priv->stats.shints++; 3923 3924 if (!inta) { 3925 spin_unlock_irqrestore(&priv->irq_th_lock, flags); 3926 return IRQ_HANDLED; 3927 /* 3928 * most probably we can safely return IRQ_NONE, 3929 * but for now is better to avoid problems 3930 */ 3931 } 3932 3933 if (inta == 0xffff) { 3934 /* HW disappared */ 3935 spin_unlock_irqrestore(&priv->irq_th_lock, flags); 3936 return IRQ_HANDLED; 3937 } 3938 3939 priv->stats.ints++; 3940 3941 if (!netif_running(dev)) { 3942 spin_unlock_irqrestore(&priv->irq_th_lock, flags); 3943 return IRQ_HANDLED; 3944 } 3945 3946 if (inta & ISR_TimeOut) 3947 write_nic_dword(dev, TimerInt, 0); 3948 3949 if (inta & ISR_TBDOK) 3950 priv->stats.txbeacon++; 3951 3952 if (inta & ISR_TBDER) 3953 priv->stats.txbeaconerr++; 3954 3955 if (inta & IMR_TMGDOK) 3956 rtl8180_tx_isr(dev, MANAGE_PRIORITY, 0); 3957 3958 if (inta & ISR_THPDER) { 3959 priv->stats.txhperr++; 3960 rtl8180_tx_isr(dev, HI_PRIORITY, 1); 3961 priv->ieee80211->stats.tx_errors++; 3962 } 3963 3964 if (inta & ISR_THPDOK) { /* High priority tx ok */ 3965 priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ 3966 priv->stats.txhpokint++; 3967 rtl8180_tx_isr(dev, HI_PRIORITY, 0); 3968 } 3969 3970 if (inta & ISR_RER) 3971 priv->stats.rxerr++; 3972 3973 if (inta & ISR_TBKDER) { /* corresponding to BK_PRIORITY */ 3974 priv->stats.txbkperr++; 3975 priv->ieee80211->stats.tx_errors++; 3976 rtl8180_tx_isr(dev, BK_PRIORITY, 1); 3977 rtl8180_try_wake_queue(dev, BE_PRIORITY); 3978 } 3979 3980 if (inta & ISR_TBEDER) { /* corresponding to BE_PRIORITY */ 3981 priv->stats.txbeperr++; 3982 priv->ieee80211->stats.tx_errors++; 3983 rtl8180_tx_isr(dev, BE_PRIORITY, 1); 3984 rtl8180_try_wake_queue(dev, BE_PRIORITY); 3985 } 3986 if (inta & ISR_TNPDER) { /* corresponding to VO_PRIORITY */ 3987 priv->stats.txnperr++; 3988 priv->ieee80211->stats.tx_errors++; 3989 rtl8180_tx_isr(dev, NORM_PRIORITY, 1); 3990 rtl8180_try_wake_queue(dev, NORM_PRIORITY); 3991 } 3992 3993 if (inta & ISR_TLPDER) { /* corresponding to VI_PRIORITY */ 3994 priv->stats.txlperr++; 3995 priv->ieee80211->stats.tx_errors++; 3996 rtl8180_tx_isr(dev, LOW_PRIORITY, 1); 3997 rtl8180_try_wake_queue(dev, LOW_PRIORITY); 3998 } 3999 4000 if (inta & ISR_ROK) { 4001 priv->stats.rxint++; 4002 tasklet_schedule(&priv->irq_rx_tasklet); 4003 } 4004 4005 if (inta & ISR_RQoSOK) { 4006 priv->stats.rxint++; 4007 tasklet_schedule(&priv->irq_rx_tasklet); 4008 } 4009 4010 if (inta & ISR_BcnInt) 4011 rtl8180_prepare_beacon(dev); 4012 4013 if (inta & ISR_RDU) { 4014 DMESGW("No RX descriptor available"); 4015 priv->stats.rxrdu++; 4016 tasklet_schedule(&priv->irq_rx_tasklet); 4017 } 4018 4019 if (inta & ISR_RXFOVW) { 4020 priv->stats.rxoverflow++; 4021 tasklet_schedule(&priv->irq_rx_tasklet); 4022 } 4023 4024 if (inta & ISR_TXFOVW) 4025 priv->stats.txoverflow++; 4026 4027 if (inta & ISR_TNPDOK) { /* Normal priority tx ok */ 4028 priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ 4029 priv->stats.txnpokint++; 4030 rtl8180_tx_isr(dev, NORM_PRIORITY, 0); 4031 } 4032 4033 if (inta & ISR_TLPDOK) { /* Low priority tx ok */ 4034 priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ 4035 priv->stats.txlpokint++; 4036 rtl8180_tx_isr(dev, LOW_PRIORITY, 0); 4037 rtl8180_try_wake_queue(dev, LOW_PRIORITY); 4038 } 4039 4040 if (inta & ISR_TBKDOK) { /* corresponding to BK_PRIORITY */ 4041 priv->stats.txbkpokint++; 4042 priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ 4043 rtl8180_tx_isr(dev, BK_PRIORITY, 0); 4044 rtl8180_try_wake_queue(dev, BE_PRIORITY); 4045 } 4046 4047 if (inta & ISR_TBEDOK) { /* corresponding to BE_PRIORITY */ 4048 priv->stats.txbeperr++; 4049 priv->link_detect.NumTxOkInPeriod++; /* YJ,add,080828 */ 4050 rtl8180_tx_isr(dev, BE_PRIORITY, 0); 4051 rtl8180_try_wake_queue(dev, BE_PRIORITY); 4052 } 4053 force_pci_posting(dev); 4054 spin_unlock_irqrestore(&priv->irq_th_lock, flags); 4055 4056 return IRQ_HANDLED; 4057} 4058 4059void rtl8180_irq_rx_tasklet(struct r8180_priv *priv) 4060{ 4061 rtl8180_rx(priv->dev); 4062} 4063 4064void GPIOChangeRFWorkItemCallBack(struct work_struct *work) 4065{ 4066 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work); 4067 struct net_device *dev = ieee->dev; 4068 struct r8180_priv *priv = ieee80211_priv(dev); 4069 u8 btPSR; 4070 u8 btConfig0; 4071 RT_RF_POWER_STATE eRfPowerStateToSet; 4072 bool bActuallySet = false; 4073 4074 char *argv[3]; 4075 static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh"; 4076 static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL}; 4077 static int readf_count = 0; 4078 4079 if (readf_count % 10 == 0) 4080 priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state"); 4081 4082 readf_count = (readf_count+1)%0xffff; 4083 /* We should turn off LED before polling FF51[4]. */ 4084 4085 /* Turn off LED. */ 4086 btPSR = read_nic_byte(dev, PSR); 4087 write_nic_byte(dev, PSR, (btPSR & ~BIT3)); 4088 4089 /* It need to delay 4us suggested by Jong, 2008-01-16 */ 4090 udelay(4); 4091 4092 /* HW radio On/Off according to the value of FF51[4](config0) */ 4093 btConfig0 = btPSR = read_nic_byte(dev, CONFIG0); 4094 4095 eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff; 4096 4097 /* Turn LED back on when radio enabled */ 4098 if (eRfPowerStateToSet == eRfOn) 4099 write_nic_byte(dev, PSR, btPSR | BIT3); 4100 4101 if ((priv->ieee80211->bHwRadioOff == true) && 4102 (eRfPowerStateToSet == eRfOn)) { 4103 priv->ieee80211->bHwRadioOff = false; 4104 bActuallySet = true; 4105 } else if ((priv->ieee80211->bHwRadioOff == false) && 4106 (eRfPowerStateToSet == eRfOff)) { 4107 priv->ieee80211->bHwRadioOff = true; 4108 bActuallySet = true; 4109 } 4110 4111 if (bActuallySet) { 4112 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); 4113 4114 /* To update the UI status for Power status changed */ 4115 if (priv->ieee80211->bHwRadioOff == true) 4116 argv[1] = "RFOFF"; 4117 else 4118 argv[1] = "RFON"; 4119 argv[0] = RadioPowerPath; 4120 argv[2] = NULL; 4121 4122 call_usermodehelper(RadioPowerPath, argv, envp, 1); 4123 } 4124} 4125 4126static u8 read_acadapter_file(char *filename) 4127{ 4128 return 0; 4129} 4130 4131module_init(rtl8180_pci_module_init); 4132module_exit(rtl8180_pci_module_exit); 4133