1/* 2 * Copyright (c) 2007-2008 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16#include "../80211core/cprecomp.h" 17#include "hpani.h" 18#include "hpusb.h" 19#include "hpreg.h" 20#include "../80211core/ratectrl.h" 21 22extern void zfIdlCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen); 23 24extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy); 25u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val); 26u16_t zfFlushDelayWrite(zdev_t* dev); 27 28//#define zm_hp_priv(x) struct zsHpPriv* hpPriv=zgWlanDev.hpPrivate; 29 30void zfInitCmdQueue(zdev_t* dev) 31{ 32 struct zsHpPriv* hpPriv; 33 34 zmw_get_wlan_dev(dev); 35 hpPriv = (struct zsHpPriv*)(wd->hpPrivate); 36 37 zmw_declare_for_critical_section(); 38 39 zmw_enter_critical_section(dev); 40#ifdef ZM_XP_USB_MULTCMD 41 hpPriv->cmdTail = hpPriv->cmdHead = hpPriv->cmdSend = 0; 42#else 43 hpPriv->cmdTail = hpPriv->cmdHead = 0; 44#endif 45 hpPriv->cmdPending = 0; 46 hpPriv->cmd.delayWcmdCount = 0; 47 zmw_leave_critical_section(dev); 48} 49 50u16_t zfPutCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen, u16_t src, u8_t* buf) 51{ 52 u16_t i; 53 struct zsHpPriv* hpPriv; 54 55 zmw_get_wlan_dev(dev); 56 hpPriv=wd->hpPrivate; 57 58 /* Make sure command length < ZM_MAX_CMD_SIZE */ 59 zm_assert(cmdLen <= ZM_MAX_CMD_SIZE); 60 /* Make sure command queue not full */ 61 //zm_assert(((hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1)) != hpPriv->cmdHead); 62 if (((hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1)) == hpPriv->cmdHead ) { 63 zm_debug_msg0("CMD queue full!!"); 64 return 0; 65 } 66 67 hpPriv->cmdQ[hpPriv->cmdTail].cmdLen = cmdLen; 68 hpPriv->cmdQ[hpPriv->cmdTail].src = src; 69 hpPriv->cmdQ[hpPriv->cmdTail].buf = buf; 70 for (i=0; i<(cmdLen>>2); i++) 71 { 72 hpPriv->cmdQ[hpPriv->cmdTail].cmd[i] = cmd[i]; 73 } 74 75 hpPriv->cmdTail = (hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1); 76 77 return 0; 78} 79 80u16_t zfGetCmd(zdev_t* dev, u32_t* cmd, u16_t* cmdLen, u16_t* src, u8_t** buf) 81{ 82 u16_t i; 83 struct zsHpPriv* hpPriv; 84 85 zmw_get_wlan_dev(dev); 86 hpPriv=wd->hpPrivate; 87 88 if (hpPriv->cmdTail == hpPriv->cmdHead) 89 { 90 return 3; 91 } 92 93 *cmdLen = hpPriv->cmdQ[hpPriv->cmdHead].cmdLen; 94 *src = hpPriv->cmdQ[hpPriv->cmdHead].src; 95 *buf = hpPriv->cmdQ[hpPriv->cmdHead].buf; 96 for (i=0; i<((*cmdLen)>>2); i++) 97 { 98 cmd[i] = hpPriv->cmdQ[hpPriv->cmdHead].cmd[i]; 99 } 100 101 hpPriv->cmdHead = (hpPriv->cmdHead+1) & (ZM_CMD_QUEUE_SIZE-1); 102 103 return 0; 104} 105 106#ifdef ZM_XP_USB_MULTCMD 107void zfSendCmdEx(zdev_t* dev) 108{ 109 u32_t ncmd[ZM_MAX_CMD_SIZE/4]; 110 u16_t ncmdLen = 0; 111 u16_t cmdFlag = 0; 112 u16_t i; 113 struct zsHpPriv* hpPriv; 114 115 zmw_get_wlan_dev(dev); 116 hpPriv=wd->hpPrivate; 117 118 zmw_declare_for_critical_section(); 119 120 zmw_enter_critical_section(dev); 121 122 if (hpPriv->cmdPending == 0) 123 { 124 if (hpPriv->cmdTail != hpPriv->cmdSend) 125 { 126 cmdFlag = 1; 127 /* Get queueing command */ 128 ncmdLen= hpPriv->cmdQ[hpPriv->cmdSend].cmdLen; 129 for (i=0; i<(ncmdLen>>2); i++) 130 { 131 ncmd[i] = hpPriv->cmdQ[hpPriv->cmdSend].cmd[i]; 132 } 133 hpPriv->cmdSend = (hpPriv->cmdSend+1) & (ZM_CMD_QUEUE_SIZE-1); 134 135 hpPriv->cmdPending = 1; 136 } 137 } 138 139 zmw_leave_critical_section(dev); 140 141 if ((cmdFlag == 1)) 142 { 143 zfIdlCmd(dev, ncmd, ncmdLen); 144 } 145} 146 147void zfiSendCmdComp(zdev_t* dev) 148{ 149 struct zsHpPriv* hpPriv; 150 151 zmw_get_wlan_dev(dev); 152 hpPriv=wd->hpPrivate; 153 154 zmw_declare_for_critical_section(); 155 156 zmw_enter_critical_section(dev); 157 hpPriv->cmdPending = 0; 158 zmw_leave_critical_section(dev); 159 160 zfSendCmdEx(dev); 161} 162#endif 163 164u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen, u16_t src, u8_t* buf) 165{ 166 u16_t cmdFlag = 0; 167 u16_t ret; 168 struct zsHpPriv* hpPriv; 169 170 zmw_get_wlan_dev(dev); 171 hpPriv=wd->hpPrivate; 172 173 zmw_declare_for_critical_section(); 174 175 zm_msg2_mm(ZM_LV_1, "cmdLen=", cmdLen); 176 177 zmw_enter_critical_section(dev); 178 179#ifdef ZM_XP_USB_MULTCMD 180 ret = zfPutCmd(dev, cmd, cmdLen, src, buf); 181 zmw_leave_critical_section(dev); 182 183 if (ret != 0) 184 { 185 return 1; 186 } 187 188 zfSendCmdEx(dev); 189#else 190 if (hpPriv->cmdPending == 0) 191 { 192 hpPriv->cmdPending = 1; 193 cmdFlag = 1; 194 } 195 ret = zfPutCmd(dev, cmd, cmdLen, src, buf); 196 197 zmw_leave_critical_section(dev); 198 199 if (ret != 0) 200 { 201 return 1; 202 } 203 204 if (cmdFlag == 1) 205 { 206 zfIdlCmd(dev, cmd, cmdLen); 207 } 208#endif 209 return 0; 210} 211 212void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen) 213{ 214 u32_t cmd[ZM_MAX_CMD_SIZE/4]; 215 u16_t cmdLen; 216 u16_t src; 217 u8_t* buf; 218 u32_t ncmd[ZM_MAX_CMD_SIZE/4]; 219 u16_t ncmdLen = 0; 220 u16_t ret; 221 u16_t cmdFlag = 0; 222 u16_t i; 223 s32_t nf; 224 s32_t noisefloor[4]; 225 struct zsHpPriv* hpPriv; 226 227 zmw_get_wlan_dev(dev); 228 hpPriv=wd->hpPrivate; 229 230 231 zmw_declare_for_critical_section(); 232 233 zmw_enter_critical_section(dev); 234 235 ret = zfGetCmd(dev, cmd, &cmdLen, &src, &buf); 236 if (ret != 0) 237 { 238 zm_debug_msg0("Error IdlRsp because none cmd!!\n"); 239 #ifndef ZM_XP_USB_MULTCMD 240 zmw_leave_critical_section(dev); 241 return; 242 #endif 243 } 244#ifdef ZM_XP_USB_MULTCMD 245 zmw_leave_critical_section(dev); 246#else 247 if (hpPriv->cmdTail != hpPriv->cmdHead) 248 { 249 cmdFlag = 1; 250 /* Get queueing command */ 251 ncmdLen= hpPriv->cmdQ[hpPriv->cmdHead].cmdLen; 252 for (i=0; i<(ncmdLen>>2); i++) 253 { 254 ncmd[i] = hpPriv->cmdQ[hpPriv->cmdHead].cmd[i]; 255 } 256 } 257 else 258 { 259 hpPriv->cmdPending = 0; 260 } 261 262 zmw_leave_critical_section(dev); 263 264 if (cmdFlag == 1) 265 { 266 zfIdlCmd(dev, ncmd, ncmdLen); 267 } 268#endif 269 if (src == ZM_OID_READ) 270 { 271 ZM_PERFORMANCE_REG(dev, 0x11772c, rsp[1]); 272 zfwDbgReadRegDone(dev, cmd[1], rsp[1]); 273 } 274 else if (src == ZM_OID_FLASH_CHKSUM) 275 { 276 zfwDbgGetFlashChkSumDone(dev, rsp+1); 277 } 278 else if (src == ZM_OID_FLASH_READ) 279 { 280 u32_t datalen; 281 282 datalen = (rsp[0] & 255); 283 284 zfwDbgReadFlashDone(dev, cmd[1], rsp+1, datalen); 285 } 286 else if (src == ZM_OID_FLASH_PROGRAM) 287 { 288 /* Non do */ 289 } 290 else if (src == ZM_OID_WRITE) 291 { 292 zfwDbgWriteRegDone(dev, cmd[1], cmd[2]); 293 } 294 else if (src == ZM_OID_TALLY) 295 { 296 zfCollectHWTally(dev, rsp, 0); 297 } 298 else if (src == ZM_OID_TALLY_APD) 299 { 300 zfCollectHWTally(dev, rsp, 1); 301 zfwDbgReadTallyDone(dev); 302#ifdef ZM_ENABLE_BA_RATECTRL 303 zfRateCtrlAggrSta(dev); 304#endif 305 } 306 else if (src == ZM_OID_DKTX_STATUS) 307 { 308 zm_debug_msg0("src = zm_OID_DKTX_STATUS"); 309 zfwDbgQueryHwTxBusyDone(dev, rsp[1]); 310 } 311 else if (src == ZM_CMD_SET_FREQUENCY) 312 { 313 314//#ifdef ZM_OTUS_ENABLE_RETRY_FREQ_CHANGE 315 316/* ret: Bit0: AGC calibration 0=>finish 1=>unfinish */ 317/* Bit1: Noise calibration 0=>finish 1=>unfinish */ 318/* Bit2: Noise calibration finish, but NF value unexcepted => 1 */ 319 if ( (rsp[1] & 0x1) || (rsp[1] & 0x4) ) 320 { 321 zm_debug_msg1("Set Frequency fail : ret = ", rsp[1]); 322 323 /* 1. AGC Calibration fail */ 324 /* 2. Noise Calibration finish but error NoiseFloor value */ 325 /* and not in sitesurvey, try more twice */ 326 if ( hpPriv->isSiteSurvey == 2 ) 327 { 328 if ( hpPriv->recordFreqRetryCounter < 2 ) 329 { 330 /* cold reset */ 331 zfHpSetFrequencyEx(dev, hpPriv->latestFrequency, 332 hpPriv->latestBw40, 333 hpPriv->latestExtOffset, 334 2); 335 hpPriv->recordFreqRetryCounter++; 336 zm_debug_msg1("Retry to issue the frequency change command(cold reset) counter = ", hpPriv->recordFreqRetryCounter); 337 } 338 else 339 { 340 /* Fail : we would not accept this result! */ 341 zm_debug_msg0("\n\n\n\n Fail twice cold reset \n\n\n\n"); 342 hpPriv->coldResetNeedFreq = 0; 343 hpPriv->recordFreqRetryCounter = 0; 344 zfCoreSetFrequencyComplete(dev); 345 } 346 } 347 else 348 { 349 /* in sitesurvey, coldreset in next channel */ 350 hpPriv->coldResetNeedFreq = 1; 351 hpPriv->recordFreqRetryCounter = 0; 352 zfCoreSetFrequencyComplete(dev); 353 } 354 } 355 else if (rsp[1] & 0x2) 356 { 357 zm_debug_msg1("Set Frequency fail 2 : ret = ", rsp[1]); 358 359 /* Noise Calibration un-finish */ 360 /* and not in sitesurvey, try more once */ 361 if ( hpPriv->isSiteSurvey == 2 ) 362 { 363 if ( hpPriv->recordFreqRetryCounter < 1 ) 364 { 365 /* cold reset */ 366 zfHpSetFrequencyEx(dev, hpPriv->latestFrequency, 367 hpPriv->latestBw40, 368 hpPriv->latestExtOffset, 369 2); 370 hpPriv->recordFreqRetryCounter++; 371 zm_debug_msg1("2 Retry to issue the frequency change command(cold reset) counter = ", hpPriv->recordFreqRetryCounter); 372 } 373 else 374 { 375 /* Fail : we would not accept this result! */ 376 zm_debug_msg0("\n\n\n\n 2 Fail twice cold reset \n\n\n\n"); 377 hpPriv->coldResetNeedFreq = 0; 378 hpPriv->recordFreqRetryCounter = 0; 379 zfCoreSetFrequencyComplete(dev); 380 } 381 } 382 else 383 { 384 /* in sitesurvey, skip this frequency */ 385 hpPriv->coldResetNeedFreq = 0; 386 hpPriv->recordFreqRetryCounter = 0; 387 zfCoreSetFrequencyComplete(dev); 388 } 389 } 390 //else if (rsp[1] & 0x4) 391 //{ 392 // zm_debug_msg1("Set Frequency fail 3 : ret = ", rsp[1]); 393 // hpPriv->coldResetNeedFreq = 0; 394 // hpPriv->recordFreqRetryCounter = 0; 395 // zfCoreSetFrequencyComplete(dev); 396 //} 397 else 398 { 399 //hpPriv->freqRetryCounter = 0; 400 zm_debug_msg2(" return complete, ret = ", rsp[1]); 401 402 /* set bb_heavy_clip_enable */ 403 if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip && 404 hpPriv->doBBHeavyClip) 405 { 406 u32_t setValue = 0x200; 407 408 setValue |= hpPriv->setValueHeavyClip; 409 410 //zm_dbg(("Do heavy clip setValue = %d\n", setValue)); 411 412 zfDelayWriteInternalReg(dev, 0x99e0+0x1bc000, setValue); 413 zfFlushDelayWrite(dev); 414 } 415 416 hpPriv->coldResetNeedFreq = 0; 417 hpPriv->recordFreqRetryCounter = 0; 418 zfCoreSetFrequencyComplete(dev); 419 } 420 421 // Read the Noise Floor value ! 422 nf = ((rsp[2]>>19) & 0x1ff); 423 if ((nf & 0x100) != 0x0) 424 { 425 noisefloor[0] = 0 - ((nf ^ 0x1ff) + 1); 426 } 427 else 428 { 429 noisefloor[0] = nf; 430 } 431 432 //zm_debug_msg1("Noise Floor[1] = ", noisefloor[0]); 433 434 nf = ((rsp[3]>>19) & 0x1ff); 435 if ((nf & 0x100) != 0x0) 436 { 437 noisefloor[1] = 0 - ((nf ^ 0x1ff) + 1); 438 } 439 else 440 { 441 noisefloor[1] = nf; 442 } 443 444 //zm_debug_msg1("Noise Floor[2] = ", noisefloor[1]); 445 446 nf = ((rsp[5]>>23) & 0x1ff); 447 if ((nf & 0x100) != 0x0) 448 { 449 noisefloor[2] = 0 - ((nf ^ 0x1ff) + 1); 450 } 451 else 452 { 453 noisefloor[2] = nf; 454 } 455 456 //zm_debug_msg1("Noise Floor ext[1] = ", noisefloor[2]); 457 458 nf = ((rsp[6]>>23) & 0x1ff); 459 if ((nf & 0x100) != 0x0) 460 { 461 noisefloor[3] = 0 - ((nf ^ 0x1ff) + 1); 462 } 463 else 464 { 465 noisefloor[3] = nf; 466 } 467 468 //zm_debug_msg1("Noise Floor ext[2] = ", noisefloor[3]); 469 470 //zm_debug_msg1("Is Site Survey = ", hpPriv->isSiteSurvey); 471 } 472 else if (src == ZM_CMD_SET_KEY) 473 { 474 zfCoreSetKeyComplete(dev); 475 } 476 else if (src == ZM_CWM_READ) 477 { 478 zm_msg2_mm(ZM_LV_0, "CWM rsp[1]=", rsp[1]); 479 zm_msg2_mm(ZM_LV_0, "CWM rsp[2]=", rsp[2]); 480 zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(rsp[1], rsp[2])); 481 } 482 else if (src == ZM_MAC_READ) 483 { 484 /* rsp[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET; */ 485 /* rsp[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4; */ 486 /* rsp[3] = ZM_SEEPROM_REGDOMAIN_OFFSET; */ 487 /* rsp[4] = ZM_SEEPROM_VERISON_OFFSET; */ 488 /* rsp[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET; */ 489 /* rsp[6] = ZM_SEEPROM_HW_HEAVY_CLIP; */ 490 491 u8_t addr[6], CCS, WWR; 492 u16_t CountryDomainCode; 493 494 /* BB heavy clip */ 495 //hpPriv->eepromHeavyClipFlag = (u8_t)((rsp[6]>>24) & 0xff); // force enable 8107 496 //zm_msg2_mm(ZM_LV_0, "eepromHeavyClipFlag", hpPriv->eepromHeavyClipFlag); 497 zm_msg2_mm(ZM_LV_0, "MAC rsp[1]=", rsp[1]); 498 zm_msg2_mm(ZM_LV_0, "MAC rsp[2]=", rsp[2]); 499 500 addr[0] = (u8_t)(rsp[1] & 0xff); 501 addr[1] = (u8_t)((rsp[1]>>8) & 0xff); 502 addr[2] = (u8_t)((rsp[1]>>16) & 0xff); 503 addr[3] = (u8_t)((rsp[1]>>24) & 0xff); 504 addr[4] = (u8_t)(rsp[2] & 0xff); 505 addr[5] = (u8_t)((rsp[2]>>8) & 0xff); 506/*#ifdef ZM_FB50 507 addr[0] = (u8_t)(0 & 0xff); 508 addr[1] = (u8_t)(3 & 0xff); 509 addr[2] = (u8_t)(127 & 0xff); 510 addr[3] = (u8_t)(0 & 0xff); 511 addr[4] = (u8_t)(9 & 0xff); 512 addr[5] = (u8_t)(11 & 0xff); 513#endif*/ 514 515 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L, 516 ((((u32_t)addr[3])<<24) | (((u32_t)addr[2])<<16) | (((u32_t)addr[1])<<8) | addr[0])); 517 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, 518 ((((u32_t)addr[5])<<8) | addr[4])); 519 zfFlushDelayWrite(dev); 520 521 wd->ledStruct.ledMode[0] = (u16_t)(rsp[5]&0xffff); 522 wd->ledStruct.ledMode[1] = (u16_t)(rsp[5]>>16); 523 zm_msg2_mm(ZM_LV_0, "ledMode[0]=", wd->ledStruct.ledMode[0]); 524 zm_msg2_mm(ZM_LV_0, "ledMode[1]=", wd->ledStruct.ledMode[1]); 525 526 /* Regulatory Related Setting */ 527 zm_msg2_mm(ZM_LV_0, "RegDomain rsp=", rsp[3]); 528 zm_msg2_mm(ZM_LV_0, "OpFlags+EepMisc=", rsp[4]); 529 hpPriv->OpFlags = (u8_t)((rsp[4]>>16) & 0xff); 530 if ((rsp[2] >> 24) == 0x1) //Tx mask == 0x1 531 { 532 zm_msg0_mm(ZM_LV_0, "OTUS 1x2"); 533 hpPriv->halCapability |= ZM_HP_CAP_11N_ONE_TX_STREAM; 534 } 535 else 536 { 537 zm_msg0_mm(ZM_LV_0, "OTUS 2x2"); 538 } 539 if (hpPriv->OpFlags & 0x1) 540 { 541 hpPriv->halCapability |= ZM_HP_CAP_5G; 542 } 543 if (hpPriv->OpFlags & 0x2) 544 { 545 hpPriv->halCapability |= ZM_HP_CAP_2G; 546 } 547 548 549 CCS = (u8_t)((rsp[3] & 0x8000) >> 15); 550 WWR = (u8_t)((rsp[3] & 0x4000) >> 14); 551 CountryDomainCode = (u16_t)(rsp[3] & 0x3FFF); 552 553 if (rsp[3] != 0xffffffff) 554 { 555 if (CCS) 556 { 557 //zm_debug_msg0("CWY - Get Regulation Table from Country Code"); 558 zfHpGetRegulationTablefromCountry(dev, CountryDomainCode); 559 } 560 else 561 { 562 //zm_debug_msg0("CWY - Get Regulation Table from Reg Domain"); 563 zfHpGetRegulationTablefromRegionCode(dev, CountryDomainCode); 564 } 565 if (WWR) 566 { 567 //zm_debug_msg0("CWY - Enable 802.11d"); 568 /* below line shall be unmarked after A band is ready */ 569 //zfiWlanSetDot11DMode(dev, 1); 570 } 571 } 572 else 573 { 574 zfHpGetRegulationTablefromRegionCode(dev, NO_ENUMRD); 575 } 576 577 zfCoreMacAddressNotify(dev, addr); 578 579 } 580 else if (src == ZM_EEPROM_READ) 581 { 582 for (i=0; i<ZM_HAL_MAX_EEPROM_PRQ; i++) 583 { 584 if (hpPriv->eepromImageIndex < 1024) 585 { 586 hpPriv->eepromImage[hpPriv->eepromImageIndex++] = rsp[i+1]; 587 } 588 } 589 590 if (hpPriv->eepromImageIndex == (ZM_HAL_MAX_EEPROM_REQ*ZM_HAL_MAX_EEPROM_PRQ)) 591 { 592 zm_msg2_mm(ZM_LV_0, "MAC [1]=", hpPriv->eepromImage[0x20c/4]); 593 zm_msg2_mm(ZM_LV_0, "MAC [2]=", hpPriv->eepromImage[0x210/4]); 594 zfCoreHalInitComplete(dev); 595 } 596 else 597 { 598 hpPriv->eepromImageRdReq++; 599 zfHpLoadEEPROMFromFW(dev); 600 } 601 } 602 else if (src == ZM_EEPROM_WRITE) 603 { 604 zfwDbgWriteEepromDone(dev, cmd[1], cmd[2]); 605 } 606 else if (src == ZM_ANI_READ) 607 { 608 u32_t cycleTime, ctlClear; 609 610 zm_msg2_mm(ZM_LV_0, "ANI rsp[1]=", rsp[1]); 611 zm_msg2_mm(ZM_LV_0, "ANI rsp[2]=", rsp[2]); 612 zm_msg2_mm(ZM_LV_0, "ANI rsp[3]=", rsp[3]); 613 zm_msg2_mm(ZM_LV_0, "ANI rsp[4]=", rsp[4]); 614 615 hpPriv->ctlBusy += rsp[1]; 616 hpPriv->extBusy += rsp[2]; 617 618 cycleTime = 100000; //100 miniseconds 619 620 if (cycleTime > rsp[1]) 621 { 622 ctlClear = (cycleTime - rsp[1]) / 100; 623 } 624 else 625 { 626 ctlClear = 0; 627 } 628 if (wd->aniEnable) 629 zfHpAniArPoll(dev, ctlClear, rsp[3], rsp[4]); 630 } 631 else if (src == ZM_CMD_ECHO) 632 { 633 if ( ((struct zsHpPriv*)wd->hpPrivate)->halReInit ) 634 { 635 zfCoreHalInitComplete(dev); 636 ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 0; 637 } 638 else 639 { 640 zfHpLoadEEPROMFromFW(dev); 641 } 642 } 643 else if (src == ZM_OID_FW_DL_INIT) 644 { 645 zfwDbgDownloadFwInitDone(dev); 646 } 647 return; 648} 649 650 651/************************************************************************/ 652/* */ 653/* FUNCTION DESCRIPTION zfWriteRegInternalReg */ 654/* Write on chip internal register immediately. */ 655/* */ 656/* INPUTS */ 657/* dev : device pointer */ 658/* addr : register address */ 659/* val : value */ 660/* */ 661/* OUTPUTS */ 662/* 0 : success */ 663/* other : fail */ 664/* */ 665/* AUTHOR */ 666/* Stephen Chen ZyDAS Technology Corporation 2005.11 */ 667/* */ 668/************************************************************************/ 669u32_t zfWriteRegInternalReg(zdev_t* dev, u32_t addr, u32_t val) 670{ 671 u32_t cmd[3]; 672 u16_t ret; 673 674 cmd[0] = 0x00000108; 675 cmd[1] = addr; 676 cmd[2] = val; 677 678 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, NULL); 679 return ret; 680} 681 682 683/************************************************************************/ 684/* */ 685/* FUNCTION DESCRIPTION zfDelayWriteInternalReg */ 686/* Write on chip internal register, write operation may be */ 687/* postponed to form a multiple write command. */ 688/* */ 689/* INPUTS */ 690/* dev : device pointer */ 691/* addr : register address */ 692/* val : value */ 693/* */ 694/* OUTPUTS */ 695/* 0 : command been postponed */ 696/* 1 : commands been executed */ 697/* */ 698/* AUTHOR */ 699/* Stephen Chen ZyDAS Technology Corporation 2005.11 */ 700/* */ 701/************************************************************************/ 702u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val) 703{ 704 u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; 705 u16_t i; 706 u16_t ret; 707 struct zsHpPriv* hpPriv; 708 709 zmw_get_wlan_dev(dev); 710 hpPriv=wd->hpPrivate; 711 712 zmw_declare_for_critical_section(); 713 714 /* enter critical section */ 715 zmw_enter_critical_section(dev); 716 717 /* Store command to global buffer */ 718 hpPriv->cmd.delayWcmdAddr[hpPriv->cmd.delayWcmdCount] = addr; 719 hpPriv->cmd.delayWcmdVal[hpPriv->cmd.delayWcmdCount++] = val; 720 721 /* If pending command reach size limit */ 722 if ((hpPriv->cmd.delayWcmdCount) >= ((ZM_MAX_CMD_SIZE - 4) >> 3)) 723 { 724 cmd[0] = 0x00000100 + (hpPriv->cmd.delayWcmdCount<<3); 725 726 /* copy command to cmd buffer */ 727 for (i=0; i<hpPriv->cmd.delayWcmdCount; i++) 728 { 729 cmd[1+(i<<1)] = hpPriv->cmd.delayWcmdAddr[i]; 730 cmd[2+(i<<1)] = hpPriv->cmd.delayWcmdVal[i]; 731 } 732 /* reset pending command */ 733 hpPriv->cmd.delayWcmdCount = 0; 734 735 /* leave critical section */ 736 zmw_leave_critical_section(dev); 737 738 /* issue write command */ 739 ret = zfIssueCmd(dev, cmd, 4+(i<<3), ZM_OID_INTERNAL_WRITE, NULL); 740 741 return 1; 742 } 743 else 744 { 745 /* leave critical section */ 746 zmw_leave_critical_section(dev); 747 748 return 0; 749 } 750} 751 752 753/************************************************************************/ 754/* */ 755/* FUNCTION DESCRIPTION zfFlushDelayWrite */ 756/* Flush pending write command. */ 757/* */ 758/* INPUTS */ 759/* dev : device pointer */ 760/* */ 761/* OUTPUTS */ 762/* 0 : no pending command */ 763/* 1 : commands been executed */ 764/* */ 765/* AUTHOR */ 766/* Stephen Chen ZyDAS Technology Corporation 2005.11 */ 767/* */ 768/************************************************************************/ 769u16_t zfFlushDelayWrite(zdev_t* dev) 770{ 771 u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; 772 u16_t i; 773 u16_t ret; 774 struct zsHpPriv* hpPriv; 775 776 zmw_get_wlan_dev(dev); 777 hpPriv=wd->hpPrivate; 778 779 zmw_declare_for_critical_section(); 780 781 /* enter critical section */ 782 zmw_enter_critical_section(dev); 783 784 /* If there is pending command */ 785 if (hpPriv->cmd.delayWcmdCount > 0) 786 { 787 cmd[0] = 0x00000100 + (hpPriv->cmd.delayWcmdCount<<3); 788 789 /* copy command to cmd buffer */ 790 for (i=0; i<hpPriv->cmd.delayWcmdCount; i++) 791 { 792 cmd[1+(i<<1)] = hpPriv->cmd.delayWcmdAddr[i]; 793 cmd[2+(i<<1)] = hpPriv->cmd.delayWcmdVal[i]; 794 } 795 /* reset pending command */ 796 hpPriv->cmd.delayWcmdCount = 0; 797 798 /* leave critical section */ 799 zmw_leave_critical_section(dev); 800 801 /* issue write command */ 802 ret = zfIssueCmd(dev, cmd, 4+(i<<3), ZM_OID_INTERNAL_WRITE, NULL); 803 804 return 1; 805 } 806 else 807 { 808 /* leave critical section */ 809 zmw_leave_critical_section(dev); 810 811 return 0; 812 } 813} 814 815 816u32_t zfiDbgDelayWriteReg(zdev_t* dev, u32_t addr, u32_t val) 817{ 818 zfDelayWriteInternalReg(dev, addr, val); 819 return 0; 820} 821 822u32_t zfiDbgFlushDelayWrite(zdev_t* dev) 823{ 824 zfFlushDelayWrite(dev); 825 return 0; 826} 827 828/************************************************************************/ 829/* */ 830/* FUNCTION DESCRIPTION zfiDbgWriteReg */ 831/* Write register. */ 832/* */ 833/* INPUTS */ 834/* dev : device pointer */ 835/* addr : register address */ 836/* val : value */ 837/* */ 838/* OUTPUTS */ 839/* 0 : success */ 840/* other : fail */ 841/* */ 842/* AUTHOR */ 843/* Stephen Chen ZyDAS Technology Corporation 2005.10 */ 844/* */ 845/************************************************************************/ 846u32_t zfiDbgWriteReg(zdev_t* dev, u32_t addr, u32_t val) 847{ 848 u32_t cmd[3]; 849 u16_t ret; 850 851 cmd[0] = 0x00000108; 852 cmd[1] = addr; 853 cmd[2] = val; 854 855 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_WRITE, 0); 856 return ret; 857} 858/************************************************************************/ 859/* */ 860/* FUNCTION DESCRIPTION zfiDbgWriteFlash */ 861/* Write flash. */ 862/* */ 863/* INPUTS */ 864/* dev : device pointer */ 865/* addr : register address */ 866/* val : value */ 867/* */ 868/* OUTPUTS */ 869/* 0 : success */ 870/* other : fail */ 871/* */ 872/* AUTHOR */ 873/* Yjsung ZyDAS Technology Corporation 2007.02 */ 874/* */ 875/************************************************************************/ 876u32_t zfiDbgWriteFlash(zdev_t* dev, u32_t addr, u32_t val) 877{ 878 u32_t cmd[3]; 879 u16_t ret; 880 881 //cmd[0] = 0x0000B008; 882 /* len[0] : type[0xB0] : seq[?] */ 883 cmd[0] = 8 | (ZM_CMD_WFLASH << 8); 884 cmd[1] = addr; 885 cmd[2] = val; 886 887 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_WRITE, 0); 888 return ret; 889} 890 891/************************************************************************/ 892/* */ 893/* FUNCTION DESCRIPTION zfiDbgWriteEeprom */ 894/* Write EEPROM. */ 895/* */ 896/* INPUTS */ 897/* dev : device pointer */ 898/* addr : register address */ 899/* val : value */ 900/* */ 901/* OUTPUTS */ 902/* 0 : success */ 903/* other : fail */ 904/* */ 905/* AUTHOR */ 906/* Paul ZyDAS Technology Corporation 2007.06 */ 907/* */ 908/************************************************************************/ 909u32_t zfiDbgWriteEeprom(zdev_t* dev, u32_t addr, u32_t val) 910{ 911 u32_t cmd[3]; 912 u16_t ret; 913 914 //cmd[0] = 0x0000B008; 915 /* len[0] : type[0xB0] : seq[?] */ 916 cmd[0] = 8 | (ZM_CMD_WREEPROM << 8); 917 cmd[1] = addr; 918 cmd[2] = val; 919 920 ret = zfIssueCmd(dev, cmd, 12, ZM_EEPROM_WRITE, 0); 921 return ret; 922} 923 924/************************************************************************/ 925/* */ 926/* FUNCTION DESCRIPTION zfiDbgBlockWriteEeprom */ 927/* Block Write Eeprom. */ 928/* */ 929/* p.s: now,it will write 16 bytes register data per block (N=4) */ 930/* */ 931/* INPUTS */ 932/* dev : device pointer */ 933/* addr : register address */ 934/* buf : input data buffer pointer */ 935/* */ 936/* OUTPUTS */ 937/* 0 : success */ 938/* other : fail */ 939/* */ 940/* AUTHOR */ 941/* Paul ZyDAS Technology Corporation 2007.06 */ 942/* */ 943/************************************************************************/ 944//#define N buflen/4 945//#define SIZE (2*N+1) 946 947u32_t zfiDbgBlockWriteEeprom(zdev_t* dev, u32_t addr, u32_t* buf) 948{ 949 u32_t cmd[9]; //2N+1 950 u16_t ret,i; 951 952 //cmd[0] = 0x0000B008; 953 /* len[0] : type[0xB0] : seq[?] */ 954 955 //cmd[0] = (8*N) | (ZM_CMD_WFLASH << 8); 956 cmd[0] = 32 | (ZM_CMD_WREEPROM << 8); //8N 957 958 for (i=0; i<4; i++) // i<N 959 { 960 cmd[(2*i)+1] = addr+(4*i); 961 cmd[(2*i)+2] = *(buf+i); 962 } 963 964 ret = zfIssueCmd(dev, cmd, 36, ZM_EEPROM_WRITE, 0); //8N+4 965 966 // added for EEPROMUpdate, wait a moment for prevent cmd queue full! 967 //zfwSleep(dev, 1); 968 969 return ret; 970} 971 972 973/* write EEPROM with wrlen : wrlen must be 4*n */ 974/* command format : cmd_info(4) + addr(4) + eeprom(wrlen) */ 975u32_t zfiDbgBlockWriteEeprom_v2(zdev_t* dev, u32_t addr, u32_t* buf, u32_t wrlen) 976{ 977 u32_t cmd[16]; 978 u16_t ret,i; 979 980 /* len[0] : type[0xB0] : seq[?] */ 981 /* len = addr(4) + eeprom_block(wrlen) */ 982 cmd[0] = (wrlen+4) | (ZM_CMD_MEM_WREEPROM << 8); 983 cmd[1] = addr; 984 985 for (i=0; i<(wrlen/4); i++) // i<wrlen/4 986 { 987 cmd[2+i] = *(buf+i); 988 } 989 /* cmd_info(4) + addr(4) + eeprom(wrlen) */ 990 ret = zfIssueCmd(dev, cmd, (u16_t)(wrlen+8), ZM_EEPROM_WRITE, 0); 991 992 return ret; 993} 994 995/************************************************************************/ 996/* */ 997/* FUNCTION DESCRIPTION zfDbgOpenEeprom */ 998/* Open EEPROM. */ 999/* */ 1000/* INPUTS */ 1001/* dev : device pointer */ 1002/* */ 1003/* OUTPUTS */ 1004/* */ 1005/* AUTHOR */ 1006/* Paul ZyDAS Technology Corporation 2007.06 */ 1007/* */ 1008/************************************************************************/ 1009void zfDbgOpenEeprom(zdev_t* dev) 1010{ 1011 // unlock EEPROM 1012 zfDelayWriteInternalReg(dev, 0x1D1400, 0x12345678); 1013 zfDelayWriteInternalReg(dev, 0x1D1404, 0x55aa00ff); 1014 zfDelayWriteInternalReg(dev, 0x1D1408, 0x13579ace); 1015 zfDelayWriteInternalReg(dev, 0x1D1414, 0x0); 1016 zfFlushDelayWrite(dev); 1017} 1018 1019/************************************************************************/ 1020/* */ 1021/* FUNCTION DESCRIPTION zfDbgCloseEeprom */ 1022/* Close EEPROM. */ 1023/* */ 1024/* INPUTS */ 1025/* dev : device pointer */ 1026/* */ 1027/* OUTPUTS */ 1028/* */ 1029/* AUTHOR */ 1030/* Paul ZyDAS Technology Corporation 2007.05 */ 1031/* */ 1032/************************************************************************/ 1033void zfDbgCloseEeprom(zdev_t* dev) 1034{ 1035 // lock EEPROM 1036 zfDelayWriteInternalReg(dev, 0x1D1400, 0x87654321); 1037 //zfDelayWriteInternalReg(dev, 0x1D1404, 0xffffffff); 1038 //zfDelayWriteInternalReg(dev, 0x1D1408, 0xffffffff); 1039 //zfDelayWriteInternalReg(dev, 0x1D1414, 0x100); 1040 zfFlushDelayWrite(dev); 1041} 1042/************************************************************************/ 1043/* */ 1044/* FUNCTION DESCRIPTION zfiDbgReadReg */ 1045/* Read register. */ 1046/* */ 1047/* INPUTS */ 1048/* dev : device pointer */ 1049/* addr : register address */ 1050/* */ 1051/* OUTPUTS */ 1052/* 0 : success */ 1053/* other : fail */ 1054/* */ 1055/* AUTHOR */ 1056/* Stephen Chen ZyDAS Technology Corporation 2005.10 */ 1057/* */ 1058/************************************************************************/ 1059u32_t zfiDbgReadReg(zdev_t* dev, u32_t addr) 1060{ 1061 u32_t cmd[2]; 1062 u16_t ret; 1063 1064 cmd[0] = 0x00000004; 1065 cmd[1] = addr; 1066 1067 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_READ, 0); 1068 return ret; 1069} 1070 1071 1072/************************************************************************/ 1073/* */ 1074/* FUNCTION DESCRIPTION zfiDbgReadTally */ 1075/* Read register. */ 1076/* */ 1077/* INPUTS */ 1078/* dev : device pointer */ 1079/* */ 1080/* OUTPUTS */ 1081/* 0 : success */ 1082/* other : fail */ 1083/* */ 1084/* AUTHOR */ 1085/* Stephen Chen ZyDAS Technology Corporation 2005.10 */ 1086/* */ 1087/************************************************************************/ 1088u32_t zfiDbgReadTally(zdev_t* dev) 1089{ 1090 u32_t cmd[1]; 1091 u16_t ret; 1092 zmw_get_wlan_dev(dev); 1093 1094 if ( ((struct zsHpPriv*)wd->hpPrivate)->halReInit ) 1095 { 1096 return 1; 1097 } 1098 1099 /* len[0] : type[0x81] : seq[?] */ 1100 cmd[0] = 0 | (ZM_CMD_TALLY << 8); 1101 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_TALLY, 0); 1102 1103 /* len[0] : type[0x82] : seq[?] */ 1104 cmd[0] = 0 | (ZM_CMD_TALLY_APD << 8); 1105 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_TALLY_APD, 0); 1106 1107 return ret; 1108} 1109 1110 1111u32_t zfiDbgSetIFSynthesizer(zdev_t* dev, u32_t value) 1112{ 1113 u32_t cmd[2]; 1114 u16_t ret; 1115 1116 /* len[4] : type[0x32] : seq[?] */ 1117 cmd[0] = 0x4 | (ZM_OID_SYNTH << 8); 1118 cmd[1] = value; 1119 1120 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_SYNTH, 0); 1121 return ret; 1122} 1123 1124u32_t zfiDbgQueryHwTxBusy(zdev_t* dev) 1125{ 1126 u32_t cmd[1]; 1127 u16_t ret; 1128 1129 /* len[4] : type[0xC0] : seq[?] */ 1130 cmd[0] = 0 | (ZM_CMD_DKTX_STATUS << 8); 1131 1132 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_DKTX_STATUS, 0); 1133 return ret; 1134} 1135 1136//Paul++ 1137 1138 1139/************************************************************************/ 1140/* */ 1141/* FUNCTION DESCRIPTION zfiDbgChipEraseFlash */ 1142/* Chip Erase Flash. */ 1143/* */ 1144/* INPUTS */ 1145/* dev : device pointer */ 1146/* */ 1147/* OUTPUTS */ 1148/* 0 : success */ 1149/* other : fail */ 1150/* */ 1151/* AUTHOR */ 1152/* Paul Atheros Technology Corporation 2007.09 */ 1153/* */ 1154/************************************************************************/ 1155u16_t zfiDbgChipEraseFlash(zdev_t *dev) 1156{ 1157 u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; 1158 u16_t ret; 1159 1160 cmd[0] = 0x00000000 | (ZM_CMD_FLASH_ERASE << 8); 1161 1162 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL); 1163 return ret; 1164} 1165/************************************************************************/ 1166/* */ 1167/* FUNCTION DESCRIPTION zfiDbgGetFlashCheckSum */ 1168/* Get FlashCheckSum. */ 1169/* */ 1170/* INPUTS */ 1171/* dev : device pointer */ 1172/* addr : Start address of getchksum */ 1173/* len : total lenth of calculate getchksum */ 1174/* */ 1175/* OUTPUTS */ 1176/* 0 : success */ 1177/* other : fail */ 1178/* */ 1179/* AUTHOR */ 1180/* Paul Atheros Technology Corporation 2007.08 */ 1181/* */ 1182/************************************************************************/ 1183u32_t zfiDbgGetFlashCheckSum(zdev_t *dev, u32_t addr, u32_t len) 1184{ 1185 u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; 1186 u32_t ret; 1187 1188 cmd[0] = 0x00000008 | (ZM_CMD_FLASH_CHKSUM << 8); 1189 cmd[1] = addr; 1190 cmd[2] = len; 1191 1192 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_FLASH_CHKSUM, NULL); 1193 1194 return ret; 1195} 1196 1197/************************************************************************/ 1198/* */ 1199/* FUNCTION DESCRIPTION zfiDbgReadFlash */ 1200/* Read Flash. */ 1201/* */ 1202/* INPUTS */ 1203/* dev : device pointer */ 1204/* addr : Start address of read flash */ 1205/* len : total lenth of read flash data */ 1206/* */ 1207/* OUTPUTS */ 1208/* 0 : success */ 1209/* other : fail */ 1210/* */ 1211/* AUTHOR */ 1212/* Paul Atheros Technology Corporation 2007.09 */ 1213/* */ 1214/************************************************************************/ 1215u32_t zfiDbgReadFlash(zdev_t *dev, u32_t addr, u32_t len) 1216{ 1217 u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; 1218 u32_t ret; 1219 1220 cmd[0] = len | (ZM_CMD_FLASH_READ << 8); 1221 cmd[1] = addr; 1222 1223 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_FLASH_READ, NULL); 1224 return ret; 1225} 1226 1227/************************************************************************/ 1228/* */ 1229/* FUNCTION DESCRIPTION zfiDownloadFwSet */ 1230/* Before Download FW, */ 1231/* Command FW to Software reset and close watch dog control. */ 1232/* */ 1233/* */ 1234/* INPUTS */ 1235/* dev : device pointer */ 1236/* */ 1237/* OUTPUTS */ 1238/* 0 : success */ 1239/* other : fail */ 1240/* */ 1241/* AUTHOR */ 1242/* Paul Atheros Technology Corporation 2007.09 */ 1243/* */ 1244/************************************************************************/ 1245u32_t zfiDownloadFwSet(zdev_t *dev) 1246{ 1247//softwarereset 1248//close watch dog 1249 u32_t cmd[(ZM_MAX_CMD_SIZE/4)]; 1250 u32_t ret; 1251 1252 cmd[0] = 0x00000008 | (ZM_CMD_FW_DL_INIT << 8); 1253 1254 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_FW_DL_INIT, NULL); 1255 1256 return ret; 1257} 1258//Paul-- 1259