1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * * Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * * Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * * Neither the name of Code Aurora nor 11 * the names of its contributors may be used to endorse or promote 12 * products derived from this software without specific prior written 13 * permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 19 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef MDP4_H 30#define MDP4_H 31 32extern struct mdp_dma_data dma2_data; 33extern struct mdp_dma_data dma_s_data; 34extern struct mdp_dma_data dma_e_data; 35extern struct mdp_histogram mdp_hist; 36extern struct completion mdp_hist_comp; 37extern boolean mdp_is_in_isr; 38extern uint32 mdp_intr_mask; 39extern spinlock_t mdp_spin_lock; 40 41 42#define MDP4_NONBLOCKING /* enable non blocking ioctl */ 43 44#define MDP4_OVERLAYPROC0_BASE 0x10000 45#define MDP4_OVERLAYPROC1_BASE 0x18000 46 47#define MDP4_VIDEO_BASE 0x20000 48#define MDP4_VIDEO_OFF 0x10000 49 50#define MDP4_RGB_BASE 0x40000 51#define MDP4_RGB_OFF 0x10000 52 53enum { /* display */ 54 PRIMARY_INTF_SEL, 55 SECONDARY_INTF_SEL, 56 EXTERNAL_INTF_SEL 57}; 58 59enum { 60 LCDC_RGB_INTF, 61 DTV_INTF = LCDC_RGB_INTF, 62 MDDI_LCDC_INTF, 63 MDDI_INTF, 64 EBI2_INTF 65}; 66 67enum { 68 MDDI_PRIMARY_SET, 69 MDDI_SECONDARY_SET, 70 MDDI_EXTERNAL_SET 71}; 72 73enum { 74 EBI2_LCD0, 75 EBI2_LCD1 76}; 77 78enum { 79 OVERLAY_MODE_NONE, 80 OVERLAY_MODE_BLT 81}; 82 83enum { 84 OVERLAY_REFRESH_ON_DEMAND, 85 OVERLAY_REFRESH_VSYNC, 86 OVERLAY_REFRESH_VSYNC_HALF, 87 OVERLAY_REFRESH_VSYNC_QUARTER 88}; 89 90enum { 91 OVERLAY_FRAMEBUF, 92 OVERLAY_DIRECTOUT 93}; 94 95/* system interrupts */ 96#define INTR_OVERLAY0_DONE BIT(0) 97#define INTR_OVERLAY1_DONE BIT(1) 98#define INTR_DMA_S_DONE BIT(2) 99#define INTR_DMA_E_DONE BIT(3) 100#define INTR_DMA_P_DONE BIT(4) 101#define INTR_VG1_HISTOGRAM BIT(5) 102#define INTR_VG2_HISTOGRAM BIT(6) 103#define INTR_PRIMARY_VSYNC BIT(7) 104#define INTR_PRIMARY_INTF_UDERRUN BIT(8) 105#define INTR_EXTERNAL_VSYNC BIT(9) 106#define INTR_EXTERNAL_INTF_UDERRUN BIT(10) 107#define INTR_DMA_P_HISTOGRAM BIT(17) 108 109/* histogram interrupts */ 110#define INTR_HIST_DONE BIT(0) 111#define INTR_HIST_RESET_SEQ_DONE BIT(1) 112 113 114#ifdef CONFIG_FB_MSM_OVERLAY 115#define MDP4_ANY_INTR_MASK (INTR_OVERLAY0_DONE) 116#else 117#define MDP4_ANY_INTR_MASK (INTR_DMA_P_DONE) 118#endif 119 120enum { 121 OVERLAY_PIPE_RGB1, 122 OVERLAY_PIPE_RGB2, 123}; 124 125enum { 126 OVERLAY_PIPE_VG1, /* video/graphic */ 127 OVERLAY_PIPE_VG2 128}; 129 130enum { 131 OVERLAY_TYPE_RGB, 132 OVERLAY_TYPE_VG /* video/graphic */ 133}; 134 135enum { 136 MDP4_MIXER0, 137 MDP4_MIXER1 138}; 139 140#define MDP4_MAX_MIXER 2 141 142enum { 143 OVERLAY_PLANE_INTERLEAVED, 144 OVERLAY_PLANE_PLANAR, 145 OVERLAY_PLANE_PSEUDO_PLANAR 146}; 147 148enum { 149 MDP4_MIXER_STAGE_UNUNSED, /* pipe not used */ 150 MDP4_MIXER_STAGE_BASE, 151 MDP4_MIXER_STAGE0, /* zorder 0 */ 152 MDP4_MIXER_STAGE1, /* zorder 1 */ 153 MDP4_MIXER_STAGE2 /* zorder 2 */ 154}; 155 156#define MDP4_MAX_STAGE 4 157 158enum { 159 MDP4_FRAME_FORMAT_LINEAR, 160 MDP4_FRAME_FORMAT_ARGB_TILE, 161 MDP4_FRAME_FORMAT_VIDEO_SUPERTILE 162}; 163 164enum { 165 MDP4_CHROMA_RGB, 166 MDP4_CHROMA_H2V1, 167 MDP4_CHROMA_H1V2, 168 MDP4_CHROMA_420 169}; 170 171#define MDP4_BLEND_BG_TRANSP_EN BIT(9) 172#define MDP4_BLEND_FG_TRANSP_EN BIT(8) 173#define MDP4_BLEND_BG_MOD_ALPHA BIT(7) 174#define MDP4_BLEND_BG_INV_ALPHA BIT(6) 175#define MDP4_BLEND_BG_ALPHA_FG_CONST (0 << 4) 176#define MDP4_BLEND_BG_ALPHA_BG_CONST (1 << 4) 177#define MDP4_BLEND_BG_ALPHA_FG_PIXEL (2 << 4) 178#define MDP4_BLEND_BG_ALPHA_BG_PIXEL (3 << 4) 179#define MDP4_BLEND_FG_MOD_ALPHA BIT(3) 180#define MDP4_BLEND_FG_INV_ALPHA BIT(2) 181#define MDP4_BLEND_FG_ALPHA_FG_CONST (0 << 0) 182#define MDP4_BLEND_FG_ALPHA_BG_CONST (1 << 0) 183#define MDP4_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 184#define MDP4_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 185 186#define MDP4_FORMAT_SOLID_FILL BIT(22) 187#define MDP4_FORMAT_UNPACK_ALIGN_MSB BIT(18) 188#define MDP4_FORMAT_UNPACK_TIGHT BIT(17) 189#define MDP4_FORMAT_90_ROTATED BIT(12) 190#define MDP4_FORMAT_ALPHA_ENABLE BIT(8) 191 192#define MDP4_OP_DEINT_ODD_REF BIT(19) 193#define MDP4_OP_IGC_LUT_EN BIT(16) 194#define MDP4_OP_DITHER_EN BIT(15) 195#define MDP4_OP_FLIP_UD BIT(14) 196#define MDP4_OP_FLIP_LR BIT(13) 197#define MDP4_OP_CSC_EN BIT(11) 198#define MDP4_OP_SRC_DATA_YCBCR BIT(9) 199#define MDP4_OP_SCALEY_FIR (0 << 4) 200#define MDP4_OP_SCALEY_MN_PHASE (1 << 4) 201#define MDP4_OP_SCALEY_PIXEL_RPT (2 << 4) 202#define MDP4_OP_SCALEX_FIR (0 << 2) 203#define MDP4_OP_SCALEX_MN_PHASE (1 << 2) 204#define MDP4_OP_SCALEX_PIXEL_RPT (2 << 2) 205#define MDP4_OP_SCALEY_EN BIT(1) 206#define MDP4_OP_SCALEX_EN BIT(0) 207 208#define MDP4_PIPE_PER_MIXER 2 209 210#define MDP4_MAX_PLANE 4 211 212#define MDP4_MAX_VIDEO_PIPE 2 213#define MDP4_MAX_RGB_PIPE 2 214#define MDP4_MAX_OVERLAY_PIPE 16 215 216 217struct mdp4_overlay_pipe { 218 uint32 pipe_type; /* rgb, video/graphic */ 219 uint32 pipe_num; 220 uint32 pipe_ndx; 221 uint32 mixer_num; /* which mixer used */ 222 uint32 mixer_stage; /* which stage of mixer used */ 223 uint32 src_format; 224 uint32 src_width; /* source img width */ 225 uint32 src_height; /* source img height */ 226 uint32 src_w; /* roi */ 227 uint32 src_h; /* roi */ 228 uint32 src_x; /* roi */ 229 uint32 src_y; /* roi */ 230 uint32 dst_w; /* roi */ 231 uint32 dst_h; /* roi */ 232 uint32 dst_x; /* roi */ 233 uint32 dst_y; /* roi */ 234 uint32 op_mode; 235 uint32 transp; 236 uint32 blend_op; 237 uint32 phasex_step; 238 uint32 phasey_step; 239 uint32 alpha; 240 uint32 is_fg; /* control alpha & color key */ 241 uint32 srcp0_addr; /* interleave, luma */ 242 uint32 srcp0_ystride; 243 uint32 srcp1_addr; /* pseudoplanar, chroma plane */ 244 uint32 srcp1_ystride; 245 uint32 srcp2_addr; /* planar color 2*/ 246 uint32 srcp2_ystride; 247 uint32 srcp3_addr; /* alpha/color 3 */ 248 uint32 srcp3_ystride; 249 uint32 fetch_plane; 250 uint32 frame_format; /* video */ 251 uint32 chroma_site; /* video */ 252 uint32 chroma_sample; /* video */ 253 uint32 solid_fill; 254 uint32 vc1_reduce; /* video */ 255 uint32 fatch_planes; /* video */ 256 uint32 unpack_align_msb;/* 0 to LSB, 1 to MSB */ 257 uint32 unpack_tight;/* 0 for loose, 1 for tight */ 258 uint32 unpack_count;/* 0 = 1 component, 1 = 2 component ... */ 259 uint32 rotated_90; /* has been rotated 90 degree */ 260 uint32 bpp; /* byte per pixel */ 261 uint32 alpha_enable;/* source has alpha */ 262 /* 263 * number of bits for source component, 264 * 0 = 1 bit, 1 = 2 bits, 2 = 6 bits, 3 = 8 bits 265 */ 266 uint32 a_bit; /* component 3, alpha */ 267 uint32 r_bit; /* component 2, R_Cr */ 268 uint32 b_bit; /* component 1, B_Cb */ 269 uint32 g_bit; /* component 0, G_lumz */ 270 /* 271 * unpack pattern 272 * A = C3, R = C2, B = C1, G = C0 273 */ 274 uint32 element3; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */ 275 uint32 element2; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */ 276 uint32 element1; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */ 277 uint32 element0; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */ 278 struct completion comp; 279 struct mdp_overlay req_data; 280}; 281 282void mdp4_sw_reset(unsigned long bits); 283void mdp4_display_intf_sel(int output, unsigned long intf); 284void mdp4_overlay_cfg(int layer, int blt_mode, int refresh, int direct_out); 285void mdp4_ebi2_lcd_setup(int lcd, unsigned long base, int ystride); 286void mdp4_mddi_setup(int which, unsigned long id); 287unsigned long mdp4_display_status(void); 288void mdp4_enable_clk_irq(void); 289void mdp4_disable_clk_irq(void); 290void mdp4_dma_p_update(struct msm_fb_data_type *mfd); 291void mdp4_dma_s_update(struct msm_fb_data_type *mfd); 292void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state, 293 boolean isr); 294void mdp4_pipe_kickoff(uint32 pipe, struct msm_fb_data_type *mfd); 295int mdp4_lcdc_on(struct platform_device *pdev); 296int mdp4_lcdc_off(struct platform_device *pdev); 297void mdp4_lcdc_update(struct msm_fb_data_type *mfd); 298void mdp4_intr_clear_set(ulong clear, ulong set); 299void mdp4_dma_p_cfg(void); 300void mdp4_hw_init(void); 301void mdp4_isr_read(int); 302void mdp4_clear_lcdc(void); 303void mdp4_mixer_blend_init(int mixer_num); 304void mdp4_vg_qseed_init(int vg_num); 305void mdp4_vg_csc_mv_setup(int vp_num); 306void mdp4_vg_csc_pre_bv_setup(int vp_num); 307void mdp4_vg_csc_post_bv_setup(int vp_num); 308void mdp4_vg_csc_pre_lv_setup(int vp_num); 309void mdp4_vg_csc_post_lv_setup(int vp_num); 310irqreturn_t mdp4_isr(int irq, void *ptr); 311void mdp4_overlay_format_to_pipe(uint32 format, struct mdp4_overlay_pipe *pipe); 312uint32 mdp4_overlay_format(struct mdp4_overlay_pipe *pipe); 313uint32 mdp4_overlay_unpack_pattern(struct mdp4_overlay_pipe *pipe); 314uint32 mdp4_overlay_op_mode(struct mdp4_overlay_pipe *pipe); 315void mdp4_lcdc_overlay(struct msm_fb_data_type *mfd); 316void mdp4_overlay_rgb_setup(struct mdp4_overlay_pipe *pipe); 317void mdp4_overlay_reg_flush(struct mdp4_overlay_pipe *pipe, int all); 318void mdp4_mixer_blend_setup(struct mdp4_overlay_pipe *pipe); 319void mdp4_mixer_stage_up(struct mdp4_overlay_pipe *pipe); 320void mdp4_mixer_stage_down(struct mdp4_overlay_pipe *pipe); 321int mdp4_mixer_stage_can_run(struct mdp4_overlay_pipe *pipe); 322void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe); 323void mdp4_mddi_overlay(struct msm_fb_data_type *mfd); 324int mdp4_overlay_format2type(uint32 format); 325int mdp4_overlay_format2pipe(struct mdp4_overlay_pipe *pipe); 326int mdp4_overlay_get(struct fb_info *info, struct mdp_overlay *req); 327int mdp4_overlay_set(struct fb_info *info, struct mdp_overlay *req); 328int mdp4_overlay_unset(struct fb_info *info, int ndx); 329int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req, 330 struct file **pp_src_file); 331struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(void); 332void mdp4_overlay_pipe_free(struct mdp4_overlay_pipe *pipe); 333void mdp4_overlay_dmap_cfg(struct msm_fb_data_type *mfd, int lcdc); 334void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe); 335int mdp4_overlay_active(int mixer); 336void mdp4_overlay0_done_lcdc(void); 337void mdp4_overlay0_done_mddi(void); 338void mdp4_mddi_overlay_restore(void); 339void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd, 340 struct mdp4_overlay_pipe *pipe); 341void mdp4_rgb_igc_lut_setup(int num); 342void mdp4_vg_igc_lut_setup(int num); 343void mdp4_mixer_gc_lut_setup(int mixer_num); 344 345#ifdef CONFIG_DEBUG_FS 346int mdp4_debugfs_init(void); 347#endif 348 349int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req, 350 struct file **pp_src_file, struct file **pp_dst_file); 351 352#endif /* MDP_H */ 353