1/* 2 * Agere Systems Inc. 3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs 4 * 5 * Copyright �� 2005 Agere Systems Inc. 6 * All rights reserved. 7 * http://www.agere.com 8 * 9 *------------------------------------------------------------------------------ 10 * 11 * et131x_isr.c - File which contains the ISR, ISR handler, and related routines 12 * for processing interrupts from the device. 13 * 14 *------------------------------------------------------------------------------ 15 * 16 * SOFTWARE LICENSE 17 * 18 * This software is provided subject to the following terms and conditions, 19 * which you should read carefully before using the software. Using this 20 * software indicates your acceptance of these terms and conditions. If you do 21 * not agree with these terms and conditions, do not use the software. 22 * 23 * Copyright �� 2005 Agere Systems Inc. 24 * All rights reserved. 25 * 26 * Redistribution and use in source or binary forms, with or without 27 * modifications, are permitted provided that the following conditions are met: 28 * 29 * . Redistributions of source code must retain the above copyright notice, this 30 * list of conditions and the following Disclaimer as comments in the code as 31 * well as in the documentation and/or other materials provided with the 32 * distribution. 33 * 34 * . Redistributions in binary form must reproduce the above copyright notice, 35 * this list of conditions and the following Disclaimer in the documentation 36 * and/or other materials provided with the distribution. 37 * 38 * . Neither the name of Agere Systems Inc. nor the names of the contributors 39 * may be used to endorse or promote products derived from this software 40 * without specific prior written permission. 41 * 42 * Disclaimer 43 * 44 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 45 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY 47 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN 48 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY 49 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 51 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 52 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 55 * DAMAGE. 56 * 57 */ 58 59#include "et131x_version.h" 60#include "et131x_defs.h" 61 62#include <linux/init.h> 63#include <linux/module.h> 64#include <linux/types.h> 65#include <linux/kernel.h> 66 67#include <linux/sched.h> 68#include <linux/ptrace.h> 69#include <linux/ctype.h> 70#include <linux/string.h> 71#include <linux/timer.h> 72#include <linux/interrupt.h> 73#include <linux/in.h> 74#include <linux/delay.h> 75#include <linux/io.h> 76#include <linux/bitops.h> 77#include <linux/pci.h> 78#include <asm/system.h> 79 80#include <linux/netdevice.h> 81#include <linux/etherdevice.h> 82#include <linux/skbuff.h> 83#include <linux/if_arp.h> 84#include <linux/ioport.h> 85 86#include "et1310_phy.h" 87#include "et131x_adapter.h" 88#include "et131x.h" 89 90/* 91 * For interrupts, normal running is: 92 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, 93 * watchdog_interrupt & txdma_xfer_done 94 * 95 * In both cases, when flow control is enabled for either Tx or bi-direction, 96 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the 97 * buffer rings are running low. 98 */ 99#define INT_MASK_DISABLE 0xffffffff 100 101/* NOTE: Masking out MAC_STAT Interrupt for now... 102 * #define INT_MASK_ENABLE 0xfff6bf17 103 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 104 */ 105#define INT_MASK_ENABLE 0xfffebf17 106#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 107 108 109/** 110 * et131x_enable_interrupts - enable interrupt 111 * @adapter: et131x device 112 * 113 * Enable the appropriate interrupts on the ET131x according to our 114 * configuration 115 */ 116 117void et131x_enable_interrupts(struct et131x_adapter *adapter) 118{ 119 u32 mask; 120 121 /* Enable all global interrupts */ 122 if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both) 123 mask = INT_MASK_ENABLE; 124 else 125 mask = INT_MASK_ENABLE_NO_FLOW; 126 127 adapter->CachedMaskValue = mask; 128 writel(mask, &adapter->regs->global.int_mask); 129} 130 131/** 132 * et131x_disable_interrupts - interrupt disable 133 * @adapter: et131x device 134 * 135 * Block all interrupts from the et131x device at the device itself 136 */ 137 138void et131x_disable_interrupts(struct et131x_adapter *adapter) 139{ 140 /* Disable all global interrupts */ 141 adapter->CachedMaskValue = INT_MASK_DISABLE; 142 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask); 143} 144 145 146/** 147 * et131x_isr - The Interrupt Service Routine for the driver. 148 * @irq: the IRQ on which the interrupt was received. 149 * @dev_id: device-specific info (here a pointer to a net_device struct) 150 * 151 * Returns a value indicating if the interrupt was handled. 152 */ 153 154irqreturn_t et131x_isr(int irq, void *dev_id) 155{ 156 bool handled = true; 157 struct net_device *netdev = (struct net_device *)dev_id; 158 struct et131x_adapter *adapter = NULL; 159 u32 status; 160 161 if (!netif_device_present(netdev)) { 162 handled = false; 163 goto out; 164 } 165 166 adapter = netdev_priv(netdev); 167 168 /* If the adapter is in low power state, then it should not 169 * recognize any interrupt 170 */ 171 172 /* Disable Device Interrupts */ 173 et131x_disable_interrupts(adapter); 174 175 /* Get a copy of the value in the interrupt status register 176 * so we can process the interrupting section 177 */ 178 status = readl(&adapter->regs->global.int_status); 179 180 if (adapter->FlowControl == TxOnly || 181 adapter->FlowControl == Both) { 182 status &= ~INT_MASK_ENABLE; 183 } else { 184 status &= ~INT_MASK_ENABLE_NO_FLOW; 185 } 186 187 /* Make sure this is our interrupt */ 188 if (!status) { 189 handled = false; 190 et131x_enable_interrupts(adapter); 191 goto out; 192 } 193 194 /* This is our interrupt, so process accordingly */ 195 196 if (status & ET_INTR_WATCHDOG) { 197 struct tcb *tcb = adapter->tx_ring.send_head; 198 199 if (tcb) 200 if (++tcb->stale > 1) 201 status |= ET_INTR_TXDMA_ISR; 202 203 if (adapter->rx_ring.UnfinishedReceives) 204 status |= ET_INTR_RXDMA_XFR_DONE; 205 else if (tcb == NULL) 206 writel(0, &adapter->regs->global.watchdog_timer); 207 208 status &= ~ET_INTR_WATCHDOG; 209 } 210 211 if (status == 0) { 212 /* This interrupt has in some way been "handled" by 213 * the ISR. Either it was a spurious Rx interrupt, or 214 * it was a Tx interrupt that has been filtered by 215 * the ISR. 216 */ 217 et131x_enable_interrupts(adapter); 218 goto out; 219 } 220 221 /* We need to save the interrupt status value for use in our 222 * DPC. We will clear the software copy of that in that 223 * routine. 224 */ 225 adapter->Stats.InterruptStatus = status; 226 227 /* Schedule the ISR handler as a bottom-half task in the 228 * kernel's tq_immediate queue, and mark the queue for 229 * execution 230 */ 231 schedule_work(&adapter->task); 232out: 233 return IRQ_RETVAL(handled); 234} 235 236/** 237 * et131x_isr_handler - The ISR handler 238 * @p_adapter, a pointer to the device's private adapter structure 239 * 240 * scheduled to run in a deferred context by the ISR. This is where the ISR's 241 * work actually gets done. 242 */ 243void et131x_isr_handler(struct work_struct *work) 244{ 245 struct et131x_adapter *etdev = 246 container_of(work, struct et131x_adapter, task); 247 u32 status = etdev->Stats.InterruptStatus; 248 ADDRESS_MAP_t __iomem *iomem = etdev->regs; 249 250 /* 251 * These first two are by far the most common. Once handled, we clear 252 * their two bits in the status word. If the word is now zero, we 253 * exit. 254 */ 255 /* Handle all the completed Transmit interrupts */ 256 if (status & ET_INTR_TXDMA_ISR) 257 et131x_handle_send_interrupt(etdev); 258 259 /* Handle all the completed Receives interrupts */ 260 if (status & ET_INTR_RXDMA_XFR_DONE) 261 et131x_handle_recv_interrupt(etdev); 262 263 status &= 0xffffffd7; 264 265 if (status) { 266 /* Handle the TXDMA Error interrupt */ 267 if (status & ET_INTR_TXDMA_ERR) { 268 u32 txdma_err; 269 270 /* Following read also clears the register (COR) */ 271 txdma_err = readl(&iomem->txdma.TxDmaError); 272 273 dev_warn(&etdev->pdev->dev, 274 "TXDMA_ERR interrupt, error = %d\n", 275 txdma_err); 276 } 277 278 /* Handle Free Buffer Ring 0 and 1 Low interrupt */ 279 if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) { 280 /* 281 * This indicates the number of unused buffers in 282 * RXDMA free buffer ring 0 is <= the limit you 283 * programmed. Free buffer resources need to be 284 * returned. Free buffers are consumed as packets 285 * are passed from the network to the host. The host 286 * becomes aware of the packets from the contents of 287 * the packet status ring. This ring is queried when 288 * the packet done interrupt occurs. Packets are then 289 * passed to the OS. When the OS is done with the 290 * packets the resources can be returned to the 291 * ET1310 for re-use. This interrupt is one method of 292 * returning resources. 293 */ 294 295 /* If the user has flow control on, then we will 296 * send a pause packet, otherwise just exit 297 */ 298 if (etdev->FlowControl == TxOnly || 299 etdev->FlowControl == Both) { 300 u32 pm_csr; 301 302 /* Tell the device to send a pause packet via 303 * the back pressure register (bp req and 304 * bp xon/xoff) 305 */ 306 pm_csr = readl(&iomem->global.pm_csr); 307 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) 308 writel(3, &iomem->txmac.bp_ctrl); 309 } 310 } 311 312 /* Handle Packet Status Ring Low Interrupt */ 313 if (status & ET_INTR_RXDMA_STAT_LOW) { 314 315 /* 316 * Same idea as with the two Free Buffer Rings. 317 * Packets going from the network to the host each 318 * consume a free buffer resource and a packet status 319 * resource. These resoures are passed to the OS. 320 * When the OS is done with the resources, they need 321 * to be returned to the ET1310. This is one method 322 * of returning the resources. 323 */ 324 } 325 326 /* Handle RXDMA Error Interrupt */ 327 if (status & ET_INTR_RXDMA_ERR) { 328 /* 329 * The rxdma_error interrupt is sent when a time-out 330 * on a request issued by the JAGCore has occurred or 331 * a completion is returned with an un-successful 332 * status. In both cases the request is considered 333 * complete. The JAGCore will automatically re-try the 334 * request in question. Normally information on events 335 * like these are sent to the host using the "Advanced 336 * Error Reporting" capability. This interrupt is 337 * another way of getting similar information. The 338 * only thing required is to clear the interrupt by 339 * reading the ISR in the global resources. The 340 * JAGCore will do a re-try on the request. Normally 341 * you should never see this interrupt. If you start 342 * to see this interrupt occurring frequently then 343 * something bad has occurred. A reset might be the 344 * thing to do. 345 */ 346 /* TRAP();*/ 347 348 dev_warn(&etdev->pdev->dev, 349 "RxDMA_ERR interrupt, error %x\n", 350 readl(&iomem->txmac.tx_test)); 351 } 352 353 /* Handle the Wake on LAN Event */ 354 if (status & ET_INTR_WOL) { 355 /* 356 * This is a secondary interrupt for wake on LAN. 357 * The driver should never see this, if it does, 358 * something serious is wrong. We will TRAP the 359 * message when we are in DBG mode, otherwise we 360 * will ignore it. 361 */ 362 dev_err(&etdev->pdev->dev, "WAKE_ON_LAN interrupt\n"); 363 } 364 365 /* Handle the PHY interrupt */ 366 if (status & ET_INTR_PHY) { 367 u32 pm_csr; 368 MI_BMSR_t BmsrInts, BmsrData; 369 MI_ISR_t myIsr; 370 371 /* If we are in coma mode when we get this interrupt, 372 * we need to disable it. 373 */ 374 pm_csr = readl(&iomem->global.pm_csr); 375 if (pm_csr & ET_PM_PHY_SW_COMA) { 376 /* 377 * Check to see if we are in coma mode and if 378 * so, disable it because we will not be able 379 * to read PHY values until we are out. 380 */ 381 DisablePhyComa(etdev); 382 } 383 384 /* Read the PHY ISR to clear the reason for the 385 * interrupt. 386 */ 387 MiRead(etdev, (uint8_t) offsetof(MI_REGS_t, isr), 388 &myIsr.value); 389 390 if (!etdev->ReplicaPhyLoopbk) { 391 MiRead(etdev, 392 (uint8_t) offsetof(MI_REGS_t, bmsr), 393 &BmsrData.value); 394 395 BmsrInts.value = 396 etdev->Bmsr.value ^ BmsrData.value; 397 etdev->Bmsr.value = BmsrData.value; 398 399 /* Do all the cable in / cable out stuff */ 400 et131x_Mii_check(etdev, BmsrData, BmsrInts); 401 } 402 } 403 404 /* Let's move on to the TxMac */ 405 if (status & ET_INTR_TXMAC) { 406 u32 err = readl(&iomem->txmac.err); 407 408 /* 409 * When any of the errors occur and TXMAC generates 410 * an interrupt to report these errors, it usually 411 * means that TXMAC has detected an error in the data 412 * stream retrieved from the on-chip Tx Q. All of 413 * these errors are catastrophic and TXMAC won't be 414 * able to recover data when these errors occur. In 415 * a nutshell, the whole Tx path will have to be reset 416 * and re-configured afterwards. 417 */ 418 dev_warn(&etdev->pdev->dev, 419 "TXMAC interrupt, error 0x%08x\n", 420 err); 421 422 /* If we are debugging, we want to see this error, 423 * otherwise we just want the device to be reset and 424 * continue 425 */ 426 } 427 428 /* Handle RXMAC Interrupt */ 429 if (status & ET_INTR_RXMAC) { 430 /* 431 * These interrupts are catastrophic to the device, 432 * what we need to do is disable the interrupts and 433 * set the flag to cause us to reset so we can solve 434 * this issue. 435 */ 436 /* MP_SET_FLAG( etdev, 437 fMP_ADAPTER_HARDWARE_ERROR); */ 438 439 dev_warn(&etdev->pdev->dev, 440 "RXMAC interrupt, error 0x%08x. Requesting reset\n", 441 readl(&iomem->rxmac.err_reg)); 442 443 dev_warn(&etdev->pdev->dev, 444 "Enable 0x%08x, Diag 0x%08x\n", 445 readl(&iomem->rxmac.ctrl), 446 readl(&iomem->rxmac.rxq_diag)); 447 448 /* 449 * If we are debugging, we want to see this error, 450 * otherwise we just want the device to be reset and 451 * continue 452 */ 453 } 454 455 /* Handle MAC_STAT Interrupt */ 456 if (status & ET_INTR_MAC_STAT) { 457 /* 458 * This means at least one of the un-masked counters 459 * in the MAC_STAT block has rolled over. Use this 460 * to maintain the top, software managed bits of the 461 * counter(s). 462 */ 463 HandleMacStatInterrupt(etdev); 464 } 465 466 /* Handle SLV Timeout Interrupt */ 467 if (status & ET_INTR_SLV_TIMEOUT) { 468 /* 469 * This means a timeout has occured on a read or 470 * write request to one of the JAGCore registers. The 471 * Global Resources block has terminated the request 472 * and on a read request, returned a "fake" value. 473 * The most likely reasons are: Bad Address or the 474 * addressed module is in a power-down state and 475 * can't respond. 476 */ 477 } 478 } 479 et131x_enable_interrupts(etdev); 480} 481