1/*************************************************************************** 2 * Copyright (c) 2005-2009, Broadcom Corporation. 3 * 4 * Name: crystalhd_hw . h 5 * 6 * Description: 7 * BCM70012 Linux driver hardware layer. 8 * 9 * HISTORY: 10 * 11 ********************************************************************** 12 * This file is part of the crystalhd device driver. 13 * 14 * This driver is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation, version 2 of the License. 17 * 18 * This driver is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this driver. If not, see <http://www.gnu.org/licenses/>. 25 **********************************************************************/ 26 27#ifndef _CRYSTALHD_HW_H_ 28#define _CRYSTALHD_HW_H_ 29 30#include "crystalhd_misc.h" 31#include "crystalhd_fw_if.h" 32 33/* HW constants..*/ 34#define DMA_ENGINE_CNT 2 35#define MAX_PIB_Q_DEPTH 64 36#define MIN_PIB_Q_DEPTH 2 37#define WR_POINTER_OFF 4 38 39#define ASPM_L1_ENABLE (BC_BIT(27)) 40 41/************************************************* 42 7412 Decoder Registers. 43**************************************************/ 44#define FW_CMD_BUFF_SZ 64 45#define TS_Host2CpuSnd 0x00000100 46#define Hst2CpuMbx1 0x00100F00 47#define Cpu2HstMbx1 0x00100F04 48#define MbxStat1 0x00100F08 49#define Stream2Host_Intr_Sts 0x00100F24 50#define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */ 51 52/* TS input status register */ 53#define TS_StreamAFIFOStatus 0x0010044C 54#define TS_StreamBFIFOStatus 0x0010084C 55 56/*UART Selection definitions*/ 57#define UartSelectA 0x00100300 58#define UartSelectB 0x00100304 59 60#define BSVS_UART_DEC_NONE 0x00 61#define BSVS_UART_DEC_OUTER 0x01 62#define BSVS_UART_DEC_INNER 0x02 63#define BSVS_UART_STREAM 0x03 64 65/* Code-In fifo */ 66#define REG_DecCA_RegCinCTL 0xa00 67#define REG_DecCA_RegCinBase 0xa0c 68#define REG_DecCA_RegCinEnd 0xa10 69#define REG_DecCA_RegCinWrPtr 0xa04 70#define REG_DecCA_RegCinRdPtr 0xa08 71 72#define REG_Dec_TsUser0Base 0x100864 73#define REG_Dec_TsUser0Rdptr 0x100868 74#define REG_Dec_TsUser0Wrptr 0x10086C 75#define REG_Dec_TsUser0End 0x100874 76 77/* ASF Case ...*/ 78#define REG_Dec_TsAudCDB2Base 0x10036c 79#define REG_Dec_TsAudCDB2Rdptr 0x100378 80#define REG_Dec_TsAudCDB2Wrptr 0x100374 81#define REG_Dec_TsAudCDB2End 0x100370 82 83/* DRAM bringup Registers */ 84#define SDRAM_PARAM 0x00040804 85#define SDRAM_PRECHARGE 0x000408B0 86#define SDRAM_EXT_MODE 0x000408A4 87#define SDRAM_MODE 0x000408A0 88#define SDRAM_REFRESH 0x00040890 89#define SDRAM_REF_PARAM 0x00040808 90 91#define DecHt_PllACtl 0x34000C 92#define DecHt_PllBCtl 0x340010 93#define DecHt_PllCCtl 0x340014 94#define DecHt_PllDCtl 0x340034 95#define DecHt_PllECtl 0x340038 96#define AUD_DSP_MISC_SOFT_RESET 0x00240104 97#define AIO_MISC_PLL_RESET 0x0026000C 98#define PCIE_CLK_REQ_REG 0xDC 99#define PCI_CLK_REQ_ENABLE (BC_BIT(8)) 100 101/************************************************* 102 F/W Copy engine definitions.. 103**************************************************/ 104#define BC_FWIMG_ST_ADDR 0x00000000 105#define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n))) 106#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00)) 107 108#define DecHt_HostSwReset 0x340000 109#define BC_DRAM_FW_CFG_ADDR 0x001c2000 110 111union addr_64 { 112 struct { 113 uint32_t low_part; 114 uint32_t high_part; 115 }; 116 117 uint64_t full_addr; 118 119}; 120 121union intr_mask_reg { 122 struct { 123 uint32_t mask_tx_done:1; 124 uint32_t mask_tx_err:1; 125 uint32_t mask_rx_done:1; 126 uint32_t mask_rx_err:1; 127 uint32_t mask_pcie_err:1; 128 uint32_t mask_pcie_rbusmast_err:1; 129 uint32_t mask_pcie_rgr_bridge:1; 130 uint32_t reserved:25; 131 }; 132 133 uint32_t whole_reg; 134 135}; 136 137union link_misc_perst_deco_ctrl { 138 struct { 139 uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ 140 uint32_t reserved0:3; /* Reserved.No Effect*/ 141 uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ 142 uint32_t reserved1:27; /* Reseved. No Effect*/ 143 }; 144 145 uint32_t whole_reg; 146 147}; 148 149union link_misc_perst_clk_ctrl { 150 struct { 151 uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */ 152 uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */ 153 uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set 154 to select an alternate clock before setting this bit.*/ 155 uint32_t reserved0:5; /* Reserved */ 156 uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */ 157 uint32_t pll_div:4; /* This setting controls the divider for the PLL. */ 158 uint32_t reserved1:12; /* Reserved */ 159 }; 160 161 uint32_t whole_reg; 162 163}; 164 165union link_misc_perst_decoder_ctrl { 166 struct { 167 uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ 168 uint32_t res0:3; /* Reserved.No Effect*/ 169 uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ 170 uint32_t res1:27; /* Reseved. No Effect */ 171 }; 172 173 uint32_t whole_reg; 174 175}; 176 177union desc_low_addr_reg { 178 struct { 179 uint32_t list_valid:1; 180 uint32_t reserved:4; 181 uint32_t low_addr:27; 182 }; 183 184 uint32_t whole_reg; 185 186}; 187 188struct dma_descriptor { /* 8 32-bit values */ 189 /* 0th u32 */ 190 uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ 191 uint32_t res0:4; /* bits 28-31: Reserved */ 192 193 /* 1st u32 */ 194 uint32_t buff_addr_low; /* 1 buffer address low */ 195 uint32_t buff_addr_high; /* 2 buffer address high */ 196 197 /* 3rd u32 */ 198 uint32_t res2:2; /* 0-1 - Reserved */ 199 uint32_t xfer_size:23; /* 2-24 = Xfer size in words */ 200 uint32_t res3:6; /* 25-30 reserved */ 201 uint32_t intr_enable:1; /* 31 - Interrupt After this desc */ 202 203 /* 4th u32 */ 204 uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */ 205 uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */ 206 uint32_t res4:25; /* 3 - 27 Reserved bits */ 207 uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */ 208 uint32_t dma_dir:1; /* 30 bit DMA Direction */ 209 uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */ 210 211 /* 5th u32 */ 212 uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */ 213 214 /* 6th u32 */ 215 uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */ 216 217 /* 7th u32 */ 218 uint32_t res8; /* Last 32bits reserved */ 219 220}; 221 222/* 223 * We will allocate the memory in 4K pages 224 * the linked list will be a list of 32 byte descriptors. 225 * The virtual address will determine what should be freed. 226 */ 227struct dma_desc_mem { 228 struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */ 229 dma_addr_t phy_addr; /* physical address of each DMA desc */ 230 uint32_t sz; 231 struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */ 232 233}; 234 235enum list_sts { 236 sts_free = 0, 237 238 /* RX-Y Bits 0:7 */ 239 rx_waiting_y_intr = 0x00000001, 240 rx_y_error = 0x00000004, 241 242 /* RX-UV Bits 8:16 */ 243 rx_waiting_uv_intr = 0x0000100, 244 rx_uv_error = 0x0000400, 245 246 rx_sts_waiting = (rx_waiting_y_intr|rx_waiting_uv_intr), 247 rx_sts_error = (rx_y_error|rx_uv_error), 248 249 rx_y_mask = 0x000000FF, 250 rx_uv_mask = 0x0000FF00, 251}; 252 253struct tx_dma_pkt { 254 struct dma_desc_mem desc_mem; 255 hw_comp_callback call_back; 256 struct crystalhd_dio_req *dio_req; 257 wait_queue_head_t *cb_event; 258 uint32_t list_tag; 259}; 260 261struct crystalhd_rx_dma_pkt { 262 struct dma_desc_mem desc_mem; 263 struct crystalhd_dio_req *dio_req; 264 uint32_t pkt_tag; 265 uint32_t flags; 266 struct BC_PIC_INFO_BLOCK pib; 267 dma_addr_t uv_phy_addr; 268 struct crystalhd_rx_dma_pkt *next; 269}; 270 271struct crystalhd_hw_stats { 272 uint32_t rx_errors; 273 uint32_t tx_errors; 274 uint32_t freeq_count; 275 uint32_t rdyq_count; 276 uint32_t num_interrupts; 277 uint32_t dev_interrupts; 278 uint32_t cin_busy; 279 uint32_t pause_cnt; 280}; 281 282struct crystalhd_hw { 283 struct tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT]; 284 spinlock_t lock; 285 286 uint32_t tx_ioq_tag_seed; 287 uint32_t tx_list_post_index; 288 289 struct crystalhd_rx_dma_pkt *rx_pkt_pool_head; 290 uint32_t rx_pkt_tag_seed; 291 292 bool dev_started; 293 void *adp; 294 295 wait_queue_head_t *pfw_cmd_event; 296 int fwcmd_evt_sts; 297 298 uint32_t pib_del_Q_addr; 299 uint32_t pib_rel_Q_addr; 300 301 struct crystalhd_dioq *tx_freeq; 302 struct crystalhd_dioq *tx_actq; 303 304 /* Rx DMA Engine Specific Locks */ 305 spinlock_t rx_lock; 306 uint32_t rx_list_post_index; 307 enum list_sts rx_list_sts[DMA_ENGINE_CNT]; 308 struct crystalhd_dioq *rx_rdyq; 309 struct crystalhd_dioq *rx_freeq; 310 struct crystalhd_dioq *rx_actq; 311 uint32_t stop_pending; 312 313 /* HW counters.. */ 314 struct crystalhd_hw_stats stats; 315 316 /* Core clock in MHz */ 317 uint32_t core_clock_mhz; 318 uint32_t prev_n; 319 uint32_t pwr_lock; 320}; 321 322/* Clock defines for power control */ 323#define CLOCK_PRESET 175 324 325/* DMA engine register BIT mask wrappers.. */ 326#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 327 328#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ 329 INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ 330 INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ 331 INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ 332 INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ 333 INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ 334 INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ 335 INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) 336 337#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ 338 MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ 339 MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ 340 MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) 341 342#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ 343 MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ 344 MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ 345 MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) 346 347#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ 348 MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ 349 MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ 350 MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) 351 352#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ 353 MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ 354 MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ 355 MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) 356 357 358/**** API Exposed to the other layers ****/ 359enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp, 360 void *buffer, uint32_t sz); 361enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw, struct BC_FW_CMD *fw_cmd); 362bool crystalhd_hw_interrupt(struct crystalhd_adp *adp, struct crystalhd_hw *hw); 363enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *, struct crystalhd_adp *); 364enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *); 365enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *); 366enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *); 367 368 369enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, 370 hw_comp_callback call_back, 371 wait_queue_head_t *cb_event, 372 uint32_t *list_id, uint8_t data_flags); 373 374enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw); 375enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw); 376enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw); 377enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id); 378enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, 379 struct crystalhd_dio_req *ioreq, bool en_post); 380enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, 381 struct BC_PIC_INFO_BLOCK *pib, 382 struct crystalhd_dio_req **ioreq); 383enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw); 384enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw); 385void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats); 386 387/* API to program the core clock on the decoder */ 388enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *); 389 390#endif 391