1/* 2 comedi/drivers/ni_atmio16d.c 3 Hardware driver for National Instruments AT-MIO16D board 4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20 */ 21/* 22Driver: ni_atmio16d 23Description: National Instruments AT-MIO-16D 24Author: Chris R. Baugher <baugher@enteract.com> 25Status: unknown 26Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d) 27*/ 28/* 29 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who 30 * wrote the driver for Advantec's pcl812 boards. I used the interrupt 31 * handling code from his driver as an example for this one. 32 * 33 * Chris Baugher 34 * 5/1/2000 35 * 36 */ 37 38#include <linux/interrupt.h> 39#include "../comedidev.h" 40 41#include <linux/ioport.h> 42 43#include "8255.h" 44 45/* Configuration and Status Registers */ 46#define COM_REG_1 0x00 /* wo 16 */ 47#define STAT_REG 0x00 /* ro 16 */ 48#define COM_REG_2 0x02 /* wo 16 */ 49/* Event Strobe Registers */ 50#define START_CONVERT_REG 0x08 /* wo 16 */ 51#define START_DAQ_REG 0x0A /* wo 16 */ 52#define AD_CLEAR_REG 0x0C /* wo 16 */ 53#define EXT_STROBE_REG 0x0E /* wo 16 */ 54/* Analog Output Registers */ 55#define DAC0_REG 0x10 /* wo 16 */ 56#define DAC1_REG 0x12 /* wo 16 */ 57#define INT2CLR_REG 0x14 /* wo 16 */ 58/* Analog Input Registers */ 59#define MUX_CNTR_REG 0x04 /* wo 16 */ 60#define MUX_GAIN_REG 0x06 /* wo 16 */ 61#define AD_FIFO_REG 0x16 /* ro 16 */ 62#define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */ 63/* AM9513A Counter/Timer Registers */ 64#define AM9513A_DATA_REG 0x18 /* rw 16 */ 65#define AM9513A_COM_REG 0x1A /* wo 16 */ 66#define AM9513A_STAT_REG 0x1A /* ro 16 */ 67/* MIO-16 Digital I/O Registers */ 68#define MIO_16_DIG_IN_REG 0x1C /* ro 16 */ 69#define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */ 70/* RTSI Switch Registers */ 71#define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */ 72#define RTSI_SW_STROBE_REG 0x1F /* wo 8 */ 73/* DIO-24 Registers */ 74#define DIO_24_PORTA_REG 0x00 /* rw 8 */ 75#define DIO_24_PORTB_REG 0x01 /* rw 8 */ 76#define DIO_24_PORTC_REG 0x02 /* rw 8 */ 77#define DIO_24_CNFG_REG 0x03 /* wo 8 */ 78 79/* Command Register bits */ 80#define COMREG1_2SCADC 0x0001 81#define COMREG1_1632CNT 0x0002 82#define COMREG1_SCANEN 0x0008 83#define COMREG1_DAQEN 0x0010 84#define COMREG1_DMAEN 0x0020 85#define COMREG1_CONVINTEN 0x0080 86#define COMREG2_SCN2 0x0010 87#define COMREG2_INTEN 0x0080 88#define COMREG2_DOUTEN0 0x0100 89#define COMREG2_DOUTEN1 0x0200 90/* Status Register bits */ 91#define STAT_AD_OVERRUN 0x0100 92#define STAT_AD_OVERFLOW 0x0200 93#define STAT_AD_DAQPROG 0x0800 94#define STAT_AD_CONVAVAIL 0x2000 95#define STAT_AD_DAQSTOPINT 0x4000 96/* AM9513A Counter/Timer defines */ 97#define CLOCK_1_MHZ 0x8B25 98#define CLOCK_100_KHZ 0x8C25 99#define CLOCK_10_KHZ 0x8D25 100#define CLOCK_1_KHZ 0x8E25 101#define CLOCK_100_HZ 0x8F25 102/* Other miscellaneous defines */ 103#define ATMIO16D_SIZE 32 /* bus address range */ 104#define devpriv ((struct atmio16d_private *)dev->private) 105#define ATMIO16D_TIMEOUT 10 106 107struct atmio16_board_t { 108 109 const char *name; 110 int has_8255; 111}; 112 113static const struct atmio16_board_t atmio16_boards[] = { 114 { 115 .name = "atmio16", 116 .has_8255 = 0, 117 }, 118 { 119 .name = "atmio16d", 120 .has_8255 = 1, 121 }, 122}; 123 124#define n_atmio16_boards ARRAY_SIZE(atmio16_boards) 125 126#define boardtype ((const struct atmio16_board_t *)dev->board_ptr) 127 128/* function prototypes */ 129static int atmio16d_attach(struct comedi_device *dev, 130 struct comedi_devconfig *it); 131static int atmio16d_detach(struct comedi_device *dev); 132static irqreturn_t atmio16d_interrupt(int irq, void *d); 133static int atmio16d_ai_cmdtest(struct comedi_device *dev, 134 struct comedi_subdevice *s, 135 struct comedi_cmd *cmd); 136static int atmio16d_ai_cmd(struct comedi_device *dev, 137 struct comedi_subdevice *s); 138static int atmio16d_ai_cancel(struct comedi_device *dev, 139 struct comedi_subdevice *s); 140static void reset_counters(struct comedi_device *dev); 141static void reset_atmio16d(struct comedi_device *dev); 142 143/* main driver struct */ 144static struct comedi_driver driver_atmio16d = { 145 .driver_name = "atmio16", 146 .module = THIS_MODULE, 147 .attach = atmio16d_attach, 148 .detach = atmio16d_detach, 149 .board_name = &atmio16_boards[0].name, 150 .num_names = n_atmio16_boards, 151 .offset = sizeof(struct atmio16_board_t), 152}; 153 154static int __init driver_atmio16d_init_module(void) 155{ 156 return comedi_driver_register(&driver_atmio16d); 157} 158 159static void __exit driver_atmio16d_cleanup_module(void) 160{ 161 comedi_driver_unregister(&driver_atmio16d); 162} 163 164module_init(driver_atmio16d_init_module); 165module_exit(driver_atmio16d_cleanup_module); 166 167/* range structs */ 168static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, { 169 BIP_RANGE 170 (10), 171 BIP_RANGE 172 (1), 173 BIP_RANGE 174 (0.1), 175 BIP_RANGE 176 (0.02) 177 } 178}; 179 180static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, { 181 BIP_RANGE 182 (5), 183 BIP_RANGE 184 (0.5), 185 BIP_RANGE 186 (0.05), 187 BIP_RANGE 188 (0.01) 189 } 190}; 191 192static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, { 193 UNI_RANGE 194 (10), 195 UNI_RANGE 196 (1), 197 UNI_RANGE 198 (0.1), 199 UNI_RANGE 200 (0.02) 201 } 202}; 203 204/* private data struct */ 205struct atmio16d_private { 206 enum { adc_diff, adc_singleended } adc_mux; 207 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range; 208 enum { adc_2comp, adc_straight } adc_coding; 209 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range; 210 enum { dac_internal, dac_external } dac0_reference, dac1_reference; 211 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding; 212 const struct comedi_lrange *ao_range_type_list[2]; 213 unsigned int ao_readback[2]; 214 unsigned int com_reg_1_state; /* current state of command register 1 */ 215 unsigned int com_reg_2_state; /* current state of command register 2 */ 216}; 217 218static void reset_counters(struct comedi_device *dev) 219{ 220 /* Counter 2 */ 221 outw(0xFFC2, dev->iobase + AM9513A_COM_REG); 222 outw(0xFF02, dev->iobase + AM9513A_COM_REG); 223 outw(0x4, dev->iobase + AM9513A_DATA_REG); 224 outw(0xFF0A, dev->iobase + AM9513A_COM_REG); 225 outw(0x3, dev->iobase + AM9513A_DATA_REG); 226 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 227 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 228 /* Counter 3 */ 229 outw(0xFFC4, dev->iobase + AM9513A_COM_REG); 230 outw(0xFF03, dev->iobase + AM9513A_COM_REG); 231 outw(0x4, dev->iobase + AM9513A_DATA_REG); 232 outw(0xFF0B, dev->iobase + AM9513A_COM_REG); 233 outw(0x3, dev->iobase + AM9513A_DATA_REG); 234 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 235 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 236 /* Counter 4 */ 237 outw(0xFFC8, dev->iobase + AM9513A_COM_REG); 238 outw(0xFF04, dev->iobase + AM9513A_COM_REG); 239 outw(0x4, dev->iobase + AM9513A_DATA_REG); 240 outw(0xFF0C, dev->iobase + AM9513A_COM_REG); 241 outw(0x3, dev->iobase + AM9513A_DATA_REG); 242 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 243 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 244 /* Counter 5 */ 245 outw(0xFFD0, dev->iobase + AM9513A_COM_REG); 246 outw(0xFF05, dev->iobase + AM9513A_COM_REG); 247 outw(0x4, dev->iobase + AM9513A_DATA_REG); 248 outw(0xFF0D, dev->iobase + AM9513A_COM_REG); 249 outw(0x3, dev->iobase + AM9513A_DATA_REG); 250 outw(0xFF50, dev->iobase + AM9513A_COM_REG); 251 outw(0xFF50, dev->iobase + AM9513A_COM_REG); 252 253 outw(0, dev->iobase + AD_CLEAR_REG); 254} 255 256static void reset_atmio16d(struct comedi_device *dev) 257{ 258 int i; 259 260 /* now we need to initialize the board */ 261 outw(0, dev->iobase + COM_REG_1); 262 outw(0, dev->iobase + COM_REG_2); 263 outw(0, dev->iobase + MUX_GAIN_REG); 264 /* init AM9513A timer */ 265 outw(0xFFFF, dev->iobase + AM9513A_COM_REG); 266 outw(0xFFEF, dev->iobase + AM9513A_COM_REG); 267 outw(0xFF17, dev->iobase + AM9513A_COM_REG); 268 outw(0xF000, dev->iobase + AM9513A_DATA_REG); 269 for (i = 1; i <= 5; ++i) { 270 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG); 271 outw(0x0004, dev->iobase + AM9513A_DATA_REG); 272 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG); 273 outw(0x3, dev->iobase + AM9513A_DATA_REG); 274 } 275 outw(0xFF5F, dev->iobase + AM9513A_COM_REG); 276 /* timer init done */ 277 outw(0, dev->iobase + AD_CLEAR_REG); 278 outw(0, dev->iobase + INT2CLR_REG); 279 /* select straight binary mode for Analog Input */ 280 devpriv->com_reg_1_state |= 1; 281 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 282 devpriv->adc_coding = adc_straight; 283 /* zero the analog outputs */ 284 outw(2048, dev->iobase + DAC0_REG); 285 outw(2048, dev->iobase + DAC1_REG); 286} 287 288static irqreturn_t atmio16d_interrupt(int irq, void *d) 289{ 290 struct comedi_device *dev = d; 291 struct comedi_subdevice *s = dev->subdevices + 0; 292 293#ifdef DEBUG1 294 printk(KERN_DEBUG "atmio16d_interrupt!\n"); 295#endif 296 297 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG)); 298 299 comedi_event(dev, s); 300 return IRQ_HANDLED; 301} 302 303static int atmio16d_ai_cmdtest(struct comedi_device *dev, 304 struct comedi_subdevice *s, 305 struct comedi_cmd *cmd) 306{ 307 int err = 0, tmp; 308#ifdef DEBUG1 309 printk(KERN_DEBUG "atmio16d_ai_cmdtest\n"); 310#endif 311 /* make sure triggers are valid */ 312 tmp = cmd->start_src; 313 cmd->start_src &= TRIG_NOW; 314 if (!cmd->start_src || tmp != cmd->start_src) 315 err++; 316 317 tmp = cmd->scan_begin_src; 318 cmd->scan_begin_src &= TRIG_FOLLOW | TRIG_TIMER; 319 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 320 err++; 321 322 tmp = cmd->convert_src; 323 cmd->convert_src &= TRIG_TIMER; 324 if (!cmd->convert_src || tmp != cmd->convert_src) 325 err++; 326 327 tmp = cmd->scan_end_src; 328 cmd->scan_end_src &= TRIG_COUNT; 329 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 330 err++; 331 332 tmp = cmd->stop_src; 333 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 334 if (!cmd->stop_src || tmp != cmd->stop_src) 335 err++; 336 337 if (err) 338 return 1; 339 340 /* step 2: make sure trigger sources are unique & mutually compatible */ 341 /* note that mutual compatibility is not an issue here */ 342 if (cmd->scan_begin_src != TRIG_FOLLOW && 343 cmd->scan_begin_src != TRIG_EXT && 344 cmd->scan_begin_src != TRIG_TIMER) 345 err++; 346 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 347 err++; 348 349 if (err) 350 return 2; 351 352 /* step 3: make sure arguments are trivially compatible */ 353 354 if (cmd->start_arg != 0) { 355 cmd->start_arg = 0; 356 err++; 357 } 358 if (cmd->scan_begin_src == TRIG_FOLLOW) { 359 /* internal trigger */ 360 if (cmd->scan_begin_arg != 0) { 361 cmd->scan_begin_arg = 0; 362 err++; 363 } 364 } else { 365 } 366 367 if (cmd->convert_arg < 10000) { 368 cmd->convert_arg = 10000; 369 err++; 370 } 371 if (cmd->scan_end_arg != cmd->chanlist_len) { 372 cmd->scan_end_arg = cmd->chanlist_len; 373 err++; 374 } 375 if (cmd->stop_src == TRIG_COUNT) { 376 /* any count is allowed */ 377 } else { 378 /* TRIG_NONE */ 379 if (cmd->stop_arg != 0) { 380 cmd->stop_arg = 0; 381 err++; 382 } 383 } 384 385 if (err) 386 return 3; 387 388 return 0; 389} 390 391static int atmio16d_ai_cmd(struct comedi_device *dev, 392 struct comedi_subdevice *s) 393{ 394 struct comedi_cmd *cmd = &s->async->cmd; 395 unsigned int timer, base_clock; 396 unsigned int sample_count, tmp, chan, gain; 397 int i; 398#ifdef DEBUG1 399 printk(KERN_DEBUG "atmio16d_ai_cmd\n"); 400#endif 401 /* This is slowly becoming a working command interface. * 402 * It is still uber-experimental */ 403 404 reset_counters(dev); 405 s->async->cur_chan = 0; 406 407 /* check if scanning multiple channels */ 408 if (cmd->chanlist_len < 2) { 409 devpriv->com_reg_1_state &= ~COMREG1_SCANEN; 410 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 411 } else { 412 devpriv->com_reg_1_state |= COMREG1_SCANEN; 413 devpriv->com_reg_2_state |= COMREG2_SCN2; 414 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 415 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 416 } 417 418 /* Setup the Mux-Gain Counter */ 419 for (i = 0; i < cmd->chanlist_len; ++i) { 420 chan = CR_CHAN(cmd->chanlist[i]); 421 gain = CR_RANGE(cmd->chanlist[i]); 422 outw(i, dev->iobase + MUX_CNTR_REG); 423 tmp = chan | (gain << 6); 424 if (i == cmd->scan_end_arg - 1) 425 tmp |= 0x0010; /* set LASTONE bit */ 426 outw(tmp, dev->iobase + MUX_GAIN_REG); 427 } 428 429 /* Now program the sample interval timer */ 430 /* Figure out which clock to use then get an 431 * appropriate timer value */ 432 if (cmd->convert_arg < 65536000) { 433 base_clock = CLOCK_1_MHZ; 434 timer = cmd->convert_arg / 1000; 435 } else if (cmd->convert_arg < 655360000) { 436 base_clock = CLOCK_100_KHZ; 437 timer = cmd->convert_arg / 10000; 438 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) { 439 base_clock = CLOCK_10_KHZ; 440 timer = cmd->convert_arg / 100000; 441 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) { 442 base_clock = CLOCK_1_KHZ; 443 timer = cmd->convert_arg / 1000000; 444 } 445 outw(0xFF03, dev->iobase + AM9513A_COM_REG); 446 outw(base_clock, dev->iobase + AM9513A_DATA_REG); 447 outw(0xFF0B, dev->iobase + AM9513A_COM_REG); 448 outw(0x2, dev->iobase + AM9513A_DATA_REG); 449 outw(0xFF44, dev->iobase + AM9513A_COM_REG); 450 outw(0xFFF3, dev->iobase + AM9513A_COM_REG); 451 outw(timer, dev->iobase + AM9513A_DATA_REG); 452 outw(0xFF24, dev->iobase + AM9513A_COM_REG); 453 454 /* Now figure out how many samples to get */ 455 /* and program the sample counter */ 456 sample_count = cmd->stop_arg * cmd->scan_end_arg; 457 outw(0xFF04, dev->iobase + AM9513A_COM_REG); 458 outw(0x1025, dev->iobase + AM9513A_DATA_REG); 459 outw(0xFF0C, dev->iobase + AM9513A_COM_REG); 460 if (sample_count < 65536) { 461 /* use only Counter 4 */ 462 outw(sample_count, dev->iobase + AM9513A_DATA_REG); 463 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 464 outw(0xFFF4, dev->iobase + AM9513A_COM_REG); 465 outw(0xFF28, dev->iobase + AM9513A_COM_REG); 466 devpriv->com_reg_1_state &= ~COMREG1_1632CNT; 467 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 468 } else { 469 /* Counter 4 and 5 are needed */ 470 471 tmp = sample_count & 0xFFFF; 472 if (tmp) 473 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG); 474 else 475 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG); 476 477 outw(0xFF48, dev->iobase + AM9513A_COM_REG); 478 outw(0, dev->iobase + AM9513A_DATA_REG); 479 outw(0xFF28, dev->iobase + AM9513A_COM_REG); 480 outw(0xFF05, dev->iobase + AM9513A_COM_REG); 481 outw(0x25, dev->iobase + AM9513A_DATA_REG); 482 outw(0xFF0D, dev->iobase + AM9513A_COM_REG); 483 tmp = sample_count & 0xFFFF; 484 if ((tmp == 0) || (tmp == 1)) { 485 outw((sample_count >> 16) & 0xFFFF, 486 dev->iobase + AM9513A_DATA_REG); 487 } else { 488 outw(((sample_count >> 16) & 0xFFFF) + 1, 489 dev->iobase + AM9513A_DATA_REG); 490 } 491 outw(0xFF70, dev->iobase + AM9513A_COM_REG); 492 devpriv->com_reg_1_state |= COMREG1_1632CNT; 493 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 494 } 495 496 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */ 497 /* Figure out which clock to use then get an 498 * appropriate timer value */ 499 if (cmd->chanlist_len > 1) { 500 if (cmd->scan_begin_arg < 65536000) { 501 base_clock = CLOCK_1_MHZ; 502 timer = cmd->scan_begin_arg / 1000; 503 } else if (cmd->scan_begin_arg < 655360000) { 504 base_clock = CLOCK_100_KHZ; 505 timer = cmd->scan_begin_arg / 10000; 506 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) { 507 base_clock = CLOCK_10_KHZ; 508 timer = cmd->scan_begin_arg / 100000; 509 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) { 510 base_clock = CLOCK_1_KHZ; 511 timer = cmd->scan_begin_arg / 1000000; 512 } 513 outw(0xFF02, dev->iobase + AM9513A_COM_REG); 514 outw(base_clock, dev->iobase + AM9513A_DATA_REG); 515 outw(0xFF0A, dev->iobase + AM9513A_COM_REG); 516 outw(0x2, dev->iobase + AM9513A_DATA_REG); 517 outw(0xFF42, dev->iobase + AM9513A_COM_REG); 518 outw(0xFFF2, dev->iobase + AM9513A_COM_REG); 519 outw(timer, dev->iobase + AM9513A_DATA_REG); 520 outw(0xFF22, dev->iobase + AM9513A_COM_REG); 521 } 522 523 /* Clear the A/D FIFO and reset the MUX counter */ 524 outw(0, dev->iobase + AD_CLEAR_REG); 525 outw(0, dev->iobase + MUX_CNTR_REG); 526 outw(0, dev->iobase + INT2CLR_REG); 527 /* enable this acquisition operation */ 528 devpriv->com_reg_1_state |= COMREG1_DAQEN; 529 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 530 /* enable interrupts for conversion completion */ 531 devpriv->com_reg_1_state |= COMREG1_CONVINTEN; 532 devpriv->com_reg_2_state |= COMREG2_INTEN; 533 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1); 534 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 535 /* apply a trigger. this starts the counters! */ 536 outw(0, dev->iobase + START_DAQ_REG); 537 538 return 0; 539} 540 541/* This will cancel a running acquisition operation */ 542static int atmio16d_ai_cancel(struct comedi_device *dev, 543 struct comedi_subdevice *s) 544{ 545 reset_atmio16d(dev); 546 547 return 0; 548} 549 550/* Mode 0 is used to get a single conversion on demand */ 551static int atmio16d_ai_insn_read(struct comedi_device *dev, 552 struct comedi_subdevice *s, 553 struct comedi_insn *insn, unsigned int *data) 554{ 555 int i, t; 556 int chan; 557 int gain; 558 int status; 559 560#ifdef DEBUG1 561 printk(KERN_DEBUG "atmio16d_ai_insn_read\n"); 562#endif 563 chan = CR_CHAN(insn->chanspec); 564 gain = CR_RANGE(insn->chanspec); 565 566 /* reset the Analog input circuitry */ 567 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */ 568 /* reset the Analog Input MUX Counter to 0 */ 569 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */ 570 571 /* set the Input MUX gain */ 572 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG); 573 574 for (i = 0; i < insn->n; i++) { 575 /* start the conversion */ 576 outw(0, dev->iobase + START_CONVERT_REG); 577 /* wait for it to finish */ 578 for (t = 0; t < ATMIO16D_TIMEOUT; t++) { 579 /* check conversion status */ 580 status = inw(dev->iobase + STAT_REG); 581#ifdef DEBUG1 582 printk(KERN_DEBUG "status=%x\n", status); 583#endif 584 if (status & STAT_AD_CONVAVAIL) { 585 /* read the data now */ 586 data[i] = inw(dev->iobase + AD_FIFO_REG); 587 /* change to two's complement if need be */ 588 if (devpriv->adc_coding == adc_2comp) 589 data[i] ^= 0x800; 590 break; 591 } 592 if (status & STAT_AD_OVERFLOW) { 593 printk(KERN_INFO "atmio16d: a/d FIFO overflow\n"); 594 outw(0, dev->iobase + AD_CLEAR_REG); 595 596 return -ETIME; 597 } 598 } 599 /* end waiting, now check if it timed out */ 600 if (t == ATMIO16D_TIMEOUT) { 601 printk(KERN_INFO "atmio16d: timeout\n"); 602 603 return -ETIME; 604 } 605 } 606 607 return i; 608} 609 610static int atmio16d_ao_insn_read(struct comedi_device *dev, 611 struct comedi_subdevice *s, 612 struct comedi_insn *insn, unsigned int *data) 613{ 614 int i; 615#ifdef DEBUG1 616 printk(KERN_DEBUG "atmio16d_ao_insn_read\n"); 617#endif 618 619 for (i = 0; i < insn->n; i++) 620 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)]; 621 return i; 622} 623 624static int atmio16d_ao_insn_write(struct comedi_device *dev, 625 struct comedi_subdevice *s, 626 struct comedi_insn *insn, unsigned int *data) 627{ 628 int i; 629 int chan; 630 int d; 631#ifdef DEBUG1 632 printk(KERN_DEBUG "atmio16d_ao_insn_write\n"); 633#endif 634 635 chan = CR_CHAN(insn->chanspec); 636 637 for (i = 0; i < insn->n; i++) { 638 d = data[i]; 639 switch (chan) { 640 case 0: 641 if (devpriv->dac0_coding == dac_2comp) 642 d ^= 0x800; 643 outw(d, dev->iobase + DAC0_REG); 644 break; 645 case 1: 646 if (devpriv->dac1_coding == dac_2comp) 647 d ^= 0x800; 648 outw(d, dev->iobase + DAC1_REG); 649 break; 650 default: 651 return -EINVAL; 652 } 653 devpriv->ao_readback[chan] = data[i]; 654 } 655 return i; 656} 657 658static int atmio16d_dio_insn_bits(struct comedi_device *dev, 659 struct comedi_subdevice *s, 660 struct comedi_insn *insn, unsigned int *data) 661{ 662 if (insn->n != 2) 663 return -EINVAL; 664 665 if (data[0]) { 666 s->state &= ~data[0]; 667 s->state |= (data[0] | data[1]); 668 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG); 669 } 670 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG); 671 672 return 2; 673} 674 675static int atmio16d_dio_insn_config(struct comedi_device *dev, 676 struct comedi_subdevice *s, 677 struct comedi_insn *insn, 678 unsigned int *data) 679{ 680 int i; 681 int mask; 682 683 for (i = 0; i < insn->n; i++) { 684 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0; 685 s->io_bits &= ~mask; 686 if (data[i]) 687 s->io_bits |= mask; 688 } 689 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1); 690 if (s->io_bits & 0x0f) 691 devpriv->com_reg_2_state |= COMREG2_DOUTEN0; 692 if (s->io_bits & 0xf0) 693 devpriv->com_reg_2_state |= COMREG2_DOUTEN1; 694 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2); 695 696 return i; 697} 698 699/* 700 options[0] - I/O port 701 options[1] - MIO irq 702 0 == no irq 703 N == irq N {3,4,5,6,7,9,10,11,12,14,15} 704 options[2] - DIO irq 705 0 == no irq 706 N == irq N {3,4,5,6,7,9} 707 options[3] - DMA1 channel 708 0 == no DMA 709 N == DMA N {5,6,7} 710 options[4] - DMA2 channel 711 0 == no DMA 712 N == DMA N {5,6,7} 713 714 options[5] - a/d mux 715 0=differential, 1=single 716 options[6] - a/d range 717 0=bipolar10, 1=bipolar5, 2=unipolar10 718 719 options[7] - dac0 range 720 0=bipolar, 1=unipolar 721 options[8] - dac0 reference 722 0=internal, 1=external 723 options[9] - dac0 coding 724 0=2's comp, 1=straight binary 725 726 options[10] - dac1 range 727 options[11] - dac1 reference 728 options[12] - dac1 coding 729 */ 730 731static int atmio16d_attach(struct comedi_device *dev, 732 struct comedi_devconfig *it) 733{ 734 unsigned int irq; 735 unsigned long iobase; 736 int ret; 737 738 struct comedi_subdevice *s; 739 740 /* make sure the address range is free and allocate it */ 741 iobase = it->options[0]; 742 printk(KERN_INFO "comedi%d: atmio16d: 0x%04lx ", dev->minor, iobase); 743 if (!request_region(iobase, ATMIO16D_SIZE, "ni_atmio16d")) { 744 printk("I/O port conflict\n"); 745 return -EIO; 746 } 747 dev->iobase = iobase; 748 749 /* board name */ 750 dev->board_name = boardtype->name; 751 752 ret = alloc_subdevices(dev, 4); 753 if (ret < 0) 754 return ret; 755 756 ret = alloc_private(dev, sizeof(struct atmio16d_private)); 757 if (ret < 0) 758 return ret; 759 760 /* reset the atmio16d hardware */ 761 reset_atmio16d(dev); 762 763 /* check if our interrupt is available and get it */ 764 irq = it->options[1]; 765 if (irq) { 766 767 ret = request_irq(irq, atmio16d_interrupt, 0, "atmio16d", dev); 768 if (ret < 0) { 769 printk(KERN_INFO "failed to allocate irq %u\n", irq); 770 return ret; 771 } 772 dev->irq = irq; 773 printk(KERN_INFO "( irq = %u )\n", irq); 774 } else { 775 printk(KERN_INFO "( no irq )"); 776 } 777 778 /* set device options */ 779 devpriv->adc_mux = it->options[5]; 780 devpriv->adc_range = it->options[6]; 781 782 devpriv->dac0_range = it->options[7]; 783 devpriv->dac0_reference = it->options[8]; 784 devpriv->dac0_coding = it->options[9]; 785 devpriv->dac1_range = it->options[10]; 786 devpriv->dac1_reference = it->options[11]; 787 devpriv->dac1_coding = it->options[12]; 788 789 /* setup sub-devices */ 790 s = dev->subdevices + 0; 791 dev->read_subdev = s; 792 /* ai subdevice */ 793 s->type = COMEDI_SUBD_AI; 794 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ; 795 s->n_chan = (devpriv->adc_mux ? 16 : 8); 796 s->len_chanlist = 16; 797 s->insn_read = atmio16d_ai_insn_read; 798 s->do_cmdtest = atmio16d_ai_cmdtest; 799 s->do_cmd = atmio16d_ai_cmd; 800 s->cancel = atmio16d_ai_cancel; 801 s->maxdata = 0xfff; /* 4095 decimal */ 802 switch (devpriv->adc_range) { 803 case adc_bipolar10: 804 s->range_table = &range_atmio16d_ai_10_bipolar; 805 break; 806 case adc_bipolar5: 807 s->range_table = &range_atmio16d_ai_5_bipolar; 808 break; 809 case adc_unipolar10: 810 s->range_table = &range_atmio16d_ai_unipolar; 811 break; 812 } 813 814 /* ao subdevice */ 815 s++; 816 s->type = COMEDI_SUBD_AO; 817 s->subdev_flags = SDF_WRITABLE; 818 s->n_chan = 2; 819 s->insn_read = atmio16d_ao_insn_read; 820 s->insn_write = atmio16d_ao_insn_write; 821 s->maxdata = 0xfff; /* 4095 decimal */ 822 s->range_table_list = devpriv->ao_range_type_list; 823 switch (devpriv->dac0_range) { 824 case dac_bipolar: 825 devpriv->ao_range_type_list[0] = &range_bipolar10; 826 break; 827 case dac_unipolar: 828 devpriv->ao_range_type_list[0] = &range_unipolar10; 829 break; 830 } 831 switch (devpriv->dac1_range) { 832 case dac_bipolar: 833 devpriv->ao_range_type_list[1] = &range_bipolar10; 834 break; 835 case dac_unipolar: 836 devpriv->ao_range_type_list[1] = &range_unipolar10; 837 break; 838 } 839 840 /* Digital I/O */ 841 s++; 842 s->type = COMEDI_SUBD_DIO; 843 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 844 s->n_chan = 8; 845 s->insn_bits = atmio16d_dio_insn_bits; 846 s->insn_config = atmio16d_dio_insn_config; 847 s->maxdata = 1; 848 s->range_table = &range_digital; 849 850 /* 8255 subdevice */ 851 s++; 852 if (boardtype->has_8255) 853 subdev_8255_init(dev, s, NULL, dev->iobase); 854 else 855 s->type = COMEDI_SUBD_UNUSED; 856 857/* don't yet know how to deal with counter/timers */ 858 printk("\n"); 859 860 return 0; 861} 862 863static int atmio16d_detach(struct comedi_device *dev) 864{ 865 printk(KERN_INFO "comedi%d: atmio16d: remove\n", dev->minor); 866 867 if (dev->subdevices && boardtype->has_8255) 868 subdev_8255_cleanup(dev, dev->subdevices + 3); 869 870 if (dev->irq) 871 free_irq(dev->irq, dev); 872 873 reset_atmio16d(dev); 874 875 if (dev->iobase) 876 release_region(dev->iobase, ATMIO16D_SIZE); 877 878 return 0; 879} 880 881MODULE_AUTHOR("Comedi http://www.comedi.org"); 882MODULE_DESCRIPTION("Comedi low-level driver"); 883MODULE_LICENSE("GPL"); 884