1/* 2 * MPC52xx SPI bus driver. 3 * 4 * Copyright (C) 2008 Secret Lab Technologies Ltd. 5 * 6 * This file is released under the GPLv2 7 * 8 * This is the driver for the MPC5200's dedicated SPI controller. 9 * 10 * Note: this driver does not support the MPC5200 PSC in SPI mode. For 11 * that driver see drivers/spi/mpc52xx_psc_spi.c 12 */ 13 14#include <linux/module.h> 15#include <linux/init.h> 16#include <linux/errno.h> 17#include <linux/of_platform.h> 18#include <linux/interrupt.h> 19#include <linux/delay.h> 20#include <linux/spi/spi.h> 21#include <linux/io.h> 22#include <linux/of_gpio.h> 23#include <linux/slab.h> 24#include <asm/time.h> 25#include <asm/mpc52xx.h> 26 27MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); 28MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver"); 29MODULE_LICENSE("GPL"); 30 31/* Register offsets */ 32#define SPI_CTRL1 0x00 33#define SPI_CTRL1_SPIE (1 << 7) 34#define SPI_CTRL1_SPE (1 << 6) 35#define SPI_CTRL1_MSTR (1 << 4) 36#define SPI_CTRL1_CPOL (1 << 3) 37#define SPI_CTRL1_CPHA (1 << 2) 38#define SPI_CTRL1_SSOE (1 << 1) 39#define SPI_CTRL1_LSBFE (1 << 0) 40 41#define SPI_CTRL2 0x01 42#define SPI_BRR 0x04 43 44#define SPI_STATUS 0x05 45#define SPI_STATUS_SPIF (1 << 7) 46#define SPI_STATUS_WCOL (1 << 6) 47#define SPI_STATUS_MODF (1 << 4) 48 49#define SPI_DATA 0x09 50#define SPI_PORTDATA 0x0d 51#define SPI_DATADIR 0x10 52 53/* FSM state return values */ 54#define FSM_STOP 0 /* Nothing more for the state machine to */ 55 /* do. If something interesting happens */ 56 /* then an IRQ will be received */ 57#define FSM_POLL 1 /* need to poll for completion, an IRQ is */ 58 /* not expected */ 59#define FSM_CONTINUE 2 /* Keep iterating the state machine */ 60 61/* Driver internal data */ 62struct mpc52xx_spi { 63 struct spi_master *master; 64 void __iomem *regs; 65 int irq0; /* MODF irq */ 66 int irq1; /* SPIF irq */ 67 unsigned int ipb_freq; 68 69 /* Statistics; not used now, but will be reintroduced for debugfs */ 70 int msg_count; 71 int wcol_count; 72 int wcol_ticks; 73 u32 wcol_tx_timestamp; 74 int modf_count; 75 int byte_count; 76 77 struct list_head queue; /* queue of pending messages */ 78 spinlock_t lock; 79 struct work_struct work; 80 81 /* Details of current transfer (length, and buffer pointers) */ 82 struct spi_message *message; /* current message */ 83 struct spi_transfer *transfer; /* current transfer */ 84 int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data); 85 int len; 86 int timestamp; 87 u8 *rx_buf; 88 const u8 *tx_buf; 89 int cs_change; 90 int gpio_cs_count; 91 unsigned int *gpio_cs; 92}; 93 94/* 95 * CS control function 96 */ 97static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value) 98{ 99 int cs; 100 101 if (ms->gpio_cs_count > 0) { 102 cs = ms->message->spi->chip_select; 103 gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1); 104 } else 105 out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08); 106} 107 108/* 109 * Start a new transfer. This is called both by the idle state 110 * for the first transfer in a message, and by the wait state when the 111 * previous transfer in a message is complete. 112 */ 113static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms) 114{ 115 ms->rx_buf = ms->transfer->rx_buf; 116 ms->tx_buf = ms->transfer->tx_buf; 117 ms->len = ms->transfer->len; 118 119 /* Activate the chip select */ 120 if (ms->cs_change) 121 mpc52xx_spi_chipsel(ms, 1); 122 ms->cs_change = ms->transfer->cs_change; 123 124 /* Write out the first byte */ 125 ms->wcol_tx_timestamp = get_tbl(); 126 if (ms->tx_buf) 127 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); 128 else 129 out_8(ms->regs + SPI_DATA, 0); 130} 131 132/* Forward declaration of state handlers */ 133static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, 134 u8 status, u8 data); 135static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, 136 u8 status, u8 data); 137 138/* 139 * IDLE state 140 * 141 * No transfers are in progress; if another transfer is pending then retrieve 142 * it and kick it off. Otherwise, stop processing the state machine 143 */ 144static int 145mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) 146{ 147 struct spi_device *spi; 148 int spr, sppr; 149 u8 ctrl1; 150 151 if (status && (irq != NO_IRQ)) 152 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", 153 status); 154 155 /* Check if there is another transfer waiting. */ 156 if (list_empty(&ms->queue)) 157 return FSM_STOP; 158 159 /* get the head of the queue */ 160 ms->message = list_first_entry(&ms->queue, struct spi_message, queue); 161 list_del_init(&ms->message->queue); 162 163 /* Setup the controller parameters */ 164 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; 165 spi = ms->message->spi; 166 if (spi->mode & SPI_CPHA) 167 ctrl1 |= SPI_CTRL1_CPHA; 168 if (spi->mode & SPI_CPOL) 169 ctrl1 |= SPI_CTRL1_CPOL; 170 if (spi->mode & SPI_LSB_FIRST) 171 ctrl1 |= SPI_CTRL1_LSBFE; 172 out_8(ms->regs + SPI_CTRL1, ctrl1); 173 174 /* Setup the controller speed */ 175 /* minimum divider is '2'. Also, add '1' to force rounding the 176 * divider up. */ 177 sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1; 178 spr = 0; 179 if (sppr < 1) 180 sppr = 1; 181 while (((sppr - 1) & ~0x7) != 0) { 182 sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */ 183 spr++; 184 } 185 sppr--; /* sppr quantity in register is offset by 1 */ 186 if (spr > 7) { 187 /* Don't overrun limits of SPI baudrate register */ 188 spr = 7; 189 sppr = 7; 190 } 191 out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */ 192 193 ms->cs_change = 1; 194 ms->transfer = container_of(ms->message->transfers.next, 195 struct spi_transfer, transfer_list); 196 197 mpc52xx_spi_start_transfer(ms); 198 ms->state = mpc52xx_spi_fsmstate_transfer; 199 200 return FSM_CONTINUE; 201} 202 203/* 204 * TRANSFER state 205 * 206 * In the middle of a transfer. If the SPI core has completed processing 207 * a byte, then read out the received data and write out the next byte 208 * (unless this transfer is finished; in which case go on to the wait 209 * state) 210 */ 211static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, 212 u8 status, u8 data) 213{ 214 if (!status) 215 return ms->irq0 ? FSM_STOP : FSM_POLL; 216 217 if (status & SPI_STATUS_WCOL) { 218 /* The SPI controller is stoopid. At slower speeds, it may 219 * raise the SPIF flag before the state machine is actually 220 * finished, which causes a collision (internal to the state 221 * machine only). The manual recommends inserting a delay 222 * between receiving the interrupt and sending the next byte, 223 * but it can also be worked around simply by retrying the 224 * transfer which is what we do here. */ 225 ms->wcol_count++; 226 ms->wcol_ticks += get_tbl() - ms->wcol_tx_timestamp; 227 ms->wcol_tx_timestamp = get_tbl(); 228 data = 0; 229 if (ms->tx_buf) 230 data = *(ms->tx_buf - 1); 231 out_8(ms->regs + SPI_DATA, data); /* try again */ 232 return FSM_CONTINUE; 233 } else if (status & SPI_STATUS_MODF) { 234 ms->modf_count++; 235 dev_err(&ms->master->dev, "mode fault\n"); 236 mpc52xx_spi_chipsel(ms, 0); 237 ms->message->status = -EIO; 238 ms->message->complete(ms->message->context); 239 ms->state = mpc52xx_spi_fsmstate_idle; 240 return FSM_CONTINUE; 241 } 242 243 /* Read data out of the spi device */ 244 ms->byte_count++; 245 if (ms->rx_buf) 246 *ms->rx_buf++ = data; 247 248 /* Is the transfer complete? */ 249 ms->len--; 250 if (ms->len == 0) { 251 ms->timestamp = get_tbl(); 252 ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec; 253 ms->state = mpc52xx_spi_fsmstate_wait; 254 return FSM_CONTINUE; 255 } 256 257 /* Write out the next byte */ 258 ms->wcol_tx_timestamp = get_tbl(); 259 if (ms->tx_buf) 260 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); 261 else 262 out_8(ms->regs + SPI_DATA, 0); 263 264 return FSM_CONTINUE; 265} 266 267/* 268 * WAIT state 269 * 270 * A transfer has completed; need to wait for the delay period to complete 271 * before starting the next transfer 272 */ 273static int 274mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) 275{ 276 if (status && irq) 277 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", 278 status); 279 280 if (((int)get_tbl()) - ms->timestamp < 0) 281 return FSM_POLL; 282 283 ms->message->actual_length += ms->transfer->len; 284 285 /* Check if there is another transfer in this message. If there 286 * aren't then deactivate CS, notify sender, and drop back to idle 287 * to start the next message. */ 288 if (ms->transfer->transfer_list.next == &ms->message->transfers) { 289 ms->msg_count++; 290 mpc52xx_spi_chipsel(ms, 0); 291 ms->message->status = 0; 292 ms->message->complete(ms->message->context); 293 ms->state = mpc52xx_spi_fsmstate_idle; 294 return FSM_CONTINUE; 295 } 296 297 /* There is another transfer; kick it off */ 298 299 if (ms->cs_change) 300 mpc52xx_spi_chipsel(ms, 0); 301 302 ms->transfer = container_of(ms->transfer->transfer_list.next, 303 struct spi_transfer, transfer_list); 304 mpc52xx_spi_start_transfer(ms); 305 ms->state = mpc52xx_spi_fsmstate_transfer; 306 return FSM_CONTINUE; 307} 308 309/** 310 * mpc52xx_spi_fsm_process - Finite State Machine iteration function 311 * @irq: irq number that triggered the FSM or 0 for polling 312 * @ms: pointer to mpc52xx_spi driver data 313 */ 314static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms) 315{ 316 int rc = FSM_CONTINUE; 317 u8 status, data; 318 319 while (rc == FSM_CONTINUE) { 320 /* Interrupt cleared by read of STATUS followed by 321 * read of DATA registers */ 322 status = in_8(ms->regs + SPI_STATUS); 323 data = in_8(ms->regs + SPI_DATA); 324 rc = ms->state(irq, ms, status, data); 325 } 326 327 if (rc == FSM_POLL) 328 schedule_work(&ms->work); 329} 330 331/** 332 * mpc52xx_spi_irq - IRQ handler 333 */ 334static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms) 335{ 336 struct mpc52xx_spi *ms = _ms; 337 spin_lock(&ms->lock); 338 mpc52xx_spi_fsm_process(irq, ms); 339 spin_unlock(&ms->lock); 340 return IRQ_HANDLED; 341} 342 343/** 344 * mpc52xx_spi_wq - Workqueue function for polling the state machine 345 */ 346static void mpc52xx_spi_wq(struct work_struct *work) 347{ 348 struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work); 349 unsigned long flags; 350 351 spin_lock_irqsave(&ms->lock, flags); 352 mpc52xx_spi_fsm_process(0, ms); 353 spin_unlock_irqrestore(&ms->lock, flags); 354} 355 356/* 357 * spi_master ops 358 */ 359 360static int mpc52xx_spi_setup(struct spi_device *spi) 361{ 362 if (spi->bits_per_word % 8) 363 return -EINVAL; 364 365 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) 366 return -EINVAL; 367 368 if (spi->chip_select >= spi->master->num_chipselect) 369 return -EINVAL; 370 371 return 0; 372} 373 374static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) 375{ 376 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master); 377 unsigned long flags; 378 379 m->actual_length = 0; 380 m->status = -EINPROGRESS; 381 382 spin_lock_irqsave(&ms->lock, flags); 383 list_add_tail(&m->queue, &ms->queue); 384 spin_unlock_irqrestore(&ms->lock, flags); 385 schedule_work(&ms->work); 386 387 return 0; 388} 389 390/* 391 * OF Platform Bus Binding 392 */ 393static int __devinit mpc52xx_spi_probe(struct platform_device *op, 394 const struct of_device_id *match) 395{ 396 struct spi_master *master; 397 struct mpc52xx_spi *ms; 398 void __iomem *regs; 399 u8 ctrl1; 400 int rc, i = 0; 401 int gpio_cs; 402 403 /* MMIO registers */ 404 dev_dbg(&op->dev, "probing mpc5200 SPI device\n"); 405 regs = of_iomap(op->dev.of_node, 0); 406 if (!regs) 407 return -ENODEV; 408 409 /* initialize the device */ 410 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; 411 out_8(regs + SPI_CTRL1, ctrl1); 412 out_8(regs + SPI_CTRL2, 0x0); 413 out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */ 414 out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */ 415 416 /* Clear the status register and re-read it to check for a MODF 417 * failure. This driver cannot currently handle multiple masters 418 * on the SPI bus. This fault will also occur if the SPI signals 419 * are not connected to any pins (port_config setting) */ 420 in_8(regs + SPI_STATUS); 421 out_8(regs + SPI_CTRL1, ctrl1); 422 423 in_8(regs + SPI_DATA); 424 if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) { 425 dev_err(&op->dev, "mode fault; is port_config correct?\n"); 426 rc = -EIO; 427 goto err_init; 428 } 429 430 dev_dbg(&op->dev, "allocating spi_master struct\n"); 431 master = spi_alloc_master(&op->dev, sizeof *ms); 432 if (!master) { 433 rc = -ENOMEM; 434 goto err_alloc; 435 } 436 437 master->bus_num = -1; 438 master->setup = mpc52xx_spi_setup; 439 master->transfer = mpc52xx_spi_transfer; 440 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 441 master->dev.of_node = op->dev.of_node; 442 443 dev_set_drvdata(&op->dev, master); 444 445 ms = spi_master_get_devdata(master); 446 ms->master = master; 447 ms->regs = regs; 448 ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0); 449 ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1); 450 ms->state = mpc52xx_spi_fsmstate_idle; 451 ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node); 452 ms->gpio_cs_count = of_gpio_count(op->dev.of_node); 453 if (ms->gpio_cs_count > 0) { 454 master->num_chipselect = ms->gpio_cs_count; 455 ms->gpio_cs = kmalloc(ms->gpio_cs_count * sizeof(unsigned int), 456 GFP_KERNEL); 457 if (!ms->gpio_cs) { 458 rc = -ENOMEM; 459 goto err_alloc; 460 } 461 462 for (i = 0; i < ms->gpio_cs_count; i++) { 463 gpio_cs = of_get_gpio(op->dev.of_node, i); 464 if (gpio_cs < 0) { 465 dev_err(&op->dev, 466 "could not parse the gpio field " 467 "in oftree\n"); 468 rc = -ENODEV; 469 goto err_gpio; 470 } 471 472 rc = gpio_request(gpio_cs, dev_name(&op->dev)); 473 if (rc) { 474 dev_err(&op->dev, 475 "can't request spi cs gpio #%d " 476 "on gpio line %d\n", i, gpio_cs); 477 goto err_gpio; 478 } 479 480 gpio_direction_output(gpio_cs, 1); 481 ms->gpio_cs[i] = gpio_cs; 482 } 483 } else { 484 master->num_chipselect = 1; 485 } 486 487 spin_lock_init(&ms->lock); 488 INIT_LIST_HEAD(&ms->queue); 489 INIT_WORK(&ms->work, mpc52xx_spi_wq); 490 491 /* Decide if interrupts can be used */ 492 if (ms->irq0 && ms->irq1) { 493 rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0, 494 "mpc5200-spi-modf", ms); 495 rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0, 496 "mpc5200-spi-spif", ms); 497 if (rc) { 498 free_irq(ms->irq0, ms); 499 free_irq(ms->irq1, ms); 500 ms->irq0 = ms->irq1 = 0; 501 } 502 } else { 503 /* operate in polled mode */ 504 ms->irq0 = ms->irq1 = 0; 505 } 506 507 if (!ms->irq0) 508 dev_info(&op->dev, "using polled mode\n"); 509 510 dev_dbg(&op->dev, "registering spi_master struct\n"); 511 rc = spi_register_master(master); 512 if (rc) 513 goto err_register; 514 515 dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n"); 516 517 return rc; 518 519 err_register: 520 dev_err(&ms->master->dev, "initialization failed\n"); 521 spi_master_put(master); 522 err_gpio: 523 while (i-- > 0) 524 gpio_free(ms->gpio_cs[i]); 525 526 kfree(ms->gpio_cs); 527 err_alloc: 528 err_init: 529 iounmap(regs); 530 return rc; 531} 532 533static int __devexit mpc52xx_spi_remove(struct platform_device *op) 534{ 535 struct spi_master *master = dev_get_drvdata(&op->dev); 536 struct mpc52xx_spi *ms = spi_master_get_devdata(master); 537 int i; 538 539 free_irq(ms->irq0, ms); 540 free_irq(ms->irq1, ms); 541 542 for (i = 0; i < ms->gpio_cs_count; i++) 543 gpio_free(ms->gpio_cs[i]); 544 545 kfree(ms->gpio_cs); 546 spi_unregister_master(master); 547 spi_master_put(master); 548 iounmap(ms->regs); 549 550 return 0; 551} 552 553static const struct of_device_id mpc52xx_spi_match[] __devinitconst = { 554 { .compatible = "fsl,mpc5200-spi", }, 555 {} 556}; 557MODULE_DEVICE_TABLE(of, mpc52xx_spi_match); 558 559static struct of_platform_driver mpc52xx_spi_of_driver = { 560 .driver = { 561 .name = "mpc52xx-spi", 562 .owner = THIS_MODULE, 563 .of_match_table = mpc52xx_spi_match, 564 }, 565 .probe = mpc52xx_spi_probe, 566 .remove = __exit_p(mpc52xx_spi_remove), 567}; 568 569static int __init mpc52xx_spi_init(void) 570{ 571 return of_register_platform_driver(&mpc52xx_spi_of_driver); 572} 573module_init(mpc52xx_spi_init); 574 575static void __exit mpc52xx_spi_exit(void) 576{ 577 of_unregister_platform_driver(&mpc52xx_spi_of_driver); 578} 579module_exit(mpc52xx_spi_exit); 580