1#include <linux/serial_core.h> 2#include <linux/io.h> 3#include <linux/gpio.h> 4 5#if defined(CONFIG_H83007) || defined(CONFIG_H83068) 6#include <asm/regs306x.h> 7#endif 8#if defined(CONFIG_H8S2678) 9#include <asm/regs267x.h> 10#endif 11 12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 13 defined(CONFIG_CPU_SUBTYPE_SH7708) || defined(CONFIG_CPU_SUBTYPE_SH7709) 14# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 15# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 16# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 17#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 18# define SCIF0 0xA4400000 19# define SCIF2 0xA4410000 20# define SCSMR_Ir 0xA44A0000 21# define IRDA_SCIF SCIF0 22# define SCPCR 0xA4000116 23# define SCPDR 0xA4000136 24 25/* Set the clock source, 26 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input 27 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 28 */ 29# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 30#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 31 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 32 defined(CONFIG_ARCH_SH7367) || \ 33 defined(CONFIG_ARCH_SH7377) || \ 34 defined(CONFIG_ARCH_SH7372) 35# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 36# define PORT_PTCR 0xA405011EUL 37# define PORT_PVCR 0xA4050122UL 38# define SCIF_ORER 0x0200 /* overrun error bit */ 39#elif defined(CONFIG_SH_RTS7751R2D) 40# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 41# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 42# define SCIF_ORER 0x0001 /* overrun error bit */ 43# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 44#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 45 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 46 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 47 defined(CONFIG_CPU_SUBTYPE_SH7091) || \ 48 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 49 defined(CONFIG_CPU_SUBTYPE_SH7751R) 50# define SCSPTR1 0xffe0001c /* 8 bit SCI */ 51# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 52# define SCIF_ORER 0x0001 /* overrun error bit */ 53# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 54 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 55 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) 56#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 57# define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 58# define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 59# define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 60# define SCIF_ORER 0x0001 /* overrun error bit */ 61# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 62#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 63# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 64# define SCIF_ORER 0x0001 /* overrun error bit */ 65# define PACR 0xa4050100 66# define PBCR 0xa4050102 67# define SCSCR_INIT(port) 0x3B 68#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 69# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 70# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 71# define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 72# define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 73# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 74#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 75# define PADR 0xA4050120 76# define PSDR 0xA405013e 77# define PWDR 0xA4050166 78# define PSCR 0xA405011E 79# define SCIF_ORER 0x0001 /* overrun error bit */ 80# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 81#elif defined(CONFIG_CPU_SUBTYPE_SH7366) 82# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 83# define SCSPTR0 SCPDR0 84# define SCIF_ORER 0x0001 /* overrun error bit */ 85# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 86#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 87# define SCSPTR0 0xa4050160 88# define SCSPTR1 0xa405013e 89# define SCSPTR2 0xa4050160 90# define SCSPTR3 0xa405013e 91# define SCSPTR4 0xa4050128 92# define SCSPTR5 0xa4050128 93# define SCIF_ORER 0x0001 /* overrun error bit */ 94# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 95#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 96# define SCIF_ORER 0x0001 /* overrun error bit */ 97# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ 98 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 99 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) 100#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 101# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 102# define SCIF_ORER 0x0001 /* overrun error bit */ 103# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 104#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 105# define SCIF_BASE_ADDR 0x01030000 106# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR 107# define SCIF_PTR2_OFFS 0x0000020 108# define SCIF_LSR2_OFFS 0x0000024 109# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 110# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 111# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ 112#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 113# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 114# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 115#elif defined(CONFIG_H8S2678) 116# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 117# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 118#elif defined(CONFIG_CPU_SUBTYPE_SH7757) 119# define SCSPTR0 0xfe4b0020 120# define SCSPTR1 0xfe4b0020 121# define SCSPTR2 0xfe4b0020 122# define SCIF_ORER 0x0001 123# define SCSCR_INIT(port) 0x38 124# define SCIF_ONLY 125#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 126# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 127# define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 128# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 129# define SCIF_ORER 0x0001 /* overrun error bit */ 130# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 131#elif defined(CONFIG_CPU_SUBTYPE_SH7770) 132# define SCSPTR0 0xff923020 /* 16 bit SCIF */ 133# define SCSPTR1 0xff924020 /* 16 bit SCIF */ 134# define SCSPTR2 0xff925020 /* 16 bit SCIF */ 135# define SCIF_ORER 0x0001 /* overrun error bit */ 136# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 137#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 138# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 139# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 140# define SCIF_ORER 0x0001 /* Overrun error bit */ 141# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 142#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 143 defined(CONFIG_CPU_SUBTYPE_SH7786) 144# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 145# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 146# define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 147# define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 148# define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 149# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 150# define SCIF_ORER 0x0001 /* Overrun error bit */ 151# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 152#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ 153 defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 154 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 155 defined(CONFIG_CPU_SUBTYPE_SH7263) 156# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 157# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 158# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 159# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 160# if defined(CONFIG_CPU_SUBTYPE_SH7201) 161# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ 162# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ 163# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 164# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 165# endif 166# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 167#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 168# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 169# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 170# define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 171# define SCIF_ORER 0x0001 /* overrun error bit */ 172# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 173#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 174# define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 175# define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 176# define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 177# define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 178# define SCIF_ORER 0x0001 /* Overrun error bit */ 179# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 180#else 181# error CPU subtype not defined 182#endif 183 184/* SCSCR */ 185#define SCI_CTRL_FLAGS_TIE 0x80 /* all */ 186#define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 187#define SCI_CTRL_FLAGS_TE 0x20 /* all */ 188#define SCI_CTRL_FLAGS_RE 0x10 /* all */ 189#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) || \ 190 defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 191 defined(CONFIG_CPU_SUBTYPE_SH7750S) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 192 defined(CONFIG_CPU_SUBTYPE_SH7751R) || defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 193 defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 194 defined(CONFIG_CPU_SUBTYPE_SH7786) || defined(CONFIG_CPU_SUBTYPE_SHX3) 195#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 196#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 197#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) 198#else 199#define SCI_CTRL_FLAGS_REIE 0 200#endif 201/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 202/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 203/* SCI_CTRL_FLAGS_CKE1 0x02 * all */ 204/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ 205 206/* SCxSR SCI */ 207#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 208#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 209#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 210#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 211#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 212#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 213/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 214/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 215 216#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 217 218/* SCxSR SCIF */ 219#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 220#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 221#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 222#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 223#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 224#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 225#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 226#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 227 228#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 229 defined(CONFIG_CPU_SUBTYPE_SH7721) || defined(CONFIG_ARCH_SH7367) || \ 230 defined(CONFIG_ARCH_SH7377) || defined(CONFIG_ARCH_SH7372) 231# define SCIF_ORER 0x0200 232# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 233# define SCIF_RFDC_MASK 0x007f 234# define SCIF_TXROOM_MAX 64 235#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 236# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK ) 237# define SCIF_RFDC_MASK 0x007f 238# define SCIF_TXROOM_MAX 64 239/* SH7763 SCIF2 support */ 240# define SCIF2_RFDC_MASK 0x001f 241# define SCIF2_TXROOM_MAX 16 242#else 243# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 244# define SCIF_RFDC_MASK 0x001f 245# define SCIF_TXROOM_MAX 16 246#endif 247 248#ifndef SCIF_ORER 249#define SCIF_ORER 0x0000 250#endif 251 252#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 253#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 254#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 255#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 256#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 257#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 258#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 259#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 260 261#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 262 defined(CONFIG_CPU_SUBTYPE_SH7721) || defined(CONFIG_ARCH_SH7367) || \ 263 defined(CONFIG_ARCH_SH7377) || defined(CONFIG_ARCH_SH7372) 264# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 265# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 266# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 267# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) 268#else 269# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 270# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 271# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 272# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 273#endif 274 275/* SCFCR */ 276#define SCFCR_RFRST 0x0002 277#define SCFCR_TFRST 0x0004 278#define SCFCR_TCRST 0x4000 279#define SCFCR_MCE 0x0008 280 281#define SCI_MAJOR 204 282#define SCI_MINOR_START 8 283 284/* Generic serial flags */ 285#define SCI_RX_THROTTLE 0x0000001 286 287#define SCI_MAGIC 0xbabeface 288 289/* 290 * Events are used to schedule things to happen at timer-interrupt 291 * time, instead of at rs interrupt time. 292 */ 293#define SCI_EVENT_WRITE_WAKEUP 0 294 295#define SCI_IN(size, offset) \ 296 if ((size) == 8) { \ 297 return ioread8(port->membase + (offset)); \ 298 } else { \ 299 return ioread16(port->membase + (offset)); \ 300 } 301#define SCI_OUT(size, offset, value) \ 302 if ((size) == 8) { \ 303 iowrite8(value, port->membase + (offset)); \ 304 } else if ((size) == 16) { \ 305 iowrite16(value, port->membase + (offset)); \ 306 } 307 308#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 309 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 310 { \ 311 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \ 312 SCI_IN(scif_size, scif_offset) \ 313 } else { /* PORT_SCI or PORT_SCIFA */ \ 314 SCI_IN(sci_size, sci_offset); \ 315 } \ 316 } \ 317 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 318 { \ 319 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \ 320 SCI_OUT(scif_size, scif_offset, value) \ 321 } else { /* PORT_SCI or PORT_SCIFA */ \ 322 SCI_OUT(sci_size, sci_offset, value); \ 323 } \ 324 } 325 326#ifdef CONFIG_H8300 327/* h8300 don't have SCIF */ 328#define CPU_SCIF_FNS(name) \ 329 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 330 { \ 331 return 0; \ 332 } \ 333 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 334 { \ 335 } 336#else 337#define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 338 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 339 { \ 340 SCI_IN(scif_size, scif_offset); \ 341 } \ 342 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 343 { \ 344 SCI_OUT(scif_size, scif_offset, value); \ 345 } 346#endif 347 348#define CPU_SCI_FNS(name, sci_offset, sci_size) \ 349 static inline unsigned int sci_##name##_in(struct uart_port* port) \ 350 { \ 351 SCI_IN(sci_size, sci_offset); \ 352 } \ 353 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ 354 { \ 355 SCI_OUT(sci_size, sci_offset, value); \ 356 } 357 358#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SH7367) || \ 359 defined(CONFIG_ARCH_SH7377) || defined(CONFIG_ARCH_SH7372) 360#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 361#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 362 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 363 h8_sci_offset, h8_sci_size) \ 364 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 365#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 366 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 367#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 368 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 369 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 370 defined(CONFIG_ARCH_SH7367) || \ 371 defined(CONFIG_ARCH_SH7377) 372#define SCIF_FNS(name, scif_offset, scif_size) \ 373 CPU_SCIF_FNS(name, scif_offset, scif_size) 374#elif defined(CONFIG_ARCH_SH7372) 375#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \ 376 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) 377#define SCIF_FNS(name, scif_offset, scif_size) \ 378 CPU_SCIF_FNS(name, scif_offset, scif_size) 379#else 380#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 381 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 382 h8_sci_offset, h8_sci_size) \ 383 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) 384#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 385 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 386#endif 387#elif defined(__H8300H__) || defined(__H8300S__) 388#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 389 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 390 h8_sci_offset, h8_sci_size) \ 391 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 392#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 393 CPU_SCIF_FNS(name) 394#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 395 defined(CONFIG_CPU_SUBTYPE_SH7724) 396 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ 397 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) 398 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 399 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 400#else 401#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 402 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 403 h8_sci_offset, h8_sci_size) \ 404 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 405#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 406 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 407#endif 408 409#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 410 defined(CONFIG_CPU_SUBTYPE_SH7721) || defined(CONFIG_ARCH_SH7367) || \ 411 defined(CONFIG_ARCH_SH7377) 412 413SCIF_FNS(SCSMR, 0x00, 16) 414SCIF_FNS(SCBRR, 0x04, 8) 415SCIF_FNS(SCSCR, 0x08, 16) 416SCIF_FNS(SCTDSR, 0x0c, 8) 417SCIF_FNS(SCFER, 0x10, 16) 418SCIF_FNS(SCxSR, 0x14, 16) 419SCIF_FNS(SCFCR, 0x18, 16) 420SCIF_FNS(SCFDR, 0x1c, 16) 421SCIF_FNS(SCxTDR, 0x20, 8) 422SCIF_FNS(SCxRDR, 0x24, 8) 423SCIF_FNS(SCLSR, 0x00, 0) 424#elif defined(CONFIG_ARCH_SH7372) 425SCIF_FNS(SCSMR, 0x00, 16) 426SCIF_FNS(SCBRR, 0x04, 8) 427SCIF_FNS(SCSCR, 0x08, 16) 428SCIF_FNS(SCTDSR, 0x0c, 16) 429SCIF_FNS(SCFER, 0x10, 16) 430SCIF_FNS(SCxSR, 0x14, 16) 431SCIF_FNS(SCFCR, 0x18, 16) 432SCIF_FNS(SCFDR, 0x1c, 16) 433SCIF_FNS(SCTFDR, 0x38, 16) 434SCIF_FNS(SCRFDR, 0x3c, 16) 435SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) 436SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) 437SCIF_FNS(SCLSR, 0x00, 0) 438#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 439 defined(CONFIG_CPU_SUBTYPE_SH7724) 440SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 441SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 442SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 443SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) 444SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 445SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 446SCIx_FNS(SCSPTR, 0, 0, 0, 0) 447SCIF_FNS(SCTDSR, 0x0c, 8) 448SCIF_FNS(SCFER, 0x10, 16) 449SCIF_FNS(SCFCR, 0x18, 16) 450SCIF_FNS(SCFDR, 0x1c, 16) 451SCIF_FNS(SCLSR, 0x24, 16) 452#else 453/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 454/* name off sz off sz off sz off sz off sz*/ 455SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 456SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 457SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 458SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 459SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 460SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 461SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 462#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 463 defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7786) 464SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 465SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 466SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 467SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 468SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 469#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 470SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 471SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 472SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) 473SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 474SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 475SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 476SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 477#else 478SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 479#if defined(CONFIG_CPU_SUBTYPE_SH7722) 480SCIF_FNS(SCSPTR, 0, 0, 0, 0) 481#else 482SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 483#endif 484SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 485#endif 486#endif 487#define sci_in(port, reg) sci_##reg##_in(port) 488#define sci_out(port, reg, value) sci_##reg##_out(port, value) 489 490/* H8/300 series SCI pins assignment */ 491#if defined(__H8300H__) || defined(__H8300S__) 492static const struct __attribute__((packed)) { 493 int port; /* GPIO port no */ 494 unsigned short rx,tx; /* GPIO bit no */ 495} h8300_sci_pins[] = { 496#if defined(CONFIG_H83007) || defined(CONFIG_H83068) 497 { /* SCI0 */ 498 .port = H8300_GPIO_P9, 499 .rx = H8300_GPIO_B2, 500 .tx = H8300_GPIO_B0, 501 }, 502 { /* SCI1 */ 503 .port = H8300_GPIO_P9, 504 .rx = H8300_GPIO_B3, 505 .tx = H8300_GPIO_B1, 506 }, 507 { /* SCI2 */ 508 .port = H8300_GPIO_PB, 509 .rx = H8300_GPIO_B7, 510 .tx = H8300_GPIO_B6, 511 } 512#elif defined(CONFIG_H8S2678) 513 { /* SCI0 */ 514 .port = H8300_GPIO_P3, 515 .rx = H8300_GPIO_B2, 516 .tx = H8300_GPIO_B0, 517 }, 518 { /* SCI1 */ 519 .port = H8300_GPIO_P3, 520 .rx = H8300_GPIO_B3, 521 .tx = H8300_GPIO_B1, 522 }, 523 { /* SCI2 */ 524 .port = H8300_GPIO_P5, 525 .rx = H8300_GPIO_B1, 526 .tx = H8300_GPIO_B0, 527 } 528#endif 529}; 530#endif 531 532#if defined(CONFIG_CPU_SUBTYPE_SH7706) || defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 533 defined(CONFIG_CPU_SUBTYPE_SH7708) || defined(CONFIG_CPU_SUBTYPE_SH7709) 534static inline int sci_rxd_in(struct uart_port *port) 535{ 536 if (port->mapbase == 0xfffffe80) 537 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 538 return 1; 539} 540#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 541 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 542 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ 543 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 544 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 545 defined(CONFIG_CPU_SUBTYPE_SH7091) 546static inline int sci_rxd_in(struct uart_port *port) 547{ 548 if (port->mapbase == 0xffe00000) 549 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 550 return 1; 551} 552#elif defined(__H8300H__) || defined(__H8300S__) 553static inline int sci_rxd_in(struct uart_port *port) 554{ 555 int ch = (port->mapbase - SMR0) >> 3; 556 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 557} 558#else /* default case for non-SCI processors */ 559static inline int sci_rxd_in(struct uart_port *port) 560{ 561 return 1; 562} 563#endif 564 565/* 566 * Values for the BitRate Register (SCBRR) 567 * 568 * The values are actually divisors for a frequency which can 569 * be internal to the SH3 (14.7456MHz) or derived from an external 570 * clock source. This driver assumes the internal clock is used; 571 * to support using an external clock source, config options or 572 * possibly command-line options would need to be added. 573 * 574 * Also, to support speeds below 2400 (why?) the lower 2 bits of 575 * the SCSMR register would also need to be set to non-zero values. 576 * 577 * -- Greg Banks 27Feb2000 578 * 579 * Answer: The SCBRR register is only eight bits, and the value in 580 * it gets larger with lower baud rates. At around 2400 (depending on 581 * the peripherial module clock) you run out of bits. However the 582 * lower two bits of SCSMR allow the module clock to be divided down, 583 * scaling the value which is needed in SCBRR. 584 * 585 * -- Stuart Menefy - 23 May 2000 586 * 587 * I meant, why would anyone bother with bitrates below 2400. 588 * 589 * -- Greg Banks - 7Jul2000 590 * 591 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper 592 * tape reader as a console! 593 * 594 * -- Mitch Davis - 15 Jul 2000 595 */ 596 597#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 598 defined(CONFIG_CPU_SUBTYPE_SH7786) 599#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 600#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 601 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 602 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 603 defined(CONFIG_ARCH_SH7367) || \ 604 defined(CONFIG_ARCH_SH7377) || \ 605 defined(CONFIG_ARCH_SH7372) 606#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 607#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ 608 defined(CONFIG_CPU_SUBTYPE_SH7724) 609static inline int scbrr_calc(struct uart_port *port, int bps, int clk) 610{ 611 if (port->type == PORT_SCIF) 612 return (clk+16*bps)/(32*bps)-1; 613 else 614 return ((clk*2)+16*bps)/(16*bps)-1; 615} 616#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) 617#elif defined(__H8300H__) || defined(__H8300S__) 618#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) 619#else /* Generic SH */ 620#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 621#endif 622