1/* 2 * Copyright (c) 2000-2010 LSI Corporation. 3 * 4 * 5 * Name: mpi2_cnfg.h 6 * Title: MPI Configuration messages and pages 7 * Creation Date: November 10, 2006 8 * 9 * mpi2_cnfg.h Version: 02.00.14 10 * 11 * Version History 12 * --------------- 13 * 14 * Date Version Description 15 * -------- -------- ------------------------------------------------------ 16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 18 * Added Manufacturing Page 11. 19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 20 * define. 21 * 06-26-07 02.00.02 Adding generic structure for product-specific 22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 23 * Rework of BIOS Page 2 configuration page. 24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 25 * forms. 26 * Added configuration pages IOC Page 8 and Driver 27 * Persistent Mapping Page 0. 28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 30 * RAID Physical Disk Pages 0 and 1, RAID Configuration 31 * Page 0). 32 * Added new value for AccessStatus field of SAS Device 33 * Page 0 (_SATA_NEEDS_INITIALIZATION). 34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 37 * NVDATA. 38 * Modified IOC Page 7 to use masks and added field for 39 * SASBroadcastPrimitiveMasks. 40 * Added MPI2_CONFIG_PAGE_BIOS_4. 41 * Added MPI2_CONFIG_PAGE_LOG_0. 42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 43 * Added SAS Device IDs. 44 * Updated Integrated RAID configuration pages including 45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 46 * Page 0. 47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 50 * Added missing MaxNumRoutedSasAddresses field to 51 * MPI2_CONFIG_PAGE_EXPANDER_0. 52 * Added SAS Port Page 0. 53 * Modified structure layout for 54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 58 * to 0x000000FF. 59 * Added two new values for the Physical Disk Coercion Size 60 * bits in the Flags field of Manufacturing Page 4. 61 * Added product-specific Manufacturing pages 16 to 31. 62 * Modified Flags bits for controlling write cache on SATA 63 * drives in IO Unit Page 1. 64 * Added new bit to AdditionalControlFlags of SAS IO Unit 65 * Page 1 to control Invalid Topology Correction. 66 * Added additional defines for RAID Volume Page 0 67 * VolumeStatusFlags field. 68 * Modified meaning of RAID Volume Page 0 VolumeSettings 69 * define for auto-configure of hot-swap drives. 70 * Added SupportedPhysDisks field to RAID Volume Page 1 and 71 * added related defines. 72 * Added PhysDiskAttributes field (and related defines) to 73 * RAID Physical Disk Page 0. 74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 75 * Added three new DiscoveryStatus bits for SAS IO Unit 76 * Page 0 and SAS Expander Page 0. 77 * Removed multiplexing information from SAS IO Unit pages. 78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 79 * Removed Zone Address Resolved bit from PhyInfo and from 80 * Expander Page 0 Flags field. 81 * Added two new AccessStatus values to SAS Device Page 0 82 * for indicating routing problems. Added 3 reserved words 83 * to this page. 84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 85 * Inserted missing reserved field into structure for IOC 86 * Page 6. 87 * Added more pending task bits to RAID Volume Page 0 88 * VolumeStatusFlags defines. 89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 91 * and SAS Expander Page 0 to flag a downstream initiator 92 * when in simplified routing mode. 93 * Removed SATA Init Failure defines for DiscoveryStatus 94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 96 * Added PortGroups, DmaGroup, and ControlGroup fields to 97 * SAS Device Page 0. 98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 99 * Unit Page 6. 100 * Added expander reduced functionality data to SAS 101 * Expander Page 0. 102 * Added SAS PHY Page 2 and SAS PHY Page 3. 103 * 07-30-09 02.00.12 Added IO Unit Page 7. 104 * Added new device ids. 105 * Added SAS IO Unit Page 5. 106 * Added partial and slumber power management capable flags 107 * to SAS Device Page 0 Flags field. 108 * Added PhyInfo defines for power condition. 109 * Added Ethernet configuration pages. 110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 111 * Added SAS PHY Page 4 structure and defines. 112 * 02-10-10 02.00.14 Modified the comments for the configuration page 113 * structures that contain an array of data. The host 114 * should use the "count" field in the page data (e.g. the 115 * NumPhys field) to determine the number of valid elements 116 * in the array. 117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 118 * Added PowerManagementCapabilities to IO Unit Page 7. 119 * Added PortWidthModGroup field to 120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 124 * -------------------------------------------------------------------------- 125 */ 126 127#ifndef MPI2_CNFG_H 128#define MPI2_CNFG_H 129 130/***************************************************************************** 131* Configuration Page Header and defines 132*****************************************************************************/ 133 134/* Config Page Header */ 135typedef struct _MPI2_CONFIG_PAGE_HEADER 136{ 137 U8 PageVersion; /* 0x00 */ 138 U8 PageLength; /* 0x01 */ 139 U8 PageNumber; /* 0x02 */ 140 U8 PageType; /* 0x03 */ 141} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 142 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 143 144typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 145{ 146 MPI2_CONFIG_PAGE_HEADER Struct; 147 U8 Bytes[4]; 148 U16 Word16[2]; 149 U32 Word32; 150} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 151 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 152 153/* Extended Config Page Header */ 154typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 155{ 156 U8 PageVersion; /* 0x00 */ 157 U8 Reserved1; /* 0x01 */ 158 U8 PageNumber; /* 0x02 */ 159 U8 PageType; /* 0x03 */ 160 U16 ExtPageLength; /* 0x04 */ 161 U8 ExtPageType; /* 0x06 */ 162 U8 Reserved2; /* 0x07 */ 163} MPI2_CONFIG_EXTENDED_PAGE_HEADER, 164 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 165 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 166 167typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 168{ 169 MPI2_CONFIG_PAGE_HEADER Struct; 170 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 171 U8 Bytes[8]; 172 U16 Word16[4]; 173 U32 Word32[2]; 174} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 175 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 176 177 178/* PageType field values */ 179#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 180#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 181#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 182#define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 183 184#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 185#define MPI2_CONFIG_PAGETYPE_IOC (0x01) 186#define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 187#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 188#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 189#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 190#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 191#define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 192 193#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 194 195 196/* ExtPageType field values */ 197#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 198#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 199#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 200#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 201#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 202#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 203#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 204#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 205#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 206#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 207 208 209/***************************************************************************** 210* PageAddress defines 211*****************************************************************************/ 212 213/* RAID Volume PageAddress format */ 214#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 215#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 216#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 217 218#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 219 220 221/* RAID Physical Disk PageAddress format */ 222#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 223#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 224#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 225#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 226 227#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 228#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 229 230 231/* SAS Expander PageAddress format */ 232#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 233#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 234#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 235#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 236 237#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 238#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 239#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 240 241 242/* SAS Device PageAddress format */ 243#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 244#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 245#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 246 247#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 248 249 250/* SAS PHY PageAddress format */ 251#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 252#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 253#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 254 255#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 256#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 257 258 259/* SAS Port PageAddress format */ 260#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 261#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 262#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 263 264#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 265 266 267/* SAS Enclosure PageAddress format */ 268#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 269#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 270#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 271 272#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 273 274 275/* RAID Configuration PageAddress format */ 276#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 277#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 278#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 279#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 280 281#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 282 283 284/* Driver Persistent Mapping PageAddress format */ 285#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 286#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 287 288#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 289#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 290#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 291 292 293/* Ethernet PageAddress format */ 294#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 295#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 296 297#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 298 299 300 301/**************************************************************************** 302* Configuration messages 303****************************************************************************/ 304 305/* Configuration Request Message */ 306typedef struct _MPI2_CONFIG_REQUEST 307{ 308 U8 Action; /* 0x00 */ 309 U8 SGLFlags; /* 0x01 */ 310 U8 ChainOffset; /* 0x02 */ 311 U8 Function; /* 0x03 */ 312 U16 ExtPageLength; /* 0x04 */ 313 U8 ExtPageType; /* 0x06 */ 314 U8 MsgFlags; /* 0x07 */ 315 U8 VP_ID; /* 0x08 */ 316 U8 VF_ID; /* 0x09 */ 317 U16 Reserved1; /* 0x0A */ 318 U32 Reserved2; /* 0x0C */ 319 U32 Reserved3; /* 0x10 */ 320 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 321 U32 PageAddress; /* 0x18 */ 322 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 323} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 324 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 325 326/* values for the Action field */ 327#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 328#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 329#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 330#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 331#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 332#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 333#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 334#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 335 336/* values for SGLFlags field are in the SGL section of mpi2.h */ 337 338 339/* Config Reply Message */ 340typedef struct _MPI2_CONFIG_REPLY 341{ 342 U8 Action; /* 0x00 */ 343 U8 SGLFlags; /* 0x01 */ 344 U8 MsgLength; /* 0x02 */ 345 U8 Function; /* 0x03 */ 346 U16 ExtPageLength; /* 0x04 */ 347 U8 ExtPageType; /* 0x06 */ 348 U8 MsgFlags; /* 0x07 */ 349 U8 VP_ID; /* 0x08 */ 350 U8 VF_ID; /* 0x09 */ 351 U16 Reserved1; /* 0x0A */ 352 U16 Reserved2; /* 0x0C */ 353 U16 IOCStatus; /* 0x0E */ 354 U32 IOCLogInfo; /* 0x10 */ 355 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 356} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 357 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 358 359 360 361/***************************************************************************** 362* 363* C o n f i g u r a t i o n P a g e s 364* 365*****************************************************************************/ 366 367/**************************************************************************** 368* Manufacturing Config pages 369****************************************************************************/ 370 371#define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 372 373/* SAS */ 374#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 375#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 376#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 377#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 378#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 379#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 380#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 381 382#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 383#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 384#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 385#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 386#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 387#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 388#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 389#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 390#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 391 392 393/* Manufacturing Page 0 */ 394 395typedef struct _MPI2_CONFIG_PAGE_MAN_0 396{ 397 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 398 U8 ChipName[16]; /* 0x04 */ 399 U8 ChipRevision[8]; /* 0x14 */ 400 U8 BoardName[16]; /* 0x1C */ 401 U8 BoardAssembly[16]; /* 0x2C */ 402 U8 BoardTracerNumber[16]; /* 0x3C */ 403} MPI2_CONFIG_PAGE_MAN_0, 404 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 405 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 406 407#define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 408 409 410/* Manufacturing Page 1 */ 411 412typedef struct _MPI2_CONFIG_PAGE_MAN_1 413{ 414 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 415 U8 VPD[256]; /* 0x04 */ 416} MPI2_CONFIG_PAGE_MAN_1, 417 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 418 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 419 420#define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 421 422 423typedef struct _MPI2_CHIP_REVISION_ID 424{ 425 U16 DeviceID; /* 0x00 */ 426 U8 PCIRevisionID; /* 0x02 */ 427 U8 Reserved; /* 0x03 */ 428} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 429 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 430 431 432/* Manufacturing Page 2 */ 433 434/* 435 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 436 * one and check Header.PageLength at runtime. 437 */ 438#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 439#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 440#endif 441 442typedef struct _MPI2_CONFIG_PAGE_MAN_2 443{ 444 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 445 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 446 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 447} MPI2_CONFIG_PAGE_MAN_2, 448 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 449 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 450 451#define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 452 453 454/* Manufacturing Page 3 */ 455 456/* 457 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 458 * one and check Header.PageLength at runtime. 459 */ 460#ifndef MPI2_MAN_PAGE_3_INFO_WORDS 461#define MPI2_MAN_PAGE_3_INFO_WORDS (1) 462#endif 463 464typedef struct _MPI2_CONFIG_PAGE_MAN_3 465{ 466 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 467 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 468 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 469} MPI2_CONFIG_PAGE_MAN_3, 470 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 471 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 472 473#define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 474 475 476/* Manufacturing Page 4 */ 477 478typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 479{ 480 U8 PowerSaveFlags; /* 0x00 */ 481 U8 InternalOperationsSleepTime; /* 0x01 */ 482 U8 InternalOperationsRunTime; /* 0x02 */ 483 U8 HostIdleTime; /* 0x03 */ 484} MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 485 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 486 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 487 488/* defines for the PowerSaveFlags field */ 489#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 490#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 491#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 492#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 493 494typedef struct _MPI2_CONFIG_PAGE_MAN_4 495{ 496 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 497 U32 Reserved1; /* 0x04 */ 498 U32 Flags; /* 0x08 */ 499 U8 InquirySize; /* 0x0C */ 500 U8 Reserved2; /* 0x0D */ 501 U16 Reserved3; /* 0x0E */ 502 U8 InquiryData[56]; /* 0x10 */ 503 U32 RAID0VolumeSettings; /* 0x48 */ 504 U32 RAID1EVolumeSettings; /* 0x4C */ 505 U32 RAID1VolumeSettings; /* 0x50 */ 506 U32 RAID10VolumeSettings; /* 0x54 */ 507 U32 Reserved4; /* 0x58 */ 508 U32 Reserved5; /* 0x5C */ 509 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 510 U8 MaxOCEDisks; /* 0x64 */ 511 U8 ResyncRate; /* 0x65 */ 512 U16 DataScrubDuration; /* 0x66 */ 513 U8 MaxHotSpares; /* 0x68 */ 514 U8 MaxPhysDisksPerVol; /* 0x69 */ 515 U8 MaxPhysDisks; /* 0x6A */ 516 U8 MaxVolumes; /* 0x6B */ 517} MPI2_CONFIG_PAGE_MAN_4, 518 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 519 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 520 521#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 522 523/* Manufacturing Page 4 Flags field */ 524#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 525#define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 526 527#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 528#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 529#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 530 531#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 532#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 533#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 534#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 535#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 536 537#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 538#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 539#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 540#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 541 542#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 543#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 544#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 545#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 546#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 547#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 548#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 549#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 550 551 552/* Manufacturing Page 5 */ 553 554/* 555 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 556 * one and check the value returned for NumPhys at runtime. 557 */ 558#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 559#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 560#endif 561 562typedef struct _MPI2_MANUFACTURING5_ENTRY 563{ 564 U64 WWID; /* 0x00 */ 565 U64 DeviceName; /* 0x08 */ 566} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 567 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 568 569typedef struct _MPI2_CONFIG_PAGE_MAN_5 570{ 571 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 572 U8 NumPhys; /* 0x04 */ 573 U8 Reserved1; /* 0x05 */ 574 U16 Reserved2; /* 0x06 */ 575 U32 Reserved3; /* 0x08 */ 576 U32 Reserved4; /* 0x0C */ 577 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 578} MPI2_CONFIG_PAGE_MAN_5, 579 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 580 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 581 582#define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 583 584 585/* Manufacturing Page 6 */ 586 587typedef struct _MPI2_CONFIG_PAGE_MAN_6 588{ 589 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 590 U32 ProductSpecificInfo;/* 0x04 */ 591} MPI2_CONFIG_PAGE_MAN_6, 592 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 593 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 594 595#define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 596 597 598/* Manufacturing Page 7 */ 599 600typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 601{ 602 U32 Pinout; /* 0x00 */ 603 U8 Connector[16]; /* 0x04 */ 604 U8 Location; /* 0x14 */ 605 U8 Reserved1; /* 0x15 */ 606 U16 Slot; /* 0x16 */ 607 U32 Reserved2; /* 0x18 */ 608} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 609 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 610 611/* defines for the Pinout field */ 612#define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 613#define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 614#define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 615#define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 616#define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 617#define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 618#define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 619#define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 620#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 621#define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 622 623/* defines for the Location field */ 624#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 625#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 626#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 627#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 628#define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 629#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 630#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 631 632/* 633 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 634 * one and check the value returned for NumPhys at runtime. 635 */ 636#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 637#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 638#endif 639 640typedef struct _MPI2_CONFIG_PAGE_MAN_7 641{ 642 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 643 U32 Reserved1; /* 0x04 */ 644 U32 Reserved2; /* 0x08 */ 645 U32 Flags; /* 0x0C */ 646 U8 EnclosureName[16]; /* 0x10 */ 647 U8 NumPhys; /* 0x20 */ 648 U8 Reserved3; /* 0x21 */ 649 U16 Reserved4; /* 0x22 */ 650 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 651} MPI2_CONFIG_PAGE_MAN_7, 652 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 653 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 654 655#define MPI2_MANUFACTURING7_PAGEVERSION (0x00) 656 657/* defines for the Flags field */ 658#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 659 660 661/* 662 * Generic structure to use for product-specific manufacturing pages 663 * (currently Manufacturing Page 8 through Manufacturing Page 31). 664 */ 665 666typedef struct _MPI2_CONFIG_PAGE_MAN_PS 667{ 668 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 669 U32 ProductSpecificInfo;/* 0x04 */ 670} MPI2_CONFIG_PAGE_MAN_PS, 671 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 672 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 673 674#define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 675#define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 676#define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 677#define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 678#define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 679#define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 680#define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 681#define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 682#define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 683#define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 684#define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 685#define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 686#define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 687#define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 688#define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 689#define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 690#define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 691#define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 692#define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 693#define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 694#define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 695#define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 696#define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 697#define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 698 699 700/**************************************************************************** 701* IO Unit Config Pages 702****************************************************************************/ 703 704/* IO Unit Page 0 */ 705 706typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 707{ 708 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 709 U64 UniqueValue; /* 0x04 */ 710 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 711 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 712} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 713 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 714 715#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 716 717 718/* IO Unit Page 1 */ 719 720typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 721{ 722 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 723 U32 Flags; /* 0x04 */ 724} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 725 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 726 727#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 728 729/* IO Unit Page 1 Flags defines */ 730#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 731#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 732#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 733#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 734#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 735#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 736#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 737#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 738#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 739#define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002) 740#define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 741 742 743/* IO Unit Page 3 */ 744 745/* 746 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 747 * one and check the value returned for GPIOCount at runtime. 748 */ 749#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 750#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 751#endif 752 753typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 754{ 755 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 756 U8 GPIOCount; /* 0x04 */ 757 U8 Reserved1; /* 0x05 */ 758 U16 Reserved2; /* 0x06 */ 759 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 760} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 761 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 762 763#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 764 765/* defines for IO Unit Page 3 GPIOVal field */ 766#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 767#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 768#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 769#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 770 771 772/* IO Unit Page 5 */ 773 774/* 775 * Upper layer code (drivers, utilities, etc.) should leave this define set to 776 * one and check the value returned for NumDmaEngines at runtime. 777 */ 778#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 779#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 780#endif 781 782typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 783 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 784 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 785 U64 RaidAcceleratorBufferSize; /* 0x0C */ 786 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 787 U8 RAControlSize; /* 0x1C */ 788 U8 NumDmaEngines; /* 0x1D */ 789 U8 RAMinControlSize; /* 0x1E */ 790 U8 RAMaxControlSize; /* 0x1F */ 791 U32 Reserved1; /* 0x20 */ 792 U32 Reserved2; /* 0x24 */ 793 U32 Reserved3; /* 0x28 */ 794 U32 DmaEngineCapabilities 795 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 796} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 797 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 798 799#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 800 801/* defines for IO Unit Page 5 DmaEngineCapabilities field */ 802#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 803#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 804 805#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 806#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 807#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 808#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 809 810 811/* IO Unit Page 6 */ 812 813typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 814 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 815 U16 Flags; /* 0x04 */ 816 U8 RAHostControlSize; /* 0x06 */ 817 U8 Reserved0; /* 0x07 */ 818 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 819 U32 Reserved1; /* 0x10 */ 820 U32 Reserved2; /* 0x14 */ 821 U32 Reserved3; /* 0x18 */ 822} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 823 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 824 825#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 826 827/* defines for IO Unit Page 6 Flags field */ 828#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 829 830 831/* IO Unit Page 7 */ 832 833typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 834 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 835 U16 Reserved1; /* 0x04 */ 836 U8 PCIeWidth; /* 0x06 */ 837 U8 PCIeSpeed; /* 0x07 */ 838 U32 ProcessorState; /* 0x08 */ 839 U32 PowerManagementCapabilities; /* 0x0C */ 840 U16 IOCTemperature; /* 0x10 */ 841 U8 IOCTemperatureUnits; /* 0x12 */ 842 U8 IOCSpeed; /* 0x13 */ 843 U32 Reserved3; /* 0x14 */ 844} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 845 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 846 847#define MPI2_IOUNITPAGE7_PAGEVERSION (0x01) 848 849/* defines for IO Unit Page 7 PCIeWidth field */ 850#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 851#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 852#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 853#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 854 855/* defines for IO Unit Page 7 PCIeSpeed field */ 856#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 857#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 858#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 859 860/* defines for IO Unit Page 7 ProcessorState field */ 861#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 862#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 863 864#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 865#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 866#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 867 868/* defines for IO Unit Page 7 PowerManagementCapabilities field */ 869#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 870#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 871#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 872#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) 873#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) 874 875 876/* defines for IO Unit Page 7 IOCTemperatureUnits field */ 877#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 878#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 879#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 880 881/* defines for IO Unit Page 7 IOCSpeed field */ 882#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 883#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 884#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 885#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 886 887 888 889/**************************************************************************** 890* IOC Config Pages 891****************************************************************************/ 892 893/* IOC Page 0 */ 894 895typedef struct _MPI2_CONFIG_PAGE_IOC_0 896{ 897 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 898 U32 Reserved1; /* 0x04 */ 899 U32 Reserved2; /* 0x08 */ 900 U16 VendorID; /* 0x0C */ 901 U16 DeviceID; /* 0x0E */ 902 U8 RevisionID; /* 0x10 */ 903 U8 Reserved3; /* 0x11 */ 904 U16 Reserved4; /* 0x12 */ 905 U32 ClassCode; /* 0x14 */ 906 U16 SubsystemVendorID; /* 0x18 */ 907 U16 SubsystemID; /* 0x1A */ 908} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 909 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 910 911#define MPI2_IOCPAGE0_PAGEVERSION (0x02) 912 913 914/* IOC Page 1 */ 915 916typedef struct _MPI2_CONFIG_PAGE_IOC_1 917{ 918 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 919 U32 Flags; /* 0x04 */ 920 U32 CoalescingTimeout; /* 0x08 */ 921 U8 CoalescingDepth; /* 0x0C */ 922 U8 PCISlotNum; /* 0x0D */ 923 U8 PCIBusNum; /* 0x0E */ 924 U8 PCIDomainSegment; /* 0x0F */ 925 U32 Reserved1; /* 0x10 */ 926 U32 Reserved2; /* 0x14 */ 927} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 928 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 929 930#define MPI2_IOCPAGE1_PAGEVERSION (0x05) 931 932/* defines for IOC Page 1 Flags field */ 933#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 934 935#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 936#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 937#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 938 939/* IOC Page 6 */ 940 941typedef struct _MPI2_CONFIG_PAGE_IOC_6 942{ 943 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 944 U32 CapabilitiesFlags; /* 0x04 */ 945 U8 MaxDrivesRAID0; /* 0x08 */ 946 U8 MaxDrivesRAID1; /* 0x09 */ 947 U8 MaxDrivesRAID1E; /* 0x0A */ 948 U8 MaxDrivesRAID10; /* 0x0B */ 949 U8 MinDrivesRAID0; /* 0x0C */ 950 U8 MinDrivesRAID1; /* 0x0D */ 951 U8 MinDrivesRAID1E; /* 0x0E */ 952 U8 MinDrivesRAID10; /* 0x0F */ 953 U32 Reserved1; /* 0x10 */ 954 U8 MaxGlobalHotSpares; /* 0x14 */ 955 U8 MaxPhysDisks; /* 0x15 */ 956 U8 MaxVolumes; /* 0x16 */ 957 U8 MaxConfigs; /* 0x17 */ 958 U8 MaxOCEDisks; /* 0x18 */ 959 U8 Reserved2; /* 0x19 */ 960 U16 Reserved3; /* 0x1A */ 961 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 962 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 963 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 964 U32 Reserved4; /* 0x28 */ 965 U32 Reserved5; /* 0x2C */ 966 U16 DefaultMetadataSize; /* 0x30 */ 967 U16 Reserved6; /* 0x32 */ 968 U16 MaxBadBlockTableEntries; /* 0x34 */ 969 U16 Reserved7; /* 0x36 */ 970 U32 IRNvsramVersion; /* 0x38 */ 971} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 972 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 973 974#define MPI2_IOCPAGE6_PAGEVERSION (0x04) 975 976/* defines for IOC Page 6 CapabilitiesFlags */ 977#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 978#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 979#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 980#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 981#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 982 983 984/* IOC Page 7 */ 985 986#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 987 988typedef struct _MPI2_CONFIG_PAGE_IOC_7 989{ 990 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 991 U32 Reserved1; /* 0x04 */ 992 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 993 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 994 U16 Reserved2; /* 0x1A */ 995 U32 Reserved3; /* 0x1C */ 996} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 997 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 998 999#define MPI2_IOCPAGE7_PAGEVERSION (0x01) 1000 1001 1002/* IOC Page 8 */ 1003 1004typedef struct _MPI2_CONFIG_PAGE_IOC_8 1005{ 1006 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1007 U8 NumDevsPerEnclosure; /* 0x04 */ 1008 U8 Reserved1; /* 0x05 */ 1009 U16 Reserved2; /* 0x06 */ 1010 U16 MaxPersistentEntries; /* 0x08 */ 1011 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1012 U16 Flags; /* 0x0C */ 1013 U16 Reserved3; /* 0x0E */ 1014 U16 IRVolumeMappingFlags; /* 0x10 */ 1015 U16 Reserved4; /* 0x12 */ 1016 U32 Reserved5; /* 0x14 */ 1017} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1018 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1019 1020#define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1021 1022/* defines for IOC Page 8 Flags field */ 1023#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1024#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1025 1026#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1027#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1028#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1029 1030#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1031#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1032 1033/* defines for IOC Page 8 IRVolumeMappingFlags */ 1034#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1035#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1036#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1037 1038 1039/**************************************************************************** 1040* BIOS Config Pages 1041****************************************************************************/ 1042 1043/* BIOS Page 1 */ 1044 1045typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1046{ 1047 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1048 U32 BiosOptions; /* 0x04 */ 1049 U32 IOCSettings; /* 0x08 */ 1050 U32 Reserved1; /* 0x0C */ 1051 U32 DeviceSettings; /* 0x10 */ 1052 U16 NumberOfDevices; /* 0x14 */ 1053 U16 Reserved2; /* 0x16 */ 1054 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1055 U16 IOTimeoutSequential; /* 0x1A */ 1056 U16 IOTimeoutOther; /* 0x1C */ 1057 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1058} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1059 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1060 1061#define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 1062 1063/* values for BIOS Page 1 BiosOptions field */ 1064#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1065 1066/* values for BIOS Page 1 IOCSettings field */ 1067#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1068#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1069#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1070 1071#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1072#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1073#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1074#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1075 1076#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1077#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1078#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1079#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1080#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1081 1082#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1083 1084/* values for BIOS Page 1 DeviceSettings field */ 1085#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1086#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1087#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1088#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1089#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1090 1091 1092/* BIOS Page 2 */ 1093 1094typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1095{ 1096 U32 Reserved1; /* 0x00 */ 1097 U32 Reserved2; /* 0x04 */ 1098 U32 Reserved3; /* 0x08 */ 1099 U32 Reserved4; /* 0x0C */ 1100 U32 Reserved5; /* 0x10 */ 1101 U32 Reserved6; /* 0x14 */ 1102} MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1103 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1104 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1105 1106typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1107{ 1108 U64 SASAddress; /* 0x00 */ 1109 U8 LUN[8]; /* 0x08 */ 1110 U32 Reserved1; /* 0x10 */ 1111 U32 Reserved2; /* 0x14 */ 1112} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1113 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1114 1115typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1116{ 1117 U64 EnclosureLogicalID; /* 0x00 */ 1118 U32 Reserved1; /* 0x08 */ 1119 U32 Reserved2; /* 0x0C */ 1120 U16 SlotNumber; /* 0x10 */ 1121 U16 Reserved3; /* 0x12 */ 1122 U32 Reserved4; /* 0x14 */ 1123} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1124 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1125 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1126 1127typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1128{ 1129 U64 DeviceName; /* 0x00 */ 1130 U8 LUN[8]; /* 0x08 */ 1131 U32 Reserved1; /* 0x10 */ 1132 U32 Reserved2; /* 0x14 */ 1133} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1134 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1135 1136typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1137{ 1138 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1139 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1140 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1141 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1142} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1143 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1144 1145typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1146{ 1147 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1148 U32 Reserved1; /* 0x04 */ 1149 U32 Reserved2; /* 0x08 */ 1150 U32 Reserved3; /* 0x0C */ 1151 U32 Reserved4; /* 0x10 */ 1152 U32 Reserved5; /* 0x14 */ 1153 U32 Reserved6; /* 0x18 */ 1154 U8 ReqBootDeviceForm; /* 0x1C */ 1155 U8 Reserved7; /* 0x1D */ 1156 U16 Reserved8; /* 0x1E */ 1157 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1158 U8 ReqAltBootDeviceForm; /* 0x38 */ 1159 U8 Reserved9; /* 0x39 */ 1160 U16 Reserved10; /* 0x3A */ 1161 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1162 U8 CurrentBootDeviceForm; /* 0x58 */ 1163 U8 Reserved11; /* 0x59 */ 1164 U16 Reserved12; /* 0x5A */ 1165 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1166} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1167 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1168 1169#define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1170 1171/* values for BIOS Page 2 BootDeviceForm fields */ 1172#define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1173#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1174#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1175#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1176#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1177 1178 1179/* BIOS Page 3 */ 1180 1181typedef struct _MPI2_ADAPTER_INFO 1182{ 1183 U8 PciBusNumber; /* 0x00 */ 1184 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1185 U16 AdapterFlags; /* 0x02 */ 1186} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1187 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1188 1189#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1190#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1191 1192typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1193{ 1194 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1195 U32 GlobalFlags; /* 0x04 */ 1196 U32 BiosVersion; /* 0x08 */ 1197 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1198 U32 Reserved1; /* 0x1C */ 1199} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1200 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1201 1202#define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1203 1204/* values for BIOS Page 3 GlobalFlags */ 1205#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1206#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1207#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1208 1209#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1210#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1211#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1212#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1213 1214 1215/* BIOS Page 4 */ 1216 1217/* 1218 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1219 * one and check the value returned for NumPhys at runtime. 1220 */ 1221#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1222#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1223#endif 1224 1225typedef struct _MPI2_BIOS4_ENTRY 1226{ 1227 U64 ReassignmentWWID; /* 0x00 */ 1228 U64 ReassignmentDeviceName; /* 0x08 */ 1229} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1230 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1231 1232typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1233{ 1234 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1235 U8 NumPhys; /* 0x04 */ 1236 U8 Reserved1; /* 0x05 */ 1237 U16 Reserved2; /* 0x06 */ 1238 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1239} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1240 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1241 1242#define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1243 1244 1245/**************************************************************************** 1246* RAID Volume Config Pages 1247****************************************************************************/ 1248 1249/* RAID Volume Page 0 */ 1250 1251typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1252{ 1253 U8 RAIDSetNum; /* 0x00 */ 1254 U8 PhysDiskMap; /* 0x01 */ 1255 U8 PhysDiskNum; /* 0x02 */ 1256 U8 Reserved; /* 0x03 */ 1257} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1258 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1259 1260/* defines for the PhysDiskMap field */ 1261#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1262#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1263 1264typedef struct _MPI2_RAIDVOL0_SETTINGS 1265{ 1266 U16 Settings; /* 0x00 */ 1267 U8 HotSparePool; /* 0x01 */ 1268 U8 Reserved; /* 0x02 */ 1269} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1270 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1271 1272/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1273#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1274#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1275#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1276#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1277#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1278#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1279#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1280#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1281 1282/* RAID Volume Page 0 VolumeSettings defines */ 1283#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1284#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1285 1286#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1287#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1288#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1289#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1290 1291/* 1292 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1293 * one and check the value returned for NumPhysDisks at runtime. 1294 */ 1295#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1296#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1297#endif 1298 1299typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1300{ 1301 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1302 U16 DevHandle; /* 0x04 */ 1303 U8 VolumeState; /* 0x06 */ 1304 U8 VolumeType; /* 0x07 */ 1305 U32 VolumeStatusFlags; /* 0x08 */ 1306 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1307 U64 MaxLBA; /* 0x10 */ 1308 U32 StripeSize; /* 0x18 */ 1309 U16 BlockSize; /* 0x1C */ 1310 U16 Reserved1; /* 0x1E */ 1311 U8 SupportedPhysDisks; /* 0x20 */ 1312 U8 ResyncRate; /* 0x21 */ 1313 U16 DataScrubDuration; /* 0x22 */ 1314 U8 NumPhysDisks; /* 0x24 */ 1315 U8 Reserved2; /* 0x25 */ 1316 U8 Reserved3; /* 0x26 */ 1317 U8 InactiveStatus; /* 0x27 */ 1318 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1319} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1320 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1321 1322#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1323 1324/* values for RAID VolumeState */ 1325#define MPI2_RAID_VOL_STATE_MISSING (0x00) 1326#define MPI2_RAID_VOL_STATE_FAILED (0x01) 1327#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1328#define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1329#define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1330#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1331 1332/* values for RAID VolumeType */ 1333#define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1334#define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1335#define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1336#define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1337#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1338 1339/* values for RAID Volume Page 0 VolumeStatusFlags field */ 1340#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1341#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1342#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1343#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1344#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1345#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1346#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1347#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1348#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1349#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1350#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1351#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1352#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1353#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1354#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1355#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1356#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1357#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1358 1359/* values for RAID Volume Page 0 SupportedPhysDisks field */ 1360#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1361#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1362#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1363#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1364 1365/* values for RAID Volume Page 0 InactiveStatus field */ 1366#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1367#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1368#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1369#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1370#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1371#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1372#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1373 1374 1375/* RAID Volume Page 1 */ 1376 1377typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1378{ 1379 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1380 U16 DevHandle; /* 0x04 */ 1381 U16 Reserved0; /* 0x06 */ 1382 U8 GUID[24]; /* 0x08 */ 1383 U8 Name[16]; /* 0x20 */ 1384 U64 WWID; /* 0x30 */ 1385 U32 Reserved1; /* 0x38 */ 1386 U32 Reserved2; /* 0x3C */ 1387} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1388 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1389 1390#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1391 1392 1393/**************************************************************************** 1394* RAID Physical Disk Config Pages 1395****************************************************************************/ 1396 1397/* RAID Physical Disk Page 0 */ 1398 1399typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1400{ 1401 U16 Reserved1; /* 0x00 */ 1402 U8 HotSparePool; /* 0x02 */ 1403 U8 Reserved2; /* 0x03 */ 1404} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1405 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1406 1407/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1408 1409typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1410{ 1411 U8 VendorID[8]; /* 0x00 */ 1412 U8 ProductID[16]; /* 0x08 */ 1413 U8 ProductRevLevel[4]; /* 0x18 */ 1414 U8 SerialNum[32]; /* 0x1C */ 1415} MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1416 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1417 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1418 1419typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1420{ 1421 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1422 U16 DevHandle; /* 0x04 */ 1423 U8 Reserved1; /* 0x06 */ 1424 U8 PhysDiskNum; /* 0x07 */ 1425 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1426 U32 Reserved2; /* 0x0C */ 1427 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1428 U32 Reserved3; /* 0x4C */ 1429 U8 PhysDiskState; /* 0x50 */ 1430 U8 OfflineReason; /* 0x51 */ 1431 U8 IncompatibleReason; /* 0x52 */ 1432 U8 PhysDiskAttributes; /* 0x53 */ 1433 U32 PhysDiskStatusFlags; /* 0x54 */ 1434 U64 DeviceMaxLBA; /* 0x58 */ 1435 U64 HostMaxLBA; /* 0x60 */ 1436 U64 CoercedMaxLBA; /* 0x68 */ 1437 U16 BlockSize; /* 0x70 */ 1438 U16 Reserved5; /* 0x72 */ 1439 U32 Reserved6; /* 0x74 */ 1440} MPI2_CONFIG_PAGE_RD_PDISK_0, 1441 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1442 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1443 1444#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1445 1446/* PhysDiskState defines */ 1447#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1448#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1449#define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1450#define MPI2_RAID_PD_STATE_ONLINE (0x03) 1451#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1452#define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1453#define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1454#define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1455 1456/* OfflineReason defines */ 1457#define MPI2_PHYSDISK0_ONLINE (0x00) 1458#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1459#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1460#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1461#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1462#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1463#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1464 1465/* IncompatibleReason defines */ 1466#define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1467#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1468#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1469#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1470#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1471#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1472#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1473 1474/* PhysDiskAttributes defines */ 1475#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1476#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1477#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1478#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1479 1480/* PhysDiskStatusFlags defines */ 1481#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1482#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1483#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1484#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1485#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1486#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1487#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1488#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1489 1490 1491/* RAID Physical Disk Page 1 */ 1492 1493/* 1494 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1495 * one and check the value returned for NumPhysDiskPaths at runtime. 1496 */ 1497#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1498#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1499#endif 1500 1501typedef struct _MPI2_RAIDPHYSDISK1_PATH 1502{ 1503 U16 DevHandle; /* 0x00 */ 1504 U16 Reserved1; /* 0x02 */ 1505 U64 WWID; /* 0x04 */ 1506 U64 OwnerWWID; /* 0x0C */ 1507 U8 OwnerIdentifier; /* 0x14 */ 1508 U8 Reserved2; /* 0x15 */ 1509 U16 Flags; /* 0x16 */ 1510} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1511 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1512 1513/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1514#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1515#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1516#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1517 1518typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1519{ 1520 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1521 U8 NumPhysDiskPaths; /* 0x04 */ 1522 U8 PhysDiskNum; /* 0x05 */ 1523 U16 Reserved1; /* 0x06 */ 1524 U32 Reserved2; /* 0x08 */ 1525 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1526} MPI2_CONFIG_PAGE_RD_PDISK_1, 1527 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1528 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1529 1530#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1531 1532 1533/**************************************************************************** 1534* values for fields used by several types of SAS Config Pages 1535****************************************************************************/ 1536 1537/* values for NegotiatedLinkRates fields */ 1538#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1539#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1540#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1541/* link rates used for Negotiated Physical and Logical Link Rate */ 1542#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1543#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1544#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1545#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1546#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1547#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1548#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1549#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1550#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1551 1552 1553/* values for AttachedPhyInfo fields */ 1554#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1555#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1556#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1557 1558#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1559#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1560#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1561#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1562#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1563#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1564#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1565#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1566#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1567#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1568 1569 1570/* values for PhyInfo fields */ 1571#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1572 1573#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1574#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1575#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1576#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1577 1578#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1579#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1580#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1581#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1582#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1583#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1584 1585#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1586#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1587#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1588#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1589#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1590#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1591#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1592#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1593#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1594#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1595 1596#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1597#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1598#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1599#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1600 1601#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1602#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1603 1604#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1605#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1606#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1607#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1608 1609 1610/* values for SAS ProgrammedLinkRate fields */ 1611#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1612#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1613#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1614#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1615#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1616#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1617#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1618#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1619#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1620#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1621 1622 1623/* values for SAS HwLinkRate fields */ 1624#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1625#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1626#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1627#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1628#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1629#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1630#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1631#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1632 1633 1634 1635/**************************************************************************** 1636* SAS IO Unit Config Pages 1637****************************************************************************/ 1638 1639/* SAS IO Unit Page 0 */ 1640 1641typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1642{ 1643 U8 Port; /* 0x00 */ 1644 U8 PortFlags; /* 0x01 */ 1645 U8 PhyFlags; /* 0x02 */ 1646 U8 NegotiatedLinkRate; /* 0x03 */ 1647 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1648 U16 AttachedDevHandle; /* 0x08 */ 1649 U16 ControllerDevHandle; /* 0x0A */ 1650 U32 DiscoveryStatus; /* 0x0C */ 1651 U32 Reserved; /* 0x10 */ 1652} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1653 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1654 1655/* 1656 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1657 * one and check the value returned for NumPhys at runtime. 1658 */ 1659#ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1660#define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1661#endif 1662 1663typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1664{ 1665 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1666 U32 Reserved1; /* 0x08 */ 1667 U8 NumPhys; /* 0x0C */ 1668 U8 Reserved2; /* 0x0D */ 1669 U16 Reserved3; /* 0x0E */ 1670 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1671} MPI2_CONFIG_PAGE_SASIOUNIT_0, 1672 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1673 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1674 1675#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1676 1677/* values for SAS IO Unit Page 0 PortFlags */ 1678#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1679#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1680 1681/* values for SAS IO Unit Page 0 PhyFlags */ 1682#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1683#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1684 1685/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1686 1687/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1688 1689/* values for SAS IO Unit Page 0 DiscoveryStatus */ 1690#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1691#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1692#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1693#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1694#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1695#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1696#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1697#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1698#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1699#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1700#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1701#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1702#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1703#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1704#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1705#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1706#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1707#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1708#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1709#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1710 1711 1712/* SAS IO Unit Page 1 */ 1713 1714typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1715{ 1716 U8 Port; /* 0x00 */ 1717 U8 PortFlags; /* 0x01 */ 1718 U8 PhyFlags; /* 0x02 */ 1719 U8 MaxMinLinkRate; /* 0x03 */ 1720 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1721 U16 MaxTargetPortConnectTime; /* 0x08 */ 1722 U16 Reserved1; /* 0x0A */ 1723} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1724 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1725 1726/* 1727 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1728 * one and check the value returned for NumPhys at runtime. 1729 */ 1730#ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1731#define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1732#endif 1733 1734typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1735{ 1736 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1737 U16 ControlFlags; /* 0x08 */ 1738 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1739 U16 AdditionalControlFlags; /* 0x0C */ 1740 U16 SASWideMaxQueueDepth; /* 0x0E */ 1741 U8 NumPhys; /* 0x10 */ 1742 U8 SATAMaxQDepth; /* 0x11 */ 1743 U8 ReportDeviceMissingDelay; /* 0x12 */ 1744 U8 IODeviceMissingDelay; /* 0x13 */ 1745 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1746} MPI2_CONFIG_PAGE_SASIOUNIT_1, 1747 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1748 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1749 1750#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1751 1752/* values for SAS IO Unit Page 1 ControlFlags */ 1753#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1754#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1755#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1756#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1757 1758#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1759#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1760#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1761#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1762#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1763 1764#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1765#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1766#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1767#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1768#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1769#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1770#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1771#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1772 1773/* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1774#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1775#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1776#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1777#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1778#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1779#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1780#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1781#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1782 1783/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1784#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1785#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1786 1787/* values for SAS IO Unit Page 1 PortFlags */ 1788#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1789 1790/* values for SAS IO Unit Page 1 PhyFlags */ 1791#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1792#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1793 1794/* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1795#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1796#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1797#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1798#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1799#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1800#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1801#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1802#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1803 1804/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1805 1806 1807/* SAS IO Unit Page 4 */ 1808 1809typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1810{ 1811 U8 MaxTargetSpinup; /* 0x00 */ 1812 U8 SpinupDelay; /* 0x01 */ 1813 U16 Reserved1; /* 0x02 */ 1814} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1815 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1816 1817/* 1818 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1819 * one and check the value returned for NumPhys at runtime. 1820 */ 1821#ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1822#define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1823#endif 1824 1825typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1826{ 1827 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1828 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1829 U32 Reserved1; /* 0x18 */ 1830 U32 Reserved2; /* 0x1C */ 1831 U32 Reserved3; /* 0x20 */ 1832 U8 BootDeviceWaitTime; /* 0x24 */ 1833 U8 Reserved4; /* 0x25 */ 1834 U16 Reserved5; /* 0x26 */ 1835 U8 NumPhys; /* 0x28 */ 1836 U8 PEInitialSpinupDelay; /* 0x29 */ 1837 U8 PEReplyDelay; /* 0x2A */ 1838 U8 Flags; /* 0x2B */ 1839 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1840} MPI2_CONFIG_PAGE_SASIOUNIT_4, 1841 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1842 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1843 1844#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1845 1846/* defines for Flags field */ 1847#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1848 1849/* defines for PHY field */ 1850#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1851 1852 1853/* SAS IO Unit Page 5 */ 1854 1855typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 1856 U8 ControlFlags; /* 0x00 */ 1857 U8 PortWidthModGroup; /* 0x01 */ 1858 U16 InactivityTimerExponent; /* 0x02 */ 1859 U8 SATAPartialTimeout; /* 0x04 */ 1860 U8 Reserved2; /* 0x05 */ 1861 U8 SATASlumberTimeout; /* 0x06 */ 1862 U8 Reserved3; /* 0x07 */ 1863 U8 SASPartialTimeout; /* 0x08 */ 1864 U8 Reserved4; /* 0x09 */ 1865 U8 SASSlumberTimeout; /* 0x0A */ 1866 U8 Reserved5; /* 0x0B */ 1867} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1868 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1869 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 1870 1871/* defines for ControlFlags field */ 1872#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1873#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1874#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1875#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1876 1877/* defines for PortWidthModeGroup field */ 1878#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 1879 1880/* defines for InactivityTimerExponent field */ 1881#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 1882#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 1883#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 1884#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 1885#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 1886#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 1887#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 1888#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 1889 1890#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 1891#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 1892#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 1893#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 1894#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 1895#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 1896#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 1897#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 1898 1899/* 1900 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1901 * one and check the value returned for NumPhys at runtime. 1902 */ 1903#ifndef MPI2_SAS_IOUNIT5_PHY_MAX 1904#define MPI2_SAS_IOUNIT5_PHY_MAX (1) 1905#endif 1906 1907typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 1908 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1909 U8 NumPhys; /* 0x08 */ 1910 U8 Reserved1; /* 0x09 */ 1911 U16 Reserved2; /* 0x0A */ 1912 U32 Reserved3; /* 0x0C */ 1913 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings 1914 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 1915} MPI2_CONFIG_PAGE_SASIOUNIT_5, 1916 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 1917 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 1918 1919#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 1920 1921 1922/* SAS IO Unit Page 6 */ 1923 1924typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 1925 U8 CurrentStatus; /* 0x00 */ 1926 U8 CurrentModulation; /* 0x01 */ 1927 U8 CurrentUtilization; /* 0x02 */ 1928 U8 Reserved1; /* 0x03 */ 1929 U32 Reserved2; /* 0x04 */ 1930} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 1931 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 1932 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 1933 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 1934 1935/* defines for CurrentStatus field */ 1936#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 1937#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 1938#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 1939#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 1940#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 1941#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 1942#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 1943#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 1944 1945/* defines for CurrentModulation field */ 1946#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 1947#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 1948#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 1949#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 1950 1951/* 1952 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1953 * one and check the value returned for NumGroups at runtime. 1954 */ 1955#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 1956#define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 1957#endif 1958 1959typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 1960 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1961 U32 Reserved1; /* 0x08 */ 1962 U32 Reserved2; /* 0x0C */ 1963 U8 NumGroups; /* 0x10 */ 1964 U8 Reserved3; /* 0x11 */ 1965 U16 Reserved4; /* 0x12 */ 1966 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1967 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 1968} MPI2_CONFIG_PAGE_SASIOUNIT_6, 1969 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 1970 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 1971 1972#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 1973 1974 1975/* SAS IO Unit Page 7 */ 1976 1977typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 1978 U8 Flags; /* 0x00 */ 1979 U8 Reserved1; /* 0x01 */ 1980 U16 Reserved2; /* 0x02 */ 1981 U8 Threshold75Pct; /* 0x04 */ 1982 U8 Threshold50Pct; /* 0x05 */ 1983 U8 Threshold25Pct; /* 0x06 */ 1984 U8 Reserved3; /* 0x07 */ 1985} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 1986 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 1987 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 1988 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 1989 1990/* defines for Flags field */ 1991#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 1992 1993 1994/* 1995 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1996 * one and check the value returned for NumGroups at runtime. 1997 */ 1998#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 1999#define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2000#endif 2001 2002typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2003 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2004 U8 SamplingInterval; /* 0x08 */ 2005 U8 WindowLength; /* 0x09 */ 2006 U16 Reserved1; /* 0x0A */ 2007 U32 Reserved2; /* 0x0C */ 2008 U32 Reserved3; /* 0x10 */ 2009 U8 NumGroups; /* 0x14 */ 2010 U8 Reserved4; /* 0x15 */ 2011 U16 Reserved5; /* 0x16 */ 2012 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2013 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2014} MPI2_CONFIG_PAGE_SASIOUNIT_7, 2015 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2016 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2017 2018#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2019 2020 2021/* SAS IO Unit Page 8 */ 2022 2023typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2024 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2025 U32 Reserved1; /* 0x08 */ 2026 U32 PowerManagementCapabilities;/* 0x0C */ 2027 U32 Reserved2; /* 0x10 */ 2028} MPI2_CONFIG_PAGE_SASIOUNIT_8, 2029 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2030 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2031 2032#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2033 2034/* defines for PowerManagementCapabilities field */ 2035#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000) 2036#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800) 2037#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400) 2038#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200) 2039#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100) 2040#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010) 2041#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008) 2042#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004) 2043#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002) 2044#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001) 2045 2046 2047 2048 2049/**************************************************************************** 2050* SAS Expander Config Pages 2051****************************************************************************/ 2052 2053/* SAS Expander Page 0 */ 2054 2055typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2056{ 2057 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2058 U8 PhysicalPort; /* 0x08 */ 2059 U8 ReportGenLength; /* 0x09 */ 2060 U16 EnclosureHandle; /* 0x0A */ 2061 U64 SASAddress; /* 0x0C */ 2062 U32 DiscoveryStatus; /* 0x14 */ 2063 U16 DevHandle; /* 0x18 */ 2064 U16 ParentDevHandle; /* 0x1A */ 2065 U16 ExpanderChangeCount; /* 0x1C */ 2066 U16 ExpanderRouteIndexes; /* 0x1E */ 2067 U8 NumPhys; /* 0x20 */ 2068 U8 SASLevel; /* 0x21 */ 2069 U16 Flags; /* 0x22 */ 2070 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2071 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2072 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2073 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2074 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2075 U16 ZoneLockInactivityLimit; /* 0x34 */ 2076 U16 Reserved1; /* 0x36 */ 2077 U8 TimeToReducedFunc; /* 0x38 */ 2078 U8 InitialTimeToReducedFunc; /* 0x39 */ 2079 U8 MaxReducedFuncTime; /* 0x3A */ 2080 U8 Reserved2; /* 0x3B */ 2081} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2082 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2083 2084#define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2085 2086/* values for SAS Expander Page 0 DiscoveryStatus field */ 2087#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2088#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2089#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2090#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2091#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2092#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2093#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2094#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2095#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2096#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2097#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2098#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2099#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2100#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2101#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2102#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2103#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2104#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2105#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2106#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2107 2108/* values for SAS Expander Page 0 Flags field */ 2109#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2110#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2111#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2112#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2113#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2114#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2115#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2116#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2117#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2118#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2119#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2120 2121 2122/* SAS Expander Page 1 */ 2123 2124typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2125{ 2126 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2127 U8 PhysicalPort; /* 0x08 */ 2128 U8 Reserved1; /* 0x09 */ 2129 U16 Reserved2; /* 0x0A */ 2130 U8 NumPhys; /* 0x0C */ 2131 U8 Phy; /* 0x0D */ 2132 U16 NumTableEntriesProgrammed; /* 0x0E */ 2133 U8 ProgrammedLinkRate; /* 0x10 */ 2134 U8 HwLinkRate; /* 0x11 */ 2135 U16 AttachedDevHandle; /* 0x12 */ 2136 U32 PhyInfo; /* 0x14 */ 2137 U32 AttachedDeviceInfo; /* 0x18 */ 2138 U16 ExpanderDevHandle; /* 0x1C */ 2139 U8 ChangeCount; /* 0x1E */ 2140 U8 NegotiatedLinkRate; /* 0x1F */ 2141 U8 PhyIdentifier; /* 0x20 */ 2142 U8 AttachedPhyIdentifier; /* 0x21 */ 2143 U8 Reserved3; /* 0x22 */ 2144 U8 DiscoveryInfo; /* 0x23 */ 2145 U32 AttachedPhyInfo; /* 0x24 */ 2146 U8 ZoneGroup; /* 0x28 */ 2147 U8 SelfConfigStatus; /* 0x29 */ 2148 U16 Reserved4; /* 0x2A */ 2149} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2150 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2151 2152#define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2153 2154/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2155 2156/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2157 2158/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2159 2160/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2161 2162/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2163 2164/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2165 2166/* values for SAS Expander Page 1 DiscoveryInfo field */ 2167#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2168#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2169#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2170 2171 2172/**************************************************************************** 2173* SAS Device Config Pages 2174****************************************************************************/ 2175 2176/* SAS Device Page 0 */ 2177 2178typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2179{ 2180 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2181 U16 Slot; /* 0x08 */ 2182 U16 EnclosureHandle; /* 0x0A */ 2183 U64 SASAddress; /* 0x0C */ 2184 U16 ParentDevHandle; /* 0x14 */ 2185 U8 PhyNum; /* 0x16 */ 2186 U8 AccessStatus; /* 0x17 */ 2187 U16 DevHandle; /* 0x18 */ 2188 U8 AttachedPhyIdentifier; /* 0x1A */ 2189 U8 ZoneGroup; /* 0x1B */ 2190 U32 DeviceInfo; /* 0x1C */ 2191 U16 Flags; /* 0x20 */ 2192 U8 PhysicalPort; /* 0x22 */ 2193 U8 MaxPortConnections; /* 0x23 */ 2194 U64 DeviceName; /* 0x24 */ 2195 U8 PortGroups; /* 0x2C */ 2196 U8 DmaGroup; /* 0x2D */ 2197 U8 ControlGroup; /* 0x2E */ 2198 U8 Reserved1; /* 0x2F */ 2199 U32 Reserved2; /* 0x30 */ 2200 U32 Reserved3; /* 0x34 */ 2201} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2202 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2203 2204#define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2205 2206/* values for SAS Device Page 0 AccessStatus field */ 2207#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2208#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2209#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2210#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2211#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2212#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2213#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2214#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2215/* specific values for SATA Init failures */ 2216#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2217#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2218#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2219#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2220#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2221#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2222#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2223#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2224#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2225#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2226#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2227 2228/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2229 2230/* values for SAS Device Page 0 Flags field */ 2231#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2232#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2233#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2234#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2235#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2236#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2237#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2238#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2239#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2240#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2241#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2242 2243 2244/* SAS Device Page 1 */ 2245 2246typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2247{ 2248 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2249 U32 Reserved1; /* 0x08 */ 2250 U64 SASAddress; /* 0x0C */ 2251 U32 Reserved2; /* 0x14 */ 2252 U16 DevHandle; /* 0x18 */ 2253 U16 Reserved3; /* 0x1A */ 2254 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2255} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2256 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2257 2258#define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2259 2260 2261/**************************************************************************** 2262* SAS PHY Config Pages 2263****************************************************************************/ 2264 2265/* SAS PHY Page 0 */ 2266 2267typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2268{ 2269 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2270 U16 OwnerDevHandle; /* 0x08 */ 2271 U16 Reserved1; /* 0x0A */ 2272 U16 AttachedDevHandle; /* 0x0C */ 2273 U8 AttachedPhyIdentifier; /* 0x0E */ 2274 U8 Reserved2; /* 0x0F */ 2275 U32 AttachedPhyInfo; /* 0x10 */ 2276 U8 ProgrammedLinkRate; /* 0x14 */ 2277 U8 HwLinkRate; /* 0x15 */ 2278 U8 ChangeCount; /* 0x16 */ 2279 U8 Flags; /* 0x17 */ 2280 U32 PhyInfo; /* 0x18 */ 2281 U8 NegotiatedLinkRate; /* 0x1C */ 2282 U8 Reserved3; /* 0x1D */ 2283 U16 Reserved4; /* 0x1E */ 2284} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2285 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2286 2287#define MPI2_SASPHY0_PAGEVERSION (0x03) 2288 2289/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2290 2291/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2292 2293/* values for SAS PHY Page 0 Flags field */ 2294#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2295 2296/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2297 2298/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2299 2300/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2301 2302 2303/* SAS PHY Page 1 */ 2304 2305typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2306{ 2307 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2308 U32 Reserved1; /* 0x08 */ 2309 U32 InvalidDwordCount; /* 0x0C */ 2310 U32 RunningDisparityErrorCount; /* 0x10 */ 2311 U32 LossDwordSynchCount; /* 0x14 */ 2312 U32 PhyResetProblemCount; /* 0x18 */ 2313} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2314 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2315 2316#define MPI2_SASPHY1_PAGEVERSION (0x01) 2317 2318 2319/* SAS PHY Page 2 */ 2320 2321typedef struct _MPI2_SASPHY2_PHY_EVENT { 2322 U8 PhyEventCode; /* 0x00 */ 2323 U8 Reserved1; /* 0x01 */ 2324 U16 Reserved2; /* 0x02 */ 2325 U32 PhyEventInfo; /* 0x04 */ 2326} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2327 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2328 2329/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2330 2331 2332/* 2333 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2334 * one and check the value returned for NumPhyEvents at runtime. 2335 */ 2336#ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2337#define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2338#endif 2339 2340typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 2341 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2342 U32 Reserved1; /* 0x08 */ 2343 U8 NumPhyEvents; /* 0x0C */ 2344 U8 Reserved2; /* 0x0D */ 2345 U16 Reserved3; /* 0x0E */ 2346 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; 2347 /* 0x10 */ 2348} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2349 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2350 2351#define MPI2_SASPHY2_PAGEVERSION (0x00) 2352 2353 2354/* SAS PHY Page 3 */ 2355 2356typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 2357 U8 PhyEventCode; /* 0x00 */ 2358 U8 Reserved1; /* 0x01 */ 2359 U16 Reserved2; /* 0x02 */ 2360 U8 CounterType; /* 0x04 */ 2361 U8 ThresholdWindow; /* 0x05 */ 2362 U8 TimeUnits; /* 0x06 */ 2363 U8 Reserved3; /* 0x07 */ 2364 U32 EventThreshold; /* 0x08 */ 2365 U16 ThresholdFlags; /* 0x0C */ 2366 U16 Reserved4; /* 0x0E */ 2367} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2368 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2369 2370/* values for PhyEventCode field */ 2371#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2372#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2373#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2374#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2375#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2376#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2377#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2378#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2379#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2380#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2381#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2382#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2383#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2384#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2385#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2386#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2387#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2388#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2389#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2390#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2391#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2392#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2393#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2394#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2395#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2396#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2397#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2398#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2399#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2400#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2401#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2402#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2403#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2404#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2405#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2406#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2407#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2408 2409/* values for the CounterType field */ 2410#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2411#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2412#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2413 2414/* values for the TimeUnits field */ 2415#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2416#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2417#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2418#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2419 2420/* values for the ThresholdFlags field */ 2421#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2422#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2423 2424/* 2425 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2426 * one and check the value returned for NumPhyEvents at runtime. 2427 */ 2428#ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2429#define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2430#endif 2431 2432typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 2433 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2434 U32 Reserved1; /* 0x08 */ 2435 U8 NumPhyEvents; /* 0x0C */ 2436 U8 Reserved2; /* 0x0D */ 2437 U16 Reserved3; /* 0x0E */ 2438 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig 2439 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2440} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2441 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2442 2443#define MPI2_SASPHY3_PAGEVERSION (0x00) 2444 2445 2446/* SAS PHY Page 4 */ 2447 2448typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 2449 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2450 U16 Reserved1; /* 0x08 */ 2451 U8 Reserved2; /* 0x0A */ 2452 U8 Flags; /* 0x0B */ 2453 U8 InitialFrame[28]; /* 0x0C */ 2454} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2455 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2456 2457#define MPI2_SASPHY4_PAGEVERSION (0x00) 2458 2459/* values for the Flags field */ 2460#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2461#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2462 2463 2464 2465 2466/**************************************************************************** 2467* SAS Port Config Pages 2468****************************************************************************/ 2469 2470/* SAS Port Page 0 */ 2471 2472typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2473{ 2474 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2475 U8 PortNumber; /* 0x08 */ 2476 U8 PhysicalPort; /* 0x09 */ 2477 U8 PortWidth; /* 0x0A */ 2478 U8 PhysicalPortWidth; /* 0x0B */ 2479 U8 ZoneGroup; /* 0x0C */ 2480 U8 Reserved1; /* 0x0D */ 2481 U16 Reserved2; /* 0x0E */ 2482 U64 SASAddress; /* 0x10 */ 2483 U32 DeviceInfo; /* 0x18 */ 2484 U32 Reserved3; /* 0x1C */ 2485 U32 Reserved4; /* 0x20 */ 2486} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2487 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2488 2489#define MPI2_SASPORT0_PAGEVERSION (0x00) 2490 2491/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2492 2493 2494/**************************************************************************** 2495* SAS Enclosure Config Pages 2496****************************************************************************/ 2497 2498/* SAS Enclosure Page 0 */ 2499 2500typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2501{ 2502 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2503 U32 Reserved1; /* 0x08 */ 2504 U64 EnclosureLogicalID; /* 0x0C */ 2505 U16 Flags; /* 0x14 */ 2506 U16 EnclosureHandle; /* 0x16 */ 2507 U16 NumSlots; /* 0x18 */ 2508 U16 StartSlot; /* 0x1A */ 2509 U16 Reserved2; /* 0x1C */ 2510 U16 SEPDevHandle; /* 0x1E */ 2511 U32 Reserved3; /* 0x20 */ 2512 U32 Reserved4; /* 0x24 */ 2513} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2514 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2515 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2516 2517#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2518 2519/* values for SAS Enclosure Page 0 Flags field */ 2520#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2521#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2522#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2523#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2524#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2525#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2526#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2527 2528 2529/**************************************************************************** 2530* Log Config Page 2531****************************************************************************/ 2532 2533/* Log Page 0 */ 2534 2535/* 2536 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2537 * one and check the value returned for NumLogEntries at runtime. 2538 */ 2539#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2540#define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2541#endif 2542 2543#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2544 2545typedef struct _MPI2_LOG_0_ENTRY 2546{ 2547 U64 TimeStamp; /* 0x00 */ 2548 U32 Reserved1; /* 0x08 */ 2549 U16 LogSequence; /* 0x0C */ 2550 U16 LogEntryQualifier; /* 0x0E */ 2551 U8 VP_ID; /* 0x10 */ 2552 U8 VF_ID; /* 0x11 */ 2553 U16 Reserved2; /* 0x12 */ 2554 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2555} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2556 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2557 2558/* values for Log Page 0 LogEntry LogEntryQualifier field */ 2559#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2560#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2561#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2562#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2563#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2564 2565typedef struct _MPI2_CONFIG_PAGE_LOG_0 2566{ 2567 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2568 U32 Reserved1; /* 0x08 */ 2569 U32 Reserved2; /* 0x0C */ 2570 U16 NumLogEntries; /* 0x10 */ 2571 U16 Reserved3; /* 0x12 */ 2572 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2573} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2574 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2575 2576#define MPI2_LOG_0_PAGEVERSION (0x02) 2577 2578 2579/**************************************************************************** 2580* RAID Config Page 2581****************************************************************************/ 2582 2583/* RAID Page 0 */ 2584 2585/* 2586 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2587 * one and check the value returned for NumElements at runtime. 2588 */ 2589#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2590#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2591#endif 2592 2593typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2594{ 2595 U16 ElementFlags; /* 0x00 */ 2596 U16 VolDevHandle; /* 0x02 */ 2597 U8 HotSparePool; /* 0x04 */ 2598 U8 PhysDiskNum; /* 0x05 */ 2599 U16 PhysDiskDevHandle; /* 0x06 */ 2600} MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2601 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2602 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2603 2604/* values for the ElementFlags field */ 2605#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2606#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2607#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2608#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2609#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2610 2611 2612typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2613{ 2614 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2615 U8 NumHotSpares; /* 0x08 */ 2616 U8 NumPhysDisks; /* 0x09 */ 2617 U8 NumVolumes; /* 0x0A */ 2618 U8 ConfigNum; /* 0x0B */ 2619 U32 Flags; /* 0x0C */ 2620 U8 ConfigGUID[24]; /* 0x10 */ 2621 U32 Reserved1; /* 0x28 */ 2622 U8 NumElements; /* 0x2C */ 2623 U8 Reserved2; /* 0x2D */ 2624 U16 Reserved3; /* 0x2E */ 2625 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2626} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2627 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2628 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2629 2630#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2631 2632/* values for RAID Configuration Page 0 Flags field */ 2633#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2634 2635 2636/**************************************************************************** 2637* Driver Persistent Mapping Config Pages 2638****************************************************************************/ 2639 2640/* Driver Persistent Mapping Page 0 */ 2641 2642typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2643{ 2644 U64 PhysicalIdentifier; /* 0x00 */ 2645 U16 MappingInformation; /* 0x08 */ 2646 U16 DeviceIndex; /* 0x0A */ 2647 U32 PhysicalBitsMapping; /* 0x0C */ 2648 U32 Reserved1; /* 0x10 */ 2649} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2650 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2651 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2652 2653typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2654{ 2655 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2656 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2657} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2658 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2659 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2660 2661#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2662 2663/* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2664#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2665#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2666#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2667 2668 2669/**************************************************************************** 2670* Ethernet Config Pages 2671****************************************************************************/ 2672 2673/* Ethernet Page 0 */ 2674 2675/* IP address (union of IPv4 and IPv6) */ 2676typedef union _MPI2_ETHERNET_IP_ADDR { 2677 U32 IPv4Addr; 2678 U32 IPv6Addr[4]; 2679} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2680 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2681 2682#define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2683 2684typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 2685 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2686 U8 NumInterfaces; /* 0x08 */ 2687 U8 Reserved0; /* 0x09 */ 2688 U16 Reserved1; /* 0x0A */ 2689 U32 Status; /* 0x0C */ 2690 U8 MediaState; /* 0x10 */ 2691 U8 Reserved2; /* 0x11 */ 2692 U16 Reserved3; /* 0x12 */ 2693 U8 MacAddress[6]; /* 0x14 */ 2694 U8 Reserved4; /* 0x1A */ 2695 U8 Reserved5; /* 0x1B */ 2696 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2697 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2698 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2699 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2700 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2701 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2702 U8 HostName 2703 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2704} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2705 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2706 2707#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2708 2709/* values for Ethernet Page 0 Status field */ 2710#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2711#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2712#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2713#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2714#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2715#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2716#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2717#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2718#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2719#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2720#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2721#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2722 2723/* values for Ethernet Page 0 MediaState field */ 2724#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2725#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2726#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2727 2728#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2729#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2730#define MPI2_ETHPG0_MS_10MBIT (0x01) 2731#define MPI2_ETHPG0_MS_100MBIT (0x02) 2732#define MPI2_ETHPG0_MS_1GBIT (0x03) 2733 2734 2735/* Ethernet Page 1 */ 2736 2737typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 2738 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2739 U32 Reserved0; /* 0x08 */ 2740 U32 Flags; /* 0x0C */ 2741 U8 MediaState; /* 0x10 */ 2742 U8 Reserved1; /* 0x11 */ 2743 U16 Reserved2; /* 0x12 */ 2744 U8 MacAddress[6]; /* 0x14 */ 2745 U8 Reserved3; /* 0x1A */ 2746 U8 Reserved4; /* 0x1B */ 2747 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2748 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2749 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2750 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2751 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2752 U32 Reserved5; /* 0x6C */ 2753 U32 Reserved6; /* 0x70 */ 2754 U32 Reserved7; /* 0x74 */ 2755 U32 Reserved8; /* 0x78 */ 2756 U8 HostName 2757 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2758} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2759 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2760 2761#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2762 2763/* values for Ethernet Page 1 Flags field */ 2764#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2765#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2766#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2767#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2768#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2769#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2770#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2771#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2772#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2773 2774/* values for Ethernet Page 1 MediaState field */ 2775#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 2776#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 2777#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 2778 2779#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 2780#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 2781#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 2782#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 2783#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 2784 2785 2786#endif 2787