1/* 2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism 3 * 4 * (C) Copyright 2008-2010 Intel Corporation 5 * Author: Sreedhara DS (sreedhara.ds@intel.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 * 12 * SCU runing in ARC processor communicates with other entity running in IA 13 * core through IPC mechanism which in turn messaging between IA core ad SCU. 14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and 15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with 16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC) 17 * along with other APIs. 18 */ 19#include <linux/delay.h> 20#include <linux/errno.h> 21#include <linux/init.h> 22#include <linux/sysdev.h> 23#include <linux/pm.h> 24#include <linux/pci.h> 25#include <linux/interrupt.h> 26#include <asm/mrst.h> 27#include <asm/intel_scu_ipc.h> 28 29/* IPC defines the following message types */ 30#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ 31#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ 32#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */ 33#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ 34#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ 35 36/* Command id associated with message IPCMSG_PCNTRL */ 37#define IPC_CMD_PCNTRL_W 0 /* Register write */ 38#define IPC_CMD_PCNTRL_R 1 /* Register read */ 39#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ 40 41/* 42 * IPC register summary 43 * 44 * IPC register blocks are memory mapped at fixed address of 0xFF11C000 45 * To read or write information to the SCU, driver writes to IPC-1 memory 46 * mapped registers (base address 0xFF11C000). The following is the IPC 47 * mechanism 48 * 49 * 1. IA core cDMI interface claims this transaction and converts it to a 50 * Transaction Layer Packet (TLP) message which is sent across the cDMI. 51 * 52 * 2. South Complex cDMI block receives this message and writes it to 53 * the IPC-1 register block, causing an interrupt to the SCU 54 * 55 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate 56 * message handler is called within firmware. 57 */ 58 59#define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */ 60#define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */ 61#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ 62#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ 63#define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */ 64#define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */ 65 66static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id); 67static void ipc_remove(struct pci_dev *pdev); 68 69struct intel_scu_ipc_dev { 70 struct pci_dev *pdev; 71 void __iomem *ipc_base; 72 void __iomem *i2c_base; 73}; 74 75static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ 76 77static int platform; /* Platform type */ 78 79/* 80 * IPC Read Buffer (Read Only): 81 * 16 byte buffer for receiving data from SCU, if IPC command 82 * processing results in response data 83 */ 84#define IPC_READ_BUFFER 0x90 85 86#define IPC_I2C_CNTRL_ADDR 0 87#define I2C_DATA_ADDR 0x04 88 89static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */ 90 91/* 92 * Command Register (Write Only): 93 * A write to this register results in an interrupt to the SCU core processor 94 * Format: 95 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)| 96 */ 97static inline void ipc_command(u32 cmd) /* Send ipc command */ 98{ 99 writel(cmd, ipcdev.ipc_base); 100} 101 102/* 103 * IPC Write Buffer (Write Only): 104 * 16-byte buffer for sending data associated with IPC command to 105 * SCU. Size of the data is specified in the IPC_COMMAND_REG register 106 */ 107static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */ 108{ 109 writel(data, ipcdev.ipc_base + 0x80 + offset); 110} 111 112/* 113 * Status Register (Read Only): 114 * Driver will read this register to get the ready/busy status of the IPC 115 * block and error status of the IPC command that was just processed by SCU 116 * Format: 117 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)| 118 */ 119 120static inline u8 ipc_read_status(void) 121{ 122 return __raw_readl(ipcdev.ipc_base + 0x04); 123} 124 125static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */ 126{ 127 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); 128} 129 130static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */ 131{ 132 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); 133} 134 135static inline int busy_loop(void) /* Wait till scu status is busy */ 136{ 137 u32 status = 0; 138 u32 loop_count = 0; 139 140 status = ipc_read_status(); 141 while (status & 1) { 142 udelay(1); /* scu processing time is in few u secods */ 143 status = ipc_read_status(); 144 loop_count++; 145 /* break if scu doesn't reset busy bit after huge retry */ 146 if (loop_count > 100000) { 147 dev_err(&ipcdev.pdev->dev, "IPC timed out"); 148 return -ETIMEDOUT; 149 } 150 } 151 if ((status >> 1) & 1) 152 return -EIO; 153 154 return 0; 155} 156 157/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ 158static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) 159{ 160 int i, nc, bytes, d; 161 u32 offset = 0; 162 u32 err = 0; 163 u8 cbuf[IPC_WWBUF_SIZE] = { }; 164 u32 *wbuf = (u32 *)&cbuf; 165 166 mutex_lock(&ipclock); 167 168 memset(cbuf, 0, sizeof(cbuf)); 169 170 if (ipcdev.pdev == NULL) { 171 mutex_unlock(&ipclock); 172 return -ENODEV; 173 } 174 175 if (platform != MRST_CPU_CHIP_PENWELL) { 176 bytes = 0; 177 d = 0; 178 for (i = 0; i < count; i++) { 179 cbuf[bytes++] = addr[i]; 180 cbuf[bytes++] = addr[i] >> 8; 181 if (id != IPC_CMD_PCNTRL_R) 182 cbuf[bytes++] = data[d++]; 183 if (id == IPC_CMD_PCNTRL_M) 184 cbuf[bytes++] = data[d++]; 185 } 186 for (i = 0; i < bytes; i += 4) 187 ipc_data_writel(wbuf[i/4], i); 188 ipc_command(bytes << 16 | id << 12 | 0 << 8 | op); 189 } else { 190 for (nc = 0; nc < count; nc++, offset += 2) { 191 cbuf[offset] = addr[nc]; 192 cbuf[offset + 1] = addr[nc] >> 8; 193 } 194 195 if (id == IPC_CMD_PCNTRL_R) { 196 for (nc = 0, offset = 0; nc < count; nc++, offset += 4) 197 ipc_data_writel(wbuf[nc], offset); 198 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op); 199 } else if (id == IPC_CMD_PCNTRL_W) { 200 for (nc = 0; nc < count; nc++, offset += 1) 201 cbuf[offset] = data[nc]; 202 for (nc = 0, offset = 0; nc < count; nc++, offset += 4) 203 ipc_data_writel(wbuf[nc], offset); 204 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op); 205 } else if (id == IPC_CMD_PCNTRL_M) { 206 cbuf[offset] = data[0]; 207 cbuf[offset + 1] = data[1]; 208 ipc_data_writel(wbuf[0], 0); /* Write wbuff */ 209 ipc_command(4 << 16 | id << 12 | 0 << 8 | op); 210 } 211 } 212 213 err = busy_loop(); 214 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ 215 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16); 216 if (platform != MRST_CPU_CHIP_PENWELL) { 217 for (nc = 0, offset = 2; nc < count; nc++, offset += 3) 218 data[nc] = ipc_data_readb(offset); 219 } else { 220 for (nc = 0; nc < count; nc++) 221 data[nc] = ipc_data_readb(nc); 222 } 223 } 224 mutex_unlock(&ipclock); 225 return err; 226} 227 228/** 229 * intel_scu_ipc_ioread8 - read a word via the SCU 230 * @addr: register on SCU 231 * @data: return pointer for read byte 232 * 233 * Read a single register. Returns 0 on success or an error code. All 234 * locking between SCU accesses is handled for the caller. 235 * 236 * This function may sleep. 237 */ 238int intel_scu_ipc_ioread8(u16 addr, u8 *data) 239{ 240 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 241} 242EXPORT_SYMBOL(intel_scu_ipc_ioread8); 243 244/** 245 * intel_scu_ipc_ioread16 - read a word via the SCU 246 * @addr: register on SCU 247 * @data: return pointer for read word 248 * 249 * Read a register pair. Returns 0 on success or an error code. All 250 * locking between SCU accesses is handled for the caller. 251 * 252 * This function may sleep. 253 */ 254int intel_scu_ipc_ioread16(u16 addr, u16 *data) 255{ 256 u16 x[2] = {addr, addr + 1 }; 257 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 258} 259EXPORT_SYMBOL(intel_scu_ipc_ioread16); 260 261/** 262 * intel_scu_ipc_ioread32 - read a dword via the SCU 263 * @addr: register on SCU 264 * @data: return pointer for read dword 265 * 266 * Read four registers. Returns 0 on success or an error code. All 267 * locking between SCU accesses is handled for the caller. 268 * 269 * This function may sleep. 270 */ 271int intel_scu_ipc_ioread32(u16 addr, u32 *data) 272{ 273 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; 274 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 275} 276EXPORT_SYMBOL(intel_scu_ipc_ioread32); 277 278/** 279 * intel_scu_ipc_iowrite8 - write a byte via the SCU 280 * @addr: register on SCU 281 * @data: byte to write 282 * 283 * Write a single register. Returns 0 on success or an error code. All 284 * locking between SCU accesses is handled for the caller. 285 * 286 * This function may sleep. 287 */ 288int intel_scu_ipc_iowrite8(u16 addr, u8 data) 289{ 290 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 291} 292EXPORT_SYMBOL(intel_scu_ipc_iowrite8); 293 294/** 295 * intel_scu_ipc_iowrite16 - write a word via the SCU 296 * @addr: register on SCU 297 * @data: word to write 298 * 299 * Write two registers. Returns 0 on success or an error code. All 300 * locking between SCU accesses is handled for the caller. 301 * 302 * This function may sleep. 303 */ 304int intel_scu_ipc_iowrite16(u16 addr, u16 data) 305{ 306 u16 x[2] = {addr, addr + 1 }; 307 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 308} 309EXPORT_SYMBOL(intel_scu_ipc_iowrite16); 310 311/** 312 * intel_scu_ipc_iowrite32 - write a dword via the SCU 313 * @addr: register on SCU 314 * @data: dword to write 315 * 316 * Write four registers. Returns 0 on success or an error code. All 317 * locking between SCU accesses is handled for the caller. 318 * 319 * This function may sleep. 320 */ 321int intel_scu_ipc_iowrite32(u16 addr, u32 data) 322{ 323 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; 324 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 325} 326EXPORT_SYMBOL(intel_scu_ipc_iowrite32); 327 328/** 329 * intel_scu_ipc_readvv - read a set of registers 330 * @addr: register list 331 * @data: bytes to return 332 * @len: length of array 333 * 334 * Read registers. Returns 0 on success or an error code. All 335 * locking between SCU accesses is handled for the caller. 336 * 337 * The largest array length permitted by the hardware is 5 items. 338 * 339 * This function may sleep. 340 */ 341int intel_scu_ipc_readv(u16 *addr, u8 *data, int len) 342{ 343 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 344} 345EXPORT_SYMBOL(intel_scu_ipc_readv); 346 347/** 348 * intel_scu_ipc_writev - write a set of registers 349 * @addr: register list 350 * @data: bytes to write 351 * @len: length of array 352 * 353 * Write registers. Returns 0 on success or an error code. All 354 * locking between SCU accesses is handled for the caller. 355 * 356 * The largest array length permitted by the hardware is 5 items. 357 * 358 * This function may sleep. 359 * 360 */ 361int intel_scu_ipc_writev(u16 *addr, u8 *data, int len) 362{ 363 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 364} 365EXPORT_SYMBOL(intel_scu_ipc_writev); 366 367 368/** 369 * intel_scu_ipc_update_register - r/m/w a register 370 * @addr: register address 371 * @bits: bits to update 372 * @mask: mask of bits to update 373 * 374 * Read-modify-write power control unit register. The first data argument 375 * must be register value and second is mask value 376 * mask is a bitmap that indicates which bits to update. 377 * 0 = masked. Don't modify this bit, 1 = modify this bit. 378 * returns 0 on success or an error code. 379 * 380 * This function may sleep. Locking between SCU accesses is handled 381 * for the caller. 382 */ 383int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) 384{ 385 u8 data[2] = { bits, mask }; 386 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M); 387} 388EXPORT_SYMBOL(intel_scu_ipc_update_register); 389 390/** 391 * intel_scu_ipc_simple_command - send a simple command 392 * @cmd: command 393 * @sub: sub type 394 * 395 * Issue a simple command to the SCU. Do not use this interface if 396 * you must then access data as any data values may be overwritten 397 * by another SCU access by the time this function returns. 398 * 399 * This function may sleep. Locking for SCU accesses is handled for 400 * the caller. 401 */ 402int intel_scu_ipc_simple_command(int cmd, int sub) 403{ 404 u32 err = 0; 405 406 mutex_lock(&ipclock); 407 if (ipcdev.pdev == NULL) { 408 mutex_unlock(&ipclock); 409 return -ENODEV; 410 } 411 ipc_command(sub << 12 | cmd); 412 err = busy_loop(); 413 mutex_unlock(&ipclock); 414 return err; 415} 416EXPORT_SYMBOL(intel_scu_ipc_simple_command); 417 418/** 419 * intel_scu_ipc_command - command with data 420 * @cmd: command 421 * @sub: sub type 422 * @in: input data 423 * @inlen: input length in dwords 424 * @out: output data 425 * @outlein: output length in dwords 426 * 427 * Issue a command to the SCU which involves data transfers. Do the 428 * data copies under the lock but leave it for the caller to interpret 429 */ 430 431int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, 432 u32 *out, int outlen) 433{ 434 u32 err = 0; 435 int i = 0; 436 437 mutex_lock(&ipclock); 438 if (ipcdev.pdev == NULL) { 439 mutex_unlock(&ipclock); 440 return -ENODEV; 441 } 442 443 for (i = 0; i < inlen; i++) 444 ipc_data_writel(*in++, 4 * i); 445 446 ipc_command((inlen << 16) | (sub << 12) | cmd); 447 err = busy_loop(); 448 449 for (i = 0; i < outlen; i++) 450 *out++ = ipc_data_readl(4 * i); 451 452 mutex_unlock(&ipclock); 453 return err; 454} 455EXPORT_SYMBOL(intel_scu_ipc_command); 456 457/*I2C commands */ 458#define IPC_I2C_WRITE 1 /* I2C Write command */ 459#define IPC_I2C_READ 2 /* I2C Read command */ 460 461/** 462 * intel_scu_ipc_i2c_cntrl - I2C read/write operations 463 * @addr: I2C address + command bits 464 * @data: data to read/write 465 * 466 * Perform an an I2C read/write operation via the SCU. All locking is 467 * handled for the caller. This function may sleep. 468 * 469 * Returns an error code or 0 on success. 470 * 471 * This has to be in the IPC driver for the locking. 472 */ 473int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data) 474{ 475 u32 cmd = 0; 476 477 mutex_lock(&ipclock); 478 if (ipcdev.pdev == NULL) { 479 mutex_unlock(&ipclock); 480 return -ENODEV; 481 } 482 cmd = (addr >> 24) & 0xFF; 483 if (cmd == IPC_I2C_READ) { 484 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); 485 /* Write not getting updated without delay */ 486 mdelay(1); 487 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR); 488 } else if (cmd == IPC_I2C_WRITE) { 489 writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR); 490 mdelay(1); 491 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); 492 } else { 493 dev_err(&ipcdev.pdev->dev, 494 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd); 495 496 mutex_unlock(&ipclock); 497 return -1; 498 } 499 mutex_unlock(&ipclock); 500 return 0; 501} 502EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl); 503 504#define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */ 505#define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */ 506#define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */ 507#define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */ 508/* IPC inform SCU to get ready for update process */ 509#define IPC_CMD_FW_UPDATE_READY 0x10FE 510/* IPC inform SCU to go for update process */ 511#define IPC_CMD_FW_UPDATE_GO 0x20FE 512/* Status code for fw update */ 513#define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */ 514#define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */ 515#define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */ 516#define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */ 517 518struct fw_update_mailbox { 519 u32 status; 520 u32 scu_flag; 521 u32 driver_flag; 522}; 523 524 525/** 526 * intel_scu_ipc_fw_update - Firmware update utility 527 * @buffer: firmware buffer 528 * @length: size of firmware buffer 529 * 530 * This function provides an interface to load the firmware into 531 * the SCU. Returns 0 on success or -1 on failure 532 */ 533int intel_scu_ipc_fw_update(u8 *buffer, u32 length) 534{ 535 void __iomem *fw_update_base; 536 struct fw_update_mailbox __iomem *mailbox = NULL; 537 int retry_cnt = 0; 538 u32 status; 539 540 mutex_lock(&ipclock); 541 fw_update_base = ioremap_nocache(IPC_FW_LOAD_ADDR, (128*1024)); 542 if (fw_update_base == NULL) { 543 mutex_unlock(&ipclock); 544 return -ENOMEM; 545 } 546 mailbox = ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR, 547 sizeof(struct fw_update_mailbox)); 548 if (mailbox == NULL) { 549 iounmap(fw_update_base); 550 mutex_unlock(&ipclock); 551 return -ENOMEM; 552 } 553 554 ipc_command(IPC_CMD_FW_UPDATE_READY); 555 556 /* Intitialize mailbox */ 557 writel(0, &mailbox->status); 558 writel(0, &mailbox->scu_flag); 559 writel(0, &mailbox->driver_flag); 560 561 /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/ 562 memcpy_toio(fw_update_base, buffer, 0x800); 563 564 /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02). 565 * Upon receiving this command, SCU will write the 2K MIP header 566 * from 0xFFFC0000 into NAND. 567 * SCU will write a status code into the Mailbox, and then set scu_flag. 568 */ 569 570 ipc_command(IPC_CMD_FW_UPDATE_GO); 571 572 /*Driver stalls until scu_flag is set */ 573 while (readl(&mailbox->scu_flag) != 1) { 574 rmb(); 575 mdelay(1); 576 } 577 578 /* Driver checks Mailbox status. 579 * If the status is 'BADN', then abort (bad NAND). 580 * If the status is 'IPC_FW_TXLOW', then continue. 581 */ 582 while (readl(&mailbox->status) != IPC_FW_TXLOW) { 583 rmb(); 584 mdelay(10); 585 } 586 mdelay(10); 587 588update_retry: 589 if (retry_cnt > 5) 590 goto update_end; 591 592 if (readl(&mailbox->status) != IPC_FW_TXLOW) 593 goto update_end; 594 buffer = buffer + 0x800; 595 memcpy_toio(fw_update_base, buffer, 0x20000); 596 writel(1, &mailbox->driver_flag); 597 while (readl(&mailbox->scu_flag) == 1) { 598 rmb(); 599 mdelay(1); 600 } 601 602 /* check for 'BADN' */ 603 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN) 604 goto update_end; 605 606 while (readl(&mailbox->status) != IPC_FW_TXHIGH) { 607 rmb(); 608 mdelay(10); 609 } 610 mdelay(10); 611 612 if (readl(&mailbox->status) != IPC_FW_TXHIGH) 613 goto update_end; 614 615 buffer = buffer + 0x20000; 616 memcpy_toio(fw_update_base, buffer, 0x20000); 617 writel(0, &mailbox->driver_flag); 618 619 while (mailbox->scu_flag == 0) { 620 rmb(); 621 mdelay(1); 622 } 623 624 /* check for 'BADN' */ 625 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN) 626 goto update_end; 627 628 if (readl(&mailbox->status) == IPC_FW_TXLOW) { 629 ++retry_cnt; 630 goto update_retry; 631 } 632 633update_end: 634 status = readl(&mailbox->status); 635 636 iounmap(fw_update_base); 637 iounmap(mailbox); 638 mutex_unlock(&ipclock); 639 640 if (status == IPC_FW_UPDATE_SUCCESS) 641 return 0; 642 return -1; 643} 644EXPORT_SYMBOL(intel_scu_ipc_fw_update); 645 646/* 647 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1 648 * When ioc bit is set to 1, caller api must wait for interrupt handler called 649 * which in turn unlocks the caller api. Currently this is not used 650 * 651 * This is edge triggered so we need take no action to clear anything 652 */ 653static irqreturn_t ioc(int irq, void *dev_id) 654{ 655 return IRQ_HANDLED; 656} 657 658/** 659 * ipc_probe - probe an Intel SCU IPC 660 * @dev: the PCI device matching 661 * @id: entry in the match table 662 * 663 * Enable and install an intel SCU IPC. This appears in the PCI space 664 * but uses some hard coded addresses as well. 665 */ 666static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id) 667{ 668 int err; 669 resource_size_t pci_resource; 670 671 if (ipcdev.pdev) /* We support only one SCU */ 672 return -EBUSY; 673 674 ipcdev.pdev = pci_dev_get(dev); 675 676 err = pci_enable_device(dev); 677 if (err) 678 return err; 679 680 err = pci_request_regions(dev, "intel_scu_ipc"); 681 if (err) 682 return err; 683 684 pci_resource = pci_resource_start(dev, 0); 685 if (!pci_resource) 686 return -ENOMEM; 687 688 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev)) 689 return -EBUSY; 690 691 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR); 692 if (!ipcdev.ipc_base) 693 return -ENOMEM; 694 695 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR); 696 if (!ipcdev.i2c_base) { 697 iounmap(ipcdev.ipc_base); 698 return -ENOMEM; 699 } 700 return 0; 701} 702 703/** 704 * ipc_remove - remove a bound IPC device 705 * @pdev: PCI device 706 * 707 * In practice the SCU is not removable but this function is also 708 * called for each device on a module unload or cleanup which is the 709 * path that will get used. 710 * 711 * Free up the mappings and release the PCI resources 712 */ 713static void ipc_remove(struct pci_dev *pdev) 714{ 715 free_irq(pdev->irq, &ipcdev); 716 pci_release_regions(pdev); 717 pci_dev_put(ipcdev.pdev); 718 iounmap(ipcdev.ipc_base); 719 iounmap(ipcdev.i2c_base); 720 ipcdev.pdev = NULL; 721} 722 723static const struct pci_device_id pci_ids[] = { 724 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)}, 725 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)}, 726 { 0,} 727}; 728MODULE_DEVICE_TABLE(pci, pci_ids); 729 730static struct pci_driver ipc_driver = { 731 .name = "intel_scu_ipc", 732 .id_table = pci_ids, 733 .probe = ipc_probe, 734 .remove = ipc_remove, 735}; 736 737 738static int __init intel_scu_ipc_init(void) 739{ 740 platform = mrst_identify_cpu(); 741 if (platform == 0) 742 return -ENODEV; 743 return pci_register_driver(&ipc_driver); 744} 745 746static void __exit intel_scu_ipc_exit(void) 747{ 748 pci_unregister_driver(&ipc_driver); 749} 750 751MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>"); 752MODULE_DESCRIPTION("Intel SCU IPC driver"); 753MODULE_LICENSE("GPL"); 754 755module_init(intel_scu_ipc_init); 756module_exit(intel_scu_ipc_exit); 757