1/* 2 * Driver for Intel I82092AA PCI-PCMCIA bridge. 3 * 4 * (C) 2001 Red Hat, Inc. 5 * 6 * Author: Arjan Van De Ven <arjanv@redhat.com> 7 * Loosly based on i82365.c from the pcmcia-cs package 8 */ 9 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/pci.h> 13#include <linux/init.h> 14#include <linux/workqueue.h> 15#include <linux/interrupt.h> 16#include <linux/device.h> 17 18#include <pcmcia/ss.h> 19#include <pcmcia/cs.h> 20 21#include <asm/system.h> 22#include <asm/io.h> 23 24#include "i82092aa.h" 25#include "i82365.h" 26 27MODULE_LICENSE("GPL"); 28 29/* PCI core routines */ 30static struct pci_device_id i82092aa_pci_ids[] = { 31 { 32 .vendor = PCI_VENDOR_ID_INTEL, 33 .device = PCI_DEVICE_ID_INTEL_82092AA_0, 34 .subvendor = PCI_ANY_ID, 35 .subdevice = PCI_ANY_ID, 36 }, 37 {} 38}; 39MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); 40 41static struct pci_driver i82092aa_pci_driver = { 42 .name = "i82092aa", 43 .id_table = i82092aa_pci_ids, 44 .probe = i82092aa_pci_probe, 45 .remove = __devexit_p(i82092aa_pci_remove), 46}; 47 48 49/* the pccard structure and its functions */ 50static struct pccard_operations i82092aa_operations = { 51 .init = i82092aa_init, 52 .get_status = i82092aa_get_status, 53 .set_socket = i82092aa_set_socket, 54 .set_io_map = i82092aa_set_io_map, 55 .set_mem_map = i82092aa_set_mem_map, 56}; 57 58/* The card can do upto 4 sockets, allocate a structure for each of them */ 59 60struct socket_info { 61 int number; 62 int card_state; /* 0 = no socket, 63 1 = empty socket, 64 2 = card but not initialized, 65 3 = operational card */ 66 unsigned int io_base; /* base io address of the socket */ 67 68 struct pcmcia_socket socket; 69 struct pci_dev *dev; /* The PCI device for the socket */ 70}; 71 72#define MAX_SOCKETS 4 73static struct socket_info sockets[MAX_SOCKETS]; 74static int socket_count; /* shortcut */ 75 76 77static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 78{ 79 unsigned char configbyte; 80 int i, ret; 81 82 enter("i82092aa_pci_probe"); 83 84 if ((ret = pci_enable_device(dev))) 85 return ret; 86 87 pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */ 88 switch(configbyte&6) { 89 case 0: 90 socket_count = 2; 91 break; 92 case 2: 93 socket_count = 1; 94 break; 95 case 4: 96 case 6: 97 socket_count = 4; 98 break; 99 100 default: 101 printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n"); 102 ret = -EIO; 103 goto err_out_disable; 104 } 105 printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count); 106 107 if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { 108 ret = -EBUSY; 109 goto err_out_disable; 110 } 111 112 for (i = 0;i<socket_count;i++) { 113 sockets[i].card_state = 1; /* 1 = present but empty */ 114 sockets[i].io_base = pci_resource_start(dev, 0); 115 sockets[i].socket.features |= SS_CAP_PCCARD; 116 sockets[i].socket.map_size = 0x1000; 117 sockets[i].socket.irq_mask = 0; 118 sockets[i].socket.pci_irq = dev->irq; 119 sockets[i].socket.cb_dev = dev; 120 sockets[i].socket.owner = THIS_MODULE; 121 122 sockets[i].number = i; 123 124 if (card_present(i)) { 125 sockets[i].card_state = 3; 126 dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i); 127 } else { 128 dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i); 129 } 130 } 131 132 /* Now, specifiy that all interrupts are to be done as PCI interrupts */ 133 configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */ 134 pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */ 135 136 /* Register the interrupt handler */ 137 dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq); 138 if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) { 139 printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq); 140 goto err_out_free_res; 141 } 142 143 pci_set_drvdata(dev, &sockets[i].socket); 144 145 for (i = 0; i<socket_count; i++) { 146 sockets[i].socket.dev.parent = &dev->dev; 147 sockets[i].socket.ops = &i82092aa_operations; 148 sockets[i].socket.resource_ops = &pccard_nonstatic_ops; 149 ret = pcmcia_register_socket(&sockets[i].socket); 150 if (ret) { 151 goto err_out_free_sockets; 152 } 153 } 154 155 leave("i82092aa_pci_probe"); 156 return 0; 157 158err_out_free_sockets: 159 if (i) { 160 for (i--;i>=0;i--) { 161 pcmcia_unregister_socket(&sockets[i].socket); 162 } 163 } 164 free_irq(dev->irq, i82092aa_interrupt); 165err_out_free_res: 166 release_region(pci_resource_start(dev, 0), 2); 167err_out_disable: 168 pci_disable_device(dev); 169 return ret; 170} 171 172static void __devexit i82092aa_pci_remove(struct pci_dev *dev) 173{ 174 struct pcmcia_socket *socket = pci_get_drvdata(dev); 175 176 enter("i82092aa_pci_remove"); 177 178 free_irq(dev->irq, i82092aa_interrupt); 179 180 if (socket) 181 pcmcia_unregister_socket(socket); 182 183 leave("i82092aa_pci_remove"); 184} 185 186static DEFINE_SPINLOCK(port_lock); 187 188/* basic value read/write functions */ 189 190static unsigned char indirect_read(int socket, unsigned short reg) 191{ 192 unsigned short int port; 193 unsigned char val; 194 unsigned long flags; 195 spin_lock_irqsave(&port_lock,flags); 196 reg += socket * 0x40; 197 port = sockets[socket].io_base; 198 outb(reg,port); 199 val = inb(port+1); 200 spin_unlock_irqrestore(&port_lock,flags); 201 return val; 202} 203 204 205static void indirect_write(int socket, unsigned short reg, unsigned char value) 206{ 207 unsigned short int port; 208 unsigned long flags; 209 spin_lock_irqsave(&port_lock,flags); 210 reg = reg + socket * 0x40; 211 port = sockets[socket].io_base; 212 outb(reg,port); 213 outb(value,port+1); 214 spin_unlock_irqrestore(&port_lock,flags); 215} 216 217static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) 218{ 219 unsigned short int port; 220 unsigned char val; 221 unsigned long flags; 222 spin_lock_irqsave(&port_lock,flags); 223 reg = reg + socket * 0x40; 224 port = sockets[socket].io_base; 225 outb(reg,port); 226 val = inb(port+1); 227 val |= mask; 228 outb(reg,port); 229 outb(val,port+1); 230 spin_unlock_irqrestore(&port_lock,flags); 231} 232 233 234static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) 235{ 236 unsigned short int port; 237 unsigned char val; 238 unsigned long flags; 239 spin_lock_irqsave(&port_lock,flags); 240 reg = reg + socket * 0x40; 241 port = sockets[socket].io_base; 242 outb(reg,port); 243 val = inb(port+1); 244 val &= ~mask; 245 outb(reg,port); 246 outb(val,port+1); 247 spin_unlock_irqrestore(&port_lock,flags); 248} 249 250static void indirect_write16(int socket, unsigned short reg, unsigned short value) 251{ 252 unsigned short int port; 253 unsigned char val; 254 unsigned long flags; 255 spin_lock_irqsave(&port_lock,flags); 256 reg = reg + socket * 0x40; 257 port = sockets[socket].io_base; 258 259 outb(reg,port); 260 val = value & 255; 261 outb(val,port+1); 262 263 reg++; 264 265 outb(reg,port); 266 val = value>>8; 267 outb(val,port+1); 268 spin_unlock_irqrestore(&port_lock,flags); 269} 270 271/* simple helper functions */ 272/* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ 273static int cycle_time = 120; 274 275static int to_cycles(int ns) 276{ 277 if (cycle_time!=0) 278 return ns/cycle_time; 279 else 280 return 0; 281} 282 283 284/* Interrupt handler functionality */ 285 286static irqreturn_t i82092aa_interrupt(int irq, void *dev) 287{ 288 int i; 289 int loopcount = 0; 290 int handled = 0; 291 292 unsigned int events, active=0; 293 294/* enter("i82092aa_interrupt");*/ 295 296 while (1) { 297 loopcount++; 298 if (loopcount>20) { 299 printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n"); 300 break; 301 } 302 303 active = 0; 304 305 for (i=0;i<socket_count;i++) { 306 int csc; 307 if (sockets[i].card_state==0) /* Inactive socket, should not happen */ 308 continue; 309 310 csc = indirect_read(i,I365_CSC); /* card status change register */ 311 312 if (csc==0) /* no events on this socket */ 313 continue; 314 handled = 1; 315 events = 0; 316 317 if (csc & I365_CSC_DETECT) { 318 events |= SS_DETECT; 319 printk("Card detected in socket %i!\n",i); 320 } 321 322 if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) { 323 /* For IO/CARDS, bit 0 means "read the card" */ 324 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; 325 } else { 326 /* Check for battery/ready events */ 327 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; 328 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; 329 events |= (csc & I365_CSC_READY) ? SS_READY : 0; 330 } 331 332 if (events) { 333 pcmcia_parse_events(&sockets[i].socket, events); 334 } 335 active |= events; 336 } 337 338 if (active==0) /* no more events to handle */ 339 break; 340 341 } 342 return IRQ_RETVAL(handled); 343/* leave("i82092aa_interrupt");*/ 344} 345 346 347 348/* socket functions */ 349 350static int card_present(int socketno) 351{ 352 unsigned int val; 353 enter("card_present"); 354 355 if ((socketno<0) || (socketno >= MAX_SOCKETS)) 356 return 0; 357 if (sockets[socketno].io_base == 0) 358 return 0; 359 360 361 val = indirect_read(socketno, 1); /* Interface status register */ 362 if ((val&12)==12) { 363 leave("card_present 1"); 364 return 1; 365 } 366 367 leave("card_present 0"); 368 return 0; 369} 370 371static void set_bridge_state(int sock) 372{ 373 enter("set_bridge_state"); 374 indirect_write(sock, I365_GBLCTL,0x00); 375 indirect_write(sock, I365_GENCTL,0x00); 376 377 indirect_setbit(sock, I365_INTCTL,0x08); 378 leave("set_bridge_state"); 379} 380 381 382 383 384 385 386static int i82092aa_init(struct pcmcia_socket *sock) 387{ 388 int i; 389 struct resource res = { .start = 0, .end = 0x0fff }; 390 pccard_io_map io = { 0, 0, 0, 0, 1 }; 391 pccard_mem_map mem = { .res = &res, }; 392 393 enter("i82092aa_init"); 394 395 for (i = 0; i < 2; i++) { 396 io.map = i; 397 i82092aa_set_io_map(sock, &io); 398 } 399 for (i = 0; i < 5; i++) { 400 mem.map = i; 401 i82092aa_set_mem_map(sock, &mem); 402 } 403 404 leave("i82092aa_init"); 405 return 0; 406} 407 408static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) 409{ 410 unsigned int sock = container_of(socket, struct socket_info, socket)->number; 411 unsigned int status; 412 413 enter("i82092aa_get_status"); 414 415 status = indirect_read(sock,I365_STATUS); /* Interface Status Register */ 416 *value = 0; 417 418 if ((status & I365_CS_DETECT) == I365_CS_DETECT) { 419 *value |= SS_DETECT; 420 } 421 422 /* IO cards have a different meaning of bits 0,1 */ 423 /* Also notice the inverse-logic on the bits */ 424 if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { 425 /* IO card */ 426 if (!(status & I365_CS_STSCHG)) 427 *value |= SS_STSCHG; 428 } else { /* non I/O card */ 429 if (!(status & I365_CS_BVD1)) 430 *value |= SS_BATDEAD; 431 if (!(status & I365_CS_BVD2)) 432 *value |= SS_BATWARN; 433 434 } 435 436 if (status & I365_CS_WRPROT) 437 (*value) |= SS_WRPROT; /* card is write protected */ 438 439 if (status & I365_CS_READY) 440 (*value) |= SS_READY; /* card is not busy */ 441 442 if (status & I365_CS_POWERON) 443 (*value) |= SS_POWERON; /* power is applied to the card */ 444 445 446 leave("i82092aa_get_status"); 447 return 0; 448} 449 450 451static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state) 452{ 453 unsigned int sock = container_of(socket, struct socket_info, socket)->number; 454 unsigned char reg; 455 456 enter("i82092aa_set_socket"); 457 458 /* First, set the global controller options */ 459 460 set_bridge_state(sock); 461 462 /* Values for the IGENC register */ 463 464 reg = 0; 465 if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */ 466 reg = reg | I365_PC_RESET; 467 if (state->flags & SS_IOCARD) 468 reg = reg | I365_PC_IOCARD; 469 470 indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */ 471 472 /* Power registers */ 473 474 reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ 475 476 if (state->flags & SS_PWR_AUTO) { 477 printk("Auto power\n"); 478 reg |= I365_PWR_AUTO; /* automatic power mngmnt */ 479 } 480 if (state->flags & SS_OUTPUT_ENA) { 481 printk("Power Enabled \n"); 482 reg |= I365_PWR_OUT; /* enable power */ 483 } 484 485 switch (state->Vcc) { 486 case 0: 487 break; 488 case 50: 489 printk("setting voltage to Vcc to 5V on socket %i\n",sock); 490 reg |= I365_VCC_5V; 491 break; 492 default: 493 printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc); 494 leave("i82092aa_set_socket"); 495 return -EINVAL; 496 } 497 498 499 switch (state->Vpp) { 500 case 0: 501 printk("not setting Vpp on socket %i\n",sock); 502 break; 503 case 50: 504 printk("setting Vpp to 5.0 for socket %i\n",sock); 505 reg |= I365_VPP1_5V | I365_VPP2_5V; 506 break; 507 case 120: 508 printk("setting Vpp to 12.0\n"); 509 reg |= I365_VPP1_12V | I365_VPP2_12V; 510 break; 511 default: 512 printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc); 513 leave("i82092aa_set_socket"); 514 return -EINVAL; 515 } 516 517 if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */ 518 indirect_write(sock,I365_POWER,reg); 519 520 /* Enable specific interrupt events */ 521 522 reg = 0x00; 523 if (state->csc_mask & SS_DETECT) { 524 reg |= I365_CSC_DETECT; 525 } 526 if (state->flags & SS_IOCARD) { 527 if (state->csc_mask & SS_STSCHG) 528 reg |= I365_CSC_STSCHG; 529 } else { 530 if (state->csc_mask & SS_BATDEAD) 531 reg |= I365_CSC_BVD1; 532 if (state->csc_mask & SS_BATWARN) 533 reg |= I365_CSC_BVD2; 534 if (state->csc_mask & SS_READY) 535 reg |= I365_CSC_READY; 536 537 } 538 539 /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/ 540 541 indirect_write(sock,I365_CSCINT,reg); 542 (void)indirect_read(sock,I365_CSC); 543 544 leave("i82092aa_set_socket"); 545 return 0; 546} 547 548static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io) 549{ 550 unsigned int sock = container_of(socket, struct socket_info, socket)->number; 551 unsigned char map, ioctl; 552 553 enter("i82092aa_set_io_map"); 554 555 map = io->map; 556 557 /* Check error conditions */ 558 if (map > 1) { 559 leave("i82092aa_set_io_map with invalid map"); 560 return -EINVAL; 561 } 562 if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){ 563 leave("i82092aa_set_io_map with invalid io"); 564 return -EINVAL; 565 } 566 567 /* Turn off the window before changing anything */ 568 if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) 569 indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); 570 571/* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */ 572 573 /* write the new values */ 574 indirect_write16(sock,I365_IO(map)+I365_W_START,io->start); 575 indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop); 576 577 ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map); 578 579 if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) 580 ioctl |= I365_IOCTL_16BIT(map); 581 582 indirect_write(sock,I365_IOCTL,ioctl); 583 584 /* Turn the window back on if needed */ 585 if (io->flags & MAP_ACTIVE) 586 indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map)); 587 588 leave("i82092aa_set_io_map"); 589 return 0; 590} 591 592static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem) 593{ 594 struct socket_info *sock_info = container_of(socket, struct socket_info, socket); 595 unsigned int sock = sock_info->number; 596 struct pci_bus_region region; 597 unsigned short base, i; 598 unsigned char map; 599 600 enter("i82092aa_set_mem_map"); 601 602 pcibios_resource_to_bus(sock_info->dev, ®ion, mem->res); 603 604 map = mem->map; 605 if (map > 4) { 606 leave("i82092aa_set_mem_map: invalid map"); 607 return -EINVAL; 608 } 609 610 611 if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) || 612 (mem->speed > 1000) ) { 613 leave("i82092aa_set_mem_map: invalid address / speed"); 614 printk("invalid mem map for socket %i: %llx to %llx with a " 615 "start of %x\n", 616 sock, 617 (unsigned long long)region.start, 618 (unsigned long long)region.end, 619 mem->card_start); 620 return -EINVAL; 621 } 622 623 /* Turn off the window before changing anything */ 624 if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) 625 indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 626 627 628/* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */ 629 630 /* write the start address */ 631 base = I365_MEM(map); 632 i = (region.start >> 12) & 0x0fff; 633 if (mem->flags & MAP_16BIT) 634 i |= I365_MEM_16BIT; 635 if (mem->flags & MAP_0WS) 636 i |= I365_MEM_0WS; 637 indirect_write16(sock,base+I365_W_START,i); 638 639 /* write the stop address */ 640 641 i= (region.end >> 12) & 0x0fff; 642 switch (to_cycles(mem->speed)) { 643 case 0: 644 break; 645 case 1: 646 i |= I365_MEM_WS0; 647 break; 648 case 2: 649 i |= I365_MEM_WS1; 650 break; 651 default: 652 i |= I365_MEM_WS1 | I365_MEM_WS0; 653 break; 654 } 655 656 indirect_write16(sock,base+I365_W_STOP,i); 657 658 /* card start */ 659 660 i = ((mem->card_start - region.start) >> 12) & 0x3fff; 661 if (mem->flags & MAP_WRPROT) 662 i |= I365_MEM_WRPROT; 663 if (mem->flags & MAP_ATTRIB) { 664/* printk("requesting attribute memory for socket %i\n",sock);*/ 665 i |= I365_MEM_REG; 666 } else { 667/* printk("requesting normal memory for socket %i\n",sock);*/ 668 } 669 indirect_write16(sock,base+I365_W_OFF,i); 670 671 /* Enable the window if necessary */ 672 if (mem->flags & MAP_ACTIVE) 673 indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); 674 675 leave("i82092aa_set_mem_map"); 676 return 0; 677} 678 679static int i82092aa_module_init(void) 680{ 681 return pci_register_driver(&i82092aa_pci_driver); 682} 683 684static void i82092aa_module_exit(void) 685{ 686 enter("i82092aa_module_exit"); 687 pci_unregister_driver(&i82092aa_pci_driver); 688 if (sockets[0].io_base>0) 689 release_region(sockets[0].io_base, 2); 690 leave("i82092aa_module_exit"); 691} 692 693module_init(i82092aa_module_init); 694module_exit(i82092aa_module_exit); 695