1/* 2 * This file contains work-arounds for many known PCI hardware 3 * bugs. Devices present only on certain architectures (host 4 * bridges et cetera) should be handled in arch-specific code. 5 * 6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * 10 * Init/reset quirks for USB host controllers should be in the 11 * USB quirks file, where their drivers can access reuse it. 12 * 13 * The bridge optimization stuff has been removed. If you really 14 * have a silly BIOS which is unable to set your host bridge right, 15 * use the PowerTweak utility (see http://powertweak.sourceforge.net). 16 */ 17 18#include <linux/types.h> 19#include <linux/kernel.h> 20#include <linux/pci.h> 21#include <linux/init.h> 22#include <linux/delay.h> 23#include <linux/acpi.h> 24#include <linux/kallsyms.h> 25#include <linux/dmi.h> 26#include <linux/pci-aspm.h> 27#include <linux/ioport.h> 28#include <asm/dma.h> /* isa_dma_bridge_buggy */ 29#include "pci.h" 30 31/* 32 * This quirk function disables memory decoding and releases memory resources 33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 34 * It also rounds up size to specified alignment. 35 * Later on, the kernel will assign page-aligned memory resource back 36 * to the device. 37 */ 38static void __devinit quirk_resource_alignment(struct pci_dev *dev) 39{ 40 int i; 41 struct resource *r; 42 resource_size_t align, size; 43 u16 command; 44 45 if (!pci_is_reassigndev(dev)) 46 return; 47 48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 50 dev_warn(&dev->dev, 51 "Can't reassign resources to host bridge.\n"); 52 return; 53 } 54 55 dev_info(&dev->dev, 56 "Disabling memory decoding and releasing memory resources.\n"); 57 pci_read_config_word(dev, PCI_COMMAND, &command); 58 command &= ~PCI_COMMAND_MEMORY; 59 pci_write_config_word(dev, PCI_COMMAND, command); 60 61 align = pci_specified_resource_alignment(dev); 62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) { 63 r = &dev->resource[i]; 64 if (!(r->flags & IORESOURCE_MEM)) 65 continue; 66 size = resource_size(r); 67 if (size < align) { 68 size = align; 69 dev_info(&dev->dev, 70 "Rounding up size of resource #%d to %#llx.\n", 71 i, (unsigned long long)size); 72 } 73 r->end = size - 1; 74 r->start = 0; 75 } 76 /* Need to disable bridge's resource window, 77 * to enable the kernel to reassign new resource 78 * window later on. 79 */ 80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 83 r = &dev->resource[i]; 84 if (!(r->flags & IORESOURCE_MEM)) 85 continue; 86 r->end = resource_size(r) - 1; 87 r->start = 0; 88 } 89 pci_disable_bridge_window(dev); 90 } 91} 92DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment); 93 94/* 95 * Decoding should be disabled for a PCI device during BAR sizing to avoid 96 * conflict. But doing so may cause problems on host bridge and perhaps other 97 * key system devices. For devices that need to have mmio decoding always-on, 98 * we need to set the dev->mmio_always_on bit. 99 */ 100static void __devinit quirk_mmio_always_on(struct pci_dev *dev) 101{ 102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) 103 dev->mmio_always_on = 1; 104} 105DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on); 106 107/* The Mellanox Tavor device gives false positive parity errors 108 * Mark this device with a broken_parity_status, to allow 109 * PCI scanning code to "skip" this now blacklisted device. 110 */ 111static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) 112{ 113 dev->broken_parity_status = 1; /* This device gives false positives */ 114} 115DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 117 118/* Deal with broken BIOS'es that neglect to enable passive release, 119 which can cause problems in combination with the 82441FX/PPro MTRRs */ 120static void quirk_passive_release(struct pci_dev *dev) 121{ 122 struct pci_dev *d = NULL; 123 unsigned char dlc; 124 125 /* We have to make sure a particular bit is set in the PIIX3 126 ISA bridge, so we have to go out and find it. */ 127 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 128 pci_read_config_byte(d, 0x82, &dlc); 129 if (!(dlc & 1<<1)) { 130 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); 131 dlc |= 1<<1; 132 pci_write_config_byte(d, 0x82, dlc); 133 } 134 } 135} 136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 138 139 140static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) 141{ 142 if (!isa_dma_bridge_buggy) { 143 isa_dma_bridge_buggy=1; 144 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); 145 } 146} 147 /* 148 * Its not totally clear which chipsets are the problematic ones 149 * We know 82C586 and 82C596 variants are affected. 150 */ 151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 158 159/* 160 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 161 * for some HT machines to use C4 w/o hanging. 162 */ 163static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev) 164{ 165 u32 pmbase; 166 u16 pm1a; 167 168 pci_read_config_dword(dev, 0x40, &pmbase); 169 pmbase = pmbase & 0xff80; 170 pm1a = inw(pmbase); 171 172 if (pm1a & 0x10) { 173 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); 174 outw(0x10, pmbase); 175 } 176} 177DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 178 179/* 180 * Chipsets where PCI->PCI transfers vanish or hang 181 */ 182static void __devinit quirk_nopcipci(struct pci_dev *dev) 183{ 184 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 185 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 186 pci_pci_problems |= PCIPCI_FAIL; 187 } 188} 189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 191 192static void __devinit quirk_nopciamd(struct pci_dev *dev) 193{ 194 u8 rev; 195 pci_read_config_byte(dev, 0x08, &rev); 196 if (rev == 0x13) { 197 /* Erratum 24 */ 198 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 199 pci_pci_problems |= PCIAGP_FAIL; 200 } 201} 202DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 203 204/* 205 * Triton requires workarounds to be used by the drivers 206 */ 207static void __devinit quirk_triton(struct pci_dev *dev) 208{ 209 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 210 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 211 pci_pci_problems |= PCIPCI_TRITON; 212 } 213} 214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 218 219/* 220 * VIA Apollo KT133 needs PCI latency patch 221 * Made according to a windows driver based patch by George E. Breese 222 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 223 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 224 * the info on which Mr Breese based his work. 225 * 226 * Updated based on further information from the site and also on 227 * information provided by VIA 228 */ 229static void quirk_vialatency(struct pci_dev *dev) 230{ 231 struct pci_dev *p; 232 u8 busarb; 233 /* Ok we have a potential problem chipset here. Now see if we have 234 a buggy southbridge */ 235 236 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 237 if (p!=NULL) { 238 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 239 /* Check for buggy part revisions */ 240 if (p->revision < 0x40 || p->revision > 0x42) 241 goto exit; 242 } else { 243 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 244 if (p==NULL) /* No problem parts */ 245 goto exit; 246 /* Check for buggy part revisions */ 247 if (p->revision < 0x10 || p->revision > 0x12) 248 goto exit; 249 } 250 251 /* 252 * Ok we have the problem. Now set the PCI master grant to 253 * occur every master grant. The apparent bug is that under high 254 * PCI load (quite common in Linux of course) you can get data 255 * loss when the CPU is held off the bus for 3 bus master requests 256 * This happens to include the IDE controllers.... 257 * 258 * VIA only apply this fix when an SB Live! is present but under 259 * both Linux and Windows this isnt enough, and we have seen 260 * corruption without SB Live! but with things like 3 UDMA IDE 261 * controllers. So we ignore that bit of the VIA recommendation.. 262 */ 263 264 pci_read_config_byte(dev, 0x76, &busarb); 265 /* Set bit 4 and bi 5 of byte 76 to 0x01 266 "Master priority rotation on every PCI master grant */ 267 busarb &= ~(1<<5); 268 busarb |= (1<<4); 269 pci_write_config_byte(dev, 0x76, busarb); 270 dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); 271exit: 272 pci_dev_put(p); 273} 274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 277/* Must restore this on a resume from RAM */ 278DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 279DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 280DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 281 282/* 283 * VIA Apollo VP3 needs ETBF on BT848/878 284 */ 285static void __devinit quirk_viaetbf(struct pci_dev *dev) 286{ 287 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 288 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 289 pci_pci_problems |= PCIPCI_VIAETBF; 290 } 291} 292DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 293 294static void __devinit quirk_vsfx(struct pci_dev *dev) 295{ 296 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 297 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 298 pci_pci_problems |= PCIPCI_VSFX; 299 } 300} 301DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 302 303static void __init quirk_alimagik(struct pci_dev *dev) 304{ 305 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 306 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 307 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 308 } 309} 310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 312 313/* 314 * Natoma has some interesting boundary conditions with Zoran stuff 315 * at least 316 */ 317static void __devinit quirk_natoma(struct pci_dev *dev) 318{ 319 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 320 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 321 pci_pci_problems |= PCIPCI_NATOMA; 322 } 323} 324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 328DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 329DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 330 331/* 332 * This chip can cause PCI parity errors if config register 0xA0 is read 333 * while DMAs are occurring. 334 */ 335static void __devinit quirk_citrine(struct pci_dev *dev) 336{ 337 dev->cfg_size = 0xA0; 338} 339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 340 341/* 342 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 343 * If it's needed, re-allocate the region. 344 */ 345static void __devinit quirk_s3_64M(struct pci_dev *dev) 346{ 347 struct resource *r = &dev->resource[0]; 348 349 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { 350 r->start = 0; 351 r->end = 0x3ffffff; 352 } 353} 354DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 355DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 356 357/* 358 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 359 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 360 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 361 * (which conflicts w/ BAR1's memory range). 362 */ 363static void __devinit quirk_cs5536_vsa(struct pci_dev *dev) 364{ 365 if (pci_resource_len(dev, 0) != 8) { 366 struct resource *res = &dev->resource[0]; 367 res->end = res->start + 8 - 1; 368 dev_info(&dev->dev, "CS5536 ISA bridge bug detected " 369 "(incorrect header); workaround applied.\n"); 370 } 371} 372DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 373 374static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 375 unsigned size, int nr, const char *name) 376{ 377 region &= ~(size-1); 378 if (region) { 379 struct pci_bus_region bus_region; 380 struct resource *res = dev->resource + nr; 381 382 res->name = pci_name(dev); 383 res->start = region; 384 res->end = region + size - 1; 385 res->flags = IORESOURCE_IO; 386 387 /* Convert from PCI bus to resource space. */ 388 bus_region.start = res->start; 389 bus_region.end = res->end; 390 pcibios_bus_to_resource(dev, res, &bus_region); 391 392 if (pci_claim_resource(dev, nr) == 0) 393 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", 394 res, name); 395 } 396} 397 398/* 399 * ATI Northbridge setups MCE the processor if you even 400 * read somewhere between 0x3b0->0x3bb or read 0x3d3 401 */ 402static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 403{ 404 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 405 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 406 request_region(0x3b0, 0x0C, "RadeonIGP"); 407 request_region(0x3d3, 0x01, "RadeonIGP"); 408} 409DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 410 411/* 412 * Let's make the southbridge information explicit instead 413 * of having to worry about people probing the ACPI areas, 414 * for example.. (Yes, it happens, and if you read the wrong 415 * ACPI register it will put the machine to sleep with no 416 * way of waking it up again. Bummer). 417 * 418 * ALI M7101: Two IO regions pointed to by words at 419 * 0xE0 (64 bytes of ACPI registers) 420 * 0xE2 (32 bytes of SMB registers) 421 */ 422static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) 423{ 424 u16 region; 425 426 pci_read_config_word(dev, 0xE0, ®ion); 427 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 428 pci_read_config_word(dev, 0xE2, ®ion); 429 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 430} 431DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 432 433static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 434{ 435 u32 devres; 436 u32 mask, size, base; 437 438 pci_read_config_dword(dev, port, &devres); 439 if ((devres & enable) != enable) 440 return; 441 mask = (devres >> 16) & 15; 442 base = devres & 0xffff; 443 size = 16; 444 for (;;) { 445 unsigned bit = size >> 1; 446 if ((bit & mask) == bit) 447 break; 448 size = bit; 449 } 450 /* 451 * For now we only print it out. Eventually we'll want to 452 * reserve it (at least if it's in the 0x1000+ range), but 453 * let's get enough confirmation reports first. 454 */ 455 base &= -size; 456 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 457} 458 459static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 460{ 461 u32 devres; 462 u32 mask, size, base; 463 464 pci_read_config_dword(dev, port, &devres); 465 if ((devres & enable) != enable) 466 return; 467 base = devres & 0xffff0000; 468 mask = (devres & 0x3f) << 16; 469 size = 128 << 16; 470 for (;;) { 471 unsigned bit = size >> 1; 472 if ((bit & mask) == bit) 473 break; 474 size = bit; 475 } 476 /* 477 * For now we only print it out. Eventually we'll want to 478 * reserve it, but let's get enough confirmation reports first. 479 */ 480 base &= -size; 481 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 482} 483 484/* 485 * PIIX4 ACPI: Two IO regions pointed to by longwords at 486 * 0x40 (64 bytes of ACPI registers) 487 * 0x90 (16 bytes of SMB registers) 488 * and a few strange programmable PIIX4 device resources. 489 */ 490static void __devinit quirk_piix4_acpi(struct pci_dev *dev) 491{ 492 u32 region, res_a; 493 494 pci_read_config_dword(dev, 0x40, ®ion); 495 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 496 pci_read_config_dword(dev, 0x90, ®ion); 497 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 498 499 /* Device resource A has enables for some of the other ones */ 500 pci_read_config_dword(dev, 0x5c, &res_a); 501 502 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 503 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 504 505 /* Device resource D is just bitfields for static resources */ 506 507 /* Device 12 enabled? */ 508 if (res_a & (1 << 29)) { 509 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 510 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 511 } 512 /* Device 13 enabled? */ 513 if (res_a & (1 << 30)) { 514 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 515 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 516 } 517 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 518 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 519} 520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 522 523/* 524 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 525 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 526 * 0x58 (64 bytes of GPIO I/O space) 527 */ 528static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) 529{ 530 u32 region; 531 532 pci_read_config_dword(dev, 0x40, ®ion); 533 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); 534 535 pci_read_config_dword(dev, 0x58, ®ion); 536 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 537} 538DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 539DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 540DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 541DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 542DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 543DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 544DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 545DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 546DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 547DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 548 549static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) 550{ 551 u32 region; 552 553 pci_read_config_dword(dev, 0x40, ®ion); 554 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); 555 556 pci_read_config_dword(dev, 0x48, ®ion); 557 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 558} 559 560static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 561{ 562 u32 val; 563 u32 size, base; 564 565 pci_read_config_dword(dev, reg, &val); 566 567 /* Enabled? */ 568 if (!(val & 1)) 569 return; 570 base = val & 0xfffc; 571 if (dynsize) { 572 /* 573 * This is not correct. It is 16, 32 or 64 bytes depending on 574 * register D31:F0:ADh bits 5:4. 575 * 576 * But this gets us at least _part_ of it. 577 */ 578 size = 16; 579 } else { 580 size = 128; 581 } 582 base &= ~(size-1); 583 584 /* Just print it out for now. We should reserve it after more debugging */ 585 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 586} 587 588static void __devinit quirk_ich6_lpc(struct pci_dev *dev) 589{ 590 /* Shared ACPI/GPIO decode with all ICH6+ */ 591 ich6_lpc_acpi_gpio(dev); 592 593 /* ICH6-specific generic IO decode */ 594 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 595 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 596} 597DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 599 600static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 601{ 602 u32 val; 603 u32 mask, base; 604 605 pci_read_config_dword(dev, reg, &val); 606 607 /* Enabled? */ 608 if (!(val & 1)) 609 return; 610 611 /* 612 * IO base in bits 15:2, mask in bits 23:18, both 613 * are dword-based 614 */ 615 base = val & 0xfffc; 616 mask = (val >> 16) & 0xfc; 617 mask |= 3; 618 619 /* Just print it out for now. We should reserve it after more debugging */ 620 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 621} 622 623/* ICH7-10 has the same common LPC generic IO decode registers */ 624static void __devinit quirk_ich7_lpc(struct pci_dev *dev) 625{ 626 /* We share the common ACPI/DPIO decode with ICH6 */ 627 ich6_lpc_acpi_gpio(dev); 628 629 /* And have 4 ICH7+ generic decodes */ 630 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 631 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 632 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 633 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 634} 635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 640DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 647DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 648 649/* 650 * VIA ACPI: One IO region pointed to by longword at 651 * 0x48 or 0x20 (256 bytes of ACPI registers) 652 */ 653static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) 654{ 655 u32 region; 656 657 if (dev->revision & 0x10) { 658 pci_read_config_dword(dev, 0x48, ®ion); 659 region &= PCI_BASE_ADDRESS_IO_MASK; 660 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 661 } 662} 663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 664 665/* 666 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 667 * 0x48 (256 bytes of ACPI registers) 668 * 0x70 (128 bytes of hardware monitoring register) 669 * 0x90 (16 bytes of SMB registers) 670 */ 671static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) 672{ 673 u16 hm; 674 u32 smb; 675 676 quirk_vt82c586_acpi(dev); 677 678 pci_read_config_word(dev, 0x70, &hm); 679 hm &= PCI_BASE_ADDRESS_IO_MASK; 680 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); 681 682 pci_read_config_dword(dev, 0x90, &smb); 683 smb &= PCI_BASE_ADDRESS_IO_MASK; 684 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 685} 686DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 687 688/* 689 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 690 * 0x88 (128 bytes of power management registers) 691 * 0xd0 (16 bytes of SMB registers) 692 */ 693static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) 694{ 695 u16 pm, smb; 696 697 pci_read_config_word(dev, 0x88, &pm); 698 pm &= PCI_BASE_ADDRESS_IO_MASK; 699 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 700 701 pci_read_config_word(dev, 0xd0, &smb); 702 smb &= PCI_BASE_ADDRESS_IO_MASK; 703 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); 704} 705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 706 707/* 708 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 709 * Disable fast back-to-back on the secondary bus segment 710 */ 711static void __devinit quirk_xio2000a(struct pci_dev *dev) 712{ 713 struct pci_dev *pdev; 714 u16 command; 715 716 dev_warn(&dev->dev, "TI XIO2000a quirk detected; " 717 "secondary bus fast back-to-back transfers disabled\n"); 718 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 719 pci_read_config_word(pdev, PCI_COMMAND, &command); 720 if (command & PCI_COMMAND_FAST_BACK) 721 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 722 } 723} 724DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 725 quirk_xio2000a); 726 727#ifdef CONFIG_X86_IO_APIC 728 729#include <asm/io_apic.h> 730 731/* 732 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 733 * devices to the external APIC. 734 * 735 * TODO: When we have device-specific interrupt routers, 736 * this code will go away from quirks. 737 */ 738static void quirk_via_ioapic(struct pci_dev *dev) 739{ 740 u8 tmp; 741 742 if (nr_ioapics < 1) 743 tmp = 0; /* nothing routed to external APIC */ 744 else 745 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 746 747 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 748 tmp == 0 ? "Disa" : "Ena"); 749 750 /* Offset 0x58: External APIC IRQ output control */ 751 pci_write_config_byte (dev, 0x58, tmp); 752} 753DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 754DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 755 756/* 757 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 758 * This leads to doubled level interrupt rates. 759 * Set this bit to get rid of cycle wastage. 760 * Otherwise uncritical. 761 */ 762static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 763{ 764 u8 misc_control2; 765#define BYPASS_APIC_DEASSERT 8 766 767 pci_read_config_byte(dev, 0x5B, &misc_control2); 768 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 769 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 770 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 771 } 772} 773DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 774DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 775 776/* 777 * The AMD io apic can hang the box when an apic irq is masked. 778 * We check all revs >= B0 (yet not in the pre production!) as the bug 779 * is currently marked NoFix 780 * 781 * We have multiple reports of hangs with this chipset that went away with 782 * noapic specified. For the moment we assume it's the erratum. We may be wrong 783 * of course. However the advice is demonstrably good even if so.. 784 */ 785static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 786{ 787 if (dev->revision >= 0x02) { 788 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 789 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); 790 } 791} 792DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 793 794static void __init quirk_ioapic_rmw(struct pci_dev *dev) 795{ 796 if (dev->devfn == 0 && dev->bus->number == 0) 797 sis_apic_bug = 1; 798} 799DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); 800#endif /* CONFIG_X86_IO_APIC */ 801 802/* 803 * Some settings of MMRBC can lead to data corruption so block changes. 804 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 805 */ 806static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 807{ 808 if (dev->subordinate && dev->revision <= 0x12) { 809 dev_info(&dev->dev, "AMD8131 rev %x detected; " 810 "disabling PCI-X MMRBC\n", dev->revision); 811 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 812 } 813} 814DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 815 816static void __devinit quirk_via_acpi(struct pci_dev *d) 817{ 818 /* 819 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 820 */ 821 u8 irq; 822 pci_read_config_byte(d, 0x42, &irq); 823 irq &= 0xf; 824 if (irq && (irq != 2)) 825 d->irq = irq; 826} 827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 829 830 831/* 832 * VIA bridges which have VLink 833 */ 834 835static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 836 837static void quirk_via_bridge(struct pci_dev *dev) 838{ 839 /* See what bridge we have and find the device ranges */ 840 switch (dev->device) { 841 case PCI_DEVICE_ID_VIA_82C686: 842 /* The VT82C686 is special, it attaches to PCI and can have 843 any device number. All its subdevices are functions of 844 that single device. */ 845 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 846 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 847 break; 848 case PCI_DEVICE_ID_VIA_8237: 849 case PCI_DEVICE_ID_VIA_8237A: 850 via_vlink_dev_lo = 15; 851 break; 852 case PCI_DEVICE_ID_VIA_8235: 853 via_vlink_dev_lo = 16; 854 break; 855 case PCI_DEVICE_ID_VIA_8231: 856 case PCI_DEVICE_ID_VIA_8233_0: 857 case PCI_DEVICE_ID_VIA_8233A: 858 case PCI_DEVICE_ID_VIA_8233C_0: 859 via_vlink_dev_lo = 17; 860 break; 861 } 862} 863DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 866DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 868DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 871 872/** 873 * quirk_via_vlink - VIA VLink IRQ number update 874 * @dev: PCI device 875 * 876 * If the device we are dealing with is on a PIC IRQ we need to 877 * ensure that the IRQ line register which usually is not relevant 878 * for PCI cards, is actually written so that interrupts get sent 879 * to the right place. 880 * We only do this on systems where a VIA south bridge was detected, 881 * and only for VIA devices on the motherboard (see quirk_via_bridge 882 * above). 883 */ 884 885static void quirk_via_vlink(struct pci_dev *dev) 886{ 887 u8 irq, new_irq; 888 889 /* Check if we have VLink at all */ 890 if (via_vlink_dev_lo == -1) 891 return; 892 893 new_irq = dev->irq; 894 895 /* Don't quirk interrupts outside the legacy IRQ range */ 896 if (!new_irq || new_irq > 15) 897 return; 898 899 /* Internal device ? */ 900 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 901 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 902 return; 903 904 /* This is an internal VLink device on a PIC interrupt. The BIOS 905 ought to have set this but may not have, so we redo it */ 906 907 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 908 if (new_irq != irq) { 909 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", 910 irq, new_irq); 911 udelay(15); /* unknown if delay really needed */ 912 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 913 } 914} 915DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 916 917/* 918 * VIA VT82C598 has its device ID settable and many BIOSes 919 * set it to the ID of VT82C597 for backward compatibility. 920 * We need to switch it off to be able to recognize the real 921 * type of the chip. 922 */ 923static void __devinit quirk_vt82c598_id(struct pci_dev *dev) 924{ 925 pci_write_config_byte(dev, 0xfc, 0); 926 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 927} 928DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 929 930/* 931 * CardBus controllers have a legacy base address that enables them 932 * to respond as i82365 pcmcia controllers. We don't want them to 933 * do this even if the Linux CardBus driver is not loaded, because 934 * the Linux i82365 driver does not (and should not) handle CardBus. 935 */ 936static void quirk_cardbus_legacy(struct pci_dev *dev) 937{ 938 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) 939 return; 940 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 941} 942DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 943DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); 944 945/* 946 * Following the PCI ordering rules is optional on the AMD762. I'm not 947 * sure what the designers were smoking but let's not inhale... 948 * 949 * To be fair to AMD, it follows the spec by default, its BIOS people 950 * who turn it off! 951 */ 952static void quirk_amd_ordering(struct pci_dev *dev) 953{ 954 u32 pcic; 955 pci_read_config_dword(dev, 0x4C, &pcic); 956 if ((pcic&6)!=6) { 957 pcic |= 6; 958 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 959 pci_write_config_dword(dev, 0x4C, pcic); 960 pci_read_config_dword(dev, 0x84, &pcic); 961 pcic |= (1<<23); /* Required in this mode */ 962 pci_write_config_dword(dev, 0x84, pcic); 963 } 964} 965DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 966DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 967 968static void __devinit quirk_dunord ( struct pci_dev * dev ) 969{ 970 struct resource *r = &dev->resource [1]; 971 r->start = 0; 972 r->end = 0xffffff; 973} 974DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 975 976/* 977 * i82380FB mobile docking controller: its PCI-to-PCI bridge 978 * is subtractive decoding (transparent), and does indicate this 979 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 980 * instead of 0x01. 981 */ 982static void __devinit quirk_transparent_bridge(struct pci_dev *dev) 983{ 984 dev->transparent = 1; 985} 986DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 988 989/* 990 * Common misconfiguration of the MediaGX/Geode PCI master that will 991 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 992 * datasheets found at http://www.national.com/ds/GX for info on what 993 * these bits do. <christer@weinigel.se> 994 */ 995static void quirk_mediagx_master(struct pci_dev *dev) 996{ 997 u8 reg; 998 pci_read_config_byte(dev, 0x41, ®); 999 if (reg & 2) { 1000 reg &= ~2; 1001 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 1002 pci_write_config_byte(dev, 0x41, reg); 1003 } 1004} 1005DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1006DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1007 1008/* 1009 * Ensure C0 rev restreaming is off. This is normally done by 1010 * the BIOS but in the odd case it is not the results are corruption 1011 * hence the presence of a Linux check 1012 */ 1013static void quirk_disable_pxb(struct pci_dev *pdev) 1014{ 1015 u16 config; 1016 1017 if (pdev->revision != 0x04) /* Only C0 requires this */ 1018 return; 1019 pci_read_config_word(pdev, 0x40, &config); 1020 if (config & (1<<6)) { 1021 config &= ~(1<<6); 1022 pci_write_config_word(pdev, 0x40, config); 1023 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1024 } 1025} 1026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1027DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1028 1029static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) 1030{ 1031 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1032 u8 tmp; 1033 1034 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1035 if (tmp == 0x01) { 1036 pci_read_config_byte(pdev, 0x40, &tmp); 1037 pci_write_config_byte(pdev, 0x40, tmp|1); 1038 pci_write_config_byte(pdev, 0x9, 1); 1039 pci_write_config_byte(pdev, 0xa, 6); 1040 pci_write_config_byte(pdev, 0x40, tmp); 1041 1042 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1043 dev_info(&pdev->dev, "set SATA to AHCI mode\n"); 1044 } 1045} 1046DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1047DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1048DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1049DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1051DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1052 1053/* 1054 * Serverworks CSB5 IDE does not fully support native mode 1055 */ 1056static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) 1057{ 1058 u8 prog; 1059 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1060 if (prog & 5) { 1061 prog &= ~5; 1062 pdev->class &= ~5; 1063 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1064 /* PCI layer will sort out resources */ 1065 } 1066} 1067DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1068 1069/* 1070 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1071 */ 1072static void __init quirk_ide_samemode(struct pci_dev *pdev) 1073{ 1074 u8 prog; 1075 1076 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1077 1078 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1079 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); 1080 prog &= ~5; 1081 pdev->class &= ~5; 1082 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1083 } 1084} 1085DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1086 1087/* 1088 * Some ATA devices break if put into D3 1089 */ 1090 1091static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) 1092{ 1093 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1094 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) 1095 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1096} 1097DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); 1098DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); 1099/* ALi loses some register settings that we cannot then restore */ 1100DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3); 1101/* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1102 occur when mode detecting */ 1103DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3); 1104 1105/* This was originally an Alpha specific thing, but it really fits here. 1106 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1107 */ 1108static void __init quirk_eisa_bridge(struct pci_dev *dev) 1109{ 1110 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1111} 1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1113 1114 1115/* 1116 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1117 * is not activated. The myth is that Asus said that they do not want the 1118 * users to be irritated by just another PCI Device in the Win98 device 1119 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1120 * package 2.7.0 for details) 1121 * 1122 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1123 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1124 * becomes necessary to do this tweak in two steps -- the chosen trigger 1125 * is either the Host bridge (preferred) or on-board VGA controller. 1126 * 1127 * Note that we used to unhide the SMBus that way on Toshiba laptops 1128 * (Satellite A40 and Tecra M2) but then found that the thermal management 1129 * was done by SMM code, which could cause unsynchronized concurrent 1130 * accesses to the SMBus registers, with potentially bad effects. Thus you 1131 * should be very careful when adding new entries: if SMM is accessing the 1132 * Intel SMBus, this is a very good reason to leave it hidden. 1133 * 1134 * Likewise, many recent laptops use ACPI for thermal management. If the 1135 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1136 * natively, and keeping the SMBus hidden is the right thing to do. If you 1137 * are about to add an entry in the table below, please first disassemble 1138 * the DSDT and double-check that there is no code accessing the SMBus. 1139 */ 1140static int asus_hides_smbus; 1141 1142static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 1143{ 1144 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1145 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1146 switch(dev->subsystem_device) { 1147 case 0x8025: /* P4B-LX */ 1148 case 0x8070: /* P4B */ 1149 case 0x8088: /* P4B533 */ 1150 case 0x1626: /* L3C notebook */ 1151 asus_hides_smbus = 1; 1152 } 1153 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1154 switch(dev->subsystem_device) { 1155 case 0x80b1: /* P4GE-V */ 1156 case 0x80b2: /* P4PE */ 1157 case 0x8093: /* P4B533-V */ 1158 asus_hides_smbus = 1; 1159 } 1160 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1161 switch(dev->subsystem_device) { 1162 case 0x8030: /* P4T533 */ 1163 asus_hides_smbus = 1; 1164 } 1165 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1166 switch (dev->subsystem_device) { 1167 case 0x8070: /* P4G8X Deluxe */ 1168 asus_hides_smbus = 1; 1169 } 1170 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1171 switch (dev->subsystem_device) { 1172 case 0x80c9: /* PU-DLS */ 1173 asus_hides_smbus = 1; 1174 } 1175 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1176 switch (dev->subsystem_device) { 1177 case 0x1751: /* M2N notebook */ 1178 case 0x1821: /* M5N notebook */ 1179 case 0x1897: /* A6L notebook */ 1180 asus_hides_smbus = 1; 1181 } 1182 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1183 switch (dev->subsystem_device) { 1184 case 0x184b: /* W1N notebook */ 1185 case 0x186a: /* M6Ne notebook */ 1186 asus_hides_smbus = 1; 1187 } 1188 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1189 switch (dev->subsystem_device) { 1190 case 0x80f2: /* P4P800-X */ 1191 asus_hides_smbus = 1; 1192 } 1193 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1194 switch (dev->subsystem_device) { 1195 case 0x1882: /* M6V notebook */ 1196 case 0x1977: /* A6VA notebook */ 1197 asus_hides_smbus = 1; 1198 } 1199 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1200 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1201 switch(dev->subsystem_device) { 1202 case 0x088C: /* HP Compaq nc8000 */ 1203 case 0x0890: /* HP Compaq nc6000 */ 1204 asus_hides_smbus = 1; 1205 } 1206 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1207 switch (dev->subsystem_device) { 1208 case 0x12bc: /* HP D330L */ 1209 case 0x12bd: /* HP D530 */ 1210 case 0x006a: /* HP Compaq nx9500 */ 1211 asus_hides_smbus = 1; 1212 } 1213 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1214 switch (dev->subsystem_device) { 1215 case 0x12bf: /* HP xw4100 */ 1216 asus_hides_smbus = 1; 1217 } 1218 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1219 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1220 switch(dev->subsystem_device) { 1221 case 0xC00C: /* Samsung P35 notebook */ 1222 asus_hides_smbus = 1; 1223 } 1224 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1225 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1226 switch(dev->subsystem_device) { 1227 case 0x0058: /* Compaq Evo N620c */ 1228 asus_hides_smbus = 1; 1229 } 1230 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1231 switch(dev->subsystem_device) { 1232 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1233 /* Motherboard doesn't have Host bridge 1234 * subvendor/subdevice IDs, therefore checking 1235 * its on-board VGA controller */ 1236 asus_hides_smbus = 1; 1237 } 1238 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1239 switch(dev->subsystem_device) { 1240 case 0x00b8: /* Compaq Evo D510 CMT */ 1241 case 0x00b9: /* Compaq Evo D510 SFF */ 1242 case 0x00ba: /* Compaq Evo D510 USDT */ 1243 /* Motherboard doesn't have Host bridge 1244 * subvendor/subdevice IDs and on-board VGA 1245 * controller is disabled if an AGP card is 1246 * inserted, therefore checking USB UHCI 1247 * Controller #1 */ 1248 asus_hides_smbus = 1; 1249 } 1250 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1251 switch (dev->subsystem_device) { 1252 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1253 /* Motherboard doesn't have host bridge 1254 * subvendor/subdevice IDs, therefore checking 1255 * its on-board VGA controller */ 1256 asus_hides_smbus = 1; 1257 } 1258 } 1259} 1260DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1261DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1262DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1263DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1264DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1265DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1266DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1270 1271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1274 1275static void asus_hides_smbus_lpc(struct pci_dev *dev) 1276{ 1277 u16 val; 1278 1279 if (likely(!asus_hides_smbus)) 1280 return; 1281 1282 pci_read_config_word(dev, 0xF2, &val); 1283 if (val & 0x8) { 1284 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1285 pci_read_config_word(dev, 0xF2, &val); 1286 if (val & 0x8) 1287 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1288 else 1289 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1290 } 1291} 1292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1293DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1296DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1299DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1300DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1301DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1302DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1303DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1304DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1305DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1306 1307/* It appears we just have one such device. If not, we have a warning */ 1308static void __iomem *asus_rcba_base; 1309static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1310{ 1311 u32 rcba; 1312 1313 if (likely(!asus_hides_smbus)) 1314 return; 1315 WARN_ON(asus_rcba_base); 1316 1317 pci_read_config_dword(dev, 0xF0, &rcba); 1318 /* use bits 31:14, 16 kB aligned */ 1319 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); 1320 if (asus_rcba_base == NULL) 1321 return; 1322} 1323 1324static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1325{ 1326 u32 val; 1327 1328 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1329 return; 1330 /* read the Function Disable register, dword mode only */ 1331 val = readl(asus_rcba_base + 0x3418); 1332 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1333} 1334 1335static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1336{ 1337 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1338 return; 1339 iounmap(asus_rcba_base); 1340 asus_rcba_base = NULL; 1341 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); 1342} 1343 1344static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1345{ 1346 asus_hides_smbus_lpc_ich6_suspend(dev); 1347 asus_hides_smbus_lpc_ich6_resume_early(dev); 1348 asus_hides_smbus_lpc_ich6_resume(dev); 1349} 1350DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1351DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1352DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1353DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1354 1355/* 1356 * SiS 96x south bridge: BIOS typically hides SMBus device... 1357 */ 1358static void quirk_sis_96x_smbus(struct pci_dev *dev) 1359{ 1360 u8 val = 0; 1361 pci_read_config_byte(dev, 0x77, &val); 1362 if (val & 0x10) { 1363 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); 1364 pci_write_config_byte(dev, 0x77, val & ~0x10); 1365 } 1366} 1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1371DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1372DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1373DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1374DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1375 1376/* 1377 * ... This is further complicated by the fact that some SiS96x south 1378 * bridges pretend to be 85C503/5513 instead. In that case see if we 1379 * spotted a compatible north bridge to make sure. 1380 * (pci_find_device doesn't work yet) 1381 * 1382 * We can also enable the sis96x bit in the discovery register.. 1383 */ 1384#define SIS_DETECT_REGISTER 0x40 1385 1386static void quirk_sis_503(struct pci_dev *dev) 1387{ 1388 u8 reg; 1389 u16 devid; 1390 1391 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1392 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1393 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1394 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1395 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1396 return; 1397 } 1398 1399 /* 1400 * Ok, it now shows up as a 96x.. run the 96x quirk by 1401 * hand in case it has already been processed. 1402 * (depends on link order, which is apparently not guaranteed) 1403 */ 1404 dev->device = devid; 1405 quirk_sis_96x_smbus(dev); 1406} 1407DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1408DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1409 1410 1411/* 1412 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1413 * and MC97 modem controller are disabled when a second PCI soundcard is 1414 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1415 * -- bjd 1416 */ 1417static void asus_hides_ac97_lpc(struct pci_dev *dev) 1418{ 1419 u8 val; 1420 int asus_hides_ac97 = 0; 1421 1422 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1423 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1424 asus_hides_ac97 = 1; 1425 } 1426 1427 if (!asus_hides_ac97) 1428 return; 1429 1430 pci_read_config_byte(dev, 0x50, &val); 1431 if (val & 0xc0) { 1432 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1433 pci_read_config_byte(dev, 0x50, &val); 1434 if (val & 0xc0) 1435 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1436 else 1437 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1438 } 1439} 1440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1441DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1442 1443#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1444 1445/* 1446 * If we are using libata we can drive this chip properly but must 1447 * do this early on to make the additional device appear during 1448 * the PCI scanning. 1449 */ 1450static void quirk_jmicron_ata(struct pci_dev *pdev) 1451{ 1452 u32 conf1, conf5, class; 1453 u8 hdr; 1454 1455 /* Only poke fn 0 */ 1456 if (PCI_FUNC(pdev->devfn)) 1457 return; 1458 1459 pci_read_config_dword(pdev, 0x40, &conf1); 1460 pci_read_config_dword(pdev, 0x80, &conf5); 1461 1462 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1463 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1464 1465 switch (pdev->device) { 1466 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1467 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1468 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1469 /* The controller should be in single function ahci mode */ 1470 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1471 break; 1472 1473 case PCI_DEVICE_ID_JMICRON_JMB365: 1474 case PCI_DEVICE_ID_JMICRON_JMB366: 1475 /* Redirect IDE second PATA port to the right spot */ 1476 conf5 |= (1 << 24); 1477 /* Fall through */ 1478 case PCI_DEVICE_ID_JMICRON_JMB361: 1479 case PCI_DEVICE_ID_JMICRON_JMB363: 1480 case PCI_DEVICE_ID_JMICRON_JMB369: 1481 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1482 /* Set the class codes correctly and then direct IDE 0 */ 1483 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1484 break; 1485 1486 case PCI_DEVICE_ID_JMICRON_JMB368: 1487 /* The controller should be in single function IDE mode */ 1488 conf1 |= 0x00C00000; /* Set 22, 23 */ 1489 break; 1490 } 1491 1492 pci_write_config_dword(pdev, 0x40, conf1); 1493 pci_write_config_dword(pdev, 0x80, conf5); 1494 1495 /* Update pdev accordingly */ 1496 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1497 pdev->hdr_type = hdr & 0x7f; 1498 pdev->multifunction = !!(hdr & 0x80); 1499 1500 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1501 pdev->class = class >> 8; 1502} 1503DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1504DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1505DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1506DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1507DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1508DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1509DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1510DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1511DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1512DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1513DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1514DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1515DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1516DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1517DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1518DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1519DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1520DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1521 1522#endif 1523 1524#ifdef CONFIG_X86_IO_APIC 1525static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1526{ 1527 int i; 1528 1529 if ((pdev->class >> 8) != 0xff00) 1530 return; 1531 1532 /* the first BAR is the location of the IO APIC...we must 1533 * not touch this (and it's already covered by the fixmap), so 1534 * forcibly insert it into the resource tree */ 1535 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1536 insert_resource(&iomem_resource, &pdev->resource[0]); 1537 1538 /* The next five BARs all seem to be rubbish, so just clean 1539 * them out */ 1540 for (i=1; i < 6; i++) { 1541 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1542 } 1543 1544} 1545DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1546#endif 1547 1548static void __devinit quirk_pcie_mch(struct pci_dev *pdev) 1549{ 1550 pci_msi_off(pdev); 1551 pdev->no_msi = 1; 1552} 1553DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1554DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1555DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1556 1557 1558/* 1559 * It's possible for the MSI to get corrupted if shpc and acpi 1560 * are used together on certain PXH-based systems. 1561 */ 1562static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1563{ 1564 pci_msi_off(dev); 1565 dev->no_msi = 1; 1566 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); 1567} 1568DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1569DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1570DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 1571DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 1572DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1573 1574/* 1575 * Some Intel PCI Express chipsets have trouble with downstream 1576 * device power management. 1577 */ 1578static void quirk_intel_pcie_pm(struct pci_dev * dev) 1579{ 1580 pci_pm_d3_delay = 120; 1581 dev->no_d1d2 = 1; 1582} 1583 1584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1585DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1587DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 1588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 1589DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 1590DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 1591DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 1592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 1593DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 1594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 1595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 1596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 1597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 1598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 1599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1605 1606#ifdef CONFIG_X86_IO_APIC 1607/* 1608 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1609 * remap the original interrupt in the linux kernel to the boot interrupt, so 1610 * that a PCI device's interrupt handler is installed on the boot interrupt 1611 * line instead. 1612 */ 1613static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 1614{ 1615 if (noioapicquirk || noioapicreroute) 1616 return; 1617 1618 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 1619 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", 1620 dev->vendor, dev->device); 1621} 1622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1630DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 1631DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 1632DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 1633DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 1634DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 1635DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 1636DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 1637DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 1638 1639/* 1640 * On some chipsets we can disable the generation of legacy INTx boot 1641 * interrupts. 1642 */ 1643 1644/* 1645 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1646 * 300641-004US, section 5.7.3. 1647 */ 1648#define INTEL_6300_IOAPIC_ABAR 0x40 1649#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 1650 1651static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 1652{ 1653 u16 pci_config_word; 1654 1655 if (noioapicquirk) 1656 return; 1657 1658 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); 1659 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 1660 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); 1661 1662 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1663 dev->vendor, dev->device); 1664} 1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1666DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1667 1668/* 1669 * disable boot interrupts on HT-1000 1670 */ 1671#define BC_HT1000_FEATURE_REG 0x64 1672#define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1673#define BC_HT1000_MAP_IDX 0xC00 1674#define BC_HT1000_MAP_DATA 0xC01 1675 1676static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 1677{ 1678 u32 pci_config_dword; 1679 u8 irq; 1680 1681 if (noioapicquirk) 1682 return; 1683 1684 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 1685 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 1686 BC_HT1000_PIC_REGS_ENABLE); 1687 1688 for (irq = 0x10; irq < 0x10 + 32; irq++) { 1689 outb(irq, BC_HT1000_MAP_IDX); 1690 outb(0x00, BC_HT1000_MAP_DATA); 1691 } 1692 1693 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 1694 1695 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1696 dev->vendor, dev->device); 1697} 1698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1699DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1700 1701/* 1702 * disable boot interrupts on AMD and ATI chipsets 1703 */ 1704/* 1705 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1706 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1707 * (due to an erratum). 1708 */ 1709#define AMD_813X_MISC 0x40 1710#define AMD_813X_NOIOAMODE (1<<0) 1711#define AMD_813X_REV_B1 0x12 1712#define AMD_813X_REV_B2 0x13 1713 1714static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 1715{ 1716 u32 pci_config_dword; 1717 1718 if (noioapicquirk) 1719 return; 1720 if ((dev->revision == AMD_813X_REV_B1) || 1721 (dev->revision == AMD_813X_REV_B2)) 1722 return; 1723 1724 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 1725 pci_config_dword &= ~AMD_813X_NOIOAMODE; 1726 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 1727 1728 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1729 dev->vendor, dev->device); 1730} 1731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1732DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1733DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1734DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 1735 1736#define AMD_8111_PCI_IRQ_ROUTING 0x56 1737 1738static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 1739{ 1740 u16 pci_config_word; 1741 1742 if (noioapicquirk) 1743 return; 1744 1745 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1746 if (!pci_config_word) { 1747 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " 1748 "already disabled\n", dev->vendor, dev->device); 1749 return; 1750 } 1751 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1752 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1753 dev->vendor, dev->device); 1754} 1755DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1756DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1757#endif /* CONFIG_X86_IO_APIC */ 1758 1759/* 1760 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1761 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1762 * Re-allocate the region if needed... 1763 */ 1764static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1765{ 1766 struct resource *r = &dev->resource[0]; 1767 1768 if (r->start & 0x8) { 1769 r->start = 0; 1770 r->end = 0xf; 1771 } 1772} 1773DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 1774 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1775 quirk_tc86c001_ide); 1776 1777static void __devinit quirk_netmos(struct pci_dev *dev) 1778{ 1779 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1780 unsigned int num_serial = dev->subsystem_device & 0xf; 1781 1782 /* 1783 * These Netmos parts are multiport serial devices with optional 1784 * parallel ports. Even when parallel ports are present, they 1785 * are identified as class SERIAL, which means the serial driver 1786 * will claim them. To prevent this, mark them as class OTHER. 1787 * These combo devices should be claimed by parport_serial. 1788 * 1789 * The subdevice ID is of the form 0x00PS, where <P> is the number 1790 * of parallel ports and <S> is the number of serial ports. 1791 */ 1792 switch (dev->device) { 1793 case PCI_DEVICE_ID_NETMOS_9835: 1794 /* Well, this rule doesn't hold for the following 9835 device */ 1795 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 1796 dev->subsystem_device == 0x0299) 1797 return; 1798 case PCI_DEVICE_ID_NETMOS_9735: 1799 case PCI_DEVICE_ID_NETMOS_9745: 1800 case PCI_DEVICE_ID_NETMOS_9845: 1801 case PCI_DEVICE_ID_NETMOS_9855: 1802 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1803 num_parallel) { 1804 dev_info(&dev->dev, "Netmos %04x (%u parallel, " 1805 "%u serial); changing class SERIAL to OTHER " 1806 "(use parport_serial)\n", 1807 dev->device, num_parallel, num_serial); 1808 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1809 (dev->class & 0xff); 1810 } 1811 } 1812} 1813DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1814 1815static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1816{ 1817 u16 command, pmcsr; 1818 u8 __iomem *csr; 1819 u8 cmd_hi; 1820 int pm; 1821 1822 switch (dev->device) { 1823 /* PCI IDs taken from drivers/net/e100.c */ 1824 case 0x1029: 1825 case 0x1030 ... 0x1034: 1826 case 0x1038 ... 0x103E: 1827 case 0x1050 ... 0x1057: 1828 case 0x1059: 1829 case 0x1064 ... 0x106B: 1830 case 0x1091 ... 0x1095: 1831 case 0x1209: 1832 case 0x1229: 1833 case 0x2449: 1834 case 0x2459: 1835 case 0x245D: 1836 case 0x27DC: 1837 break; 1838 default: 1839 return; 1840 } 1841 1842 /* 1843 * Some firmware hands off the e100 with interrupts enabled, 1844 * which can cause a flood of interrupts if packets are 1845 * received before the driver attaches to the device. So 1846 * disable all e100 interrupts here. The driver will 1847 * re-enable them when it's ready. 1848 */ 1849 pci_read_config_word(dev, PCI_COMMAND, &command); 1850 1851 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1852 return; 1853 1854 /* 1855 * Check that the device is in the D0 power state. If it's not, 1856 * there is no point to look any further. 1857 */ 1858 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1859 if (pm) { 1860 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); 1861 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 1862 return; 1863 } 1864 1865 /* Convert from PCI bus to resource space. */ 1866 csr = ioremap(pci_resource_start(dev, 0), 8); 1867 if (!csr) { 1868 dev_warn(&dev->dev, "Can't map e100 registers\n"); 1869 return; 1870 } 1871 1872 cmd_hi = readb(csr + 3); 1873 if (cmd_hi == 0) { 1874 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " 1875 "disabling\n"); 1876 writeb(1, csr + 3); 1877 } 1878 1879 iounmap(csr); 1880} 1881DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); 1882 1883/* 1884 * The 82575 and 82598 may experience data corruption issues when transitioning 1885 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1886 */ 1887static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) 1888{ 1889 dev_info(&dev->dev, "Disabling L0s\n"); 1890 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1891} 1892DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 1893DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 1894DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 1895DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 1896DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 1897DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 1898DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 1899DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 1900DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 1901DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 1902DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 1903DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 1904DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1905DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1906 1907static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1908{ 1909 /* rev 1 ncr53c810 chips don't set the class at all which means 1910 * they don't get their resources remapped. Fix that here. 1911 */ 1912 1913 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1914 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); 1915 dev->class = PCI_CLASS_STORAGE_SCSI; 1916 } 1917} 1918DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1919 1920/* Enable 1k I/O space granularity on the Intel P64H2 */ 1921static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) 1922{ 1923 u16 en1k; 1924 u8 io_base_lo, io_limit_lo; 1925 unsigned long base, limit; 1926 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1927 1928 pci_read_config_word(dev, 0x40, &en1k); 1929 1930 if (en1k & 0x200) { 1931 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 1932 1933 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1934 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1935 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1936 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; 1937 1938 if (base <= limit) { 1939 res->start = base; 1940 res->end = limit + 0x3ff; 1941 } 1942 } 1943} 1944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 1945 1946/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 1947 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() 1948 * in drivers/pci/setup-bus.c 1949 */ 1950static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) 1951{ 1952 u16 en1k, iobl_adr, iobl_adr_1k; 1953 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; 1954 1955 pci_read_config_word(dev, 0x40, &en1k); 1956 1957 if (en1k & 0x200) { 1958 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); 1959 1960 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 1961 1962 if (iobl_adr != iobl_adr_1k) { 1963 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", 1964 iobl_adr,iobl_adr_1k); 1965 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 1966 } 1967 } 1968} 1969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); 1970 1971/* Under some circumstances, AER is not linked with extended capabilities. 1972 * Force it to be linked by setting the corresponding control bit in the 1973 * config space. 1974 */ 1975static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 1976{ 1977 uint8_t b; 1978 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1979 if (!(b & 0x20)) { 1980 pci_write_config_byte(dev, 0xf41, b | 0x20); 1981 dev_info(&dev->dev, 1982 "Linking AER extended capability\n"); 1983 } 1984 } 1985} 1986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1987 quirk_nvidia_ck804_pcie_aer_ext_cap); 1988DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1989 quirk_nvidia_ck804_pcie_aer_ext_cap); 1990 1991static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 1992{ 1993 /* 1994 * Disable PCI Bus Parking and PCI Master read caching on CX700 1995 * which causes unspecified timing errors with a VT6212L on the PCI 1996 * bus leading to USB2.0 packet loss. 1997 * 1998 * This quirk is only enabled if a second (on the external PCI bus) 1999 * VT6212L is found -- the CX700 core itself also contains a USB 2000 * host controller with the same PCI ID as the VT6212L. 2001 */ 2002 2003 /* Count VT6212L instances */ 2004 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2005 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2006 uint8_t b; 2007 2008 /* p should contain the first (internal) VT6212L -- see if we have 2009 an external one by searching again */ 2010 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2011 if (!p) 2012 return; 2013 pci_dev_put(p); 2014 2015 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2016 if (b & 0x40) { 2017 /* Turn off PCI Bus Parking */ 2018 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2019 2020 dev_info(&dev->dev, 2021 "Disabling VIA CX700 PCI parking\n"); 2022 } 2023 } 2024 2025 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2026 if (b != 0) { 2027 /* Turn off PCI Master read caching */ 2028 pci_write_config_byte(dev, 0x72, 0x0); 2029 2030 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2031 pci_write_config_byte(dev, 0x75, 0x1); 2032 2033 /* Disable "Read FIFO Timer" */ 2034 pci_write_config_byte(dev, 0x77, 0x0); 2035 2036 dev_info(&dev->dev, 2037 "Disabling VIA CX700 PCI caching\n"); 2038 } 2039 } 2040} 2041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2042 2043/* 2044 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the 2045 * VPD end tag will hang the device. This problem was initially 2046 * observed when a vpd entry was created in sysfs 2047 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry 2048 * will dump 32k of data. Reading a full 32k will cause an access 2049 * beyond the VPD end tag causing the device to hang. Once the device 2050 * is hung, the bnx2 driver will not be able to reset the device. 2051 * We believe that it is legal to read beyond the end tag and 2052 * therefore the solution is to limit the read/write length. 2053 */ 2054static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2055{ 2056 /* 2057 * Only disable the VPD capability for 5706, 5706S, 5708, 2058 * 5708S and 5709 rev. A 2059 */ 2060 if ((dev->device == PCI_DEVICE_ID_NX2_5706) || 2061 (dev->device == PCI_DEVICE_ID_NX2_5706S) || 2062 (dev->device == PCI_DEVICE_ID_NX2_5708) || 2063 (dev->device == PCI_DEVICE_ID_NX2_5708S) || 2064 ((dev->device == PCI_DEVICE_ID_NX2_5709) && 2065 (dev->revision & 0xf0) == 0x0)) { 2066 if (dev->vpd) 2067 dev->vpd->len = 0x80; 2068 } 2069} 2070 2071DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2072 PCI_DEVICE_ID_NX2_5706, 2073 quirk_brcm_570x_limit_vpd); 2074DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2075 PCI_DEVICE_ID_NX2_5706S, 2076 quirk_brcm_570x_limit_vpd); 2077DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2078 PCI_DEVICE_ID_NX2_5708, 2079 quirk_brcm_570x_limit_vpd); 2080DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2081 PCI_DEVICE_ID_NX2_5708S, 2082 quirk_brcm_570x_limit_vpd); 2083DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2084 PCI_DEVICE_ID_NX2_5709, 2085 quirk_brcm_570x_limit_vpd); 2086DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2087 PCI_DEVICE_ID_NX2_5709S, 2088 quirk_brcm_570x_limit_vpd); 2089 2090/* Originally in EDAC sources for i82875P: 2091 * Intel tells BIOS developers to hide device 6 which 2092 * configures the overflow device access containing 2093 * the DRBs - this is where we expose device 6. 2094 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2095 */ 2096static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) 2097{ 2098 u8 reg; 2099 2100 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2101 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); 2102 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2103 } 2104} 2105 2106DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2107 quirk_unhide_mch_dev6); 2108DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2109 quirk_unhide_mch_dev6); 2110 2111 2112#ifdef CONFIG_PCI_MSI 2113/* Some chipsets do not support MSI. We cannot easily rely on setting 2114 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2115 * some other busses controlled by the chipset even if Linux is not 2116 * aware of it. Instead of setting the flag on all busses in the 2117 * machine, simply disable MSI globally. 2118 */ 2119static void __init quirk_disable_all_msi(struct pci_dev *dev) 2120{ 2121 pci_no_msi(); 2122 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2123} 2124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2129DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2131 2132/* Disable MSI on chipsets that are known to not support it */ 2133static void __devinit quirk_disable_msi(struct pci_dev *dev) 2134{ 2135 if (dev->subordinate) { 2136 dev_warn(&dev->dev, "MSI quirk detected; " 2137 "subordinate MSI disabled\n"); 2138 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2139 } 2140} 2141DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2142DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2143DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2144 2145/* 2146 * The APC bridge device in AMD 780 family northbridges has some random 2147 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2148 * we use the possible vendor/device IDs of the host bridge for the 2149 * declared quirk, and search for the APC bridge by slot number. 2150 */ 2151static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2152{ 2153 struct pci_dev *apc_bridge; 2154 2155 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2156 if (apc_bridge) { 2157 if (apc_bridge->device == 0x9602) 2158 quirk_disable_msi(apc_bridge); 2159 pci_dev_put(apc_bridge); 2160 } 2161} 2162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2164 2165/* Go through the list of Hypertransport capabilities and 2166 * return 1 if a HT MSI capability is found and enabled */ 2167static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) 2168{ 2169 int pos, ttl = 48; 2170 2171 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2172 while (pos && ttl--) { 2173 u8 flags; 2174 2175 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2176 &flags) == 0) 2177 { 2178 dev_info(&dev->dev, "Found %s HT MSI Mapping\n", 2179 flags & HT_MSI_FLAGS_ENABLE ? 2180 "enabled" : "disabled"); 2181 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2182 } 2183 2184 pos = pci_find_next_ht_capability(dev, pos, 2185 HT_CAPTYPE_MSI_MAPPING); 2186 } 2187 return 0; 2188} 2189 2190/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2191static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 2192{ 2193 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2194 dev_warn(&dev->dev, "MSI quirk detected; " 2195 "subordinate MSI disabled\n"); 2196 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2197 } 2198} 2199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2200 quirk_msi_ht_cap); 2201 2202/* The nVidia CK804 chipset may have 2 HT MSI mappings. 2203 * MSI are supported if the MSI capability set in any of these mappings. 2204 */ 2205static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2206{ 2207 struct pci_dev *pdev; 2208 2209 if (!dev->subordinate) 2210 return; 2211 2212 /* check HT MSI cap on this chipset and the root one. 2213 * a single one having MSI is enough to be sure that MSI are supported. 2214 */ 2215 pdev = pci_get_slot(dev->bus, 0); 2216 if (!pdev) 2217 return; 2218 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2219 dev_warn(&dev->dev, "MSI quirk detected; " 2220 "subordinate MSI disabled\n"); 2221 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2222 } 2223 pci_dev_put(pdev); 2224} 2225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2226 quirk_nvidia_ck804_msi_ht_cap); 2227 2228/* Force enable MSI mapping capability on HT bridges */ 2229static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) 2230{ 2231 int pos, ttl = 48; 2232 2233 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2234 while (pos && ttl--) { 2235 u8 flags; 2236 2237 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2238 &flags) == 0) { 2239 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2240 2241 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2242 flags | HT_MSI_FLAGS_ENABLE); 2243 } 2244 pos = pci_find_next_ht_capability(dev, pos, 2245 HT_CAPTYPE_MSI_MAPPING); 2246 } 2247} 2248DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2249 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2250 ht_enable_msi_mapping); 2251 2252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2253 ht_enable_msi_mapping); 2254 2255/* The P5N32-SLI motherboards from Asus have a problem with msi 2256 * for the MCP55 NIC. It is not yet determined whether the msi problem 2257 * also affects other devices. As for now, turn off msi for this device. 2258 */ 2259static void __devinit nvenet_msi_disable(struct pci_dev *dev) 2260{ 2261 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") || 2262 dmi_name_in_vendors("P5N32-E SLI")) { 2263 dev_info(&dev->dev, 2264 "Disabling msi for MCP55 NIC on P5N32-SLI\n"); 2265 dev->no_msi = 1; 2266 } 2267} 2268DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2269 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2270 nvenet_msi_disable); 2271 2272static int __devinit ht_check_msi_mapping(struct pci_dev *dev) 2273{ 2274 int pos, ttl = 48; 2275 int found = 0; 2276 2277 /* check if there is HT MSI cap or enabled on this device */ 2278 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2279 while (pos && ttl--) { 2280 u8 flags; 2281 2282 if (found < 1) 2283 found = 1; 2284 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2285 &flags) == 0) { 2286 if (flags & HT_MSI_FLAGS_ENABLE) { 2287 if (found < 2) { 2288 found = 2; 2289 break; 2290 } 2291 } 2292 } 2293 pos = pci_find_next_ht_capability(dev, pos, 2294 HT_CAPTYPE_MSI_MAPPING); 2295 } 2296 2297 return found; 2298} 2299 2300static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) 2301{ 2302 struct pci_dev *dev; 2303 int pos; 2304 int i, dev_no; 2305 int found = 0; 2306 2307 dev_no = host_bridge->devfn >> 3; 2308 for (i = dev_no + 1; i < 0x20; i++) { 2309 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2310 if (!dev) 2311 continue; 2312 2313 /* found next host bridge ?*/ 2314 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2315 if (pos != 0) { 2316 pci_dev_put(dev); 2317 break; 2318 } 2319 2320 if (ht_check_msi_mapping(dev)) { 2321 found = 1; 2322 pci_dev_put(dev); 2323 break; 2324 } 2325 pci_dev_put(dev); 2326 } 2327 2328 return found; 2329} 2330 2331#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2332#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2333 2334static int __devinit is_end_of_ht_chain(struct pci_dev *dev) 2335{ 2336 int pos, ctrl_off; 2337 int end = 0; 2338 u16 flags, ctrl; 2339 2340 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2341 2342 if (!pos) 2343 goto out; 2344 2345 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 2346 2347 ctrl_off = ((flags >> 10) & 1) ? 2348 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 2349 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 2350 2351 if (ctrl & (1 << 6)) 2352 end = 1; 2353 2354out: 2355 return end; 2356} 2357 2358static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) 2359{ 2360 struct pci_dev *host_bridge; 2361 int pos; 2362 int i, dev_no; 2363 int found = 0; 2364 2365 dev_no = dev->devfn >> 3; 2366 for (i = dev_no; i >= 0; i--) { 2367 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 2368 if (!host_bridge) 2369 continue; 2370 2371 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2372 if (pos != 0) { 2373 found = 1; 2374 break; 2375 } 2376 pci_dev_put(host_bridge); 2377 } 2378 2379 if (!found) 2380 return; 2381 2382 /* don't enable end_device/host_bridge with leaf directly here */ 2383 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 2384 host_bridge_with_leaf(host_bridge)) 2385 goto out; 2386 2387 /* root did that ! */ 2388 if (msi_ht_cap_enabled(host_bridge)) 2389 goto out; 2390 2391 ht_enable_msi_mapping(dev); 2392 2393out: 2394 pci_dev_put(host_bridge); 2395} 2396 2397static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) 2398{ 2399 int pos, ttl = 48; 2400 2401 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2402 while (pos && ttl--) { 2403 u8 flags; 2404 2405 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2406 &flags) == 0) { 2407 dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); 2408 2409 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2410 flags & ~HT_MSI_FLAGS_ENABLE); 2411 } 2412 pos = pci_find_next_ht_capability(dev, pos, 2413 HT_CAPTYPE_MSI_MAPPING); 2414 } 2415} 2416 2417static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2418{ 2419 struct pci_dev *host_bridge; 2420 int pos; 2421 int found; 2422 2423 if (!pci_msi_enabled()) 2424 return; 2425 2426 /* check if there is HT MSI cap or enabled on this device */ 2427 found = ht_check_msi_mapping(dev); 2428 2429 /* no HT MSI CAP */ 2430 if (found == 0) 2431 return; 2432 2433 /* 2434 * HT MSI mapping should be disabled on devices that are below 2435 * a non-Hypertransport host bridge. Locate the host bridge... 2436 */ 2437 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2438 if (host_bridge == NULL) { 2439 dev_warn(&dev->dev, 2440 "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 2441 return; 2442 } 2443 2444 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 2445 if (pos != 0) { 2446 /* Host bridge is to HT */ 2447 if (found == 1) { 2448 /* it is not enabled, try to enable it */ 2449 if (all) 2450 ht_enable_msi_mapping(dev); 2451 else 2452 nv_ht_enable_msi_mapping(dev); 2453 } 2454 return; 2455 } 2456 2457 /* HT MSI is not enabled */ 2458 if (found == 1) 2459 return; 2460 2461 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2462 ht_disable_msi_mapping(dev); 2463} 2464 2465static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2466{ 2467 return __nv_msi_ht_cap_quirk(dev, 1); 2468} 2469 2470static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2471{ 2472 return __nv_msi_ht_cap_quirk(dev, 0); 2473} 2474 2475DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2476DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2477 2478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2479DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2480 2481static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) 2482{ 2483 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2484} 2485static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2486{ 2487 struct pci_dev *p; 2488 2489 /* SB700 MSI issue will be fixed at HW level from revision A21, 2490 * we need check PCI REVISION ID of SMBus controller to get SB700 2491 * revision. 2492 */ 2493 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2494 NULL); 2495 if (!p) 2496 return; 2497 2498 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 2499 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2500 pci_dev_put(p); 2501} 2502DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2503 PCI_DEVICE_ID_TIGON3_5780, 2504 quirk_msi_intx_disable_bug); 2505DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2506 PCI_DEVICE_ID_TIGON3_5780S, 2507 quirk_msi_intx_disable_bug); 2508DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2509 PCI_DEVICE_ID_TIGON3_5714, 2510 quirk_msi_intx_disable_bug); 2511DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2512 PCI_DEVICE_ID_TIGON3_5714S, 2513 quirk_msi_intx_disable_bug); 2514DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2515 PCI_DEVICE_ID_TIGON3_5715, 2516 quirk_msi_intx_disable_bug); 2517DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 2518 PCI_DEVICE_ID_TIGON3_5715S, 2519 quirk_msi_intx_disable_bug); 2520 2521DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 2522 quirk_msi_intx_disable_ati_bug); 2523DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 2524 quirk_msi_intx_disable_ati_bug); 2525DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 2526 quirk_msi_intx_disable_ati_bug); 2527DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 2528 quirk_msi_intx_disable_ati_bug); 2529DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 2530 quirk_msi_intx_disable_ati_bug); 2531 2532DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 2533 quirk_msi_intx_disable_bug); 2534DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 2535 quirk_msi_intx_disable_bug); 2536DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2537 quirk_msi_intx_disable_bug); 2538 2539#endif /* CONFIG_PCI_MSI */ 2540 2541#ifdef CONFIG_PCI_IOV 2542 2543/* 2544 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the 2545 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the 2546 * old Flash Memory Space. 2547 */ 2548static void __devinit quirk_i82576_sriov(struct pci_dev *dev) 2549{ 2550 int pos, flags; 2551 u32 bar, start, size; 2552 2553 if (PAGE_SIZE > 0x10000) 2554 return; 2555 2556 flags = pci_resource_flags(dev, 0); 2557 if ((flags & PCI_BASE_ADDRESS_SPACE) != 2558 PCI_BASE_ADDRESS_SPACE_MEMORY || 2559 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != 2560 PCI_BASE_ADDRESS_MEM_TYPE_32) 2561 return; 2562 2563 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 2564 if (!pos) 2565 return; 2566 2567 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar); 2568 if (bar & PCI_BASE_ADDRESS_MEM_MASK) 2569 return; 2570 2571 start = pci_resource_start(dev, 1); 2572 size = pci_resource_len(dev, 1); 2573 if (!start || size != 0x400000 || start & (size - 1)) 2574 return; 2575 2576 pci_resource_flags(dev, 1) = 0; 2577 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); 2578 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start); 2579 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2); 2580 2581 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n"); 2582} 2583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov); 2584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov); 2585DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov); 2586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov); 2587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov); 2588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov); 2589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov); 2590 2591#endif /* CONFIG_PCI_IOV */ 2592 2593/* Allow manual resource allocation for PCI hotplug bridges 2594 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2595 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2596 * kernel fails to allocate resources when hotplug device is 2597 * inserted and PCI bus is rescanned. 2598 */ 2599static void __devinit quirk_hotplug_bridge(struct pci_dev *dev) 2600{ 2601 dev->is_hotplug_bridge = 1; 2602} 2603 2604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2605 2606/* 2607 * This is a quirk for the Ricoh MMC controller found as a part of 2608 * some mulifunction chips. 2609 2610 * This is very similiar and based on the ricoh_mmc driver written by 2611 * Philip Langdale. Thank you for these magic sequences. 2612 * 2613 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2614 * and one or both of cardbus or firewire. 2615 * 2616 * It happens that they implement SD and MMC 2617 * support as separate controllers (and PCI functions). The linux SDHCI 2618 * driver supports MMC cards but the chip detects MMC cards in hardware 2619 * and directs them to the MMC controller - so the SDHCI driver never sees 2620 * them. 2621 * 2622 * To get around this, we must disable the useless MMC controller. 2623 * At that point, the SDHCI controller will start seeing them 2624 * It seems to be the case that the relevant PCI registers to deactivate the 2625 * MMC controller live on PCI function 0, which might be the cardbus controller 2626 * or the firewire controller, depending on the particular chip in question 2627 * 2628 * This has to be done early, because as soon as we disable the MMC controller 2629 * other pci functions shift up one level, e.g. function #2 becomes function 2630 * #1, and this will confuse the pci core. 2631 */ 2632 2633#ifdef CONFIG_MMC_RICOH_MMC 2634static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2635{ 2636 /* disable via cardbus interface */ 2637 u8 write_enable; 2638 u8 write_target; 2639 u8 disable; 2640 2641 /* disable must be done via function #0 */ 2642 if (PCI_FUNC(dev->devfn)) 2643 return; 2644 2645 pci_read_config_byte(dev, 0xB7, &disable); 2646 if (disable & 0x02) 2647 return; 2648 2649 pci_read_config_byte(dev, 0x8E, &write_enable); 2650 pci_write_config_byte(dev, 0x8E, 0xAA); 2651 pci_read_config_byte(dev, 0x8D, &write_target); 2652 pci_write_config_byte(dev, 0x8D, 0xB7); 2653 pci_write_config_byte(dev, 0xB7, disable | 0x02); 2654 pci_write_config_byte(dev, 0x8E, write_enable); 2655 pci_write_config_byte(dev, 0x8D, write_target); 2656 2657 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2658 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2659} 2660DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2661DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2662 2663static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2664{ 2665 /* disable via firewire interface */ 2666 u8 write_enable; 2667 u8 disable; 2668 2669 /* disable must be done via function #0 */ 2670 if (PCI_FUNC(dev->devfn)) 2671 return; 2672 2673 pci_read_config_byte(dev, 0xCB, &disable); 2674 2675 if (disable & 0x02) 2676 return; 2677 2678 pci_read_config_byte(dev, 0xCA, &write_enable); 2679 pci_write_config_byte(dev, 0xCA, 0x57); 2680 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2681 pci_write_config_byte(dev, 0xCA, write_enable); 2682 2683 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2684 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); 2685} 2686DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2687DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2688#endif /*CONFIG_MMC_RICOH_MMC*/ 2689 2690#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP) 2691#define VTUNCERRMSK_REG 0x1ac 2692#define VTD_MSK_SPEC_ERRORS (1 << 31) 2693/* 2694 * This is a quirk for masking vt-d spec defined errors to platform error 2695 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 2696 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 2697 * on the RAS config settings of the platform) when a vt-d fault happens. 2698 * The resulting SMI caused the system to hang. 2699 * 2700 * VT-d spec related errors are already handled by the VT-d OS code, so no 2701 * need to report the same error through other channels. 2702 */ 2703static void vtd_mask_spec_errors(struct pci_dev *dev) 2704{ 2705 u32 word; 2706 2707 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 2708 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 2709} 2710DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 2711DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2712#endif 2713 2714static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2715 struct pci_fixup *end) 2716{ 2717 while (f < end) { 2718 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 2719 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 2720 dev_dbg(&dev->dev, "calling %pF\n", f->hook); 2721 f->hook(dev); 2722 } 2723 f++; 2724 } 2725} 2726 2727extern struct pci_fixup __start_pci_fixups_early[]; 2728extern struct pci_fixup __end_pci_fixups_early[]; 2729extern struct pci_fixup __start_pci_fixups_header[]; 2730extern struct pci_fixup __end_pci_fixups_header[]; 2731extern struct pci_fixup __start_pci_fixups_final[]; 2732extern struct pci_fixup __end_pci_fixups_final[]; 2733extern struct pci_fixup __start_pci_fixups_enable[]; 2734extern struct pci_fixup __end_pci_fixups_enable[]; 2735extern struct pci_fixup __start_pci_fixups_resume[]; 2736extern struct pci_fixup __end_pci_fixups_resume[]; 2737extern struct pci_fixup __start_pci_fixups_resume_early[]; 2738extern struct pci_fixup __end_pci_fixups_resume_early[]; 2739extern struct pci_fixup __start_pci_fixups_suspend[]; 2740extern struct pci_fixup __end_pci_fixups_suspend[]; 2741 2742 2743void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 2744{ 2745 struct pci_fixup *start, *end; 2746 2747 switch(pass) { 2748 case pci_fixup_early: 2749 start = __start_pci_fixups_early; 2750 end = __end_pci_fixups_early; 2751 break; 2752 2753 case pci_fixup_header: 2754 start = __start_pci_fixups_header; 2755 end = __end_pci_fixups_header; 2756 break; 2757 2758 case pci_fixup_final: 2759 start = __start_pci_fixups_final; 2760 end = __end_pci_fixups_final; 2761 break; 2762 2763 case pci_fixup_enable: 2764 start = __start_pci_fixups_enable; 2765 end = __end_pci_fixups_enable; 2766 break; 2767 2768 case pci_fixup_resume: 2769 start = __start_pci_fixups_resume; 2770 end = __end_pci_fixups_resume; 2771 break; 2772 2773 case pci_fixup_resume_early: 2774 start = __start_pci_fixups_resume_early; 2775 end = __end_pci_fixups_resume_early; 2776 break; 2777 2778 case pci_fixup_suspend: 2779 start = __start_pci_fixups_suspend; 2780 end = __end_pci_fixups_suspend; 2781 break; 2782 2783 default: 2784 /* stupid compiler warning, you would think with an enum... */ 2785 return; 2786 } 2787 pci_do_fixups(dev, start, end); 2788} 2789EXPORT_SYMBOL(pci_fixup_device); 2790 2791static int __init pci_apply_final_quirks(void) 2792{ 2793 struct pci_dev *dev = NULL; 2794 u8 cls = 0; 2795 u8 tmp; 2796 2797 if (pci_cache_line_size) 2798 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 2799 pci_cache_line_size << 2); 2800 2801 for_each_pci_dev(dev) { 2802 pci_fixup_device(pci_fixup_final, dev); 2803 /* 2804 * If arch hasn't set it explicitly yet, use the CLS 2805 * value shared by all PCI devices. If there's a 2806 * mismatch, fall back to the default value. 2807 */ 2808 if (!pci_cache_line_size) { 2809 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 2810 if (!cls) 2811 cls = tmp; 2812 if (!tmp || cls == tmp) 2813 continue; 2814 2815 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " 2816 "using %u bytes\n", cls << 2, tmp << 2, 2817 pci_dfl_cache_line_size << 2); 2818 pci_cache_line_size = pci_dfl_cache_line_size; 2819 } 2820 } 2821 if (!pci_cache_line_size) { 2822 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 2823 cls << 2, pci_dfl_cache_line_size << 2); 2824 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 2825 } 2826 2827 return 0; 2828} 2829 2830fs_initcall_sync(pci_apply_final_quirks); 2831 2832/* 2833 * Followings are device-specific reset methods which can be used to 2834 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 2835 * not available. 2836 */ 2837static int reset_intel_generic_dev(struct pci_dev *dev, int probe) 2838{ 2839 int pos; 2840 2841 /* only implement PCI_CLASS_SERIAL_USB at present */ 2842 if (dev->class == PCI_CLASS_SERIAL_USB) { 2843 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 2844 if (!pos) 2845 return -ENOTTY; 2846 2847 if (probe) 2848 return 0; 2849 2850 pci_write_config_byte(dev, pos + 0x4, 1); 2851 msleep(100); 2852 2853 return 0; 2854 } else { 2855 return -ENOTTY; 2856 } 2857} 2858 2859static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 2860{ 2861 int pos; 2862 2863 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 2864 if (!pos) 2865 return -ENOTTY; 2866 2867 if (probe) 2868 return 0; 2869 2870 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, 2871 PCI_EXP_DEVCTL_BCR_FLR); 2872 msleep(100); 2873 2874 return 0; 2875} 2876 2877#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 2878 2879static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 2880 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 2881 reset_intel_82599_sfp_virtfn }, 2882 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2883 reset_intel_generic_dev }, 2884 { 0 } 2885}; 2886 2887int pci_dev_specific_reset(struct pci_dev *dev, int probe) 2888{ 2889 const struct pci_dev_reset_methods *i; 2890 2891 for (i = pci_dev_reset_methods; i->reset; i++) { 2892 if ((i->vendor == dev->vendor || 2893 i->vendor == (u16)PCI_ANY_ID) && 2894 (i->device == dev->device || 2895 i->device == (u16)PCI_ANY_ID)) 2896 return i->reset(dev, probe); 2897 } 2898 2899 return -ENOTTY; 2900} 2901