1/* 2** ccio-dma.c: 3** DMA management routines for first generation cache-coherent machines. 4** Program U2/Uturn in "Virtual Mode" and use the I/O MMU. 5** 6** (c) Copyright 2000 Grant Grundler 7** (c) Copyright 2000 Ryan Bradetich 8** (c) Copyright 2000 Hewlett-Packard Company 9** 10** This program is free software; you can redistribute it and/or modify 11** it under the terms of the GNU General Public License as published by 12** the Free Software Foundation; either version 2 of the License, or 13** (at your option) any later version. 14** 15** 16** "Real Mode" operation refers to U2/Uturn chip operation. 17** U2/Uturn were designed to perform coherency checks w/o using 18** the I/O MMU - basically what x86 does. 19** 20** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at: 21** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc 22** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c 23** 24** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c. 25** 26** Drawbacks of using Real Mode are: 27** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal). 28** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute. 29** o Ability to do scatter/gather in HW is lost. 30** o Doesn't work under PCX-U/U+ machines since they didn't follow 31** the coherency design originally worked out. Only PCX-W does. 32*/ 33 34#include <linux/types.h> 35#include <linux/kernel.h> 36#include <linux/init.h> 37#include <linux/mm.h> 38#include <linux/spinlock.h> 39#include <linux/slab.h> 40#include <linux/string.h> 41#include <linux/pci.h> 42#include <linux/reboot.h> 43#include <linux/proc_fs.h> 44#include <linux/seq_file.h> 45#include <linux/scatterlist.h> 46#include <linux/iommu-helper.h> 47 48#include <asm/byteorder.h> 49#include <asm/cache.h> /* for L1_CACHE_BYTES */ 50#include <asm/uaccess.h> 51#include <asm/page.h> 52#include <asm/dma.h> 53#include <asm/io.h> 54#include <asm/hardware.h> /* for register_module() */ 55#include <asm/parisc-device.h> 56 57/* 58** Choose "ccio" since that's what HP-UX calls it. 59** Make it easier for folks to migrate from one to the other :^) 60*/ 61#define MODULE_NAME "ccio" 62 63#undef DEBUG_CCIO_RES 64#undef DEBUG_CCIO_RUN 65#undef DEBUG_CCIO_INIT 66#undef DEBUG_CCIO_RUN_SG 67 68#ifdef CONFIG_PROC_FS 69/* depends on proc fs support. But costs CPU performance. */ 70#undef CCIO_COLLECT_STATS 71#endif 72 73#include <asm/runway.h> /* for proc_runway_root */ 74 75#ifdef DEBUG_CCIO_INIT 76#define DBG_INIT(x...) printk(x) 77#else 78#define DBG_INIT(x...) 79#endif 80 81#ifdef DEBUG_CCIO_RUN 82#define DBG_RUN(x...) printk(x) 83#else 84#define DBG_RUN(x...) 85#endif 86 87#ifdef DEBUG_CCIO_RES 88#define DBG_RES(x...) printk(x) 89#else 90#define DBG_RES(x...) 91#endif 92 93#ifdef DEBUG_CCIO_RUN_SG 94#define DBG_RUN_SG(x...) printk(x) 95#else 96#define DBG_RUN_SG(x...) 97#endif 98 99#define CCIO_INLINE inline 100#define WRITE_U32(value, addr) __raw_writel(value, addr) 101#define READ_U32(addr) __raw_readl(addr) 102 103#define U2_IOA_RUNWAY 0x580 104#define U2_BC_GSC 0x501 105#define UTURN_IOA_RUNWAY 0x581 106#define UTURN_BC_GSC 0x502 107 108#define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */ 109#define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */ 110#define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */ 111 112struct ioa_registers { 113 /* Runway Supervisory Set */ 114 int32_t unused1[12]; 115 uint32_t io_command; /* Offset 12 */ 116 uint32_t io_status; /* Offset 13 */ 117 uint32_t io_control; /* Offset 14 */ 118 int32_t unused2[1]; 119 120 /* Runway Auxiliary Register Set */ 121 uint32_t io_err_resp; /* Offset 0 */ 122 uint32_t io_err_info; /* Offset 1 */ 123 uint32_t io_err_req; /* Offset 2 */ 124 uint32_t io_err_resp_hi; /* Offset 3 */ 125 uint32_t io_tlb_entry_m; /* Offset 4 */ 126 uint32_t io_tlb_entry_l; /* Offset 5 */ 127 uint32_t unused3[1]; 128 uint32_t io_pdir_base; /* Offset 7 */ 129 uint32_t io_io_low_hv; /* Offset 8 */ 130 uint32_t io_io_high_hv; /* Offset 9 */ 131 uint32_t unused4[1]; 132 uint32_t io_chain_id_mask; /* Offset 11 */ 133 uint32_t unused5[2]; 134 uint32_t io_io_low; /* Offset 14 */ 135 uint32_t io_io_high; /* Offset 15 */ 136}; 137 138/* 139** IOA Registers 140** ------------- 141** 142** Runway IO_CONTROL Register (+0x38) 143** 144** The Runway IO_CONTROL register controls the forwarding of transactions. 145** 146** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 | 147** | HV | TLB | reserved | HV | mode | reserved | 148** 149** o mode field indicates the address translation of transactions 150** forwarded from Runway to GSC+: 151** Mode Name Value Definition 152** Off (default) 0 Opaque to matching addresses. 153** Include 1 Transparent for matching addresses. 154** Peek 3 Map matching addresses. 155** 156** + "Off" mode: Runway transactions which match the I/O range 157** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored. 158** + "Include" mode: all addresses within the I/O range specified 159** by the IO_IO_LOW and IO_IO_HIGH registers are transparently 160** forwarded. This is the I/O Adapter's normal operating mode. 161** + "Peek" mode: used during system configuration to initialize the 162** GSC+ bus. Runway Write_Shorts in the address range specified by 163** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter 164** *AND* the GSC+ address is remapped to the Broadcast Physical 165** Address space by setting the 14 high order address bits of the 166** 32 bit GSC+ address to ones. 167** 168** o TLB field affects transactions which are forwarded from GSC+ to Runway. 169** "Real" mode is the poweron default. 170** 171** TLB Mode Value Description 172** Real 0 No TLB translation. Address is directly mapped and the 173** virtual address is composed of selected physical bits. 174** Error 1 Software fills the TLB manually. 175** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory). 176** 177** 178** IO_IO_LOW_HV +0x60 (HV dependent) 179** IO_IO_HIGH_HV +0x64 (HV dependent) 180** IO_IO_LOW +0x78 (Architected register) 181** IO_IO_HIGH +0x7c (Architected register) 182** 183** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the 184** I/O Adapter address space, respectively. 185** 186** 0 ... 7 | 8 ... 15 | 16 ... 31 | 187** 11111111 | 11111111 | address | 188** 189** Each LOW/HIGH pair describes a disjoint address space region. 190** (2 per GSC+ port). Each incoming Runway transaction address is compared 191** with both sets of LOW/HIGH registers. If the address is in the range 192** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction 193** for forwarded to the respective GSC+ bus. 194** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying 195** an address space region. 196** 197** In order for a Runway address to reside within GSC+ extended address space: 198** Runway Address [0:7] must identically compare to 8'b11111111 199** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19] 200** Runway Address [12:23] must be greater than or equal to 201** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31]. 202** Runway Address [24:39] is not used in the comparison. 203** 204** When the Runway transaction is forwarded to GSC+, the GSC+ address is 205** as follows: 206** GSC+ Address[0:3] 4'b1111 207** GSC+ Address[4:29] Runway Address[12:37] 208** GSC+ Address[30:31] 2'b00 209** 210** All 4 Low/High registers must be initialized (by PDC) once the lower bus 211** is interrogated and address space is defined. The operating system will 212** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following 213** the PDC initialization. However, the hardware version dependent IO_IO_LOW 214** and IO_IO_HIGH registers should not be subsequently altered by the OS. 215** 216** Writes to both sets of registers will take effect immediately, bypassing 217** the queues, which ensures that subsequent Runway transactions are checked 218** against the updated bounds values. However reads are queued, introducing 219** the possibility of a read being bypassed by a subsequent write to the same 220** register. This sequence can be avoided by having software wait for read 221** returns before issuing subsequent writes. 222*/ 223 224struct ioc { 225 struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */ 226 u8 *res_map; /* resource map, bit == pdir entry */ 227 u64 *pdir_base; /* physical base address */ 228 u32 pdir_size; /* bytes, function of IOV Space size */ 229 u32 res_hint; /* next available IOVP - 230 circular search */ 231 u32 res_size; /* size of resource map in bytes */ 232 spinlock_t res_lock; 233 234#ifdef CCIO_COLLECT_STATS 235#define CCIO_SEARCH_SAMPLE 0x100 236 unsigned long avg_search[CCIO_SEARCH_SAMPLE]; 237 unsigned long avg_idx; /* current index into avg_search */ 238 unsigned long used_pages; 239 unsigned long msingle_calls; 240 unsigned long msingle_pages; 241 unsigned long msg_calls; 242 unsigned long msg_pages; 243 unsigned long usingle_calls; 244 unsigned long usingle_pages; 245 unsigned long usg_calls; 246 unsigned long usg_pages; 247#endif 248 unsigned short cujo20_bug; 249 250 /* STUFF We don't need in performance path */ 251 u32 chainid_shift; /* specify bit location of chain_id */ 252 struct ioc *next; /* Linked list of discovered iocs */ 253 const char *name; /* device name from firmware */ 254 unsigned int hw_path; /* the hardware path this ioc is associatd with */ 255 struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */ 256 struct resource mmio_region[2]; /* The "routed" MMIO regions */ 257}; 258 259static struct ioc *ioc_list; 260static int ioc_count; 261 262/************************************************************** 263* 264* I/O Pdir Resource Management 265* 266* Bits set in the resource map are in use. 267* Each bit can represent a number of pages. 268* LSbs represent lower addresses (IOVA's). 269* 270* This was was copied from sba_iommu.c. Don't try to unify 271* the two resource managers unless a way to have different 272* allocation policies is also adjusted. We'd like to avoid 273* I/O TLB thrashing by having resource allocation policy 274* match the I/O TLB replacement policy. 275* 276***************************************************************/ 277#define IOVP_SIZE PAGE_SIZE 278#define IOVP_SHIFT PAGE_SHIFT 279#define IOVP_MASK PAGE_MASK 280 281/* Convert from IOVP to IOVA and vice versa. */ 282#define CCIO_IOVA(iovp,offset) ((iovp) | (offset)) 283#define CCIO_IOVP(iova) ((iova) & IOVP_MASK) 284 285#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 286#define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT) 287#define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset) 288 289/* 290** Don't worry about the 150% average search length on a miss. 291** If the search wraps around, and passes the res_hint, it will 292** cause the kernel to panic anyhow. 293*/ 294#define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \ 295 for(; res_ptr < res_end; ++res_ptr) { \ 296 int ret;\ 297 unsigned int idx;\ 298 idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \ 299 ret = iommu_is_span_boundary(idx << 3, pages_needed, 0, boundary_size);\ 300 if ((0 == (*res_ptr & mask)) && !ret) { \ 301 *res_ptr |= mask; \ 302 res_idx = idx;\ 303 ioc->res_hint = res_idx + (size >> 3); \ 304 goto resource_found; \ 305 } \ 306 } 307 308#define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \ 309 u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \ 310 u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \ 311 CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \ 312 res_ptr = (u##size *)&(ioc)->res_map[0]; \ 313 CCIO_SEARCH_LOOP(ioa, res_idx, mask, size); 314 315/* 316** Find available bit in this ioa's resource map. 317** Use a "circular" search: 318** o Most IOVA's are "temporary" - avg search time should be small. 319** o keep a history of what happened for debugging 320** o KISS. 321** 322** Perf optimizations: 323** o search for log2(size) bits at a time. 324** o search for available resource bits using byte/word/whatever. 325** o use different search for "large" (eg > 4 pages) or "very large" 326** (eg > 16 pages) mappings. 327*/ 328 329/** 330 * ccio_alloc_range - Allocate pages in the ioc's resource map. 331 * @ioc: The I/O Controller. 332 * @pages_needed: The requested number of pages to be mapped into the 333 * I/O Pdir... 334 * 335 * This function searches the resource map of the ioc to locate a range 336 * of available pages for the requested size. 337 */ 338static int 339ccio_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 340{ 341 unsigned int pages_needed = size >> IOVP_SHIFT; 342 unsigned int res_idx; 343 unsigned long boundary_size; 344#ifdef CCIO_COLLECT_STATS 345 unsigned long cr_start = mfctl(16); 346#endif 347 348 BUG_ON(pages_needed == 0); 349 BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE); 350 351 DBG_RES("%s() size: %d pages_needed %d\n", 352 __func__, size, pages_needed); 353 354 /* 355 ** "seek and ye shall find"...praying never hurts either... 356 ** ggg sacrifices another 710 to the computer gods. 357 */ 358 359 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, 360 1ULL << IOVP_SHIFT) >> IOVP_SHIFT; 361 362 if (pages_needed <= 8) { 363 /* 364 * LAN traffic will not thrash the TLB IFF the same NIC 365 * uses 8 adjacent pages to map separate payload data. 366 * ie the same byte in the resource bit map. 367 */ 368 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8); 369 } else if (pages_needed <= 16) { 370 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16); 371 } else if (pages_needed <= 32) { 372 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32); 373#ifdef __LP64__ 374 } else if (pages_needed <= 64) { 375 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64); 376#endif 377 } else { 378 panic("%s: %s() Too many pages to map. pages_needed: %u\n", 379 __FILE__, __func__, pages_needed); 380 } 381 382 panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__, 383 __func__); 384 385resource_found: 386 387 DBG_RES("%s() res_idx %d res_hint: %d\n", 388 __func__, res_idx, ioc->res_hint); 389 390#ifdef CCIO_COLLECT_STATS 391 { 392 unsigned long cr_end = mfctl(16); 393 unsigned long tmp = cr_end - cr_start; 394 /* check for roll over */ 395 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 396 } 397 ioc->avg_search[ioc->avg_idx++] = cr_start; 398 ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1; 399 ioc->used_pages += pages_needed; 400#endif 401 /* 402 ** return the bit address. 403 */ 404 return res_idx << 3; 405} 406 407#define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \ 408 u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \ 409 BUG_ON((*res_ptr & mask) != mask); \ 410 *res_ptr &= ~(mask); 411 412/** 413 * ccio_free_range - Free pages from the ioc's resource map. 414 * @ioc: The I/O Controller. 415 * @iova: The I/O Virtual Address. 416 * @pages_mapped: The requested number of pages to be freed from the 417 * I/O Pdir. 418 * 419 * This function frees the resouces allocated for the iova. 420 */ 421static void 422ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped) 423{ 424 unsigned long iovp = CCIO_IOVP(iova); 425 unsigned int res_idx = PDIR_INDEX(iovp) >> 3; 426 427 BUG_ON(pages_mapped == 0); 428 BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE); 429 BUG_ON(pages_mapped > BITS_PER_LONG); 430 431 DBG_RES("%s(): res_idx: %d pages_mapped %d\n", 432 __func__, res_idx, pages_mapped); 433 434#ifdef CCIO_COLLECT_STATS 435 ioc->used_pages -= pages_mapped; 436#endif 437 438 if(pages_mapped <= 8) { 439 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffUL, 8); 440 } else if(pages_mapped <= 16) { 441 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffffUL, 16); 442 } else if(pages_mapped <= 32) { 443 CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32); 444#ifdef __LP64__ 445 } else if(pages_mapped <= 64) { 446 CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64); 447#endif 448 } else { 449 panic("%s:%s() Too many pages to unmap.\n", __FILE__, 450 __func__); 451 } 452} 453 454/**************************************************************** 455** 456** CCIO dma_ops support routines 457** 458*****************************************************************/ 459 460typedef unsigned long space_t; 461#define KERNEL_SPACE 0 462 463#define IOPDIR_VALID 0x01UL 464#define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */ 465#ifdef CONFIG_EISA 466#define HINT_STOP_MOST 0x04UL /* LSL support */ 467#else 468#define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */ 469#endif 470#define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */ 471#define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */ 472 473 474/* 475** Use direction (ie PCI_DMA_TODEVICE) to pick hint. 476** ccio_alloc_consistent() depends on this to get SAFE_DMA 477** when it passes in BIDIRECTIONAL flag. 478*/ 479static u32 hint_lookup[] = { 480 [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID, 481 [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID, 482 [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID, 483}; 484 485/** 486 * ccio_io_pdir_entry - Initialize an I/O Pdir. 487 * @pdir_ptr: A pointer into I/O Pdir. 488 * @sid: The Space Identifier. 489 * @vba: The virtual address. 490 * @hints: The DMA Hint. 491 * 492 * Given a virtual address (vba, arg2) and space id, (sid, arg1), 493 * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir 494 * entry consists of 8 bytes as shown below (MSB == bit 0): 495 * 496 * 497 * WORD 0: 498 * +------+----------------+-----------------------------------------------+ 499 * | Phys | Virtual Index | Phys | 500 * | 0:3 | 0:11 | 4:19 | 501 * |4 bits| 12 bits | 16 bits | 502 * +------+----------------+-----------------------------------------------+ 503 * WORD 1: 504 * +-----------------------+-----------------------------------------------+ 505 * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid | 506 * | 20:39 | | Enable |Enable | |Enable|DMA | | 507 * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit | 508 * +-----------------------+-----------------------------------------------+ 509 * 510 * The virtual index field is filled with the results of the LCI 511 * (Load Coherence Index) instruction. The 8 bits used for the virtual 512 * index are bits 12:19 of the value returned by LCI. 513 */ 514static void CCIO_INLINE 515ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 516 unsigned long hints) 517{ 518 register unsigned long pa; 519 register unsigned long ci; /* coherent index */ 520 521 /* We currently only support kernel addresses */ 522 BUG_ON(sid != KERNEL_SPACE); 523 524 mtsp(sid,1); 525 526 /* 527 ** WORD 1 - low order word 528 ** "hints" parm includes the VALID bit! 529 ** "dep" clobbers the physical address offset bits as well. 530 */ 531 pa = virt_to_phys(vba); 532 asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints)); 533 ((u32 *)pdir_ptr)[1] = (u32) pa; 534 535 /* 536 ** WORD 0 - high order word 537 */ 538 539#ifdef __LP64__ 540 /* 541 ** get bits 12:15 of physical address 542 ** shift bits 16:31 of physical address 543 ** and deposit them 544 */ 545 asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa)); 546 asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa)); 547 asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci)); 548#else 549 pa = 0; 550#endif 551 /* 552 ** get CPU coherency index bits 553 ** Grab virtual index [0:11] 554 ** Deposit virt_idx bits into I/O PDIR word 555 */ 556 asm volatile ("lci %%r0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 557 asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci)); 558 asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci)); 559 560 ((u32 *)pdir_ptr)[0] = (u32) pa; 561 562 563 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 564 asm volatile("sync"); 565} 566 567static CCIO_INLINE void 568ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt) 569{ 570 u32 chain_size = 1 << ioc->chainid_shift; 571 572 iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */ 573 byte_cnt += chain_size; 574 575 while(byte_cnt > chain_size) { 576 WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command); 577 iovp += chain_size; 578 byte_cnt -= chain_size; 579 } 580} 581 582static CCIO_INLINE void 583ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 584{ 585 u32 iovp = (u32)CCIO_IOVP(iova); 586 size_t saved_byte_cnt; 587 588 /* round up to nearest page size */ 589 saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE); 590 591 while(byte_cnt > 0) { 592 /* invalidate one page at a time */ 593 unsigned int idx = PDIR_INDEX(iovp); 594 char *pdir_ptr = (char *) &(ioc->pdir_base[idx]); 595 596 BUG_ON(idx >= (ioc->pdir_size / sizeof(u64))); 597 pdir_ptr[7] = 0; /* clear only VALID bit */ 598 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr[7])); 599 600 iovp += IOVP_SIZE; 601 byte_cnt -= IOVP_SIZE; 602 } 603 604 asm volatile("sync"); 605 ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt); 606} 607 608/**************************************************************** 609** 610** CCIO dma_ops 611** 612*****************************************************************/ 613 614/** 615 * ccio_dma_supported - Verify the IOMMU supports the DMA address range. 616 * @dev: The PCI device. 617 * @mask: A bit mask describing the DMA address range of the device. 618 * 619 * This function implements the pci_dma_supported function. 620 */ 621static int 622ccio_dma_supported(struct device *dev, u64 mask) 623{ 624 if(dev == NULL) { 625 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 626 BUG(); 627 return 0; 628 } 629 630 /* only support 32-bit devices (ie PCI/GSC) */ 631 return (int)(mask == 0xffffffffUL); 632} 633 634/** 635 * ccio_map_single - Map an address range into the IOMMU. 636 * @dev: The PCI device. 637 * @addr: The start address of the DMA region. 638 * @size: The length of the DMA region. 639 * @direction: The direction of the DMA transaction (to/from device). 640 * 641 * This function implements the pci_map_single function. 642 */ 643static dma_addr_t 644ccio_map_single(struct device *dev, void *addr, size_t size, 645 enum dma_data_direction direction) 646{ 647 int idx; 648 struct ioc *ioc; 649 unsigned long flags; 650 dma_addr_t iovp; 651 dma_addr_t offset; 652 u64 *pdir_start; 653 unsigned long hint = hint_lookup[(int)direction]; 654 655 BUG_ON(!dev); 656 ioc = GET_IOC(dev); 657 658 BUG_ON(size <= 0); 659 660 /* save offset bits */ 661 offset = ((unsigned long) addr) & ~IOVP_MASK; 662 663 /* round up to nearest IOVP_SIZE */ 664 size = ALIGN(size + offset, IOVP_SIZE); 665 spin_lock_irqsave(&ioc->res_lock, flags); 666 667#ifdef CCIO_COLLECT_STATS 668 ioc->msingle_calls++; 669 ioc->msingle_pages += size >> IOVP_SHIFT; 670#endif 671 672 idx = ccio_alloc_range(ioc, dev, size); 673 iovp = (dma_addr_t)MKIOVP(idx); 674 675 pdir_start = &(ioc->pdir_base[idx]); 676 677 DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n", 678 __func__, addr, (long)iovp | offset, size); 679 680 /* If not cacheline aligned, force SAFE_DMA on the whole mess */ 681 if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES)) 682 hint |= HINT_SAFE_DMA; 683 684 while(size > 0) { 685 ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint); 686 687 DBG_RUN(" pdir %p %08x%08x\n", 688 pdir_start, 689 (u32) (((u32 *) pdir_start)[0]), 690 (u32) (((u32 *) pdir_start)[1])); 691 ++pdir_start; 692 addr += IOVP_SIZE; 693 size -= IOVP_SIZE; 694 } 695 696 spin_unlock_irqrestore(&ioc->res_lock, flags); 697 698 /* form complete address */ 699 return CCIO_IOVA(iovp, offset); 700} 701 702/** 703 * ccio_unmap_single - Unmap an address range from the IOMMU. 704 * @dev: The PCI device. 705 * @addr: The start address of the DMA region. 706 * @size: The length of the DMA region. 707 * @direction: The direction of the DMA transaction (to/from device). 708 * 709 * This function implements the pci_unmap_single function. 710 */ 711static void 712ccio_unmap_single(struct device *dev, dma_addr_t iova, size_t size, 713 enum dma_data_direction direction) 714{ 715 struct ioc *ioc; 716 unsigned long flags; 717 dma_addr_t offset = iova & ~IOVP_MASK; 718 719 BUG_ON(!dev); 720 ioc = GET_IOC(dev); 721 722 DBG_RUN("%s() iovp 0x%lx/%x\n", 723 __func__, (long)iova, size); 724 725 iova ^= offset; /* clear offset bits */ 726 size += offset; 727 size = ALIGN(size, IOVP_SIZE); 728 729 spin_lock_irqsave(&ioc->res_lock, flags); 730 731#ifdef CCIO_COLLECT_STATS 732 ioc->usingle_calls++; 733 ioc->usingle_pages += size >> IOVP_SHIFT; 734#endif 735 736 ccio_mark_invalid(ioc, iova, size); 737 ccio_free_range(ioc, iova, (size >> IOVP_SHIFT)); 738 spin_unlock_irqrestore(&ioc->res_lock, flags); 739} 740 741/** 742 * ccio_alloc_consistent - Allocate a consistent DMA mapping. 743 * @dev: The PCI device. 744 * @size: The length of the DMA region. 745 * @dma_handle: The DMA address handed back to the device (not the cpu). 746 * 747 * This function implements the pci_alloc_consistent function. 748 */ 749static void * 750ccio_alloc_consistent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) 751{ 752 void *ret; 753 ret = (void *) __get_free_pages(flag, get_order(size)); 754 755 if (ret) { 756 memset(ret, 0, size); 757 *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL); 758 } 759 760 return ret; 761} 762 763/** 764 * ccio_free_consistent - Free a consistent DMA mapping. 765 * @dev: The PCI device. 766 * @size: The length of the DMA region. 767 * @cpu_addr: The cpu address returned from the ccio_alloc_consistent. 768 * @dma_handle: The device address returned from the ccio_alloc_consistent. 769 * 770 * This function implements the pci_free_consistent function. 771 */ 772static void 773ccio_free_consistent(struct device *dev, size_t size, void *cpu_addr, 774 dma_addr_t dma_handle) 775{ 776 ccio_unmap_single(dev, dma_handle, size, 0); 777 free_pages((unsigned long)cpu_addr, get_order(size)); 778} 779 780/* 781** Since 0 is a valid pdir_base index value, can't use that 782** to determine if a value is valid or not. Use a flag to indicate 783** the SG list entry contains a valid pdir index. 784*/ 785#define PIDE_FLAG 0x80000000UL 786 787#ifdef CCIO_COLLECT_STATS 788#define IOMMU_MAP_STATS 789#endif 790#include "iommu-helpers.h" 791 792/** 793 * ccio_map_sg - Map the scatter/gather list into the IOMMU. 794 * @dev: The PCI device. 795 * @sglist: The scatter/gather list to be mapped in the IOMMU. 796 * @nents: The number of entries in the scatter/gather list. 797 * @direction: The direction of the DMA transaction (to/from device). 798 * 799 * This function implements the pci_map_sg function. 800 */ 801static int 802ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 803 enum dma_data_direction direction) 804{ 805 struct ioc *ioc; 806 int coalesced, filled = 0; 807 unsigned long flags; 808 unsigned long hint = hint_lookup[(int)direction]; 809 unsigned long prev_len = 0, current_len = 0; 810 int i; 811 812 BUG_ON(!dev); 813 ioc = GET_IOC(dev); 814 815 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 816 817 /* Fast path single entry scatterlists. */ 818 if (nents == 1) { 819 sg_dma_address(sglist) = ccio_map_single(dev, 820 (void *)sg_virt_addr(sglist), sglist->length, 821 direction); 822 sg_dma_len(sglist) = sglist->length; 823 return 1; 824 } 825 826 for(i = 0; i < nents; i++) 827 prev_len += sglist[i].length; 828 829 spin_lock_irqsave(&ioc->res_lock, flags); 830 831#ifdef CCIO_COLLECT_STATS 832 ioc->msg_calls++; 833#endif 834 835 /* 836 ** First coalesce the chunks and allocate I/O pdir space 837 ** 838 ** If this is one DMA stream, we can properly map using the 839 ** correct virtual address associated with each DMA page. 840 ** w/o this association, we wouldn't have coherent DMA! 841 ** Access to the virtual address is what forces a two pass algorithm. 842 */ 843 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, ccio_alloc_range); 844 845 /* 846 ** Program the I/O Pdir 847 ** 848 ** map the virtual addresses to the I/O Pdir 849 ** o dma_address will contain the pdir index 850 ** o dma_len will contain the number of bytes to map 851 ** o page/offset contain the virtual address. 852 */ 853 filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry); 854 855 spin_unlock_irqrestore(&ioc->res_lock, flags); 856 857 BUG_ON(coalesced != filled); 858 859 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 860 861 for (i = 0; i < filled; i++) 862 current_len += sg_dma_len(sglist + i); 863 864 BUG_ON(current_len != prev_len); 865 866 return filled; 867} 868 869/** 870 * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU. 871 * @dev: The PCI device. 872 * @sglist: The scatter/gather list to be unmapped from the IOMMU. 873 * @nents: The number of entries in the scatter/gather list. 874 * @direction: The direction of the DMA transaction (to/from device). 875 * 876 * This function implements the pci_unmap_sg function. 877 */ 878static void 879ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 880 enum dma_data_direction direction) 881{ 882 struct ioc *ioc; 883 884 BUG_ON(!dev); 885 ioc = GET_IOC(dev); 886 887 DBG_RUN_SG("%s() START %d entries, %08lx,%x\n", 888 __func__, nents, sg_virt_addr(sglist), sglist->length); 889 890#ifdef CCIO_COLLECT_STATS 891 ioc->usg_calls++; 892#endif 893 894 while(sg_dma_len(sglist) && nents--) { 895 896#ifdef CCIO_COLLECT_STATS 897 ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT; 898#endif 899 ccio_unmap_single(dev, sg_dma_address(sglist), 900 sg_dma_len(sglist), direction); 901 ++sglist; 902 } 903 904 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 905} 906 907static struct hppa_dma_ops ccio_ops = { 908 .dma_supported = ccio_dma_supported, 909 .alloc_consistent = ccio_alloc_consistent, 910 .alloc_noncoherent = ccio_alloc_consistent, 911 .free_consistent = ccio_free_consistent, 912 .map_single = ccio_map_single, 913 .unmap_single = ccio_unmap_single, 914 .map_sg = ccio_map_sg, 915 .unmap_sg = ccio_unmap_sg, 916 .dma_sync_single_for_cpu = NULL, /* NOP for U2/Uturn */ 917 .dma_sync_single_for_device = NULL, /* NOP for U2/Uturn */ 918 .dma_sync_sg_for_cpu = NULL, /* ditto */ 919 .dma_sync_sg_for_device = NULL, /* ditto */ 920}; 921 922#ifdef CONFIG_PROC_FS 923static int ccio_proc_info(struct seq_file *m, void *p) 924{ 925 int len = 0; 926 struct ioc *ioc = ioc_list; 927 928 while (ioc != NULL) { 929 unsigned int total_pages = ioc->res_size << 3; 930#ifdef CCIO_COLLECT_STATS 931 unsigned long avg = 0, min, max; 932 int j; 933#endif 934 935 len += seq_printf(m, "%s\n", ioc->name); 936 937 len += seq_printf(m, "Cujo 2.0 bug : %s\n", 938 (ioc->cujo20_bug ? "yes" : "no")); 939 940 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 941 total_pages * 8, total_pages); 942 943#ifdef CCIO_COLLECT_STATS 944 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 945 total_pages - ioc->used_pages, ioc->used_pages, 946 (int)(ioc->used_pages * 100 / total_pages)); 947#endif 948 949 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 950 ioc->res_size, total_pages); 951 952#ifdef CCIO_COLLECT_STATS 953 min = max = ioc->avg_search[0]; 954 for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) { 955 avg += ioc->avg_search[j]; 956 if(ioc->avg_search[j] > max) 957 max = ioc->avg_search[j]; 958 if(ioc->avg_search[j] < min) 959 min = ioc->avg_search[j]; 960 } 961 avg /= CCIO_SEARCH_SAMPLE; 962 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 963 min, avg, max); 964 965 len += seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n", 966 ioc->msingle_calls, ioc->msingle_pages, 967 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 968 969 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 970 min = ioc->usingle_calls - ioc->usg_calls; 971 max = ioc->usingle_pages - ioc->usg_pages; 972 len += seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n", 973 min, max, (int)((max * 1000)/min)); 974 975 len += seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n", 976 ioc->msg_calls, ioc->msg_pages, 977 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 978 979 len += seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n", 980 ioc->usg_calls, ioc->usg_pages, 981 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 982#endif /* CCIO_COLLECT_STATS */ 983 984 ioc = ioc->next; 985 } 986 987 return 0; 988} 989 990static int ccio_proc_info_open(struct inode *inode, struct file *file) 991{ 992 return single_open(file, &ccio_proc_info, NULL); 993} 994 995static const struct file_operations ccio_proc_info_fops = { 996 .owner = THIS_MODULE, 997 .open = ccio_proc_info_open, 998 .read = seq_read, 999 .llseek = seq_lseek, 1000 .release = single_release, 1001}; 1002 1003static int ccio_proc_bitmap_info(struct seq_file *m, void *p) 1004{ 1005 int len = 0; 1006 struct ioc *ioc = ioc_list; 1007 1008 while (ioc != NULL) { 1009 u32 *res_ptr = (u32 *)ioc->res_map; 1010 int j; 1011 1012 for (j = 0; j < (ioc->res_size / sizeof(u32)); j++) { 1013 if ((j & 7) == 0) 1014 len += seq_puts(m, "\n "); 1015 len += seq_printf(m, "%08x", *res_ptr); 1016 res_ptr++; 1017 } 1018 len += seq_puts(m, "\n\n"); 1019 ioc = ioc->next; 1020 break; 1021 } 1022 1023 return 0; 1024} 1025 1026static int ccio_proc_bitmap_open(struct inode *inode, struct file *file) 1027{ 1028 return single_open(file, &ccio_proc_bitmap_info, NULL); 1029} 1030 1031static const struct file_operations ccio_proc_bitmap_fops = { 1032 .owner = THIS_MODULE, 1033 .open = ccio_proc_bitmap_open, 1034 .read = seq_read, 1035 .llseek = seq_lseek, 1036 .release = single_release, 1037}; 1038#endif /* CONFIG_PROC_FS */ 1039 1040/** 1041 * ccio_find_ioc - Find the ioc in the ioc_list 1042 * @hw_path: The hardware path of the ioc. 1043 * 1044 * This function searches the ioc_list for an ioc that matches 1045 * the provide hardware path. 1046 */ 1047static struct ioc * ccio_find_ioc(int hw_path) 1048{ 1049 int i; 1050 struct ioc *ioc; 1051 1052 ioc = ioc_list; 1053 for (i = 0; i < ioc_count; i++) { 1054 if (ioc->hw_path == hw_path) 1055 return ioc; 1056 1057 ioc = ioc->next; 1058 } 1059 1060 return NULL; 1061} 1062 1063/** 1064 * ccio_get_iommu - Find the iommu which controls this device 1065 * @dev: The parisc device. 1066 * 1067 * This function searches through the registered IOMMU's and returns 1068 * the appropriate IOMMU for the device based on its hardware path. 1069 */ 1070void * ccio_get_iommu(const struct parisc_device *dev) 1071{ 1072 dev = find_pa_parent_type(dev, HPHW_IOA); 1073 if (!dev) 1074 return NULL; 1075 1076 return ccio_find_ioc(dev->hw_path); 1077} 1078 1079#define CUJO_20_STEP 0x10000000 /* inc upper nibble */ 1080 1081/* Cujo 2.0 has a bug which will silently corrupt data being transferred 1082 * to/from certain pages. To avoid this happening, we mark these pages 1083 * as `used', and ensure that nothing will try to allocate from them. 1084 */ 1085void ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp) 1086{ 1087 unsigned int idx; 1088 struct parisc_device *dev = parisc_parent(cujo); 1089 struct ioc *ioc = ccio_get_iommu(dev); 1090 u8 *res_ptr; 1091 1092 ioc->cujo20_bug = 1; 1093 res_ptr = ioc->res_map; 1094 idx = PDIR_INDEX(iovp) >> 3; 1095 1096 while (idx < ioc->res_size) { 1097 res_ptr[idx] |= 0xff; 1098 idx += PDIR_INDEX(CUJO_20_STEP) >> 3; 1099 } 1100} 1101 1102 1103/* Uturn supports 256 TLB entries */ 1104#define CCIO_CHAINID_SHIFT 8 1105#define CCIO_CHAINID_MASK 0xff 1106 1107/* We *can't* support JAVA (T600). Venture there at your own risk. */ 1108static const struct parisc_device_id ccio_tbl[] = { 1109 { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */ 1110 { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */ 1111 { 0, } 1112}; 1113 1114static int ccio_probe(struct parisc_device *dev); 1115 1116static struct parisc_driver ccio_driver = { 1117 .name = "ccio", 1118 .id_table = ccio_tbl, 1119 .probe = ccio_probe, 1120}; 1121 1122/** 1123 * ccio_ioc_init - Initialize the I/O Controller 1124 * @ioc: The I/O Controller. 1125 * 1126 * Initialize the I/O Controller which includes setting up the 1127 * I/O Page Directory, the resource map, and initalizing the 1128 * U2/Uturn chip into virtual mode. 1129 */ 1130static void 1131ccio_ioc_init(struct ioc *ioc) 1132{ 1133 int i; 1134 unsigned int iov_order; 1135 u32 iova_space_size; 1136 1137 /* 1138 ** Determine IOVA Space size from memory size. 1139 ** 1140 ** Ideally, PCI drivers would register the maximum number 1141 ** of DMA they can have outstanding for each device they 1142 ** own. Next best thing would be to guess how much DMA 1143 ** can be outstanding based on PCI Class/sub-class. Both 1144 ** methods still require some "extra" to support PCI 1145 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1146 */ 1147 1148 iova_space_size = (u32) (totalram_pages / count_parisc_driver(&ccio_driver)); 1149 1150 /* limit IOVA space size to 1MB-1GB */ 1151 1152 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1153 iova_space_size = 1 << (20 - PAGE_SHIFT); 1154#ifdef __LP64__ 1155 } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1156 iova_space_size = 1 << (30 - PAGE_SHIFT); 1157#endif 1158 } 1159 1160 /* 1161 ** iova space must be log2() in size. 1162 ** thus, pdir/res_map will also be log2(). 1163 */ 1164 1165 /* We could use larger page sizes in order to *decrease* the number 1166 ** of mappings needed. (ie 8k pages means 1/2 the mappings). 1167 ** 1168 ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either 1169 ** since the pages must also be physically contiguous - typically 1170 ** this is the case under linux." 1171 */ 1172 1173 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1174 1175 /* iova_space_size is now bytes, not pages */ 1176 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1177 1178 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1179 1180 BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */ 1181 1182 /* Verify it's a power of two */ 1183 BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT)); 1184 1185 DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n", 1186 __func__, ioc->ioc_regs, 1187 (unsigned long) totalram_pages >> (20 - PAGE_SHIFT), 1188 iova_space_size>>20, 1189 iov_order + PAGE_SHIFT); 1190 1191 ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL, 1192 get_order(ioc->pdir_size)); 1193 if(NULL == ioc->pdir_base) { 1194 panic("%s() could not allocate I/O Page Table\n", __func__); 1195 } 1196 memset(ioc->pdir_base, 0, ioc->pdir_size); 1197 1198 BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base); 1199 DBG_INIT(" base %p\n", ioc->pdir_base); 1200 1201 /* resource map size dictated by pdir_size */ 1202 ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3; 1203 DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size); 1204 1205 ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL, 1206 get_order(ioc->res_size)); 1207 if(NULL == ioc->res_map) { 1208 panic("%s() could not allocate resource map\n", __func__); 1209 } 1210 memset(ioc->res_map, 0, ioc->res_size); 1211 1212 /* Initialize the res_hint to 16 */ 1213 ioc->res_hint = 16; 1214 1215 /* Initialize the spinlock */ 1216 spin_lock_init(&ioc->res_lock); 1217 1218 /* 1219 ** Chainid is the upper most bits of an IOVP used to determine 1220 ** which TLB entry an IOVP will use. 1221 */ 1222 ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT; 1223 DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift); 1224 1225 /* 1226 ** Initialize IOA hardware 1227 */ 1228 WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift, 1229 &ioc->ioc_regs->io_chain_id_mask); 1230 1231 WRITE_U32(virt_to_phys(ioc->pdir_base), 1232 &ioc->ioc_regs->io_pdir_base); 1233 1234 /* 1235 ** Go to "Virtual Mode" 1236 */ 1237 WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control); 1238 1239 /* 1240 ** Initialize all I/O TLB entries to 0 (Valid bit off). 1241 */ 1242 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m); 1243 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l); 1244 1245 for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) { 1246 WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)), 1247 &ioc->ioc_regs->io_command); 1248 } 1249} 1250 1251static void __init 1252ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr) 1253{ 1254 int result; 1255 1256 res->parent = NULL; 1257 res->flags = IORESOURCE_MEM; 1258 /* 1259 * bracing ((signed) ...) are required for 64bit kernel because 1260 * we only want to sign extend the lower 16 bits of the register. 1261 * The upper 16-bits of range registers are hardcoded to 0xffff. 1262 */ 1263 res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16); 1264 res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1); 1265 res->name = name; 1266 /* 1267 * Check if this MMIO range is disable 1268 */ 1269 if (res->end + 1 == res->start) 1270 return; 1271 1272 /* On some platforms (e.g. K-Class), we have already registered 1273 * resources for devices reported by firmware. Some are children 1274 * of ccio. 1275 * "insert" ccio ranges in the mmio hierarchy (/proc/iomem). 1276 */ 1277 result = insert_resource(&iomem_resource, res); 1278 if (result < 0) { 1279 printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n", 1280 __func__, (unsigned long)res->start, (unsigned long)res->end); 1281 } 1282} 1283 1284static void __init ccio_init_resources(struct ioc *ioc) 1285{ 1286 struct resource *res = ioc->mmio_region; 1287 char *name = kmalloc(14, GFP_KERNEL); 1288 1289 snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); 1290 1291 ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); 1292 ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); 1293} 1294 1295static int new_ioc_area(struct resource *res, unsigned long size, 1296 unsigned long min, unsigned long max, unsigned long align) 1297{ 1298 if (max <= min) 1299 return -EBUSY; 1300 1301 res->start = (max - size + 1) &~ (align - 1); 1302 res->end = res->start + size; 1303 1304 /* We might be trying to expand the MMIO range to include 1305 * a child device that has already registered it's MMIO space. 1306 * Use "insert" instead of request_resource(). 1307 */ 1308 if (!insert_resource(&iomem_resource, res)) 1309 return 0; 1310 1311 return new_ioc_area(res, size, min, max - size, align); 1312} 1313 1314static int expand_ioc_area(struct resource *res, unsigned long size, 1315 unsigned long min, unsigned long max, unsigned long align) 1316{ 1317 unsigned long start, len; 1318 1319 if (!res->parent) 1320 return new_ioc_area(res, size, min, max, align); 1321 1322 start = (res->start - size) &~ (align - 1); 1323 len = res->end - start + 1; 1324 if (start >= min) { 1325 if (!adjust_resource(res, start, len)) 1326 return 0; 1327 } 1328 1329 start = res->start; 1330 len = ((size + res->end + align) &~ (align - 1)) - start; 1331 if (start + len <= max) { 1332 if (!adjust_resource(res, start, len)) 1333 return 0; 1334 } 1335 1336 return -EBUSY; 1337} 1338 1339/* 1340 * Dino calls this function. Beware that we may get called on systems 1341 * which have no IOC (725, B180, C160L, etc) but do have a Dino. 1342 * So it's legal to find no parent IOC. 1343 * 1344 * Some other issues: one of the resources in the ioc may be unassigned. 1345 */ 1346int ccio_allocate_resource(const struct parisc_device *dev, 1347 struct resource *res, unsigned long size, 1348 unsigned long min, unsigned long max, unsigned long align) 1349{ 1350 struct resource *parent = &iomem_resource; 1351 struct ioc *ioc = ccio_get_iommu(dev); 1352 if (!ioc) 1353 goto out; 1354 1355 parent = ioc->mmio_region; 1356 if (parent->parent && 1357 !allocate_resource(parent, res, size, min, max, align, NULL, NULL)) 1358 return 0; 1359 1360 if ((parent + 1)->parent && 1361 !allocate_resource(parent + 1, res, size, min, max, align, 1362 NULL, NULL)) 1363 return 0; 1364 1365 if (!expand_ioc_area(parent, size, min, max, align)) { 1366 __raw_writel(((parent->start)>>16) | 0xffff0000, 1367 &ioc->ioc_regs->io_io_low); 1368 __raw_writel(((parent->end)>>16) | 0xffff0000, 1369 &ioc->ioc_regs->io_io_high); 1370 } else if (!expand_ioc_area(parent + 1, size, min, max, align)) { 1371 parent++; 1372 __raw_writel(((parent->start)>>16) | 0xffff0000, 1373 &ioc->ioc_regs->io_io_low_hv); 1374 __raw_writel(((parent->end)>>16) | 0xffff0000, 1375 &ioc->ioc_regs->io_io_high_hv); 1376 } else { 1377 return -EBUSY; 1378 } 1379 1380 out: 1381 return allocate_resource(parent, res, size, min, max, align, NULL,NULL); 1382} 1383 1384int ccio_request_resource(const struct parisc_device *dev, 1385 struct resource *res) 1386{ 1387 struct resource *parent; 1388 struct ioc *ioc = ccio_get_iommu(dev); 1389 1390 if (!ioc) { 1391 parent = &iomem_resource; 1392 } else if ((ioc->mmio_region->start <= res->start) && 1393 (res->end <= ioc->mmio_region->end)) { 1394 parent = ioc->mmio_region; 1395 } else if (((ioc->mmio_region + 1)->start <= res->start) && 1396 (res->end <= (ioc->mmio_region + 1)->end)) { 1397 parent = ioc->mmio_region + 1; 1398 } else { 1399 return -EBUSY; 1400 } 1401 1402 /* "transparent" bus bridges need to register MMIO resources 1403 * firmware assigned them. e.g. children of hppb.c (e.g. K-class) 1404 * registered their resources in the PDC "bus walk" (See 1405 * arch/parisc/kernel/inventory.c). 1406 */ 1407 return insert_resource(parent, res); 1408} 1409 1410/** 1411 * ccio_probe - Determine if ccio should claim this device. 1412 * @dev: The device which has been found 1413 * 1414 * Determine if ccio should claim this chip (return 0) or not (return 1). 1415 * If so, initialize the chip and tell other partners in crime they 1416 * have work to do. 1417 */ 1418static int __init ccio_probe(struct parisc_device *dev) 1419{ 1420 int i; 1421 struct ioc *ioc, **ioc_p = &ioc_list; 1422 1423 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL); 1424 if (ioc == NULL) { 1425 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n"); 1426 return 1; 1427 } 1428 1429 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn"; 1430 1431 printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name, 1432 (unsigned long)dev->hpa.start); 1433 1434 for (i = 0; i < ioc_count; i++) { 1435 ioc_p = &(*ioc_p)->next; 1436 } 1437 *ioc_p = ioc; 1438 1439 ioc->hw_path = dev->hw_path; 1440 ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096); 1441 ccio_ioc_init(ioc); 1442 ccio_init_resources(ioc); 1443 hppa_dma_ops = &ccio_ops; 1444 dev->dev.platform_data = kzalloc(sizeof(struct pci_hba_data), GFP_KERNEL); 1445 1446 /* if this fails, no I/O cards will work, so may as well bug */ 1447 BUG_ON(dev->dev.platform_data == NULL); 1448 HBA_DATA(dev->dev.platform_data)->iommu = ioc; 1449 1450#ifdef CONFIG_PROC_FS 1451 if (ioc_count == 0) { 1452 proc_create(MODULE_NAME, 0, proc_runway_root, 1453 &ccio_proc_info_fops); 1454 proc_create(MODULE_NAME"-bitmap", 0, proc_runway_root, 1455 &ccio_proc_bitmap_fops); 1456 } 1457#endif 1458 ioc_count++; 1459 1460 parisc_has_iommu(); 1461 return 0; 1462} 1463 1464/** 1465 * ccio_init - ccio initialization procedure. 1466 * 1467 * Register this driver. 1468 */ 1469void __init ccio_init(void) 1470{ 1471 register_parisc_driver(&ccio_driver); 1472} 1473