1/* 2 * This file is part of wl1251 3 * 4 * Copyright (c) 1998-2007 Texas Instruments Incorporated 5 * Copyright (C) 2008 Nokia Corporation 6 * 7 * Contact: Kalle Valo <kalle.valo@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 */ 24 25#ifndef __WL1251_ACX_H__ 26#define __WL1251_ACX_H__ 27 28#include "wl1251.h" 29#include "wl1251_cmd.h" 30 31/* Target's information element */ 32struct acx_header { 33 struct wl1251_cmd_header cmd; 34 35 /* acx (or information element) header */ 36 u16 id; 37 38 /* payload length (not including headers */ 39 u16 len; 40}; 41 42struct acx_error_counter { 43 struct acx_header header; 44 45 /* The number of PLCP errors since the last time this */ 46 /* information element was interrogated. This field is */ 47 /* automatically cleared when it is interrogated.*/ 48 u32 PLCP_error; 49 50 /* The number of FCS errors since the last time this */ 51 /* information element was interrogated. This field is */ 52 /* automatically cleared when it is interrogated.*/ 53 u32 FCS_error; 54 55 /* The number of MPDUs without PLCP header errors received*/ 56 /* since the last time this information element was interrogated. */ 57 /* This field is automatically cleared when it is interrogated.*/ 58 u32 valid_frame; 59 60 /* the number of missed sequence numbers in the squentially */ 61 /* values of frames seq numbers */ 62 u32 seq_num_miss; 63} __packed; 64 65struct acx_revision { 66 struct acx_header header; 67 68 /* 69 * The WiLink firmware version, an ASCII string x.x.x.x, 70 * that uniquely identifies the current firmware. 71 * The left most digit is incremented each time a 72 * significant change is made to the firmware, such as 73 * code redesign or new platform support. 74 * The second digit is incremented when major enhancements 75 * are added or major fixes are made. 76 * The third digit is incremented for each GA release. 77 * The fourth digit is incremented for each build. 78 * The first two digits identify a firmware release version, 79 * in other words, a unique set of features. 80 * The first three digits identify a GA release. 81 */ 82 char fw_version[20]; 83 84 /* 85 * This 4 byte field specifies the WiLink hardware version. 86 * bits 0 - 15: Reserved. 87 * bits 16 - 23: Version ID - The WiLink version ID 88 * (1 = first spin, 2 = second spin, and so on). 89 * bits 24 - 31: Chip ID - The WiLink chip ID. 90 */ 91 u32 hw_version; 92} __packed; 93 94enum wl1251_psm_mode { 95 /* Active mode */ 96 WL1251_PSM_CAM = 0, 97 98 /* Power save mode */ 99 WL1251_PSM_PS = 1, 100 101 /* Extreme low power */ 102 WL1251_PSM_ELP = 2, 103}; 104 105struct acx_sleep_auth { 106 struct acx_header header; 107 108 /* The sleep level authorization of the device. */ 109 /* 0 - Always active*/ 110 /* 1 - Power down mode: light / fast sleep*/ 111 /* 2 - ELP mode: Deep / Max sleep*/ 112 u8 sleep_auth; 113 u8 padding[3]; 114} __packed; 115 116enum { 117 HOSTIF_PCI_MASTER_HOST_INDIRECT, 118 HOSTIF_PCI_MASTER_HOST_DIRECT, 119 HOSTIF_SLAVE, 120 HOSTIF_PKT_RING, 121 HOSTIF_DONTCARE = 0xFF 122}; 123 124#define DEFAULT_UCAST_PRIORITY 0 125#define DEFAULT_RX_Q_PRIORITY 0 126#define DEFAULT_NUM_STATIONS 1 127#define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ 128#define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ 129#define TRACE_BUFFER_MAX_SIZE 256 130 131#define DP_RX_PACKET_RING_CHUNK_SIZE 1600 132#define DP_TX_PACKET_RING_CHUNK_SIZE 1600 133#define DP_RX_PACKET_RING_CHUNK_NUM 2 134#define DP_TX_PACKET_RING_CHUNK_NUM 2 135#define DP_TX_COMPLETE_TIME_OUT 20 136#define FW_TX_CMPLT_BLOCK_SIZE 16 137 138struct acx_data_path_params { 139 struct acx_header header; 140 141 u16 rx_packet_ring_chunk_size; 142 u16 tx_packet_ring_chunk_size; 143 144 u8 rx_packet_ring_chunk_num; 145 u8 tx_packet_ring_chunk_num; 146 147 /* 148 * Maximum number of packets that can be gathered 149 * in the TX complete ring before an interrupt 150 * is generated. 151 */ 152 u8 tx_complete_threshold; 153 154 /* Number of pending TX complete entries in cyclic ring.*/ 155 u8 tx_complete_ring_depth; 156 157 /* 158 * Max num microseconds since a packet enters the TX 159 * complete ring until an interrupt is generated. 160 */ 161 u32 tx_complete_timeout; 162} __packed; 163 164 165struct acx_data_path_params_resp { 166 struct acx_header header; 167 168 u16 rx_packet_ring_chunk_size; 169 u16 tx_packet_ring_chunk_size; 170 171 u8 rx_packet_ring_chunk_num; 172 u8 tx_packet_ring_chunk_num; 173 174 u8 pad[2]; 175 176 u32 rx_packet_ring_addr; 177 u32 tx_packet_ring_addr; 178 179 u32 rx_control_addr; 180 u32 tx_control_addr; 181 182 u32 tx_complete_addr; 183} __packed; 184 185#define TX_MSDU_LIFETIME_MIN 0 186#define TX_MSDU_LIFETIME_MAX 3000 187#define TX_MSDU_LIFETIME_DEF 512 188#define RX_MSDU_LIFETIME_MIN 0 189#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF 190#define RX_MSDU_LIFETIME_DEF 512000 191 192struct acx_rx_msdu_lifetime { 193 struct acx_header header; 194 195 /* 196 * The maximum amount of time, in TU, before the 197 * firmware discards the MSDU. 198 */ 199 u32 lifetime; 200} __packed; 201 202/* 203 * RX Config Options Table 204 * Bit Definition 205 * === ========== 206 * 31:14 Reserved 207 * 13 Copy RX Status - when set, write three receive status words 208 * to top of rx'd MPDUs. 209 * When cleared, do not write three status words (added rev 1.5) 210 * 12 Reserved 211 * 11 RX Complete upon FCS error - when set, give rx complete 212 * interrupt for FCS errors, after the rx filtering, e.g. unicast 213 * frames not to us with FCS error will not generate an interrupt. 214 * 10 SSID Filter Enable - When set, the WiLink discards all beacon, 215 * probe request, and probe response frames with an SSID that does 216 * not match the SSID specified by the host in the START/JOIN 217 * command. 218 * When clear, the WiLink receives frames with any SSID. 219 * 9 Broadcast Filter Enable - When set, the WiLink discards all 220 * broadcast frames. When clear, the WiLink receives all received 221 * broadcast frames. 222 * 8:6 Reserved 223 * 5 BSSID Filter Enable - When set, the WiLink discards any frames 224 * with a BSSID that does not match the BSSID specified by the 225 * host. 226 * When clear, the WiLink receives frames from any BSSID. 227 * 4 MAC Addr Filter - When set, the WiLink discards any frames 228 * with a destination address that does not match the MAC address 229 * of the adaptor. 230 * When clear, the WiLink receives frames destined to any MAC 231 * address. 232 * 3 Promiscuous - When set, the WiLink receives all valid frames 233 * (i.e., all frames that pass the FCS check). 234 * When clear, only frames that pass the other filters specified 235 * are received. 236 * 2 FCS - When set, the WiLink includes the FCS with the received 237 * frame. 238 * When cleared, the FCS is discarded. 239 * 1 PLCP header - When set, write all data from baseband to frame 240 * buffer including PHY header. 241 * 0 Reserved - Always equal to 0. 242 * 243 * RX Filter Options Table 244 * Bit Definition 245 * === ========== 246 * 31:12 Reserved - Always equal to 0. 247 * 11 Association - When set, the WiLink receives all association 248 * related frames (association request/response, reassocation 249 * request/response, and disassociation). When clear, these frames 250 * are discarded. 251 * 10 Auth/De auth - When set, the WiLink receives all authentication 252 * and de-authentication frames. When clear, these frames are 253 * discarded. 254 * 9 Beacon - When set, the WiLink receives all beacon frames. 255 * When clear, these frames are discarded. 256 * 8 Contention Free - When set, the WiLink receives all contention 257 * free frames. 258 * When clear, these frames are discarded. 259 * 7 Control - When set, the WiLink receives all control frames. 260 * When clear, these frames are discarded. 261 * 6 Data - When set, the WiLink receives all data frames. 262 * When clear, these frames are discarded. 263 * 5 FCS Error - When set, the WiLink receives frames that have FCS 264 * errors. 265 * When clear, these frames are discarded. 266 * 4 Management - When set, the WiLink receives all management 267 * frames. 268 * When clear, these frames are discarded. 269 * 3 Probe Request - When set, the WiLink receives all probe request 270 * frames. 271 * When clear, these frames are discarded. 272 * 2 Probe Response - When set, the WiLink receives all probe 273 * response frames. 274 * When clear, these frames are discarded. 275 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK 276 * frames. 277 * When clear, these frames are discarded. 278 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames 279 * that have reserved frame types and sub types as defined by the 280 * 802.11 specification. 281 * When clear, these frames are discarded. 282 */ 283struct acx_rx_config { 284 struct acx_header header; 285 286 u32 config_options; 287 u32 filter_options; 288} __packed; 289 290enum { 291 QOS_AC_BE = 0, 292 QOS_AC_BK, 293 QOS_AC_VI, 294 QOS_AC_VO, 295 QOS_HIGHEST_AC_INDEX = QOS_AC_VO, 296}; 297 298#define MAX_NUM_OF_AC (QOS_HIGHEST_AC_INDEX+1) 299#define FIRST_AC_INDEX QOS_AC_BE 300#define MAX_NUM_OF_802_1d_TAGS 8 301#define AC_PARAMS_MAX_TSID 15 302#define MAX_APSD_CONF 0xffff 303 304#define QOS_TX_HIGH_MIN (0) 305#define QOS_TX_HIGH_MAX (100) 306 307#define QOS_TX_HIGH_BK_DEF (25) 308#define QOS_TX_HIGH_BE_DEF (35) 309#define QOS_TX_HIGH_VI_DEF (35) 310#define QOS_TX_HIGH_VO_DEF (35) 311 312#define QOS_TX_LOW_BK_DEF (15) 313#define QOS_TX_LOW_BE_DEF (25) 314#define QOS_TX_LOW_VI_DEF (25) 315#define QOS_TX_LOW_VO_DEF (25) 316 317struct acx_tx_queue_qos_config { 318 struct acx_header header; 319 320 u8 qid; 321 u8 pad[3]; 322 323 /* Max number of blocks allowd in the queue */ 324 u16 high_threshold; 325 326 /* Lowest memory blocks guaranteed for this queue */ 327 u16 low_threshold; 328} __packed; 329 330struct acx_packet_detection { 331 struct acx_header header; 332 333 u32 threshold; 334} __packed; 335 336 337enum acx_slot_type { 338 SLOT_TIME_LONG = 0, 339 SLOT_TIME_SHORT = 1, 340 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, 341 MAX_SLOT_TIMES = 0xFF 342}; 343 344#define STATION_WONE_INDEX 0 345 346struct acx_slot { 347 struct acx_header header; 348 349 u8 wone_index; /* Reserved */ 350 u8 slot_time; 351 u8 reserved[6]; 352} __packed; 353 354 355#define ADDRESS_GROUP_MAX (8) 356#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ADDRESS_GROUP_MAX) 357 358struct acx_dot11_grp_addr_tbl { 359 struct acx_header header; 360 361 u8 enabled; 362 u8 num_groups; 363 u8 pad[2]; 364 u8 mac_table[ADDRESS_GROUP_MAX_LEN]; 365} __packed; 366 367 368#define RX_TIMEOUT_PS_POLL_MIN 0 369#define RX_TIMEOUT_PS_POLL_MAX (200000) 370#define RX_TIMEOUT_PS_POLL_DEF (15) 371#define RX_TIMEOUT_UPSD_MIN 0 372#define RX_TIMEOUT_UPSD_MAX (200000) 373#define RX_TIMEOUT_UPSD_DEF (15) 374 375struct acx_rx_timeout { 376 struct acx_header header; 377 378 /* 379 * The longest time the STA will wait to receive 380 * traffic from the AP after a PS-poll has been 381 * transmitted. 382 */ 383 u16 ps_poll_timeout; 384 385 /* 386 * The longest time the STA will wait to receive 387 * traffic from the AP after a frame has been sent 388 * from an UPSD enabled queue. 389 */ 390 u16 upsd_timeout; 391} __packed; 392 393#define RTS_THRESHOLD_MIN 0 394#define RTS_THRESHOLD_MAX 4096 395#define RTS_THRESHOLD_DEF 2347 396 397struct acx_rts_threshold { 398 struct acx_header header; 399 400 u16 threshold; 401 u8 pad[2]; 402} __packed; 403 404struct acx_beacon_filter_option { 405 struct acx_header header; 406 407 u8 enable; 408 409 /* 410 * The number of beacons without the unicast TIM 411 * bit set that the firmware buffers before 412 * signaling the host about ready frames. 413 * When set to 0 and the filter is enabled, beacons 414 * without the unicast TIM bit set are dropped. 415 */ 416 u8 max_num_beacons; 417 u8 pad[2]; 418} __packed; 419 420/* 421 * ACXBeaconFilterEntry (not 221) 422 * Byte Offset Size (Bytes) Definition 423 * =========== ============ ========== 424 * 0 1 IE identifier 425 * 1 1 Treatment bit mask 426 * 427 * ACXBeaconFilterEntry (221) 428 * Byte Offset Size (Bytes) Definition 429 * =========== ============ ========== 430 * 0 1 IE identifier 431 * 1 1 Treatment bit mask 432 * 2 3 OUI 433 * 5 1 Type 434 * 6 2 Version 435 * 436 * 437 * Treatment bit mask - The information element handling: 438 * bit 0 - The information element is compared and transferred 439 * in case of change. 440 * bit 1 - The information element is transferred to the host 441 * with each appearance or disappearance. 442 * Note that both bits can be set at the same time. 443 */ 444#define BEACON_FILTER_TABLE_MAX_IE_NUM (32) 445#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) 446#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) 447#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) 448#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ 449 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ 450 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ 451 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) 452 453#define BEACON_RULE_PASS_ON_CHANGE BIT(0) 454#define BEACON_RULE_PASS_ON_APPEARANCE BIT(1) 455 456#define BEACON_FILTER_IE_ID_CHANNEL_SWITCH_ANN (37) 457 458struct acx_beacon_filter_ie_table { 459 struct acx_header header; 460 461 u8 num_ie; 462 u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; 463 u8 pad[3]; 464} __packed; 465 466#define SYNCH_FAIL_DEFAULT_THRESHOLD 10 /* number of beacons */ 467#define NO_BEACON_DEFAULT_TIMEOUT (500) /* in microseconds */ 468 469struct acx_conn_monit_params { 470 struct acx_header header; 471 472 u32 synch_fail_thold; /* number of beacons missed */ 473 u32 bss_lose_timeout; /* number of TU's from synch fail */ 474}; 475 476enum { 477 SG_ENABLE = 0, 478 SG_DISABLE, 479 SG_SENSE_NO_ACTIVITY, 480 SG_SENSE_ACTIVE 481}; 482 483struct acx_bt_wlan_coex { 484 struct acx_header header; 485 486 /* 487 * 0 -> PTA enabled 488 * 1 -> PTA disabled 489 * 2 -> sense no active mode, i.e. 490 * an interrupt is sent upon 491 * BT activity. 492 * 3 -> PTA is switched on in response 493 * to the interrupt sending. 494 */ 495 u8 enable; 496 u8 pad[3]; 497} __packed; 498 499#define PTA_ANTENNA_TYPE_DEF (0) 500#define PTA_BT_HP_MAXTIME_DEF (2000) 501#define PTA_WLAN_HP_MAX_TIME_DEF (5000) 502#define PTA_SENSE_DISABLE_TIMER_DEF (1350) 503#define PTA_PROTECTIVE_RX_TIME_DEF (1500) 504#define PTA_PROTECTIVE_TX_TIME_DEF (1500) 505#define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000) 506#define PTA_SIGNALING_TYPE_DEF (1) 507#define PTA_AFH_LEVERAGE_ON_DEF (0) 508#define PTA_NUMBER_QUIET_CYCLE_DEF (0) 509#define PTA_MAX_NUM_CTS_DEF (3) 510#define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2) 511#define PTA_NUMBER_OF_BT_PACKETS_DEF (2) 512#define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500) 513#define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000) 514#define PTA_CYCLE_TIME_FAST_DEF (8700) 515#define PTA_RX_FOR_AVALANCHE_DEF (5) 516#define PTA_ELP_HP_DEF (0) 517#define PTA_ANTI_STARVE_PERIOD_DEF (500) 518#define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4) 519#define PTA_ALLOW_PA_SD_DEF (1) 520#define PTA_TIME_BEFORE_BEACON_DEF (6300) 521#define PTA_HPDM_MAX_TIME_DEF (1600) 522#define PTA_TIME_OUT_NEXT_WLAN_DEF (2550) 523#define PTA_AUTO_MODE_NO_CTS_DEF (0) 524#define PTA_BT_HP_RESPECTED_DEF (3) 525#define PTA_WLAN_RX_MIN_RATE_DEF (24) 526#define PTA_ACK_MODE_DEF (1) 527 528struct acx_bt_wlan_coex_param { 529 struct acx_header header; 530 531 /* 532 * The minimum rate of a received WLAN packet in the STA, 533 * during protective mode, of which a new BT-HP request 534 * during this Rx will always be respected and gain the antenna. 535 */ 536 u32 min_rate; 537 538 /* Max time the BT HP will be respected. */ 539 u16 bt_hp_max_time; 540 541 /* Max time the WLAN HP will be respected. */ 542 u16 wlan_hp_max_time; 543 544 /* 545 * The time between the last BT activity 546 * and the moment when the sense mode returns 547 * to SENSE_INACTIVE. 548 */ 549 u16 sense_disable_timer; 550 551 /* Time before the next BT HP instance */ 552 u16 rx_time_bt_hp; 553 u16 tx_time_bt_hp; 554 555 /* range: 10-20000 default: 1500 */ 556 u16 rx_time_bt_hp_fast; 557 u16 tx_time_bt_hp_fast; 558 559 /* range: 2000-65535 default: 8700 */ 560 u16 wlan_cycle_fast; 561 562 /* range: 0 - 15000 (Msec) default: 1000 */ 563 u16 bt_anti_starvation_period; 564 565 /* range 400-10000(Usec) default: 3000 */ 566 u16 next_bt_lp_packet; 567 568 /* Deafult: worst case for BT DH5 traffic */ 569 u16 wake_up_beacon; 570 571 /* range: 0-50000(Usec) default: 1050 */ 572 u16 hp_dm_max_guard_time; 573 574 /* 575 * This is to prevent both BT & WLAN antenna 576 * starvation. 577 * Range: 100-50000(Usec) default:2550 578 */ 579 u16 next_wlan_packet; 580 581 /* 0 -> shared antenna */ 582 u8 antenna_type; 583 584 /* 585 * 0 -> TI legacy 586 * 1 -> Palau 587 */ 588 u8 signal_type; 589 590 /* 591 * BT AFH status 592 * 0 -> no AFH 593 * 1 -> from dedicated GPIO 594 * 2 -> AFH on (from host) 595 */ 596 u8 afh_leverage_on; 597 598 /* 599 * The number of cycles during which no 600 * TX will be sent after 1 cycle of RX 601 * transaction in protective mode 602 */ 603 u8 quiet_cycle_num; 604 605 /* 606 * The maximum number of CTSs that will 607 * be sent for receiving RX packet in 608 * protective mode 609 */ 610 u8 max_cts; 611 612 /* 613 * The number of WLAN packets 614 * transferred in common mode before 615 * switching to BT. 616 */ 617 u8 wlan_packets_num; 618 619 /* 620 * The number of BT packets 621 * transferred in common mode before 622 * switching to WLAN. 623 */ 624 u8 bt_packets_num; 625 626 /* range: 1-255 default: 5 */ 627 u8 missed_rx_avalanche; 628 629 /* range: 0-1 default: 1 */ 630 u8 wlan_elp_hp; 631 632 /* range: 0 - 15 default: 4 */ 633 u8 bt_anti_starvation_cycles; 634 635 u8 ack_mode_dual_ant; 636 637 /* 638 * Allow PA_SD assertion/de-assertion 639 * during enabled BT activity. 640 */ 641 u8 pa_sd_enable; 642 643 /* 644 * Enable/Disable PTA in auto mode: 645 * Support Both Active & P.S modes 646 */ 647 u8 pta_auto_mode_enable; 648 649 /* range: 0 - 20 default: 1 */ 650 u8 bt_hp_respected_num; 651} __packed; 652 653#define CCA_THRSH_ENABLE_ENERGY_D 0x140A 654#define CCA_THRSH_DISABLE_ENERGY_D 0xFFEF 655 656struct acx_energy_detection { 657 struct acx_header header; 658 659 /* The RX Clear Channel Assessment threshold in the PHY */ 660 u16 rx_cca_threshold; 661 u8 tx_energy_detection; 662 u8 pad; 663} __packed; 664 665#define BCN_RX_TIMEOUT_DEF_VALUE 10000 666#define BROADCAST_RX_TIMEOUT_DEF_VALUE 20000 667#define RX_BROADCAST_IN_PS_DEF_VALUE 1 668#define CONSECUTIVE_PS_POLL_FAILURE_DEF 4 669 670struct acx_beacon_broadcast { 671 struct acx_header header; 672 673 u16 beacon_rx_timeout; 674 u16 broadcast_timeout; 675 676 /* Enables receiving of broadcast packets in PS mode */ 677 u8 rx_broadcast_in_ps; 678 679 /* Consecutive PS Poll failures before updating the host */ 680 u8 ps_poll_threshold; 681 u8 pad[2]; 682} __packed; 683 684struct acx_event_mask { 685 struct acx_header header; 686 687 u32 event_mask; 688 u32 high_event_mask; /* Unused */ 689} __packed; 690 691#define CFG_RX_FCS BIT(2) 692#define CFG_RX_ALL_GOOD BIT(3) 693#define CFG_UNI_FILTER_EN BIT(4) 694#define CFG_BSSID_FILTER_EN BIT(5) 695#define CFG_MC_FILTER_EN BIT(6) 696#define CFG_MC_ADDR0_EN BIT(7) 697#define CFG_MC_ADDR1_EN BIT(8) 698#define CFG_BC_REJECT_EN BIT(9) 699#define CFG_SSID_FILTER_EN BIT(10) 700#define CFG_RX_INT_FCS_ERROR BIT(11) 701#define CFG_RX_INT_ENCRYPTED BIT(12) 702#define CFG_RX_WR_RX_STATUS BIT(13) 703#define CFG_RX_FILTER_NULTI BIT(14) 704#define CFG_RX_RESERVE BIT(15) 705#define CFG_RX_TIMESTAMP_TSF BIT(16) 706 707#define CFG_RX_RSV_EN BIT(0) 708#define CFG_RX_RCTS_ACK BIT(1) 709#define CFG_RX_PRSP_EN BIT(2) 710#define CFG_RX_PREQ_EN BIT(3) 711#define CFG_RX_MGMT_EN BIT(4) 712#define CFG_RX_FCS_ERROR BIT(5) 713#define CFG_RX_DATA_EN BIT(6) 714#define CFG_RX_CTL_EN BIT(7) 715#define CFG_RX_CF_EN BIT(8) 716#define CFG_RX_BCN_EN BIT(9) 717#define CFG_RX_AUTH_EN BIT(10) 718#define CFG_RX_ASSOC_EN BIT(11) 719 720#define SCAN_PASSIVE BIT(0) 721#define SCAN_5GHZ_BAND BIT(1) 722#define SCAN_TRIGGERED BIT(2) 723#define SCAN_PRIORITY_HIGH BIT(3) 724 725struct acx_fw_gen_frame_rates { 726 struct acx_header header; 727 728 u8 tx_ctrl_frame_rate; /* RATE_* */ 729 u8 tx_ctrl_frame_mod; /* CCK_* or PBCC_* */ 730 u8 tx_mgt_frame_rate; 731 u8 tx_mgt_frame_mod; 732} __packed; 733 734/* STA MAC */ 735struct acx_dot11_station_id { 736 struct acx_header header; 737 738 u8 mac[ETH_ALEN]; 739 u8 pad[2]; 740} __packed; 741 742struct acx_feature_config { 743 struct acx_header header; 744 745 u32 options; 746 u32 data_flow_options; 747} __packed; 748 749struct acx_current_tx_power { 750 struct acx_header header; 751 752 u8 current_tx_power; 753 u8 padding[3]; 754} __packed; 755 756struct acx_dot11_default_key { 757 struct acx_header header; 758 759 u8 id; 760 u8 pad[3]; 761} __packed; 762 763struct acx_tsf_info { 764 struct acx_header header; 765 766 u32 current_tsf_msb; 767 u32 current_tsf_lsb; 768 u32 last_TBTT_msb; 769 u32 last_TBTT_lsb; 770 u8 last_dtim_count; 771 u8 pad[3]; 772} __packed; 773 774enum acx_wake_up_event { 775 WAKE_UP_EVENT_BEACON_BITMAP = 0x01, /* Wake on every Beacon*/ 776 WAKE_UP_EVENT_DTIM_BITMAP = 0x02, /* Wake on every DTIM*/ 777 WAKE_UP_EVENT_N_DTIM_BITMAP = 0x04, /* Wake on every Nth DTIM */ 778 WAKE_UP_EVENT_N_BEACONS_BITMAP = 0x08, /* Wake on every Nth Beacon */ 779 WAKE_UP_EVENT_BITS_MASK = 0x0F 780}; 781 782struct acx_wake_up_condition { 783 struct acx_header header; 784 785 u8 wake_up_event; /* Only one bit can be set */ 786 u8 listen_interval; 787 u8 pad[2]; 788} __packed; 789 790struct acx_aid { 791 struct acx_header header; 792 793 /* 794 * To be set when associated with an AP. 795 */ 796 u16 aid; 797 u8 pad[2]; 798} __packed; 799 800enum acx_preamble_type { 801 ACX_PREAMBLE_LONG = 0, 802 ACX_PREAMBLE_SHORT = 1 803}; 804 805struct acx_preamble { 806 struct acx_header header; 807 808 /* 809 * When set, the WiLink transmits the frames with a short preamble and 810 * when cleared, the WiLink transmits the frames with a long preamble. 811 */ 812 u8 preamble; 813 u8 padding[3]; 814} __packed; 815 816enum acx_ctsprotect_type { 817 CTSPROTECT_DISABLE = 0, 818 CTSPROTECT_ENABLE = 1 819}; 820 821struct acx_ctsprotect { 822 struct acx_header header; 823 u8 ctsprotect; 824 u8 padding[3]; 825} __packed; 826 827struct acx_tx_statistics { 828 u32 internal_desc_overflow; 829} __packed; 830 831struct acx_rx_statistics { 832 u32 out_of_mem; 833 u32 hdr_overflow; 834 u32 hw_stuck; 835 u32 dropped; 836 u32 fcs_err; 837 u32 xfr_hint_trig; 838 u32 path_reset; 839 u32 reset_counter; 840} __packed; 841 842struct acx_dma_statistics { 843 u32 rx_requested; 844 u32 rx_errors; 845 u32 tx_requested; 846 u32 tx_errors; 847} __packed; 848 849struct acx_isr_statistics { 850 /* host command complete */ 851 u32 cmd_cmplt; 852 853 /* fiqisr() */ 854 u32 fiqs; 855 856 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */ 857 u32 rx_headers; 858 859 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */ 860 u32 rx_completes; 861 862 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */ 863 u32 rx_mem_overflow; 864 865 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */ 866 u32 rx_rdys; 867 868 /* irqisr() */ 869 u32 irqs; 870 871 /* (INT_STS_ND & INT_TRIG_TX_PROC) */ 872 u32 tx_procs; 873 874 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */ 875 u32 decrypt_done; 876 877 /* (INT_STS_ND & INT_TRIG_DMA0) */ 878 u32 dma0_done; 879 880 /* (INT_STS_ND & INT_TRIG_DMA1) */ 881 u32 dma1_done; 882 883 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */ 884 u32 tx_exch_complete; 885 886 /* (INT_STS_ND & INT_TRIG_COMMAND) */ 887 u32 commands; 888 889 /* (INT_STS_ND & INT_TRIG_RX_PROC) */ 890 u32 rx_procs; 891 892 /* (INT_STS_ND & INT_TRIG_PM_802) */ 893 u32 hw_pm_mode_changes; 894 895 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */ 896 u32 host_acknowledges; 897 898 /* (INT_STS_ND & INT_TRIG_PM_PCI) */ 899 u32 pci_pm; 900 901 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */ 902 u32 wakeups; 903 904 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */ 905 u32 low_rssi; 906} __packed; 907 908struct acx_wep_statistics { 909 /* WEP address keys configured */ 910 u32 addr_key_count; 911 912 /* default keys configured */ 913 u32 default_key_count; 914 915 u32 reserved; 916 917 /* number of times that WEP key not found on lookup */ 918 u32 key_not_found; 919 920 /* number of times that WEP key decryption failed */ 921 u32 decrypt_fail; 922 923 /* WEP packets decrypted */ 924 u32 packets; 925 926 /* WEP decrypt interrupts */ 927 u32 interrupt; 928} __packed; 929 930#define ACX_MISSED_BEACONS_SPREAD 10 931 932struct acx_pwr_statistics { 933 /* the amount of enters into power save mode (both PD & ELP) */ 934 u32 ps_enter; 935 936 /* the amount of enters into ELP mode */ 937 u32 elp_enter; 938 939 /* the amount of missing beacon interrupts to the host */ 940 u32 missing_bcns; 941 942 /* the amount of wake on host-access times */ 943 u32 wake_on_host; 944 945 /* the amount of wake on timer-expire */ 946 u32 wake_on_timer_exp; 947 948 /* the number of packets that were transmitted with PS bit set */ 949 u32 tx_with_ps; 950 951 /* the number of packets that were transmitted with PS bit clear */ 952 u32 tx_without_ps; 953 954 /* the number of received beacons */ 955 u32 rcvd_beacons; 956 957 /* the number of entering into PowerOn (power save off) */ 958 u32 power_save_off; 959 960 /* the number of entries into power save mode */ 961 u16 enable_ps; 962 963 /* 964 * the number of exits from power save, not including failed PS 965 * transitions 966 */ 967 u16 disable_ps; 968 969 /* 970 * the number of times the TSF counter was adjusted because 971 * of drift 972 */ 973 u32 fix_tsf_ps; 974 975 /* Gives statistics about the spread continuous missed beacons. 976 * The 16 LSB are dedicated for the PS mode. 977 * The 16 MSB are dedicated for the PS mode. 978 * cont_miss_bcns_spread[0] - single missed beacon. 979 * cont_miss_bcns_spread[1] - two continuous missed beacons. 980 * cont_miss_bcns_spread[2] - three continuous missed beacons. 981 * ... 982 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons. 983 */ 984 u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD]; 985 986 /* the number of beacons in awake mode */ 987 u32 rcvd_awake_beacons; 988} __packed; 989 990struct acx_mic_statistics { 991 u32 rx_pkts; 992 u32 calc_failure; 993} __packed; 994 995struct acx_aes_statistics { 996 u32 encrypt_fail; 997 u32 decrypt_fail; 998 u32 encrypt_packets; 999 u32 decrypt_packets; 1000 u32 encrypt_interrupt; 1001 u32 decrypt_interrupt; 1002} __packed; 1003 1004struct acx_event_statistics { 1005 u32 heart_beat; 1006 u32 calibration; 1007 u32 rx_mismatch; 1008 u32 rx_mem_empty; 1009 u32 rx_pool; 1010 u32 oom_late; 1011 u32 phy_transmit_error; 1012 u32 tx_stuck; 1013} __packed; 1014 1015struct acx_ps_statistics { 1016 u32 pspoll_timeouts; 1017 u32 upsd_timeouts; 1018 u32 upsd_max_sptime; 1019 u32 upsd_max_apturn; 1020 u32 pspoll_max_apturn; 1021 u32 pspoll_utilization; 1022 u32 upsd_utilization; 1023} __packed; 1024 1025struct acx_rxpipe_statistics { 1026 u32 rx_prep_beacon_drop; 1027 u32 descr_host_int_trig_rx_data; 1028 u32 beacon_buffer_thres_host_int_trig_rx_data; 1029 u32 missed_beacon_host_int_trig_rx_data; 1030 u32 tx_xfr_host_int_trig_rx_data; 1031} __packed; 1032 1033struct acx_statistics { 1034 struct acx_header header; 1035 1036 struct acx_tx_statistics tx; 1037 struct acx_rx_statistics rx; 1038 struct acx_dma_statistics dma; 1039 struct acx_isr_statistics isr; 1040 struct acx_wep_statistics wep; 1041 struct acx_pwr_statistics pwr; 1042 struct acx_aes_statistics aes; 1043 struct acx_mic_statistics mic; 1044 struct acx_event_statistics event; 1045 struct acx_ps_statistics ps; 1046 struct acx_rxpipe_statistics rxpipe; 1047} __packed; 1048 1049#define ACX_MAX_RATE_CLASSES 8 1050#define ACX_RATE_MASK_UNSPECIFIED 0 1051#define ACX_RATE_RETRY_LIMIT 10 1052 1053struct acx_rate_class { 1054 u32 enabled_rates; 1055 u8 short_retry_limit; 1056 u8 long_retry_limit; 1057 u8 aflags; 1058 u8 reserved; 1059}; 1060 1061struct acx_rate_policy { 1062 struct acx_header header; 1063 1064 u32 rate_class_cnt; 1065 struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES]; 1066} __packed; 1067 1068struct wl1251_acx_memory { 1069 __le16 num_stations; /* number of STAs to be supported. */ 1070 u16 reserved_1; 1071 1072 /* 1073 * Nmber of memory buffers for the RX mem pool. 1074 * The actual number may be less if there are 1075 * not enough blocks left for the minimum num 1076 * of TX ones. 1077 */ 1078 u8 rx_mem_block_num; 1079 u8 reserved_2; 1080 u8 num_tx_queues; /* From 1 to 16 */ 1081 u8 host_if_options; /* HOST_IF* */ 1082 u8 tx_min_mem_block_num; 1083 u8 num_ssid_profiles; 1084 __le16 debug_buffer_size; 1085} __packed; 1086 1087 1088#define ACX_RX_DESC_MIN 1 1089#define ACX_RX_DESC_MAX 127 1090#define ACX_RX_DESC_DEF 32 1091struct wl1251_acx_rx_queue_config { 1092 u8 num_descs; 1093 u8 pad; 1094 u8 type; 1095 u8 priority; 1096 __le32 dma_address; 1097} __packed; 1098 1099#define ACX_TX_DESC_MIN 1 1100#define ACX_TX_DESC_MAX 127 1101#define ACX_TX_DESC_DEF 16 1102struct wl1251_acx_tx_queue_config { 1103 u8 num_descs; 1104 u8 pad[2]; 1105 u8 attributes; 1106} __packed; 1107 1108#define MAX_TX_QUEUE_CONFIGS 5 1109#define MAX_TX_QUEUES 4 1110struct wl1251_acx_config_memory { 1111 struct acx_header header; 1112 1113 struct wl1251_acx_memory mem_config; 1114 struct wl1251_acx_rx_queue_config rx_queue_config; 1115 struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS]; 1116} __packed; 1117 1118struct wl1251_acx_mem_map { 1119 struct acx_header header; 1120 1121 void *code_start; 1122 void *code_end; 1123 1124 void *wep_defkey_start; 1125 void *wep_defkey_end; 1126 1127 void *sta_table_start; 1128 void *sta_table_end; 1129 1130 void *packet_template_start; 1131 void *packet_template_end; 1132 1133 void *queue_memory_start; 1134 void *queue_memory_end; 1135 1136 void *packet_memory_pool_start; 1137 void *packet_memory_pool_end; 1138 1139 void *debug_buffer1_start; 1140 void *debug_buffer1_end; 1141 1142 void *debug_buffer2_start; 1143 void *debug_buffer2_end; 1144 1145 /* Number of blocks FW allocated for TX packets */ 1146 u32 num_tx_mem_blocks; 1147 1148 /* Number of blocks FW allocated for RX packets */ 1149 u32 num_rx_mem_blocks; 1150} __packed; 1151 1152 1153struct wl1251_acx_wr_tbtt_and_dtim { 1154 1155 struct acx_header header; 1156 1157 /* Time in TUs between two consecutive beacons */ 1158 u16 tbtt; 1159 1160 /* 1161 * DTIM period 1162 * For BSS: Number of TBTTs in a DTIM period (range: 1-10) 1163 * For IBSS: value shall be set to 1 1164 */ 1165 u8 dtim; 1166 u8 padding; 1167} __packed; 1168 1169struct wl1251_acx_ac_cfg { 1170 struct acx_header header; 1171 1172 /* 1173 * Access Category - The TX queue's access category 1174 * (refer to AccessCategory_enum) 1175 */ 1176 u8 ac; 1177 1178 /* 1179 * The contention window minimum size (in slots) for 1180 * the access class. 1181 */ 1182 u8 cw_min; 1183 1184 /* 1185 * The contention window maximum size (in slots) for 1186 * the access class. 1187 */ 1188 u16 cw_max; 1189 1190 /* The AIF value (in slots) for the access class. */ 1191 u8 aifsn; 1192 1193 u8 reserved; 1194 1195 /* The TX Op Limit (in microseconds) for the access class. */ 1196 u16 txop_limit; 1197} __packed; 1198 1199 1200enum wl1251_acx_channel_type { 1201 CHANNEL_TYPE_DCF = 0, 1202 CHANNEL_TYPE_EDCF = 1, 1203 CHANNEL_TYPE_HCCA = 2, 1204}; 1205 1206enum wl1251_acx_ps_scheme { 1207 /* regular ps: simple sending of packets */ 1208 WL1251_ACX_PS_SCHEME_LEGACY = 0, 1209 1210 /* sending a packet triggers a unscheduled apsd downstream */ 1211 WL1251_ACX_PS_SCHEME_UPSD_TRIGGER = 1, 1212 1213 /* a pspoll packet will be sent before every data packet */ 1214 WL1251_ACX_PS_SCHEME_LEGACY_PSPOLL = 2, 1215 1216 /* scheduled apsd mode */ 1217 WL1251_ACX_PS_SCHEME_SAPSD = 3, 1218}; 1219 1220enum wl1251_acx_ack_policy { 1221 WL1251_ACX_ACK_POLICY_LEGACY = 0, 1222 WL1251_ACX_ACK_POLICY_NO_ACK = 1, 1223 WL1251_ACX_ACK_POLICY_BLOCK = 2, 1224}; 1225 1226struct wl1251_acx_tid_cfg { 1227 struct acx_header header; 1228 1229 /* tx queue id number (0-7) */ 1230 u8 queue; 1231 1232 /* channel access type for the queue, enum wl1251_acx_channel_type */ 1233 u8 type; 1234 1235 /* EDCA: ac index (0-3), HCCA: traffic stream id (8-15) */ 1236 u8 tsid; 1237 1238 /* ps scheme of the specified queue, enum wl1251_acx_ps_scheme */ 1239 u8 ps_scheme; 1240 1241 /* the tx queue ack policy, enum wl1251_acx_ack_policy */ 1242 u8 ack_policy; 1243 1244 u8 padding[3]; 1245 1246 /* not supported */ 1247 u32 apsdconf[2]; 1248} __packed; 1249 1250/************************************************************************* 1251 1252 Host Interrupt Register (WiLink -> Host) 1253 1254**************************************************************************/ 1255 1256/* RX packet is ready in Xfer buffer #0 */ 1257#define WL1251_ACX_INTR_RX0_DATA BIT(0) 1258 1259/* TX result(s) are in the TX complete buffer */ 1260#define WL1251_ACX_INTR_TX_RESULT BIT(1) 1261 1262/* OBSOLETE */ 1263#define WL1251_ACX_INTR_TX_XFR BIT(2) 1264 1265/* RX packet is ready in Xfer buffer #1 */ 1266#define WL1251_ACX_INTR_RX1_DATA BIT(3) 1267 1268/* Event was entered to Event MBOX #A */ 1269#define WL1251_ACX_INTR_EVENT_A BIT(4) 1270 1271/* Event was entered to Event MBOX #B */ 1272#define WL1251_ACX_INTR_EVENT_B BIT(5) 1273 1274/* OBSOLETE */ 1275#define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6) 1276 1277/* Trace meassge on MBOX #A */ 1278#define WL1251_ACX_INTR_TRACE_A BIT(7) 1279 1280/* Trace meassge on MBOX #B */ 1281#define WL1251_ACX_INTR_TRACE_B BIT(8) 1282 1283/* Command processing completion */ 1284#define WL1251_ACX_INTR_CMD_COMPLETE BIT(9) 1285 1286/* Init sequence is done */ 1287#define WL1251_ACX_INTR_INIT_COMPLETE BIT(14) 1288 1289#define WL1251_ACX_INTR_ALL 0xFFFFFFFF 1290 1291enum { 1292 ACX_WAKE_UP_CONDITIONS = 0x0002, 1293 ACX_MEM_CFG = 0x0003, 1294 ACX_SLOT = 0x0004, 1295 ACX_QUEUE_HEAD = 0x0005, /* for MASTER mode only */ 1296 ACX_AC_CFG = 0x0007, 1297 ACX_MEM_MAP = 0x0008, 1298 ACX_AID = 0x000A, 1299 ACX_RADIO_PARAM = 0x000B, /* Not used */ 1300 ACX_CFG = 0x000C, /* Not used */ 1301 ACX_FW_REV = 0x000D, 1302 ACX_MEDIUM_USAGE = 0x000F, 1303 ACX_RX_CFG = 0x0010, 1304 ACX_TX_QUEUE_CFG = 0x0011, 1305 ACX_BSS_IN_PS = 0x0012, /* for AP only */ 1306 ACX_STATISTICS = 0x0013, /* Debug API */ 1307 ACX_FEATURE_CFG = 0x0015, 1308 ACX_MISC_CFG = 0x0017, /* Not used */ 1309 ACX_TID_CFG = 0x001A, 1310 ACX_BEACON_FILTER_OPT = 0x001F, 1311 ACX_LOW_RSSI = 0x0020, 1312 ACX_NOISE_HIST = 0x0021, 1313 ACX_HDK_VERSION = 0x0022, /* ??? */ 1314 ACX_PD_THRESHOLD = 0x0023, 1315 ACX_DATA_PATH_PARAMS = 0x0024, /* WO */ 1316 ACX_DATA_PATH_RESP_PARAMS = 0x0024, /* RO */ 1317 ACX_CCA_THRESHOLD = 0x0025, 1318 ACX_EVENT_MBOX_MASK = 0x0026, 1319#ifdef FW_RUNNING_AS_AP 1320 ACX_DTIM_PERIOD = 0x0027, /* for AP only */ 1321#else 1322 ACX_WR_TBTT_AND_DTIM = 0x0027, /* STA only */ 1323#endif 1324 ACX_ACI_OPTION_CFG = 0x0029, /* OBSOLETE (for 1251)*/ 1325 ACX_GPIO_CFG = 0x002A, /* Not used */ 1326 ACX_GPIO_SET = 0x002B, /* Not used */ 1327 ACX_PM_CFG = 0x002C, /* To Be Documented */ 1328 ACX_CONN_MONIT_PARAMS = 0x002D, 1329 ACX_AVERAGE_RSSI = 0x002E, /* Not used */ 1330 ACX_CONS_TX_FAILURE = 0x002F, 1331 ACX_BCN_DTIM_OPTIONS = 0x0031, 1332 ACX_SG_ENABLE = 0x0032, 1333 ACX_SG_CFG = 0x0033, 1334 ACX_ANTENNA_DIVERSITY_CFG = 0x0035, /* To Be Documented */ 1335 ACX_LOW_SNR = 0x0037, /* To Be Documented */ 1336 ACX_BEACON_FILTER_TABLE = 0x0038, 1337 ACX_ARP_IP_FILTER = 0x0039, 1338 ACX_ROAMING_STATISTICS_TBL = 0x003B, 1339 ACX_RATE_POLICY = 0x003D, 1340 ACX_CTS_PROTECTION = 0x003E, 1341 ACX_SLEEP_AUTH = 0x003F, 1342 ACX_PREAMBLE_TYPE = 0x0040, 1343 ACX_ERROR_CNT = 0x0041, 1344 ACX_FW_GEN_FRAME_RATES = 0x0042, 1345 ACX_IBSS_FILTER = 0x0044, 1346 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045, 1347 ACX_TSF_INFO = 0x0046, 1348 ACX_CONFIG_PS_WMM = 0x0049, 1349 ACX_ENABLE_RX_DATA_FILTER = 0x004A, 1350 ACX_SET_RX_DATA_FILTER = 0x004B, 1351 ACX_GET_DATA_FILTER_STATISTICS = 0x004C, 1352 ACX_POWER_LEVEL_TABLE = 0x004D, 1353 ACX_BET_ENABLE = 0x0050, 1354 DOT11_STATION_ID = 0x1001, 1355 DOT11_RX_MSDU_LIFE_TIME = 0x1004, 1356 DOT11_CUR_TX_PWR = 0x100D, 1357 DOT11_DEFAULT_KEY = 0x1010, 1358 DOT11_RX_DOT11_MODE = 0x1012, 1359 DOT11_RTS_THRESHOLD = 0x1013, 1360 DOT11_GROUP_ADDRESS_TBL = 0x1014, 1361 1362 MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL, 1363 1364 MAX_IE = 0xFFFF 1365}; 1366 1367 1368int wl1251_acx_frame_rates(struct wl1251 *wl, u8 ctrl_rate, u8 ctrl_mod, 1369 u8 mgt_rate, u8 mgt_mod); 1370int wl1251_acx_station_id(struct wl1251 *wl); 1371int wl1251_acx_default_key(struct wl1251 *wl, u8 key_id); 1372int wl1251_acx_wake_up_conditions(struct wl1251 *wl, u8 wake_up_event, 1373 u8 listen_interval); 1374int wl1251_acx_sleep_auth(struct wl1251 *wl, u8 sleep_auth); 1375int wl1251_acx_fw_version(struct wl1251 *wl, char *buf, size_t len); 1376int wl1251_acx_tx_power(struct wl1251 *wl, int power); 1377int wl1251_acx_feature_cfg(struct wl1251 *wl); 1378int wl1251_acx_mem_map(struct wl1251 *wl, 1379 struct acx_header *mem_map, size_t len); 1380int wl1251_acx_data_path_params(struct wl1251 *wl, 1381 struct acx_data_path_params_resp *data_path); 1382int wl1251_acx_rx_msdu_life_time(struct wl1251 *wl, u32 life_time); 1383int wl1251_acx_rx_config(struct wl1251 *wl, u32 config, u32 filter); 1384int wl1251_acx_pd_threshold(struct wl1251 *wl); 1385int wl1251_acx_slot(struct wl1251 *wl, enum acx_slot_type slot_time); 1386int wl1251_acx_group_address_tbl(struct wl1251 *wl); 1387int wl1251_acx_service_period_timeout(struct wl1251 *wl); 1388int wl1251_acx_rts_threshold(struct wl1251 *wl, u16 rts_threshold); 1389int wl1251_acx_beacon_filter_opt(struct wl1251 *wl, bool enable_filter); 1390int wl1251_acx_beacon_filter_table(struct wl1251 *wl); 1391int wl1251_acx_conn_monit_params(struct wl1251 *wl); 1392int wl1251_acx_sg_enable(struct wl1251 *wl); 1393int wl1251_acx_sg_cfg(struct wl1251 *wl); 1394int wl1251_acx_cca_threshold(struct wl1251 *wl); 1395int wl1251_acx_bcn_dtim_options(struct wl1251 *wl); 1396int wl1251_acx_aid(struct wl1251 *wl, u16 aid); 1397int wl1251_acx_event_mbox_mask(struct wl1251 *wl, u32 event_mask); 1398int wl1251_acx_set_preamble(struct wl1251 *wl, enum acx_preamble_type preamble); 1399int wl1251_acx_cts_protect(struct wl1251 *wl, 1400 enum acx_ctsprotect_type ctsprotect); 1401int wl1251_acx_statistics(struct wl1251 *wl, struct acx_statistics *stats); 1402int wl1251_acx_tsf_info(struct wl1251 *wl, u64 *mactime); 1403int wl1251_acx_rate_policies(struct wl1251 *wl); 1404int wl1251_acx_mem_cfg(struct wl1251 *wl); 1405int wl1251_acx_wr_tbtt_and_dtim(struct wl1251 *wl, u16 tbtt, u8 dtim); 1406int wl1251_acx_ac_cfg(struct wl1251 *wl, u8 ac, u8 cw_min, u16 cw_max, 1407 u8 aifs, u16 txop); 1408int wl1251_acx_tid_cfg(struct wl1251 *wl, u8 queue, 1409 enum wl1251_acx_channel_type type, 1410 u8 tsid, enum wl1251_acx_ps_scheme ps_scheme, 1411 enum wl1251_acx_ack_policy ack_policy); 1412 1413#endif /* __WL1251_ACX_H__ */ 1414