1/* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> 10 <http://rt2x00.serialmonkey.com> 11 12 This program is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 2 of the License, or 15 (at your option) any later version. 16 17 This program is distributed in the hope that it will be useful, 18 but WITHOUT ANY WARRANTY; without even the implied warranty of 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 GNU General Public License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; if not, write to the 24 Free Software Foundation, Inc., 25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 26 */ 27 28/* 29 Module: rt2800 30 Abstract: Data structures and registers for the rt2800 modules. 31 Supported chipsets: RT2800E, RT2800ED & RT2800U. 32 */ 33 34#ifndef RT2800_H 35#define RT2800_H 36 37/* 38 * RF chip defines. 39 * 40 * RF2820 2.4G 2T3R 41 * RF2850 2.4G/5G 2T3R 42 * RF2720 2.4G 1T2R 43 * RF2750 2.4G/5G 1T2R 44 * RF3020 2.4G 1T1R 45 * RF2020 2.4G B/G 46 * RF3021 2.4G 1T2R 47 * RF3022 2.4G 2T2R 48 * RF3052 2.4G 2T2R 49 */ 50#define RF2820 0x0001 51#define RF2850 0x0002 52#define RF2720 0x0003 53#define RF2750 0x0004 54#define RF3020 0x0005 55#define RF2020 0x0006 56#define RF3021 0x0007 57#define RF3022 0x0008 58#define RF3052 0x0009 59#define RF3320 0x000b 60 61/* 62 * Chipset revisions. 63 */ 64#define REV_RT2860C 0x0100 65#define REV_RT2860D 0x0101 66#define REV_RT2872E 0x0200 67#define REV_RT3070E 0x0200 68#define REV_RT3070F 0x0201 69#define REV_RT3071E 0x0211 70#define REV_RT3090E 0x0211 71#define REV_RT3390E 0x0211 72 73/* 74 * Signal information. 75 * Default offset is required for RSSI <-> dBm conversion. 76 */ 77#define DEFAULT_RSSI_OFFSET 120 78 79/* 80 * Register layout information. 81 */ 82#define CSR_REG_BASE 0x1000 83#define CSR_REG_SIZE 0x0800 84#define EEPROM_BASE 0x0000 85#define EEPROM_SIZE 0x0110 86#define BBP_BASE 0x0000 87#define BBP_SIZE 0x0080 88#define RF_BASE 0x0004 89#define RF_SIZE 0x0010 90 91/* 92 * Number of TX queues. 93 */ 94#define NUM_TX_QUEUES 4 95 96/* 97 * Registers. 98 */ 99 100/* 101 * E2PROM_CSR: PCI EEPROM control register. 102 * RELOAD: Write 1 to reload eeprom content. 103 * TYPE: 0: 93c46, 1:93c66. 104 * LOAD_STATUS: 1:loading, 0:done. 105 */ 106#define E2PROM_CSR 0x0004 107#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) 108#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) 109#define E2PROM_CSR_DATA_IN FIELD32(0x00000004) 110#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) 111#define E2PROM_CSR_TYPE FIELD32(0x00000030) 112#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) 113#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 114 115/* 116 * OPT_14: Unknown register used by rt3xxx devices. 117 */ 118#define OPT_14_CSR 0x0114 119#define OPT_14_CSR_BIT0 FIELD32(0x00000001) 120 121/* 122 * INT_SOURCE_CSR: Interrupt source register. 123 * Write one to clear corresponding bit. 124 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO 125 */ 126#define INT_SOURCE_CSR 0x0200 127#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) 128#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) 129#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) 130#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) 131#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) 132#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) 133#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) 134#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) 135#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) 136#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) 137#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) 138#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) 139#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) 140#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) 141#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) 142#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) 143#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) 144#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) 145 146/* 147 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. 148 */ 149#define INT_MASK_CSR 0x0204 150#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) 151#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) 152#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) 153#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) 154#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) 155#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) 156#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) 157#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) 158#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) 159#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) 160#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) 161#define INT_MASK_CSR_TBTT FIELD32(0x00000800) 162#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) 163#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) 164#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) 165#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) 166#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) 167#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) 168 169/* 170 * WPDMA_GLO_CFG 171 */ 172#define WPDMA_GLO_CFG 0x0208 173#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) 174#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) 175#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) 176#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) 177#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) 178#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) 179#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) 180#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) 181#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) 182 183/* 184 * WPDMA_RST_IDX 185 */ 186#define WPDMA_RST_IDX 0x020c 187#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) 188#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) 189#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) 190#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) 191#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) 192#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) 193#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) 194 195/* 196 * DELAY_INT_CFG 197 */ 198#define DELAY_INT_CFG 0x0210 199#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) 200#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) 201#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) 202#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) 203#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) 204#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) 205 206/* 207 * WMM_AIFSN_CFG: Aifsn for each EDCA AC 208 * AIFSN0: AC_BE 209 * AIFSN1: AC_BK 210 * AIFSN2: AC_VI 211 * AIFSN3: AC_VO 212 */ 213#define WMM_AIFSN_CFG 0x0214 214#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) 215#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) 216#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) 217#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) 218 219/* 220 * WMM_CWMIN_CSR: CWmin for each EDCA AC 221 * CWMIN0: AC_BE 222 * CWMIN1: AC_BK 223 * CWMIN2: AC_VI 224 * CWMIN3: AC_VO 225 */ 226#define WMM_CWMIN_CFG 0x0218 227#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) 228#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) 229#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) 230#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) 231 232/* 233 * WMM_CWMAX_CSR: CWmax for each EDCA AC 234 * CWMAX0: AC_BE 235 * CWMAX1: AC_BK 236 * CWMAX2: AC_VI 237 * CWMAX3: AC_VO 238 */ 239#define WMM_CWMAX_CFG 0x021c 240#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) 241#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) 242#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) 243#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) 244 245/* 246 * AC_TXOP0: AC_BK/AC_BE TXOP register 247 * AC0TXOP: AC_BK in unit of 32us 248 * AC1TXOP: AC_BE in unit of 32us 249 */ 250#define WMM_TXOP0_CFG 0x0220 251#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) 252#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) 253 254/* 255 * AC_TXOP1: AC_VO/AC_VI TXOP register 256 * AC2TXOP: AC_VI in unit of 32us 257 * AC3TXOP: AC_VO in unit of 32us 258 */ 259#define WMM_TXOP1_CFG 0x0224 260#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) 261#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) 262 263/* 264 * GPIO_CTRL_CFG: 265 */ 266#define GPIO_CTRL_CFG 0x0228 267#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001) 268#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002) 269#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004) 270#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008) 271#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010) 272#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020) 273#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040) 274#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080) 275#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100) 276 277/* 278 * MCU_CMD_CFG 279 */ 280#define MCU_CMD_CFG 0x022c 281 282/* 283 * AC_BK register offsets 284 */ 285#define TX_BASE_PTR0 0x0230 286#define TX_MAX_CNT0 0x0234 287#define TX_CTX_IDX0 0x0238 288#define TX_DTX_IDX0 0x023c 289 290/* 291 * AC_BE register offsets 292 */ 293#define TX_BASE_PTR1 0x0240 294#define TX_MAX_CNT1 0x0244 295#define TX_CTX_IDX1 0x0248 296#define TX_DTX_IDX1 0x024c 297 298/* 299 * AC_VI register offsets 300 */ 301#define TX_BASE_PTR2 0x0250 302#define TX_MAX_CNT2 0x0254 303#define TX_CTX_IDX2 0x0258 304#define TX_DTX_IDX2 0x025c 305 306/* 307 * AC_VO register offsets 308 */ 309#define TX_BASE_PTR3 0x0260 310#define TX_MAX_CNT3 0x0264 311#define TX_CTX_IDX3 0x0268 312#define TX_DTX_IDX3 0x026c 313 314/* 315 * HCCA register offsets 316 */ 317#define TX_BASE_PTR4 0x0270 318#define TX_MAX_CNT4 0x0274 319#define TX_CTX_IDX4 0x0278 320#define TX_DTX_IDX4 0x027c 321 322/* 323 * MGMT register offsets 324 */ 325#define TX_BASE_PTR5 0x0280 326#define TX_MAX_CNT5 0x0284 327#define TX_CTX_IDX5 0x0288 328#define TX_DTX_IDX5 0x028c 329 330/* 331 * RX register offsets 332 */ 333#define RX_BASE_PTR 0x0290 334#define RX_MAX_CNT 0x0294 335#define RX_CRX_IDX 0x0298 336#define RX_DRX_IDX 0x029c 337 338/* 339 * USB_DMA_CFG 340 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. 341 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. 342 * PHY_CLEAR: phy watch dog enable. 343 * TX_CLEAR: Clear USB DMA TX path. 344 * TXOP_HALT: Halt TXOP count down when TX buffer is full. 345 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation. 346 * RX_BULK_EN: Enable USB DMA Rx. 347 * TX_BULK_EN: Enable USB DMA Tx. 348 * EP_OUT_VALID: OUT endpoint data valid. 349 * RX_BUSY: USB DMA RX FSM busy. 350 * TX_BUSY: USB DMA TX FSM busy. 351 */ 352#define USB_DMA_CFG 0x02a0 353#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff) 354#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00) 355#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000) 356#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000) 357#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000) 358#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000) 359#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000) 360#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000) 361#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000) 362#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000) 363#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000) 364 365/* 366 * US_CYC_CNT 367 */ 368#define US_CYC_CNT 0x02a4 369#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) 370 371/* 372 * PBF_SYS_CTRL 373 * HOST_RAM_WRITE: enable Host program ram write selection 374 */ 375#define PBF_SYS_CTRL 0x0400 376#define PBF_SYS_CTRL_READY FIELD32(0x00000080) 377#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) 378 379/* 380 * HOST-MCU shared memory 381 */ 382#define HOST_CMD_CSR 0x0404 383#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) 384 385/* 386 * PBF registers 387 * Most are for debug. Driver doesn't touch PBF register. 388 */ 389#define PBF_CFG 0x0408 390#define PBF_MAX_PCNT 0x040c 391#define PBF_CTRL 0x0410 392#define PBF_INT_STA 0x0414 393#define PBF_INT_ENA 0x0418 394 395/* 396 * BCN_OFFSET0: 397 */ 398#define BCN_OFFSET0 0x042c 399#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) 400#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) 401#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) 402#define BCN_OFFSET0_BCN3 FIELD32(0xff000000) 403 404/* 405 * BCN_OFFSET1: 406 */ 407#define BCN_OFFSET1 0x0430 408#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) 409#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) 410#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) 411#define BCN_OFFSET1_BCN7 FIELD32(0xff000000) 412 413/* 414 * PBF registers 415 * Most are for debug. Driver doesn't touch PBF register. 416 */ 417#define TXRXQ_PCNT 0x0438 418#define PBF_DBG 0x043c 419 420/* 421 * RF registers 422 */ 423#define RF_CSR_CFG 0x0500 424#define RF_CSR_CFG_DATA FIELD32(0x000000ff) 425#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00) 426#define RF_CSR_CFG_WRITE FIELD32(0x00010000) 427#define RF_CSR_CFG_BUSY FIELD32(0x00020000) 428 429/* 430 * EFUSE_CSR: RT30x0 EEPROM 431 */ 432#define EFUSE_CTRL 0x0580 433#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000) 434#define EFUSE_CTRL_MODE FIELD32(0x000000c0) 435#define EFUSE_CTRL_KICK FIELD32(0x40000000) 436#define EFUSE_CTRL_PRESENT FIELD32(0x80000000) 437 438/* 439 * EFUSE_DATA0 440 */ 441#define EFUSE_DATA0 0x0590 442 443/* 444 * EFUSE_DATA1 445 */ 446#define EFUSE_DATA1 0x0594 447 448/* 449 * EFUSE_DATA2 450 */ 451#define EFUSE_DATA2 0x0598 452 453/* 454 * EFUSE_DATA3 455 */ 456#define EFUSE_DATA3 0x059c 457 458/* 459 * LDO_CFG0 460 */ 461#define LDO_CFG0 0x05d4 462#define LDO_CFG0_DELAY3 FIELD32(0x000000ff) 463#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00) 464#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000) 465#define LDO_CFG0_BGSEL FIELD32(0x03000000) 466#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000) 467#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000) 468#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000) 469 470/* 471 * GPIO_SWITCH 472 */ 473#define GPIO_SWITCH 0x05dc 474#define GPIO_SWITCH_0 FIELD32(0x00000001) 475#define GPIO_SWITCH_1 FIELD32(0x00000002) 476#define GPIO_SWITCH_2 FIELD32(0x00000004) 477#define GPIO_SWITCH_3 FIELD32(0x00000008) 478#define GPIO_SWITCH_4 FIELD32(0x00000010) 479#define GPIO_SWITCH_5 FIELD32(0x00000020) 480#define GPIO_SWITCH_6 FIELD32(0x00000040) 481#define GPIO_SWITCH_7 FIELD32(0x00000080) 482 483/* 484 * MAC Control/Status Registers(CSR). 485 * Some values are set in TU, whereas 1 TU == 1024 us. 486 */ 487 488/* 489 * MAC_CSR0: ASIC revision number. 490 * ASIC_REV: 0 491 * ASIC_VER: 2860 or 2870 492 */ 493#define MAC_CSR0 0x1000 494#define MAC_CSR0_REVISION FIELD32(0x0000ffff) 495#define MAC_CSR0_CHIPSET FIELD32(0xffff0000) 496 497/* 498 * MAC_SYS_CTRL: 499 */ 500#define MAC_SYS_CTRL 0x1004 501#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) 502#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) 503#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) 504#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) 505#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) 506#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) 507#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) 508#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) 509 510/* 511 * MAC_ADDR_DW0: STA MAC register 0 512 */ 513#define MAC_ADDR_DW0 0x1008 514#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) 515#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) 516#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) 517#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) 518 519/* 520 * MAC_ADDR_DW1: STA MAC register 1 521 * UNICAST_TO_ME_MASK: 522 * Used to mask off bits from byte 5 of the MAC address 523 * to determine the UNICAST_TO_ME bit for RX frames. 524 * The full mask is complemented by BSS_ID_MASK: 525 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK 526 */ 527#define MAC_ADDR_DW1 0x100c 528#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) 529#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) 530#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) 531 532/* 533 * MAC_BSSID_DW0: BSSID register 0 534 */ 535#define MAC_BSSID_DW0 0x1010 536#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) 537#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) 538#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) 539#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) 540 541/* 542 * MAC_BSSID_DW1: BSSID register 1 543 * BSS_ID_MASK: 544 * 0: 1-BSSID mode (BSS index = 0) 545 * 1: 2-BSSID mode (BSS index: Byte5, bit 0) 546 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) 547 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) 548 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the 549 * BSSID. This will make sure that those bits will be ignored 550 * when determining the MY_BSS of RX frames. 551 */ 552#define MAC_BSSID_DW1 0x1014 553#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) 554#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) 555#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) 556#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) 557 558/* 559 * MAX_LEN_CFG: Maximum frame length register. 560 * MAX_MPDU: rt2860b max 16k bytes 561 * MAX_PSDU: Maximum PSDU length 562 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 563 */ 564#define MAX_LEN_CFG 0x1018 565#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) 566#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) 567#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) 568#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) 569 570/* 571 * BBP_CSR_CFG: BBP serial control register 572 * VALUE: Register value to program into BBP 573 * REG_NUM: Selected BBP register 574 * READ_CONTROL: 0 write BBP, 1 read BBP 575 * BUSY: ASIC is busy executing BBP commands 576 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks 577 * BBP_RW_MODE: 0 serial, 1 paralell 578 */ 579#define BBP_CSR_CFG 0x101c 580#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) 581#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) 582#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) 583#define BBP_CSR_CFG_BUSY FIELD32(0x00020000) 584#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) 585#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) 586 587/* 588 * RF_CSR_CFG0: RF control register 589 * REGID_AND_VALUE: Register value to program into RF 590 * BITWIDTH: Selected RF register 591 * STANDBYMODE: 0 high when standby, 1 low when standby 592 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate 593 * BUSY: ASIC is busy executing RF commands 594 */ 595#define RF_CSR_CFG0 0x1020 596#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) 597#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) 598#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) 599#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) 600#define RF_CSR_CFG0_SEL FIELD32(0x40000000) 601#define RF_CSR_CFG0_BUSY FIELD32(0x80000000) 602 603/* 604 * RF_CSR_CFG1: RF control register 605 * REGID_AND_VALUE: Register value to program into RF 606 * RFGAP: Gap between BB_CONTROL_RF and RF_LE 607 * 0: 3 system clock cycle (37.5usec) 608 * 1: 5 system clock cycle (62.5usec) 609 */ 610#define RF_CSR_CFG1 0x1024 611#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) 612#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) 613 614/* 615 * RF_CSR_CFG2: RF control register 616 * VALUE: Register value to program into RF 617 */ 618#define RF_CSR_CFG2 0x1028 619#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) 620 621/* 622 * LED_CFG: LED control 623 * color LED's: 624 * 0: off 625 * 1: blinking upon TX2 626 * 2: periodic slow blinking 627 * 3: always on 628 * LED polarity: 629 * 0: active low 630 * 1: active high 631 */ 632#define LED_CFG 0x102c 633#define LED_CFG_ON_PERIOD FIELD32(0x000000ff) 634#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) 635#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) 636#define LED_CFG_R_LED_MODE FIELD32(0x03000000) 637#define LED_CFG_G_LED_MODE FIELD32(0x0c000000) 638#define LED_CFG_Y_LED_MODE FIELD32(0x30000000) 639#define LED_CFG_LED_POLAR FIELD32(0x40000000) 640 641/* 642 * XIFS_TIME_CFG: MAC timing 643 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX 644 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX 645 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX 646 * when MAC doesn't reference BBP signal BBRXEND 647 * EIFS: unit 1us 648 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer 649 * 650 */ 651#define XIFS_TIME_CFG 0x1100 652#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) 653#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) 654#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) 655#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) 656#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) 657 658/* 659 * BKOFF_SLOT_CFG: 660 */ 661#define BKOFF_SLOT_CFG 0x1104 662#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) 663#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) 664 665/* 666 * NAV_TIME_CFG: 667 */ 668#define NAV_TIME_CFG 0x1108 669#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) 670#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) 671#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) 672#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) 673 674/* 675 * CH_TIME_CFG: count as channel busy 676 */ 677#define CH_TIME_CFG 0x110c 678 679/* 680 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us 681 */ 682#define PBF_LIFE_TIMER 0x1110 683 684/* 685 * BCN_TIME_CFG: 686 * BEACON_INTERVAL: in unit of 1/16 TU 687 * TSF_TICKING: Enable TSF auto counting 688 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode 689 * BEACON_GEN: Enable beacon generator 690 */ 691#define BCN_TIME_CFG 0x1114 692#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) 693#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) 694#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) 695#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) 696#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) 697#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) 698 699/* 700 * TBTT_SYNC_CFG: 701 */ 702#define TBTT_SYNC_CFG 0x1118 703 704/* 705 * TSF_TIMER_DW0: Local lsb TSF timer, read-only 706 */ 707#define TSF_TIMER_DW0 0x111c 708#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) 709 710/* 711 * TSF_TIMER_DW1: Local msb TSF timer, read-only 712 */ 713#define TSF_TIMER_DW1 0x1120 714#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) 715 716/* 717 * TBTT_TIMER: TImer remains till next TBTT, read-only 718 */ 719#define TBTT_TIMER 0x1124 720 721/* 722 * INT_TIMER_CFG: timer configuration 723 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU 724 * GP_TIMER: period of general purpose timer in units of 1/16 TU 725 */ 726#define INT_TIMER_CFG 0x1128 727#define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff) 728#define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000) 729 730/* 731 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable 732 */ 733#define INT_TIMER_EN 0x112c 734#define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001) 735#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002) 736 737/* 738 * CH_IDLE_STA: channel idle time 739 */ 740#define CH_IDLE_STA 0x1130 741 742/* 743 * CH_BUSY_STA: channel busy time 744 */ 745#define CH_BUSY_STA 0x1134 746 747/* 748 * MAC_STATUS_CFG: 749 * BBP_RF_BUSY: When set to 0, BBP and RF are stable. 750 * if 1 or higher one of the 2 registers is busy. 751 */ 752#define MAC_STATUS_CFG 0x1200 753#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) 754 755/* 756 * PWR_PIN_CFG: 757 */ 758#define PWR_PIN_CFG 0x1204 759 760/* 761 * AUTOWAKEUP_CFG: Manual power control / status register 762 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set 763 * AUTOWAKE: 0:sleep, 1:awake 764 */ 765#define AUTOWAKEUP_CFG 0x1208 766#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) 767#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) 768#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) 769 770/* 771 * EDCA_AC0_CFG: 772 */ 773#define EDCA_AC0_CFG 0x1300 774#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) 775#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) 776#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) 777#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) 778 779/* 780 * EDCA_AC1_CFG: 781 */ 782#define EDCA_AC1_CFG 0x1304 783#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) 784#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) 785#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) 786#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) 787 788/* 789 * EDCA_AC2_CFG: 790 */ 791#define EDCA_AC2_CFG 0x1308 792#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) 793#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) 794#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) 795#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) 796 797/* 798 * EDCA_AC3_CFG: 799 */ 800#define EDCA_AC3_CFG 0x130c 801#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) 802#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) 803#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) 804#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) 805 806/* 807 * EDCA_TID_AC_MAP: 808 */ 809#define EDCA_TID_AC_MAP 0x1310 810 811/* 812 * TX_PWR_CFG: 813 */ 814#define TX_PWR_CFG_RATE0 FIELD32(0x0000000f) 815#define TX_PWR_CFG_RATE1 FIELD32(0x000000f0) 816#define TX_PWR_CFG_RATE2 FIELD32(0x00000f00) 817#define TX_PWR_CFG_RATE3 FIELD32(0x0000f000) 818#define TX_PWR_CFG_RATE4 FIELD32(0x000f0000) 819#define TX_PWR_CFG_RATE5 FIELD32(0x00f00000) 820#define TX_PWR_CFG_RATE6 FIELD32(0x0f000000) 821#define TX_PWR_CFG_RATE7 FIELD32(0xf0000000) 822 823/* 824 * TX_PWR_CFG_0: 825 */ 826#define TX_PWR_CFG_0 0x1314 827#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) 828#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) 829#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) 830#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) 831#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) 832#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) 833#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) 834#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) 835 836/* 837 * TX_PWR_CFG_1: 838 */ 839#define TX_PWR_CFG_1 0x1318 840#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) 841#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) 842#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) 843#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) 844#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) 845#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) 846#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) 847#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) 848 849/* 850 * TX_PWR_CFG_2: 851 */ 852#define TX_PWR_CFG_2 0x131c 853#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) 854#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) 855#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) 856#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) 857#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) 858#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) 859#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) 860#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) 861 862/* 863 * TX_PWR_CFG_3: 864 */ 865#define TX_PWR_CFG_3 0x1320 866#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) 867#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) 868#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) 869#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) 870#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000) 871#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000) 872#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000) 873#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000) 874 875/* 876 * TX_PWR_CFG_4: 877 */ 878#define TX_PWR_CFG_4 0x1324 879#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f) 880#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0) 881#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00) 882#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000) 883 884/* 885 * TX_PIN_CFG: 886 */ 887#define TX_PIN_CFG 0x1328 888#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) 889#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) 890#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) 891#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) 892#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) 893#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) 894#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) 895#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) 896#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) 897#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) 898#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) 899#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) 900#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) 901#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) 902#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) 903#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) 904#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) 905#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) 906#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) 907#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) 908 909/* 910 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz 911 */ 912#define TX_BAND_CFG 0x132c 913#define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001) 914#define TX_BAND_CFG_A FIELD32(0x00000002) 915#define TX_BAND_CFG_BG FIELD32(0x00000004) 916 917/* 918 * TX_SW_CFG0: 919 */ 920#define TX_SW_CFG0 0x1330 921 922/* 923 * TX_SW_CFG1: 924 */ 925#define TX_SW_CFG1 0x1334 926 927/* 928 * TX_SW_CFG2: 929 */ 930#define TX_SW_CFG2 0x1338 931 932/* 933 * TXOP_THRES_CFG: 934 */ 935#define TXOP_THRES_CFG 0x133c 936 937/* 938 * TXOP_CTRL_CFG: 939 */ 940#define TXOP_CTRL_CFG 0x1340 941 942/* 943 * TX_RTS_CFG: 944 * RTS_THRES: unit:byte 945 * RTS_FBK_EN: enable rts rate fallback 946 */ 947#define TX_RTS_CFG 0x1344 948#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) 949#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) 950#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) 951 952/* 953 * TX_TIMEOUT_CFG: 954 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us 955 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure 956 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. 957 * it is recommended that: 958 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) 959 */ 960#define TX_TIMEOUT_CFG 0x1348 961#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) 962#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) 963#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) 964 965/* 966 * TX_RTY_CFG: 967 * SHORT_RTY_LIMIT: short retry limit 968 * LONG_RTY_LIMIT: long retry limit 969 * LONG_RTY_THRE: Long retry threshoold 970 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode 971 * 0:expired by retry limit, 1: expired by mpdu life timer 972 * AGG_RTY_MODE: Aggregate MPDU retry mode 973 * 0:expired by retry limit, 1: expired by mpdu life timer 974 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable 975 */ 976#define TX_RTY_CFG 0x134c 977#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) 978#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) 979#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) 980#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) 981#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) 982#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) 983 984/* 985 * TX_LINK_CFG: 986 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us 987 * MFB_ENABLE: TX apply remote MFB 1:enable 988 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable 989 * 0: not apply remote remote unsolicit (MFS=7) 990 * TX_MRQ_EN: MCS request TX enable 991 * TX_RDG_EN: RDG TX enable 992 * TX_CF_ACK_EN: Piggyback CF-ACK enable 993 * REMOTE_MFB: remote MCS feedback 994 * REMOTE_MFS: remote MCS feedback sequence number 995 */ 996#define TX_LINK_CFG 0x1350 997#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) 998#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) 999#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) 1000#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) 1001#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) 1002#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) 1003#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) 1004#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) 1005 1006/* 1007 * HT_FBK_CFG0: 1008 */ 1009#define HT_FBK_CFG0 0x1354 1010#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) 1011#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) 1012#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) 1013#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) 1014#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) 1015#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) 1016#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) 1017#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) 1018 1019/* 1020 * HT_FBK_CFG1: 1021 */ 1022#define HT_FBK_CFG1 0x1358 1023#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) 1024#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) 1025#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) 1026#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) 1027#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) 1028#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) 1029#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) 1030#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) 1031 1032/* 1033 * LG_FBK_CFG0: 1034 */ 1035#define LG_FBK_CFG0 0x135c 1036#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) 1037#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) 1038#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) 1039#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) 1040#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) 1041#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) 1042#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) 1043#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) 1044 1045/* 1046 * LG_FBK_CFG1: 1047 */ 1048#define LG_FBK_CFG1 0x1360 1049#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) 1050#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) 1051#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) 1052#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) 1053 1054/* 1055 * CCK_PROT_CFG: CCK Protection 1056 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) 1057 * PROTECT_CTRL: Protection control frame type for CCK TX 1058 * 0:none, 1:RTS/CTS, 2:CTS-to-self 1059 * PROTECT_NAV: TXOP protection type for CCK TX 1060 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect 1061 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow 1062 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow 1063 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow 1064 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow 1065 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow 1066 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow 1067 * RTS_TH_EN: RTS threshold enable on CCK TX 1068 */ 1069#define CCK_PROT_CFG 0x1364 1070#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1071#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1072#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1073#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1074#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1075#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1076#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1077#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1078#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1079#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1080 1081/* 1082 * OFDM_PROT_CFG: OFDM Protection 1083 */ 1084#define OFDM_PROT_CFG 0x1368 1085#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1086#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1087#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1088#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1089#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1090#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1091#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1092#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1093#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1094#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1095 1096/* 1097 * MM20_PROT_CFG: MM20 Protection 1098 */ 1099#define MM20_PROT_CFG 0x136c 1100#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1101#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1102#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1103#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1104#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1105#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1106#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1107#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1108#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1109#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1110 1111/* 1112 * MM40_PROT_CFG: MM40 Protection 1113 */ 1114#define MM40_PROT_CFG 0x1370 1115#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1116#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1117#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1118#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1119#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1120#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1121#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1122#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1123#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1124#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1125 1126/* 1127 * GF20_PROT_CFG: GF20 Protection 1128 */ 1129#define GF20_PROT_CFG 0x1374 1130#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1131#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1132#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1133#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1134#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1135#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1136#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1137#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1138#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1139#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1140 1141/* 1142 * GF40_PROT_CFG: GF40 Protection 1143 */ 1144#define GF40_PROT_CFG 0x1378 1145#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1146#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1147#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1148#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1149#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1150#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1151#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1152#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1153#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1154#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1155 1156/* 1157 * EXP_CTS_TIME: 1158 */ 1159#define EXP_CTS_TIME 0x137c 1160 1161/* 1162 * EXP_ACK_TIME: 1163 */ 1164#define EXP_ACK_TIME 0x1380 1165 1166/* 1167 * RX_FILTER_CFG: RX configuration register. 1168 */ 1169#define RX_FILTER_CFG 0x1400 1170#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) 1171#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) 1172#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) 1173#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) 1174#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) 1175#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) 1176#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) 1177#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) 1178#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) 1179#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) 1180#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) 1181#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) 1182#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) 1183#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) 1184#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) 1185#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) 1186#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) 1187 1188/* 1189 * AUTO_RSP_CFG: 1190 * AUTORESPONDER: 0: disable, 1: enable 1191 * BAC_ACK_POLICY: 0:long, 1:short preamble 1192 * CTS_40_MMODE: Response CTS 40MHz duplicate mode 1193 * CTS_40_MREF: Response CTS 40MHz duplicate mode 1194 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble 1195 * DUAL_CTS_EN: Power bit value in control frame 1196 * ACK_CTS_PSM_BIT:Power bit value in control frame 1197 */ 1198#define AUTO_RSP_CFG 0x1404 1199#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) 1200#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) 1201#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) 1202#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) 1203#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) 1204#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) 1205#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) 1206 1207/* 1208 * LEGACY_BASIC_RATE: 1209 */ 1210#define LEGACY_BASIC_RATE 0x1408 1211 1212/* 1213 * HT_BASIC_RATE: 1214 */ 1215#define HT_BASIC_RATE 0x140c 1216 1217/* 1218 * HT_CTRL_CFG: 1219 */ 1220#define HT_CTRL_CFG 0x1410 1221 1222/* 1223 * SIFS_COST_CFG: 1224 */ 1225#define SIFS_COST_CFG 0x1414 1226 1227/* 1228 * RX_PARSER_CFG: 1229 * Set NAV for all received frames 1230 */ 1231#define RX_PARSER_CFG 0x1418 1232 1233/* 1234 * TX_SEC_CNT0: 1235 */ 1236#define TX_SEC_CNT0 0x1500 1237 1238/* 1239 * RX_SEC_CNT0: 1240 */ 1241#define RX_SEC_CNT0 0x1504 1242 1243/* 1244 * CCMP_FC_MUTE: 1245 */ 1246#define CCMP_FC_MUTE 0x1508 1247 1248/* 1249 * TXOP_HLDR_ADDR0: 1250 */ 1251#define TXOP_HLDR_ADDR0 0x1600 1252 1253/* 1254 * TXOP_HLDR_ADDR1: 1255 */ 1256#define TXOP_HLDR_ADDR1 0x1604 1257 1258/* 1259 * TXOP_HLDR_ET: 1260 */ 1261#define TXOP_HLDR_ET 0x1608 1262 1263/* 1264 * QOS_CFPOLL_RA_DW0: 1265 */ 1266#define QOS_CFPOLL_RA_DW0 0x160c 1267 1268/* 1269 * QOS_CFPOLL_RA_DW1: 1270 */ 1271#define QOS_CFPOLL_RA_DW1 0x1610 1272 1273/* 1274 * QOS_CFPOLL_QC: 1275 */ 1276#define QOS_CFPOLL_QC 0x1614 1277 1278/* 1279 * RX_STA_CNT0: RX PLCP error count & RX CRC error count 1280 */ 1281#define RX_STA_CNT0 0x1700 1282#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) 1283#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) 1284 1285/* 1286 * RX_STA_CNT1: RX False CCA count & RX LONG frame count 1287 */ 1288#define RX_STA_CNT1 0x1704 1289#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) 1290#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) 1291 1292/* 1293 * RX_STA_CNT2: 1294 */ 1295#define RX_STA_CNT2 0x1708 1296#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) 1297#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) 1298 1299/* 1300 * TX_STA_CNT0: TX Beacon count 1301 */ 1302#define TX_STA_CNT0 0x170c 1303#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) 1304#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) 1305 1306/* 1307 * TX_STA_CNT1: TX tx count 1308 */ 1309#define TX_STA_CNT1 0x1710 1310#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) 1311#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) 1312 1313/* 1314 * TX_STA_CNT2: TX tx count 1315 */ 1316#define TX_STA_CNT2 0x1714 1317#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) 1318#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) 1319 1320/* 1321 * TX_STA_FIFO: TX Result for specific PID status fifo register 1322 */ 1323#define TX_STA_FIFO 0x1718 1324#define TX_STA_FIFO_VALID FIELD32(0x00000001) 1325#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) 1326#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) 1327#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) 1328#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) 1329#define TX_STA_FIFO_WCID FIELD32(0x0000ff00) 1330#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000) 1331#define TX_STA_FIFO_MCS FIELD32(0x007f0000) 1332#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) 1333 1334/* 1335 * TX_AGG_CNT: Debug counter 1336 */ 1337#define TX_AGG_CNT 0x171c 1338#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) 1339#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) 1340 1341/* 1342 * TX_AGG_CNT0: 1343 */ 1344#define TX_AGG_CNT0 0x1720 1345#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) 1346#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) 1347 1348/* 1349 * TX_AGG_CNT1: 1350 */ 1351#define TX_AGG_CNT1 0x1724 1352#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) 1353#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) 1354 1355/* 1356 * TX_AGG_CNT2: 1357 */ 1358#define TX_AGG_CNT2 0x1728 1359#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) 1360#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) 1361 1362/* 1363 * TX_AGG_CNT3: 1364 */ 1365#define TX_AGG_CNT3 0x172c 1366#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) 1367#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) 1368 1369/* 1370 * TX_AGG_CNT4: 1371 */ 1372#define TX_AGG_CNT4 0x1730 1373#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) 1374#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) 1375 1376/* 1377 * TX_AGG_CNT5: 1378 */ 1379#define TX_AGG_CNT5 0x1734 1380#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) 1381#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) 1382 1383/* 1384 * TX_AGG_CNT6: 1385 */ 1386#define TX_AGG_CNT6 0x1738 1387#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) 1388#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) 1389 1390/* 1391 * TX_AGG_CNT7: 1392 */ 1393#define TX_AGG_CNT7 0x173c 1394#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) 1395#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) 1396 1397/* 1398 * MPDU_DENSITY_CNT: 1399 * TX_ZERO_DEL: TX zero length delimiter count 1400 * RX_ZERO_DEL: RX zero length delimiter count 1401 */ 1402#define MPDU_DENSITY_CNT 0x1740 1403#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) 1404#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) 1405 1406/* 1407 * Security key table memory. 1408 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry 1409 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry 1410 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry 1411 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry 1412 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry 1413 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry 1414 */ 1415#define MAC_WCID_BASE 0x1800 1416#define PAIRWISE_KEY_TABLE_BASE 0x4000 1417#define MAC_IVEIV_TABLE_BASE 0x6000 1418#define MAC_WCID_ATTRIBUTE_BASE 0x6800 1419#define SHARED_KEY_TABLE_BASE 0x6c00 1420#define SHARED_KEY_MODE_BASE 0x7000 1421 1422#define MAC_WCID_ENTRY(__idx) \ 1423 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) ) 1424#define PAIRWISE_KEY_ENTRY(__idx) \ 1425 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) 1426#define MAC_IVEIV_ENTRY(__idx) \ 1427 ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) ) 1428#define MAC_WCID_ATTR_ENTRY(__idx) \ 1429 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) ) 1430#define SHARED_KEY_ENTRY(__idx) \ 1431 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) 1432#define SHARED_KEY_MODE_ENTRY(__idx) \ 1433 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) ) 1434 1435struct mac_wcid_entry { 1436 u8 mac[6]; 1437 u8 reserved[2]; 1438} __packed; 1439 1440struct hw_key_entry { 1441 u8 key[16]; 1442 u8 tx_mic[8]; 1443 u8 rx_mic[8]; 1444} __packed; 1445 1446struct mac_iveiv_entry { 1447 u8 iv[8]; 1448} __packed; 1449 1450/* 1451 * MAC_WCID_ATTRIBUTE: 1452 */ 1453#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) 1454#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) 1455#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) 1456#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) 1457#define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400) 1458#define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800) 1459#define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000) 1460#define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000) 1461 1462/* 1463 * SHARED_KEY_MODE: 1464 */ 1465#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) 1466#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) 1467#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) 1468#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) 1469#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) 1470#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) 1471#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) 1472#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) 1473 1474/* 1475 * HOST-MCU communication 1476 */ 1477 1478/* 1479 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. 1480 */ 1481#define H2M_MAILBOX_CSR 0x7010 1482#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) 1483#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) 1484#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) 1485#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) 1486 1487/* 1488 * H2M_MAILBOX_CID: 1489 */ 1490#define H2M_MAILBOX_CID 0x7014 1491#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) 1492#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) 1493#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) 1494#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) 1495 1496/* 1497 * H2M_MAILBOX_STATUS: 1498 */ 1499#define H2M_MAILBOX_STATUS 0x701c 1500 1501/* 1502 * H2M_INT_SRC: 1503 */ 1504#define H2M_INT_SRC 0x7024 1505 1506/* 1507 * H2M_BBP_AGENT: 1508 */ 1509#define H2M_BBP_AGENT 0x7028 1510 1511/* 1512 * MCU_LEDCS: LED control for MCU Mailbox. 1513 */ 1514#define MCU_LEDCS_LED_MODE FIELD8(0x1f) 1515#define MCU_LEDCS_POLARITY FIELD8(0x01) 1516 1517/* 1518 * HW_CS_CTS_BASE: 1519 * Carrier-sense CTS frame base address. 1520 * It's where mac stores carrier-sense frame for carrier-sense function. 1521 */ 1522#define HW_CS_CTS_BASE 0x7700 1523 1524/* 1525 * HW_DFS_CTS_BASE: 1526 * DFS CTS frame base address. It's where mac stores CTS frame for DFS. 1527 */ 1528#define HW_DFS_CTS_BASE 0x7780 1529 1530/* 1531 * TXRX control registers - base address 0x3000 1532 */ 1533 1534/* 1535 * TXRX_CSR1: 1536 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. 1537 */ 1538#define TXRX_CSR1 0x77d0 1539 1540/* 1541 * HW_DEBUG_SETTING_BASE: 1542 * since NULL frame won't be that long (256 byte) 1543 * We steal 16 tail bytes to save debugging settings 1544 */ 1545#define HW_DEBUG_SETTING_BASE 0x77f0 1546#define HW_DEBUG_SETTING_BASE2 0x7770 1547 1548/* 1549 * HW_BEACON_BASE 1550 * In order to support maximum 8 MBSS and its maximum length 1551 * is 512 bytes for each beacon 1552 * Three section discontinue memory segments will be used. 1553 * 1. The original region for BCN 0~3 1554 * 2. Extract memory from FCE table for BCN 4~5 1555 * 3. Extract memory from Pair-wise key table for BCN 6~7 1556 * It occupied those memory of wcid 238~253 for BCN 6 1557 * and wcid 222~237 for BCN 7 1558 * 1559 * IMPORTANT NOTE: Not sure why legacy driver does this, 1560 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. 1561 */ 1562#define HW_BEACON_BASE0 0x7800 1563#define HW_BEACON_BASE1 0x7a00 1564#define HW_BEACON_BASE2 0x7c00 1565#define HW_BEACON_BASE3 0x7e00 1566#define HW_BEACON_BASE4 0x7200 1567#define HW_BEACON_BASE5 0x7400 1568#define HW_BEACON_BASE6 0x5dc0 1569#define HW_BEACON_BASE7 0x5bc0 1570 1571#define HW_BEACON_OFFSET(__index) \ 1572 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \ 1573 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \ 1574 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) ) 1575 1576/* 1577 * BBP registers. 1578 * The wordsize of the BBP is 8 bits. 1579 */ 1580 1581/* 1582 * BBP 1: TX Antenna & Power 1583 * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm, 1584 * 3 - increase tx power by 6dBm 1585 */ 1586#define BBP1_TX_POWER FIELD8(0x07) 1587#define BBP1_TX_ANTENNA FIELD8(0x18) 1588 1589/* 1590 * BBP 3: RX Antenna 1591 */ 1592#define BBP3_RX_ANTENNA FIELD8(0x18) 1593#define BBP3_HT40_MINUS FIELD8(0x20) 1594 1595/* 1596 * BBP 4: Bandwidth 1597 */ 1598#define BBP4_TX_BF FIELD8(0x01) 1599#define BBP4_BANDWIDTH FIELD8(0x18) 1600 1601/* 1602 * BBP 138: Unknown 1603 */ 1604#define BBP138_RX_ADC1 FIELD8(0x02) 1605#define BBP138_RX_ADC2 FIELD8(0x04) 1606#define BBP138_TX_DAC1 FIELD8(0x20) 1607#define BBP138_TX_DAC2 FIELD8(0x40) 1608 1609/* 1610 * RFCSR registers 1611 * The wordsize of the RFCSR is 8 bits. 1612 */ 1613 1614/* 1615 * RFCSR 1: 1616 */ 1617#define RFCSR1_RF_BLOCK_EN FIELD8(0x01) 1618#define RFCSR1_RX0_PD FIELD8(0x04) 1619#define RFCSR1_TX0_PD FIELD8(0x08) 1620#define RFCSR1_RX1_PD FIELD8(0x10) 1621#define RFCSR1_TX1_PD FIELD8(0x20) 1622 1623/* 1624 * RFCSR 6: 1625 */ 1626#define RFCSR6_R1 FIELD8(0x03) 1627#define RFCSR6_R2 FIELD8(0x40) 1628 1629/* 1630 * RFCSR 7: 1631 */ 1632#define RFCSR7_RF_TUNING FIELD8(0x01) 1633 1634/* 1635 * RFCSR 12: 1636 */ 1637#define RFCSR12_TX_POWER FIELD8(0x1f) 1638 1639/* 1640 * RFCSR 13: 1641 */ 1642#define RFCSR13_TX_POWER FIELD8(0x1f) 1643 1644/* 1645 * RFCSR 15: 1646 */ 1647#define RFCSR15_TX_LO2_EN FIELD8(0x08) 1648 1649/* 1650 * RFCSR 17: 1651 */ 1652#define RFCSR17_TXMIXER_GAIN FIELD8(0x07) 1653#define RFCSR17_TX_LO1_EN FIELD8(0x08) 1654#define RFCSR17_R FIELD8(0x20) 1655 1656/* 1657 * RFCSR 20: 1658 */ 1659#define RFCSR20_RX_LO1_EN FIELD8(0x08) 1660 1661/* 1662 * RFCSR 21: 1663 */ 1664#define RFCSR21_RX_LO2_EN FIELD8(0x08) 1665 1666/* 1667 * RFCSR 22: 1668 */ 1669#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) 1670 1671/* 1672 * RFCSR 23: 1673 */ 1674#define RFCSR23_FREQ_OFFSET FIELD8(0x7f) 1675 1676/* 1677 * RFCSR 27: 1678 */ 1679#define RFCSR27_R1 FIELD8(0x03) 1680#define RFCSR27_R2 FIELD8(0x04) 1681#define RFCSR27_R3 FIELD8(0x30) 1682#define RFCSR27_R4 FIELD8(0x40) 1683 1684/* 1685 * RFCSR 30: 1686 */ 1687#define RFCSR30_RF_CALIBRATION FIELD8(0x80) 1688 1689/* 1690 * RF registers 1691 */ 1692 1693/* 1694 * RF 2 1695 */ 1696#define RF2_ANTENNA_RX2 FIELD32(0x00000040) 1697#define RF2_ANTENNA_TX1 FIELD32(0x00004000) 1698#define RF2_ANTENNA_RX1 FIELD32(0x00020000) 1699 1700/* 1701 * RF 3 1702 */ 1703#define RF3_TXPOWER_G FIELD32(0x00003e00) 1704#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) 1705#define RF3_TXPOWER_A FIELD32(0x00003c00) 1706 1707/* 1708 * RF 4 1709 */ 1710#define RF4_TXPOWER_G FIELD32(0x000007c0) 1711#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) 1712#define RF4_TXPOWER_A FIELD32(0x00000780) 1713#define RF4_FREQ_OFFSET FIELD32(0x001f8000) 1714#define RF4_HT40 FIELD32(0x00200000) 1715 1716/* 1717 * EEPROM content. 1718 * The wordsize of the EEPROM is 16 bits. 1719 */ 1720 1721/* 1722 * EEPROM Version 1723 */ 1724#define EEPROM_VERSION 0x0001 1725#define EEPROM_VERSION_FAE FIELD16(0x00ff) 1726#define EEPROM_VERSION_VERSION FIELD16(0xff00) 1727 1728/* 1729 * HW MAC address. 1730 */ 1731#define EEPROM_MAC_ADDR_0 0x0002 1732#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 1733#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 1734#define EEPROM_MAC_ADDR_1 0x0003 1735#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 1736#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 1737#define EEPROM_MAC_ADDR_2 0x0004 1738#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 1739#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 1740 1741/* 1742 * EEPROM ANTENNA config 1743 * RXPATH: 1: 1R, 2: 2R, 3: 3R 1744 * TXPATH: 1: 1T, 2: 2T 1745 */ 1746#define EEPROM_ANTENNA 0x001a 1747#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f) 1748#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0) 1749#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00) 1750 1751/* 1752 * EEPROM NIC config 1753 * CARDBUS_ACCEL: 0 - enable, 1 - disable 1754 */ 1755#define EEPROM_NIC 0x001b 1756#define EEPROM_NIC_HW_RADIO FIELD16(0x0001) 1757#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002) 1758#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004) 1759#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008) 1760#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010) 1761#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020) 1762#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040) 1763#define EEPROM_NIC_WPS_PBC FIELD16(0x0080) 1764#define EEPROM_NIC_BW40M_BG FIELD16(0x0100) 1765#define EEPROM_NIC_BW40M_A FIELD16(0x0200) 1766#define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800) 1767#define EEPROM_NIC_DAC_TEST FIELD16(0x8000) 1768 1769/* 1770 * EEPROM frequency 1771 */ 1772#define EEPROM_FREQ 0x001d 1773#define EEPROM_FREQ_OFFSET FIELD16(0x00ff) 1774#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) 1775#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) 1776 1777/* 1778 * EEPROM LED 1779 * POLARITY_RDY_G: Polarity RDY_G setting. 1780 * POLARITY_RDY_A: Polarity RDY_A setting. 1781 * POLARITY_ACT: Polarity ACT setting. 1782 * POLARITY_GPIO_0: Polarity GPIO0 setting. 1783 * POLARITY_GPIO_1: Polarity GPIO1 setting. 1784 * POLARITY_GPIO_2: Polarity GPIO2 setting. 1785 * POLARITY_GPIO_3: Polarity GPIO3 setting. 1786 * POLARITY_GPIO_4: Polarity GPIO4 setting. 1787 * LED_MODE: Led mode. 1788 */ 1789#define EEPROM_LED1 0x001e 1790#define EEPROM_LED2 0x001f 1791#define EEPROM_LED3 0x0020 1792#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) 1793#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) 1794#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) 1795#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) 1796#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) 1797#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) 1798#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) 1799#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) 1800#define EEPROM_LED_LED_MODE FIELD16(0x1f00) 1801 1802/* 1803 * EEPROM LNA 1804 */ 1805#define EEPROM_LNA 0x0022 1806#define EEPROM_LNA_BG FIELD16(0x00ff) 1807#define EEPROM_LNA_A0 FIELD16(0xff00) 1808 1809/* 1810 * EEPROM RSSI BG offset 1811 */ 1812#define EEPROM_RSSI_BG 0x0023 1813#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) 1814#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) 1815 1816/* 1817 * EEPROM RSSI BG2 offset 1818 */ 1819#define EEPROM_RSSI_BG2 0x0024 1820#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) 1821#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) 1822 1823/* 1824 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2). 1825 */ 1826#define EEPROM_TXMIXER_GAIN_BG 0x0024 1827#define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007) 1828 1829/* 1830 * EEPROM RSSI A offset 1831 */ 1832#define EEPROM_RSSI_A 0x0025 1833#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) 1834#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) 1835 1836/* 1837 * EEPROM RSSI A2 offset 1838 */ 1839#define EEPROM_RSSI_A2 0x0026 1840#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) 1841#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) 1842 1843/* 1844 * EEPROM Maximum TX power values 1845 */ 1846#define EEPROM_MAX_TX_POWER 0x0027 1847#define EEPROM_MAX_TX_POWER_24GHZ FIELD16(0x00ff) 1848#define EEPROM_MAX_TX_POWER_5GHZ FIELD16(0xff00) 1849 1850/* 1851 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. 1852 * This is delta in 40MHZ. 1853 * VALUE: Tx Power dalta value (MAX=4) 1854 * TYPE: 1: Plus the delta value, 0: minus the delta value 1855 * TXPOWER: Enable: 1856 */ 1857#define EEPROM_TXPOWER_DELTA 0x0028 1858#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f) 1859#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040) 1860#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080) 1861 1862/* 1863 * EEPROM TXPOWER 802.11BG 1864 */ 1865#define EEPROM_TXPOWER_BG1 0x0029 1866#define EEPROM_TXPOWER_BG2 0x0030 1867#define EEPROM_TXPOWER_BG_SIZE 7 1868#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) 1869#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) 1870 1871/* 1872 * EEPROM TXPOWER 802.11A 1873 */ 1874#define EEPROM_TXPOWER_A1 0x003c 1875#define EEPROM_TXPOWER_A2 0x0053 1876#define EEPROM_TXPOWER_A_SIZE 6 1877#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) 1878#define EEPROM_TXPOWER_A_2 FIELD16(0xff00) 1879 1880/* 1881 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode 1882 */ 1883#define EEPROM_TXPOWER_BYRATE 0x006f 1884#define EEPROM_TXPOWER_BYRATE_SIZE 9 1885 1886#define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f) 1887#define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0) 1888#define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00) 1889#define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000) 1890 1891/* 1892 * EEPROM BBP. 1893 */ 1894#define EEPROM_BBP_START 0x0078 1895#define EEPROM_BBP_SIZE 16 1896#define EEPROM_BBP_VALUE FIELD16(0x00ff) 1897#define EEPROM_BBP_REG_ID FIELD16(0xff00) 1898 1899/* 1900 * MCU mailbox commands. 1901 */ 1902#define MCU_SLEEP 0x30 1903#define MCU_WAKEUP 0x31 1904#define MCU_RADIO_OFF 0x35 1905#define MCU_CURRENT 0x36 1906#define MCU_LED 0x50 1907#define MCU_LED_STRENGTH 0x51 1908#define MCU_LED_1 0x52 1909#define MCU_LED_2 0x53 1910#define MCU_LED_3 0x54 1911#define MCU_RADAR 0x60 1912#define MCU_BOOT_SIGNAL 0x72 1913#define MCU_BBP_SIGNAL 0x80 1914#define MCU_POWER_SAVE 0x83 1915 1916/* 1917 * MCU mailbox tokens 1918 */ 1919#define TOKEN_WAKUP 3 1920 1921/* 1922 * DMA descriptor defines. 1923 */ 1924#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) ) 1925#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) ) 1926 1927/* 1928 * TX WI structure 1929 */ 1930 1931/* 1932 * Word0 1933 * FRAG: 1 To inform TKIP engine this is a fragment. 1934 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode 1935 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs 1936 * BW: Channel bandwidth 20MHz or 40 MHz 1937 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED 1938 */ 1939#define TXWI_W0_FRAG FIELD32(0x00000001) 1940#define TXWI_W0_MIMO_PS FIELD32(0x00000002) 1941#define TXWI_W0_CF_ACK FIELD32(0x00000004) 1942#define TXWI_W0_TS FIELD32(0x00000008) 1943#define TXWI_W0_AMPDU FIELD32(0x00000010) 1944#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) 1945#define TXWI_W0_TX_OP FIELD32(0x00000300) 1946#define TXWI_W0_MCS FIELD32(0x007f0000) 1947#define TXWI_W0_BW FIELD32(0x00800000) 1948#define TXWI_W0_SHORT_GI FIELD32(0x01000000) 1949#define TXWI_W0_STBC FIELD32(0x06000000) 1950#define TXWI_W0_IFS FIELD32(0x08000000) 1951#define TXWI_W0_PHYMODE FIELD32(0xc0000000) 1952 1953/* 1954 * Word1 1955 */ 1956#define TXWI_W1_ACK FIELD32(0x00000001) 1957#define TXWI_W1_NSEQ FIELD32(0x00000002) 1958#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) 1959#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) 1960#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 1961#define TXWI_W1_PACKETID FIELD32(0xf0000000) 1962 1963/* 1964 * Word2 1965 */ 1966#define TXWI_W2_IV FIELD32(0xffffffff) 1967 1968/* 1969 * Word3 1970 */ 1971#define TXWI_W3_EIV FIELD32(0xffffffff) 1972 1973/* 1974 * RX WI structure 1975 */ 1976 1977/* 1978 * Word0 1979 */ 1980#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) 1981#define RXWI_W0_KEY_INDEX FIELD32(0x00000300) 1982#define RXWI_W0_BSSID FIELD32(0x00001c00) 1983#define RXWI_W0_UDF FIELD32(0x0000e000) 1984#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 1985#define RXWI_W0_TID FIELD32(0xf0000000) 1986 1987/* 1988 * Word1 1989 */ 1990#define RXWI_W1_FRAG FIELD32(0x0000000f) 1991#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) 1992#define RXWI_W1_MCS FIELD32(0x007f0000) 1993#define RXWI_W1_BW FIELD32(0x00800000) 1994#define RXWI_W1_SHORT_GI FIELD32(0x01000000) 1995#define RXWI_W1_STBC FIELD32(0x06000000) 1996#define RXWI_W1_PHYMODE FIELD32(0xc0000000) 1997 1998/* 1999 * Word2 2000 */ 2001#define RXWI_W2_RSSI0 FIELD32(0x000000ff) 2002#define RXWI_W2_RSSI1 FIELD32(0x0000ff00) 2003#define RXWI_W2_RSSI2 FIELD32(0x00ff0000) 2004 2005/* 2006 * Word3 2007 */ 2008#define RXWI_W3_SNR0 FIELD32(0x000000ff) 2009#define RXWI_W3_SNR1 FIELD32(0x0000ff00) 2010 2011/* 2012 * Macros for converting txpower from EEPROM to mac80211 value 2013 * and from mac80211 value to register value. 2014 */ 2015#define MIN_G_TXPOWER 0 2016#define MIN_A_TXPOWER -7 2017#define MAX_G_TXPOWER 31 2018#define MAX_A_TXPOWER 15 2019#define DEFAULT_TXPOWER 5 2020 2021#define TXPOWER_G_FROM_DEV(__txpower) \ 2022 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 2023 2024#define TXPOWER_G_TO_DEV(__txpower) \ 2025 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER) 2026 2027#define TXPOWER_A_FROM_DEV(__txpower) \ 2028 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 2029 2030#define TXPOWER_A_TO_DEV(__txpower) \ 2031 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER) 2032 2033#endif /* RT2800_H */ 2034