1/* 2 * linux/drivers/net/wireless/libertas/if_spi.c 3 * 4 * Driver for Marvell SPI WLAN cards. 5 * 6 * Copyright 2008 Analog Devices Inc. 7 * 8 * Authors: 9 * Andrey Yurovsky <andrey@cozybit.com> 10 * Colin McCabe <colin@cozybit.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or (at 15 * your option) any later version. 16 */ 17 18#ifndef _LBS_IF_SPI_H_ 19#define _LBS_IF_SPI_H_ 20 21#define IPFIELD_ALIGN_OFFSET 2 22#define IF_SPI_CMD_BUF_SIZE 2400 23 24/***************** Firmware *****************/ 25 26#define IF_SPI_FW_NAME_MAX 30 27 28struct chip_ident { 29 u16 chip_id; 30 u16 name; 31}; 32 33#define MAX_MAIN_FW_LOAD_CRC_ERR 10 34 35/* Chunk size when loading the helper firmware */ 36#define HELPER_FW_LOAD_CHUNK_SZ 64 37 38/* Value to write to indicate end of helper firmware dnld */ 39#define FIRMWARE_DNLD_OK 0x0000 40 41/* Value to check once the main firmware is downloaded */ 42#define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888 43 44/***************** SPI Interface Unit *****************/ 45/* Masks used in SPI register read/write operations */ 46#define IF_SPI_READ_OPERATION_MASK 0x0 47#define IF_SPI_WRITE_OPERATION_MASK 0x8000 48 49/* SPI register offsets. 4-byte aligned. */ 50#define IF_SPI_DEVICEID_CTRL_REG 0x00 /* DeviceID controller reg */ 51#define IF_SPI_IO_READBASE_REG 0x04 /* Read I/O base reg */ 52#define IF_SPI_IO_WRITEBASE_REG 0x08 /* Write I/O base reg */ 53#define IF_SPI_IO_RDWRPORT_REG 0x0C /* Read/Write I/O port reg */ 54 55#define IF_SPI_CMD_READBASE_REG 0x10 /* Read command base reg */ 56#define IF_SPI_CMD_WRITEBASE_REG 0x14 /* Write command base reg */ 57#define IF_SPI_CMD_RDWRPORT_REG 0x18 /* Read/Write command port reg */ 58 59#define IF_SPI_DATA_READBASE_REG 0x1C /* Read data base reg */ 60#define IF_SPI_DATA_WRITEBASE_REG 0x20 /* Write data base reg */ 61#define IF_SPI_DATA_RDWRPORT_REG 0x24 /* Read/Write data port reg */ 62 63#define IF_SPI_SCRATCH_1_REG 0x28 /* Scratch reg 1 */ 64#define IF_SPI_SCRATCH_2_REG 0x2C /* Scratch reg 2 */ 65#define IF_SPI_SCRATCH_3_REG 0x30 /* Scratch reg 3 */ 66#define IF_SPI_SCRATCH_4_REG 0x34 /* Scratch reg 4 */ 67 68#define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38 /* Tx frame sequence number reg */ 69#define IF_SPI_TX_FRAME_STATUS_REG 0x3C /* Tx frame status reg */ 70 71#define IF_SPI_HOST_INT_CTRL_REG 0x40 /* Host interrupt controller reg */ 72 73#define IF_SPI_CARD_INT_CAUSE_REG 0x44 /* Card interrupt cause reg */ 74#define IF_SPI_CARD_INT_STATUS_REG 0x48 /* Card interupt status reg */ 75#define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C /* Card interrupt event mask */ 76#define IF_SPI_CARD_INT_STATUS_MASK_REG 0x50 /* Card interrupt status mask */ 77 78#define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54 /* Card interrupt reset select */ 79 80#define IF_SPI_HOST_INT_CAUSE_REG 0x58 /* Host interrupt cause reg */ 81#define IF_SPI_HOST_INT_STATUS_REG 0x5C /* Host interrupt status reg */ 82#define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60 /* Host interrupt event mask */ 83#define IF_SPI_HOST_INT_STATUS_MASK_REG 0x64 /* Host interrupt status mask */ 84#define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68 /* Host interrupt reset select */ 85 86#define IF_SPI_DELAY_READ_REG 0x6C /* Delay read reg */ 87#define IF_SPI_SPU_BUS_MODE_REG 0x70 /* SPU BUS mode reg */ 88 89/***************** IF_SPI_DEVICEID_CTRL_REG *****************/ 90#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16) 91#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff) 92 93/***************** IF_SPI_HOST_INT_CTRL_REG *****************/ 94/** Host Interrupt Control bit : Wake up */ 95#define IF_SPI_HICT_WAKE_UP (1<<0) 96/** Host Interrupt Control bit : WLAN ready */ 97#define IF_SPI_HICT_WLAN_READY (1<<1) 98/*#define IF_SPI_HICT_FIFO_FIRST_HALF_EMPTY (1<<2) */ 99/*#define IF_SPI_HICT_FIFO_SECOND_HALF_EMPTY (1<<3) */ 100/*#define IF_SPI_HICT_IRQSRC_WLAN (1<<4) */ 101/** Host Interrupt Control bit : Tx auto download */ 102#define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO (1<<5) 103/** Host Interrupt Control bit : Rx auto upload */ 104#define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO (1<<6) 105/** Host Interrupt Control bit : Command auto download */ 106#define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO (1<<7) 107/** Host Interrupt Control bit : Command auto upload */ 108#define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO (1<<8) 109 110/***************** IF_SPI_CARD_INT_CAUSE_REG *****************/ 111/** Card Interrupt Case bit : Tx download over */ 112#define IF_SPI_CIC_TX_DOWNLOAD_OVER (1<<0) 113/** Card Interrupt Case bit : Rx upload over */ 114#define IF_SPI_CIC_RX_UPLOAD_OVER (1<<1) 115/** Card Interrupt Case bit : Command download over */ 116#define IF_SPI_CIC_CMD_DOWNLOAD_OVER (1<<2) 117/** Card Interrupt Case bit : Host event */ 118#define IF_SPI_CIC_HOST_EVENT (1<<3) 119/** Card Interrupt Case bit : Command upload over */ 120#define IF_SPI_CIC_CMD_UPLOAD_OVER (1<<4) 121/** Card Interrupt Case bit : Power down */ 122#define IF_SPI_CIC_POWER_DOWN (1<<5) 123 124/***************** IF_SPI_CARD_INT_STATUS_REG *****************/ 125#define IF_SPI_CIS_TX_DOWNLOAD_OVER (1<<0) 126#define IF_SPI_CIS_RX_UPLOAD_OVER (1<<1) 127#define IF_SPI_CIS_CMD_DOWNLOAD_OVER (1<<2) 128#define IF_SPI_CIS_HOST_EVENT (1<<3) 129#define IF_SPI_CIS_CMD_UPLOAD_OVER (1<<4) 130#define IF_SPI_CIS_POWER_DOWN (1<<5) 131 132/***************** IF_SPI_HOST_INT_CAUSE_REG *****************/ 133#define IF_SPI_HICU_TX_DOWNLOAD_RDY (1<<0) 134#define IF_SPI_HICU_RX_UPLOAD_RDY (1<<1) 135#define IF_SPI_HICU_CMD_DOWNLOAD_RDY (1<<2) 136#define IF_SPI_HICU_CARD_EVENT (1<<3) 137#define IF_SPI_HICU_CMD_UPLOAD_RDY (1<<4) 138#define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW (1<<5) 139#define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW (1<<6) 140#define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW (1<<7) 141#define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW (1<<8) 142#define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW (1<<9) 143#define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW (1<<10) 144 145/***************** IF_SPI_HOST_INT_STATUS_REG *****************/ 146/** Host Interrupt Status bit : Tx download ready */ 147#define IF_SPI_HIST_TX_DOWNLOAD_RDY (1<<0) 148/** Host Interrupt Status bit : Rx upload ready */ 149#define IF_SPI_HIST_RX_UPLOAD_RDY (1<<1) 150/** Host Interrupt Status bit : Command download ready */ 151#define IF_SPI_HIST_CMD_DOWNLOAD_RDY (1<<2) 152/** Host Interrupt Status bit : Card event */ 153#define IF_SPI_HIST_CARD_EVENT (1<<3) 154/** Host Interrupt Status bit : Command upload ready */ 155#define IF_SPI_HIST_CMD_UPLOAD_RDY (1<<4) 156/** Host Interrupt Status bit : I/O write FIFO overflow */ 157#define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW (1<<5) 158/** Host Interrupt Status bit : I/O read FIFO underflow */ 159#define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW (1<<6) 160/** Host Interrupt Status bit : Data write FIFO overflow */ 161#define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW (1<<7) 162/** Host Interrupt Status bit : Data read FIFO underflow */ 163#define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW (1<<8) 164/** Host Interrupt Status bit : Command write FIFO overflow */ 165#define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW (1<<9) 166/** Host Interrupt Status bit : Command read FIFO underflow */ 167#define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW (1<<10) 168 169/***************** IF_SPI_HOST_INT_STATUS_MASK_REG *****************/ 170/** Host Interrupt Status Mask bit : Tx download ready */ 171#define IF_SPI_HISM_TX_DOWNLOAD_RDY (1<<0) 172/** Host Interrupt Status Mask bit : Rx upload ready */ 173#define IF_SPI_HISM_RX_UPLOAD_RDY (1<<1) 174/** Host Interrupt Status Mask bit : Command download ready */ 175#define IF_SPI_HISM_CMD_DOWNLOAD_RDY (1<<2) 176/** Host Interrupt Status Mask bit : Card event */ 177#define IF_SPI_HISM_CARDEVENT (1<<3) 178/** Host Interrupt Status Mask bit : Command upload ready */ 179#define IF_SPI_HISM_CMD_UPLOAD_RDY (1<<4) 180/** Host Interrupt Status Mask bit : I/O write FIFO overflow */ 181#define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW (1<<5) 182/** Host Interrupt Status Mask bit : I/O read FIFO underflow */ 183#define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW (1<<6) 184/** Host Interrupt Status Mask bit : Data write FIFO overflow */ 185#define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW (1<<7) 186/** Host Interrupt Status Mask bit : Data write FIFO underflow */ 187#define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW (1<<8) 188/** Host Interrupt Status Mask bit : Command write FIFO overflow */ 189#define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW (1<<9) 190/** Host Interrupt Status Mask bit : Command write FIFO underflow */ 191#define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW (1<<10) 192 193/***************** IF_SPI_SPU_BUS_MODE_REG *****************/ 194/* SCK edge on which the WLAN module outputs data on MISO */ 195#define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING 0x8 196#define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING 0x0 197 198/* In a SPU read operation, there is a delay between writing the SPU 199 * register name and getting back data from the WLAN module. 200 * This can be specified in terms of nanoseconds or in terms of dummy 201 * clock cycles which the master must output before receiving a response. */ 202#define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK 0x4 203#define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED 0x0 204 205/* Some different modes of SPI operation */ 206#define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA 0x00 207#define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA 0x01 208#define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA 0x02 209#define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA 0x03 210 211#endif 212