1/****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. 4 * 5 * Portions of this file are derived from the ipw3945 project, as well 6 * as portions of the ieee80211 subsystem header files. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of version 2 of the GNU General Public License as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 20 * 21 * The full GNU General Public License is included in this distribution in the 22 * file called LICENSE. 23 * 24 * Contact Information: 25 * Intel Linux Wireless <ilw@linux.intel.com> 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 * 28 *****************************************************************************/ 29 30#include <linux/etherdevice.h> 31#include <linux/sched.h> 32#include <linux/slab.h> 33#include <net/mac80211.h> 34#include "iwl-eeprom.h" 35#include "iwl-dev.h" 36#include "iwl-core.h" 37#include "iwl-sta.h" 38#include "iwl-io.h" 39#include "iwl-helpers.h" 40 41/** 42 * iwl_txq_update_write_ptr - Send new write index to hardware 43 */ 44void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) 45{ 46 u32 reg = 0; 47 int txq_id = txq->q.id; 48 49 if (txq->need_update == 0) 50 return; 51 52 /* if we're trying to save power */ 53 if (test_bit(STATUS_POWER_PMI, &priv->status)) { 54 /* wake up nic if it's powered down ... 55 * uCode will wake up, and interrupt us again, so next 56 * time we'll skip this part. */ 57 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); 58 59 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 60 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 61 txq_id, reg); 62 iwl_set_bit(priv, CSR_GP_CNTRL, 63 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 64 return; 65 } 66 67 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 68 txq->q.write_ptr | (txq_id << 8)); 69 70 /* else not in power-save mode, uCode will never sleep when we're 71 * trying to tx (during RFKILL, we're not trying to tx). */ 72 } else 73 iwl_write32(priv, HBUS_TARG_WRPTR, 74 txq->q.write_ptr | (txq_id << 8)); 75 76 txq->need_update = 0; 77} 78EXPORT_SYMBOL(iwl_txq_update_write_ptr); 79 80/** 81 * iwl_tx_queue_free - Deallocate DMA queue. 82 * @txq: Transmit queue to deallocate. 83 * 84 * Empty queue by removing and destroying all BD's. 85 * Free all buffers. 86 * 0-fill, but do not free "txq" descriptor structure. 87 */ 88void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) 89{ 90 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 91 struct iwl_queue *q = &txq->q; 92 struct device *dev = &priv->pci_dev->dev; 93 int i; 94 95 if (q->n_bd == 0) 96 return; 97 98 /* first, empty all BD's */ 99 for (; q->write_ptr != q->read_ptr; 100 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) 101 priv->cfg->ops->lib->txq_free_tfd(priv, txq); 102 103 /* De-alloc array of command/tx buffers */ 104 for (i = 0; i < TFD_TX_CMD_SLOTS; i++) 105 kfree(txq->cmd[i]); 106 107 /* De-alloc circular buffer of TFDs */ 108 if (txq->q.n_bd) 109 dma_free_coherent(dev, priv->hw_params.tfd_size * 110 txq->q.n_bd, txq->tfds, txq->q.dma_addr); 111 112 /* De-alloc array of per-TFD driver data */ 113 kfree(txq->txb); 114 txq->txb = NULL; 115 116 /* deallocate arrays */ 117 kfree(txq->cmd); 118 kfree(txq->meta); 119 txq->cmd = NULL; 120 txq->meta = NULL; 121 122 /* 0-fill queue descriptor structure */ 123 memset(txq, 0, sizeof(*txq)); 124} 125EXPORT_SYMBOL(iwl_tx_queue_free); 126 127/** 128 * iwl_cmd_queue_free - Deallocate DMA queue. 129 * @txq: Transmit queue to deallocate. 130 * 131 * Empty queue by removing and destroying all BD's. 132 * Free all buffers. 133 * 0-fill, but do not free "txq" descriptor structure. 134 */ 135void iwl_cmd_queue_free(struct iwl_priv *priv) 136{ 137 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; 138 struct iwl_queue *q = &txq->q; 139 struct device *dev = &priv->pci_dev->dev; 140 int i; 141 bool huge = false; 142 143 if (q->n_bd == 0) 144 return; 145 146 for (; q->read_ptr != q->write_ptr; 147 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { 148 /* we have no way to tell if it is a huge cmd ATM */ 149 i = get_cmd_index(q, q->read_ptr, 0); 150 151 if (txq->meta[i].flags & CMD_SIZE_HUGE) { 152 huge = true; 153 continue; 154 } 155 156 pci_unmap_single(priv->pci_dev, 157 dma_unmap_addr(&txq->meta[i], mapping), 158 dma_unmap_len(&txq->meta[i], len), 159 PCI_DMA_BIDIRECTIONAL); 160 } 161 if (huge) { 162 i = q->n_window; 163 pci_unmap_single(priv->pci_dev, 164 dma_unmap_addr(&txq->meta[i], mapping), 165 dma_unmap_len(&txq->meta[i], len), 166 PCI_DMA_BIDIRECTIONAL); 167 } 168 169 /* De-alloc array of command/tx buffers */ 170 for (i = 0; i <= TFD_CMD_SLOTS; i++) 171 kfree(txq->cmd[i]); 172 173 /* De-alloc circular buffer of TFDs */ 174 if (txq->q.n_bd) 175 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd, 176 txq->tfds, txq->q.dma_addr); 177 178 /* deallocate arrays */ 179 kfree(txq->cmd); 180 kfree(txq->meta); 181 txq->cmd = NULL; 182 txq->meta = NULL; 183 184 /* 0-fill queue descriptor structure */ 185 memset(txq, 0, sizeof(*txq)); 186} 187EXPORT_SYMBOL(iwl_cmd_queue_free); 188 189/*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 190 * DMA services 191 * 192 * Theory of operation 193 * 194 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 195 * of buffer descriptors, each of which points to one or more data buffers for 196 * the device to read from or fill. Driver and device exchange status of each 197 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 198 * entries in each circular buffer, to protect against confusing empty and full 199 * queue states. 200 * 201 * The device reads or writes the data in the queues via the device's several 202 * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 203 * 204 * For Tx queue, there are low mark and high mark limits. If, after queuing 205 * the packet for Tx, free space become < low mark, Tx queue stopped. When 206 * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 207 * Tx queue resumed. 208 * 209 * See more detailed info in iwl-4965-hw.h. 210 ***************************************************/ 211 212int iwl_queue_space(const struct iwl_queue *q) 213{ 214 int s = q->read_ptr - q->write_ptr; 215 216 if (q->read_ptr > q->write_ptr) 217 s -= q->n_bd; 218 219 if (s <= 0) 220 s += q->n_window; 221 /* keep some reserve to not confuse empty and full situations */ 222 s -= 2; 223 if (s < 0) 224 s = 0; 225 return s; 226} 227EXPORT_SYMBOL(iwl_queue_space); 228 229 230/** 231 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 232 */ 233static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, 234 int count, int slots_num, u32 id) 235{ 236 q->n_bd = count; 237 q->n_window = slots_num; 238 q->id = id; 239 240 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap 241 * and iwl_queue_dec_wrap are broken. */ 242 BUG_ON(!is_power_of_2(count)); 243 244 /* slots_num must be power-of-two size, otherwise 245 * get_cmd_index is broken. */ 246 BUG_ON(!is_power_of_2(slots_num)); 247 248 q->low_mark = q->n_window / 4; 249 if (q->low_mark < 4) 250 q->low_mark = 4; 251 252 q->high_mark = q->n_window / 8; 253 if (q->high_mark < 2) 254 q->high_mark = 2; 255 256 q->write_ptr = q->read_ptr = 0; 257 q->last_read_ptr = 0; 258 q->repeat_same_read_ptr = 0; 259 260 return 0; 261} 262 263/** 264 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue 265 */ 266static int iwl_tx_queue_alloc(struct iwl_priv *priv, 267 struct iwl_tx_queue *txq, u32 id) 268{ 269 struct device *dev = &priv->pci_dev->dev; 270 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; 271 272 /* Driver private data, only for Tx (not command) queues, 273 * not shared with device. */ 274 if (id != IWL_CMD_QUEUE_NUM) { 275 txq->txb = kzalloc(sizeof(txq->txb[0]) * 276 TFD_QUEUE_SIZE_MAX, GFP_KERNEL); 277 if (!txq->txb) { 278 IWL_ERR(priv, "kmalloc for auxiliary BD " 279 "structures failed\n"); 280 goto error; 281 } 282 } else { 283 txq->txb = NULL; 284 } 285 286 /* Circular buffer of transmit frame descriptors (TFDs), 287 * shared with device */ 288 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, 289 GFP_KERNEL); 290 if (!txq->tfds) { 291 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); 292 goto error; 293 } 294 txq->q.id = id; 295 296 return 0; 297 298 error: 299 kfree(txq->txb); 300 txq->txb = NULL; 301 302 return -ENOMEM; 303} 304 305/** 306 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue 307 */ 308int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, 309 int slots_num, u32 txq_id) 310{ 311 int i, len; 312 int ret; 313 int actual_slots = slots_num; 314 315 /* 316 * Alloc buffer array for commands (Tx or other types of commands). 317 * For the command queue (#4), allocate command space + one big 318 * command for scan, since scan command is very huge; the system will 319 * not have two scans at the same time, so only one is needed. 320 * For normal Tx queues (all other queues), no super-size command 321 * space is needed. 322 */ 323 if (txq_id == IWL_CMD_QUEUE_NUM) 324 actual_slots++; 325 326 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, 327 GFP_KERNEL); 328 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, 329 GFP_KERNEL); 330 331 if (!txq->meta || !txq->cmd) 332 goto out_free_arrays; 333 334 len = sizeof(struct iwl_device_cmd); 335 for (i = 0; i < actual_slots; i++) { 336 /* only happens for cmd queue */ 337 if (i == slots_num) 338 len = IWL_MAX_CMD_SIZE; 339 340 txq->cmd[i] = kmalloc(len, GFP_KERNEL); 341 if (!txq->cmd[i]) 342 goto err; 343 } 344 345 /* Alloc driver data array and TFD circular buffer */ 346 ret = iwl_tx_queue_alloc(priv, txq, txq_id); 347 if (ret) 348 goto err; 349 350 txq->need_update = 0; 351 352 /* 353 * Aggregation TX queues will get their ID when aggregation begins; 354 * they overwrite the setting done here. The command FIFO doesn't 355 * need an swq_id so don't set one to catch errors, all others can 356 * be set up to the identity mapping. 357 */ 358 if (txq_id != IWL_CMD_QUEUE_NUM) 359 txq->swq_id = txq_id; 360 361 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise 362 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 363 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); 364 365 /* Initialize queue's high/low-water marks, and head/tail indexes */ 366 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); 367 368 /* Tell device where to find queue */ 369 priv->cfg->ops->lib->txq_init(priv, txq); 370 371 return 0; 372err: 373 for (i = 0; i < actual_slots; i++) 374 kfree(txq->cmd[i]); 375out_free_arrays: 376 kfree(txq->meta); 377 kfree(txq->cmd); 378 379 return -ENOMEM; 380} 381EXPORT_SYMBOL(iwl_tx_queue_init); 382 383void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq, 384 int slots_num, u32 txq_id) 385{ 386 int actual_slots = slots_num; 387 388 if (txq_id == IWL_CMD_QUEUE_NUM) 389 actual_slots++; 390 391 memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots); 392 393 txq->need_update = 0; 394 395 /* Initialize queue's high/low-water marks, and head/tail indexes */ 396 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); 397 398 /* Tell device where to find queue */ 399 priv->cfg->ops->lib->txq_init(priv, txq); 400} 401EXPORT_SYMBOL(iwl_tx_queue_reset); 402 403/*************** HOST COMMAND QUEUE FUNCTIONS *****/ 404 405/** 406 * iwl_enqueue_hcmd - enqueue a uCode command 407 * @priv: device private data point 408 * @cmd: a point to the ucode command structure 409 * 410 * The function returns < 0 values to indicate the operation is 411 * failed. On success, it turns the index (> 0) of command in the 412 * command queue. 413 */ 414int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) 415{ 416 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; 417 struct iwl_queue *q = &txq->q; 418 struct iwl_device_cmd *out_cmd; 419 struct iwl_cmd_meta *out_meta; 420 dma_addr_t phys_addr; 421 unsigned long flags; 422 int len; 423 u32 idx; 424 u16 fix_size; 425 426 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); 427 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); 428 429 /* If any of the command structures end up being larger than 430 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then 431 * we will need to increase the size of the TFD entries 432 * Also, check to see if command buffer should not exceed the size 433 * of device_cmd and max_cmd_size. */ 434 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && 435 !(cmd->flags & CMD_SIZE_HUGE)); 436 BUG_ON(fix_size > IWL_MAX_CMD_SIZE); 437 438 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { 439 IWL_WARN(priv, "Not sending command - %s KILL\n", 440 iwl_is_rfkill(priv) ? "RF" : "CT"); 441 return -EIO; 442 } 443 444 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 445 IWL_ERR(priv, "No space in command queue\n"); 446 if (iwl_within_ct_kill_margin(priv)) 447 iwl_tt_enter_ct_kill(priv); 448 else { 449 IWL_ERR(priv, "Restarting adapter due to queue full\n"); 450 queue_work(priv->workqueue, &priv->restart); 451 } 452 return -ENOSPC; 453 } 454 455 spin_lock_irqsave(&priv->hcmd_lock, flags); 456 457 /* If this is a huge cmd, mark the huge flag also on the meta.flags 458 * of the _original_ cmd. This is used for DMA mapping clean up. 459 */ 460 if (cmd->flags & CMD_SIZE_HUGE) { 461 idx = get_cmd_index(q, q->write_ptr, 0); 462 txq->meta[idx].flags = CMD_SIZE_HUGE; 463 } 464 465 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); 466 out_cmd = txq->cmd[idx]; 467 out_meta = &txq->meta[idx]; 468 469 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 470 out_meta->flags = cmd->flags; 471 if (cmd->flags & CMD_WANT_SKB) 472 out_meta->source = cmd; 473 if (cmd->flags & CMD_ASYNC) 474 out_meta->callback = cmd->callback; 475 476 out_cmd->hdr.cmd = cmd->id; 477 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); 478 479 /* At this point, the out_cmd now has all of the incoming cmd 480 * information */ 481 482 out_cmd->hdr.flags = 0; 483 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | 484 INDEX_TO_SEQ(q->write_ptr)); 485 if (cmd->flags & CMD_SIZE_HUGE) 486 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; 487 len = sizeof(struct iwl_device_cmd); 488 if (idx == TFD_CMD_SLOTS) 489 len = IWL_MAX_CMD_SIZE; 490 491#ifdef CONFIG_IWLWIFI_DEBUG 492 switch (out_cmd->hdr.cmd) { 493 case REPLY_TX_LINK_QUALITY_CMD: 494 case SENSITIVITY_CMD: 495 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " 496 "%d bytes at %d[%d]:%d\n", 497 get_cmd_string(out_cmd->hdr.cmd), 498 out_cmd->hdr.cmd, 499 le16_to_cpu(out_cmd->hdr.sequence), fix_size, 500 q->write_ptr, idx, IWL_CMD_QUEUE_NUM); 501 break; 502 default: 503 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " 504 "%d bytes at %d[%d]:%d\n", 505 get_cmd_string(out_cmd->hdr.cmd), 506 out_cmd->hdr.cmd, 507 le16_to_cpu(out_cmd->hdr.sequence), fix_size, 508 q->write_ptr, idx, IWL_CMD_QUEUE_NUM); 509 } 510#endif 511 txq->need_update = 1; 512 513 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl) 514 /* Set up entry in queue's byte count circular buffer */ 515 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); 516 517 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, 518 fix_size, PCI_DMA_BIDIRECTIONAL); 519 dma_unmap_addr_set(out_meta, mapping, phys_addr); 520 dma_unmap_len_set(out_meta, len, fix_size); 521 522 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags); 523 524 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, 525 phys_addr, fix_size, 1, 526 U32_PAD(cmd->len)); 527 528 /* Increment and update queue's write index */ 529 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); 530 iwl_txq_update_write_ptr(priv, txq); 531 532 spin_unlock_irqrestore(&priv->hcmd_lock, flags); 533 return idx; 534} 535 536/** 537 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd 538 * 539 * When FW advances 'R' index, all entries between old and new 'R' index 540 * need to be reclaimed. As result, some free space forms. If there is 541 * enough free space (> low mark), wake the stack that feeds us. 542 */ 543static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, 544 int idx, int cmd_idx) 545{ 546 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 547 struct iwl_queue *q = &txq->q; 548 int nfreed = 0; 549 550 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { 551 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " 552 "is out of range [0-%d] %d %d.\n", txq_id, 553 idx, q->n_bd, q->write_ptr, q->read_ptr); 554 return; 555 } 556 557 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; 558 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { 559 560 if (nfreed++ > 0) { 561 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, 562 q->write_ptr, q->read_ptr); 563 queue_work(priv->workqueue, &priv->restart); 564 } 565 566 } 567} 568 569/** 570 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them 571 * @rxb: Rx buffer to reclaim 572 * 573 * If an Rx buffer has an async callback associated with it the callback 574 * will be executed. The attached skb (if present) will only be freed 575 * if the callback returns 1 576 */ 577void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) 578{ 579 struct iwl_rx_packet *pkt = rxb_addr(rxb); 580 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 581 int txq_id = SEQ_TO_QUEUE(sequence); 582 int index = SEQ_TO_INDEX(sequence); 583 int cmd_index; 584 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); 585 struct iwl_device_cmd *cmd; 586 struct iwl_cmd_meta *meta; 587 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; 588 589 /* If a Tx command is being handled and it isn't in the actual 590 * command queue then there a command routing bug has been introduced 591 * in the queue management code. */ 592 if (WARN(txq_id != IWL_CMD_QUEUE_NUM, 593 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n", 594 txq_id, sequence, 595 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr, 596 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) { 597 iwl_print_hex_error(priv, pkt, 32); 598 return; 599 } 600 601 /* If this is a huge cmd, clear the huge flag on the meta.flags 602 * of the _original_ cmd. So that iwl_cmd_queue_free won't unmap 603 * the DMA buffer for the scan (huge) command. 604 */ 605 if (huge) { 606 cmd_index = get_cmd_index(&txq->q, index, 0); 607 txq->meta[cmd_index].flags = 0; 608 } 609 cmd_index = get_cmd_index(&txq->q, index, huge); 610 cmd = txq->cmd[cmd_index]; 611 meta = &txq->meta[cmd_index]; 612 613 pci_unmap_single(priv->pci_dev, 614 dma_unmap_addr(meta, mapping), 615 dma_unmap_len(meta, len), 616 PCI_DMA_BIDIRECTIONAL); 617 618 /* Input error checking is done when commands are added to queue. */ 619 if (meta->flags & CMD_WANT_SKB) { 620 meta->source->reply_page = (unsigned long)rxb_addr(rxb); 621 rxb->page = NULL; 622 } else if (meta->callback) 623 meta->callback(priv, cmd, pkt); 624 625 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); 626 627 if (!(meta->flags & CMD_ASYNC)) { 628 clear_bit(STATUS_HCMD_ACTIVE, &priv->status); 629 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n", 630 get_cmd_string(cmd->hdr.cmd)); 631 wake_up_interruptible(&priv->wait_command_queue); 632 } 633 meta->flags = 0; 634} 635EXPORT_SYMBOL(iwl_tx_cmd_complete); 636 637#ifdef CONFIG_IWLWIFI_DEBUG 638#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x 639#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x 640 641const char *iwl_get_tx_fail_reason(u32 status) 642{ 643 switch (status & TX_STATUS_MSK) { 644 case TX_STATUS_SUCCESS: 645 return "SUCCESS"; 646 TX_STATUS_POSTPONE(DELAY); 647 TX_STATUS_POSTPONE(FEW_BYTES); 648 TX_STATUS_POSTPONE(BT_PRIO); 649 TX_STATUS_POSTPONE(QUIET_PERIOD); 650 TX_STATUS_POSTPONE(CALC_TTAK); 651 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY); 652 TX_STATUS_FAIL(SHORT_LIMIT); 653 TX_STATUS_FAIL(LONG_LIMIT); 654 TX_STATUS_FAIL(FIFO_UNDERRUN); 655 TX_STATUS_FAIL(DRAIN_FLOW); 656 TX_STATUS_FAIL(RFKILL_FLUSH); 657 TX_STATUS_FAIL(LIFE_EXPIRE); 658 TX_STATUS_FAIL(DEST_PS); 659 TX_STATUS_FAIL(HOST_ABORTED); 660 TX_STATUS_FAIL(BT_RETRY); 661 TX_STATUS_FAIL(STA_INVALID); 662 TX_STATUS_FAIL(FRAG_DROPPED); 663 TX_STATUS_FAIL(TID_DISABLE); 664 TX_STATUS_FAIL(FIFO_FLUSHED); 665 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL); 666 TX_STATUS_FAIL(FW_DROP); 667 TX_STATUS_FAIL(STA_COLOR_MISMATCH_DROP); 668 } 669 670 return "UNKNOWN"; 671} 672EXPORT_SYMBOL(iwl_get_tx_fail_reason); 673#endif /* CONFIG_IWLWIFI_DEBUG */ 674