1/****************************************************************************** 2 * This software may be used and distributed according to the terms of 3 * the GNU General Public License (GPL), incorporated herein by reference. 4 * Drivers based on or derived from this code fall under the GPL and must 5 * retain the authorship, copyright and license notice. This file is not 6 * a complete program and may only be used when the entire operating 7 * system is licensed under the GPL. 8 * See the file COPYING in this distribution for more information. 9 * 10 * vxge-config.h: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O 11 * Virtualized Server Adapter. 12 * Copyright(c) 2002-2010 Exar Corp. 13 ******************************************************************************/ 14#ifndef VXGE_CONFIG_H 15#define VXGE_CONFIG_H 16#include <linux/list.h> 17#include <linux/slab.h> 18 19#ifndef VXGE_CACHE_LINE_SIZE 20#define VXGE_CACHE_LINE_SIZE 128 21#endif 22 23#define vxge_os_vaprintf(level, mask, fmt, ...) { \ 24 char buff[255]; \ 25 snprintf(buff, 255, fmt, __VA_ARGS__); \ 26 printk(buff); \ 27 printk("\n"); \ 28} 29 30#ifndef VXGE_ALIGN 31#define VXGE_ALIGN(adrs, size) \ 32 (((size) - (((u64)adrs) & ((size)-1))) & ((size)-1)) 33#endif 34 35#define VXGE_HW_MIN_MTU 68 36#define VXGE_HW_MAX_MTU 9600 37#define VXGE_HW_DEFAULT_MTU 1500 38 39#ifdef VXGE_DEBUG_ASSERT 40 41/** 42 * vxge_assert 43 * @test: C-condition to check 44 * @fmt: printf like format string 45 * 46 * This function implements traditional assert. By default assertions 47 * are enabled. It can be disabled by undefining VXGE_DEBUG_ASSERT macro in 48 * compilation 49 * time. 50 */ 51#define vxge_assert(test) { \ 52 if (!(test)) \ 53 vxge_os_bug("bad cond: "#test" at %s:%d\n", \ 54 __FILE__, __LINE__); } 55#else 56#define vxge_assert(test) 57#endif /* end of VXGE_DEBUG_ASSERT */ 58 59/** 60 * enum enum vxge_debug_level 61 * @VXGE_NONE: debug disabled 62 * @VXGE_ERR: all errors going to be logged out 63 * @VXGE_TRACE: all errors plus all kind of verbose tracing print outs 64 * going to be logged out. Very noisy. 65 * 66 * This enumeration going to be used to switch between different 67 * debug levels during runtime if DEBUG macro defined during 68 * compilation. If DEBUG macro not defined than code will be 69 * compiled out. 70 */ 71enum vxge_debug_level { 72 VXGE_NONE = 0, 73 VXGE_TRACE = 1, 74 VXGE_ERR = 2 75}; 76 77#define NULL_VPID 0xFFFFFFFF 78#ifdef CONFIG_VXGE_DEBUG_TRACE_ALL 79#define VXGE_DEBUG_MODULE_MASK 0xffffffff 80#define VXGE_DEBUG_TRACE_MASK 0xffffffff 81#define VXGE_DEBUG_ERR_MASK 0xffffffff 82#define VXGE_DEBUG_MASK 0x000001ff 83#else 84#define VXGE_DEBUG_MODULE_MASK 0x20000000 85#define VXGE_DEBUG_TRACE_MASK 0x20000000 86#define VXGE_DEBUG_ERR_MASK 0x20000000 87#define VXGE_DEBUG_MASK 0x00000001 88#endif 89 90/* 91 * @VXGE_COMPONENT_LL: do debug for vxge link layer module 92 * @VXGE_COMPONENT_ALL: activate debug for all modules with no exceptions 93 * 94 * This enumeration going to be used to distinguish modules 95 * or libraries during compilation and runtime. Makefile must declare 96 * VXGE_DEBUG_MODULE_MASK macro and set it to proper value. 97 */ 98#define VXGE_COMPONENT_LL 0x20000000 99#define VXGE_COMPONENT_ALL 0xffffffff 100 101#define VXGE_HW_BASE_INF 100 102#define VXGE_HW_BASE_ERR 200 103#define VXGE_HW_BASE_BADCFG 300 104 105enum vxge_hw_status { 106 VXGE_HW_OK = 0, 107 VXGE_HW_FAIL = 1, 108 VXGE_HW_PENDING = 2, 109 VXGE_HW_COMPLETIONS_REMAIN = 3, 110 111 VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS = VXGE_HW_BASE_INF + 1, 112 VXGE_HW_INF_OUT_OF_DESCRIPTORS = VXGE_HW_BASE_INF + 2, 113 114 VXGE_HW_ERR_INVALID_HANDLE = VXGE_HW_BASE_ERR + 1, 115 VXGE_HW_ERR_OUT_OF_MEMORY = VXGE_HW_BASE_ERR + 2, 116 VXGE_HW_ERR_VPATH_NOT_AVAILABLE = VXGE_HW_BASE_ERR + 3, 117 VXGE_HW_ERR_VPATH_NOT_OPEN = VXGE_HW_BASE_ERR + 4, 118 VXGE_HW_ERR_WRONG_IRQ = VXGE_HW_BASE_ERR + 5, 119 VXGE_HW_ERR_SWAPPER_CTRL = VXGE_HW_BASE_ERR + 6, 120 VXGE_HW_ERR_INVALID_MTU_SIZE = VXGE_HW_BASE_ERR + 7, 121 VXGE_HW_ERR_INVALID_INDEX = VXGE_HW_BASE_ERR + 8, 122 VXGE_HW_ERR_INVALID_TYPE = VXGE_HW_BASE_ERR + 9, 123 VXGE_HW_ERR_INVALID_OFFSET = VXGE_HW_BASE_ERR + 10, 124 VXGE_HW_ERR_INVALID_DEVICE = VXGE_HW_BASE_ERR + 11, 125 VXGE_HW_ERR_VERSION_CONFLICT = VXGE_HW_BASE_ERR + 12, 126 VXGE_HW_ERR_INVALID_PCI_INFO = VXGE_HW_BASE_ERR + 13, 127 VXGE_HW_ERR_INVALID_TCODE = VXGE_HW_BASE_ERR + 14, 128 VXGE_HW_ERR_INVALID_BLOCK_SIZE = VXGE_HW_BASE_ERR + 15, 129 VXGE_HW_ERR_INVALID_STATE = VXGE_HW_BASE_ERR + 16, 130 VXGE_HW_ERR_PRIVILAGED_OPEARATION = VXGE_HW_BASE_ERR + 17, 131 VXGE_HW_ERR_INVALID_PORT = VXGE_HW_BASE_ERR + 18, 132 VXGE_HW_ERR_FIFO = VXGE_HW_BASE_ERR + 19, 133 VXGE_HW_ERR_VPATH = VXGE_HW_BASE_ERR + 20, 134 VXGE_HW_ERR_CRITICAL = VXGE_HW_BASE_ERR + 21, 135 VXGE_HW_ERR_SLOT_FREEZE = VXGE_HW_BASE_ERR + 22, 136 137 VXGE_HW_BADCFG_RING_INDICATE_MAX_PKTS = VXGE_HW_BASE_BADCFG + 1, 138 VXGE_HW_BADCFG_FIFO_BLOCKS = VXGE_HW_BASE_BADCFG + 2, 139 VXGE_HW_BADCFG_VPATH_MTU = VXGE_HW_BASE_BADCFG + 3, 140 VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG = VXGE_HW_BASE_BADCFG + 4, 141 VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH = VXGE_HW_BASE_BADCFG + 5, 142 VXGE_HW_BADCFG_INTR_MODE = VXGE_HW_BASE_BADCFG + 6, 143 VXGE_HW_BADCFG_RTS_MAC_EN = VXGE_HW_BASE_BADCFG + 7, 144 145 VXGE_HW_EOF_TRACE_BUF = -1 146}; 147 148/** 149 * enum enum vxge_hw_device_link_state - Link state enumeration. 150 * @VXGE_HW_LINK_NONE: Invalid link state. 151 * @VXGE_HW_LINK_DOWN: Link is down. 152 * @VXGE_HW_LINK_UP: Link is up. 153 * 154 */ 155enum vxge_hw_device_link_state { 156 VXGE_HW_LINK_NONE, 157 VXGE_HW_LINK_DOWN, 158 VXGE_HW_LINK_UP 159}; 160 161/** 162 * struct vxge_hw_device_date - Date Format 163 * @day: Day 164 * @month: Month 165 * @year: Year 166 * @date: Date in string format 167 * 168 * Structure for returning date 169 */ 170 171#define VXGE_HW_FW_STRLEN 32 172struct vxge_hw_device_date { 173 u32 day; 174 u32 month; 175 u32 year; 176 char date[VXGE_HW_FW_STRLEN]; 177}; 178 179struct vxge_hw_device_version { 180 u32 major; 181 u32 minor; 182 u32 build; 183 char version[VXGE_HW_FW_STRLEN]; 184}; 185 186u64 187__vxge_hw_vpath_pci_func_mode_get( 188 u32 vp_id, 189 struct vxge_hw_vpath_reg __iomem *vpath_reg); 190 191/** 192 * struct vxge_hw_fifo_config - Configuration of fifo. 193 * @enable: Is this fifo to be commissioned 194 * @fifo_blocks: Numbers of TxDL (that is, lists of Tx descriptors) 195 * blocks per queue. 196 * @max_frags: Max number of Tx buffers per TxDL (that is, per single 197 * transmit operation). 198 * No more than 256 transmit buffers can be specified. 199 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 200 * bytes. Setting @memblock_size to page size ensures 201 * by-page allocation of descriptors. 128K bytes is the 202 * maximum supported block size. 203 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 204 * (e.g., to align on a cache line). 205 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 206 * Use 0 otherwise. 207 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 208 * which generally improves latency of the host bridge operation 209 * (see PCI specification). For valid values please refer 210 * to struct vxge_hw_fifo_config{} in the driver sources. 211 * Configuration of all Titan fifos. 212 * Note: Valid (min, max) range for each attribute is specified in the body of 213 * the struct vxge_hw_fifo_config{} structure. 214 */ 215struct vxge_hw_fifo_config { 216 u32 enable; 217#define VXGE_HW_FIFO_ENABLE 1 218#define VXGE_HW_FIFO_DISABLE 0 219 220 u32 fifo_blocks; 221#define VXGE_HW_MIN_FIFO_BLOCKS 2 222#define VXGE_HW_MAX_FIFO_BLOCKS 128 223 224 u32 max_frags; 225#define VXGE_HW_MIN_FIFO_FRAGS 1 226#define VXGE_HW_MAX_FIFO_FRAGS 256 227 228 u32 memblock_size; 229#define VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE VXGE_HW_BLOCK_SIZE 230#define VXGE_HW_MAX_FIFO_MEMBLOCK_SIZE 131072 231#define VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE 8096 232 233 u32 alignment_size; 234#define VXGE_HW_MIN_FIFO_ALIGNMENT_SIZE 0 235#define VXGE_HW_MAX_FIFO_ALIGNMENT_SIZE 65536 236#define VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE VXGE_CACHE_LINE_SIZE 237 238 u32 intr; 239#define VXGE_HW_FIFO_QUEUE_INTR_ENABLE 1 240#define VXGE_HW_FIFO_QUEUE_INTR_DISABLE 0 241#define VXGE_HW_FIFO_QUEUE_INTR_DEFAULT 0 242 243 u32 no_snoop_bits; 244#define VXGE_HW_FIFO_NO_SNOOP_DISABLED 0 245#define VXGE_HW_FIFO_NO_SNOOP_TXD 1 246#define VXGE_HW_FIFO_NO_SNOOP_FRM 2 247#define VXGE_HW_FIFO_NO_SNOOP_ALL 3 248#define VXGE_HW_FIFO_NO_SNOOP_DEFAULT 0 249 250}; 251/** 252 * struct vxge_hw_ring_config - Ring configurations. 253 * @enable: Is this ring to be commissioned 254 * @ring_blocks: Numbers of RxD blocks in the ring 255 * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer 256 * to Titan User Guide. 257 * @scatter_mode: Titan supports two receive scatter modes: A and B. 258 * For details please refer to Titan User Guide. 259 * @rx_timer_val: The number of 32ns periods that would be counted between two 260 * timer interrupts. 261 * @greedy_return: If Set it forces the device to return absolutely all RxD 262 * that are consumed and still on board when a timer interrupt 263 * triggers. If Clear, then if the device has already returned 264 * RxD before current timer interrupt trigerred and after the 265 * previous timer interrupt triggered, then the device is not 266 * forced to returned the rest of the consumed RxD that it has 267 * on board which account for a byte count less than the one 268 * programmed into PRC_CFG6.RXD_CRXDT field 269 * @rx_timer_ci: TBD 270 * @backoff_interval_us: Time (in microseconds), after which Titan 271 * tries to download RxDs posted by the host. 272 * Note that the "backoff" does not happen if host posts receive 273 * descriptors in the timely fashion. 274 * Ring configuration. 275 */ 276struct vxge_hw_ring_config { 277 u32 enable; 278#define VXGE_HW_RING_ENABLE 1 279#define VXGE_HW_RING_DISABLE 0 280#define VXGE_HW_RING_DEFAULT 1 281 282 u32 ring_blocks; 283#define VXGE_HW_MIN_RING_BLOCKS 1 284#define VXGE_HW_MAX_RING_BLOCKS 128 285#define VXGE_HW_DEF_RING_BLOCKS 2 286 287 u32 buffer_mode; 288#define VXGE_HW_RING_RXD_BUFFER_MODE_1 1 289#define VXGE_HW_RING_RXD_BUFFER_MODE_3 3 290#define VXGE_HW_RING_RXD_BUFFER_MODE_5 5 291#define VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT 1 292 293 u32 scatter_mode; 294#define VXGE_HW_RING_SCATTER_MODE_A 0 295#define VXGE_HW_RING_SCATTER_MODE_B 1 296#define VXGE_HW_RING_SCATTER_MODE_C 2 297#define VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT 0xffffffff 298 299 u64 rxds_limit; 300#define VXGE_HW_DEF_RING_RXDS_LIMIT 44 301}; 302 303/** 304 * struct vxge_hw_vp_config - Configuration of virtual path 305 * @vp_id: Virtual Path Id 306 * @min_bandwidth: Minimum Guaranteed bandwidth 307 * @ring: See struct vxge_hw_ring_config{}. 308 * @fifo: See struct vxge_hw_fifo_config{}. 309 * @tti: Configuration of interrupt associated with Transmit. 310 * see struct vxge_hw_tim_intr_config(); 311 * @rti: Configuration of interrupt associated with Receive. 312 * see struct vxge_hw_tim_intr_config(); 313 * @mtu: mtu size used on this port. 314 * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to 315 * remove the VLAN tag from all received tagged frames that are not 316 * replicated at the internal L2 switch. 317 * 0 - Do not strip the VLAN tag. 318 * 1 - Strip the VLAN tag. Regardless of this setting, VLAN tags are 319 * always placed into the RxDMA descriptor. 320 * 321 * This structure is used by the driver to pass the configuration parameters to 322 * configure Virtual Path. 323 */ 324struct vxge_hw_vp_config { 325 u32 vp_id; 326 327#define VXGE_HW_VPATH_PRIORITY_MIN 0 328#define VXGE_HW_VPATH_PRIORITY_MAX 16 329#define VXGE_HW_VPATH_PRIORITY_DEFAULT 0 330 331 u32 min_bandwidth; 332#define VXGE_HW_VPATH_BANDWIDTH_MIN 0 333#define VXGE_HW_VPATH_BANDWIDTH_MAX 100 334#define VXGE_HW_VPATH_BANDWIDTH_DEFAULT 0 335 336 struct vxge_hw_ring_config ring; 337 struct vxge_hw_fifo_config fifo; 338 struct vxge_hw_tim_intr_config tti; 339 struct vxge_hw_tim_intr_config rti; 340 341 u32 mtu; 342#define VXGE_HW_VPATH_MIN_INITIAL_MTU VXGE_HW_MIN_MTU 343#define VXGE_HW_VPATH_MAX_INITIAL_MTU VXGE_HW_MAX_MTU 344#define VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU 0xffffffff 345 346 u32 rpa_strip_vlan_tag; 347#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE 1 348#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE 0 349#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT 0xffffffff 350 351}; 352/** 353 * struct vxge_hw_device_config - Device configuration. 354 * @dma_blockpool_initial: Initial size of DMA Pool 355 * @dma_blockpool_max: Maximum blocks in DMA pool 356 * @intr_mode: Line, or MSI-X interrupt. 357 * 358 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 359 * @rth_it_type: RTH IT table programming type 360 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 361 * @vp_config: Configuration for virtual paths 362 * @device_poll_millis: Specify the interval (in mulliseconds) 363 * to wait for register reads 364 * 365 * Titan configuration. 366 * Contains per-device configuration parameters, including: 367 * - stats sampling interval, etc. 368 * 369 * In addition, struct vxge_hw_device_config{} includes "subordinate" 370 * configurations, including: 371 * - fifos and rings; 372 * - MAC (done at firmware level). 373 * 374 * See Titan User Guide for more details. 375 * Note: Valid (min, max) range for each attribute is specified in the body of 376 * the struct vxge_hw_device_config{} structure. Please refer to the 377 * corresponding include file. 378 * See also: struct vxge_hw_tim_intr_config{}. 379 */ 380struct vxge_hw_device_config { 381 u32 dma_blockpool_initial; 382 u32 dma_blockpool_max; 383#define VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE 0 384#define VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE 0 385#define VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE 4 386#define VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE 4096 387 388#define VXGE_HW_MAX_PAYLOAD_SIZE_512 2 389 390 u32 intr_mode; 391#define VXGE_HW_INTR_MODE_IRQLINE 0 392#define VXGE_HW_INTR_MODE_MSIX 1 393#define VXGE_HW_INTR_MODE_MSIX_ONE_SHOT 2 394 395#define VXGE_HW_INTR_MODE_DEF 0 396 397 u32 rth_en; 398#define VXGE_HW_RTH_DISABLE 0 399#define VXGE_HW_RTH_ENABLE 1 400#define VXGE_HW_RTH_DEFAULT 0 401 402 u32 rth_it_type; 403#define VXGE_HW_RTH_IT_TYPE_SOLO_IT 0 404#define VXGE_HW_RTH_IT_TYPE_MULTI_IT 1 405#define VXGE_HW_RTH_IT_TYPE_DEFAULT 0 406 407 u32 rts_mac_en; 408#define VXGE_HW_RTS_MAC_DISABLE 0 409#define VXGE_HW_RTS_MAC_ENABLE 1 410#define VXGE_HW_RTS_MAC_DEFAULT 0 411 412 struct vxge_hw_vp_config vp_config[VXGE_HW_MAX_VIRTUAL_PATHS]; 413 414 u32 device_poll_millis; 415#define VXGE_HW_MIN_DEVICE_POLL_MILLIS 1 416#define VXGE_HW_MAX_DEVICE_POLL_MILLIS 100000 417#define VXGE_HW_DEF_DEVICE_POLL_MILLIS 1000 418 419}; 420 421/** 422 * function vxge_uld_link_up_f - Link-Up callback provided by driver. 423 * @devh: HW device handle. 424 * Link-up notification callback provided by the driver. 425 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. 426 * 427 * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_down_f{}, 428 * vxge_hw_driver_initialize(). 429 */ 430 431/** 432 * function vxge_uld_link_down_f - Link-Down callback provided by 433 * driver. 434 * @devh: HW device handle. 435 * 436 * Link-Down notification callback provided by the driver. 437 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. 438 * 439 * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{}, 440 * vxge_hw_driver_initialize(). 441 */ 442 443/** 444 * function vxge_uld_crit_err_f - Critical Error notification callback. 445 * @devh: HW device handle. 446 * (typically - at HW device iinitialization time). 447 * @type: Enumerated hw error, e.g.: double ECC. 448 * @serr_data: Titan status. 449 * @ext_data: Extended data. The contents depends on the @type. 450 * 451 * Link-Down notification callback provided by the driver. 452 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. 453 * 454 * See also: struct vxge_hw_uld_cbs{}, enum vxge_hw_event{}, 455 * vxge_hw_driver_initialize(). 456 */ 457 458/** 459 * struct vxge_hw_uld_cbs - driver "slow-path" callbacks. 460 * @link_up: See vxge_uld_link_up_f{}. 461 * @link_down: See vxge_uld_link_down_f{}. 462 * @crit_err: See vxge_uld_crit_err_f{}. 463 * 464 * Driver slow-path (per-driver) callbacks. 465 * Implemented by driver and provided to HW via 466 * vxge_hw_driver_initialize(). 467 * Note that these callbacks are not mandatory: HW will not invoke 468 * a callback if NULL is specified. 469 * 470 * See also: vxge_hw_driver_initialize(). 471 */ 472struct vxge_hw_uld_cbs { 473 474 void (*link_up)(struct __vxge_hw_device *devh); 475 void (*link_down)(struct __vxge_hw_device *devh); 476 void (*crit_err)(struct __vxge_hw_device *devh, 477 enum vxge_hw_event type, u64 ext_data); 478}; 479 480/* 481 * struct __vxge_hw_blockpool_entry - Block private data structure 482 * @item: List header used to link. 483 * @length: Length of the block 484 * @memblock: Virtual address block 485 * @dma_addr: DMA Address of the block. 486 * @dma_handle: DMA handle of the block. 487 * @acc_handle: DMA acc handle 488 * 489 * Block is allocated with a header to put the blocks into list. 490 * 491 */ 492struct __vxge_hw_blockpool_entry { 493 struct list_head item; 494 u32 length; 495 void *memblock; 496 dma_addr_t dma_addr; 497 struct pci_dev *dma_handle; 498 struct pci_dev *acc_handle; 499}; 500 501/* 502 * struct __vxge_hw_blockpool - Block Pool 503 * @hldev: HW device 504 * @block_size: size of each block. 505 * @Pool_size: Number of blocks in the pool 506 * @pool_max: Maximum number of blocks above which to free additional blocks 507 * @req_out: Number of block requests with OS out standing 508 * @free_block_list: List of free blocks 509 * 510 * Block pool contains the DMA blocks preallocated. 511 * 512 */ 513struct __vxge_hw_blockpool { 514 struct __vxge_hw_device *hldev; 515 u32 block_size; 516 u32 pool_size; 517 u32 pool_max; 518 u32 req_out; 519 struct list_head free_block_list; 520 struct list_head free_entry_list; 521}; 522 523/* 524 * enum enum __vxge_hw_channel_type - Enumerated channel types. 525 * @VXGE_HW_CHANNEL_TYPE_UNKNOWN: Unknown channel. 526 * @VXGE_HW_CHANNEL_TYPE_FIFO: fifo. 527 * @VXGE_HW_CHANNEL_TYPE_RING: ring. 528 * @VXGE_HW_CHANNEL_TYPE_MAX: Maximum number of HW-supported 529 * (and recognized) channel types. Currently: 2. 530 * 531 * Enumerated channel types. Currently there are only two link-layer 532 * channels - Titan fifo and Titan ring. In the future the list will grow. 533 */ 534enum __vxge_hw_channel_type { 535 VXGE_HW_CHANNEL_TYPE_UNKNOWN = 0, 536 VXGE_HW_CHANNEL_TYPE_FIFO = 1, 537 VXGE_HW_CHANNEL_TYPE_RING = 2, 538 VXGE_HW_CHANNEL_TYPE_MAX = 3 539}; 540 541/* 542 * struct __vxge_hw_channel 543 * @item: List item; used to maintain a list of open channels. 544 * @type: Channel type. See enum vxge_hw_channel_type{}. 545 * @devh: Device handle. HW device object that contains _this_ channel. 546 * @vph: Virtual path handle. Virtual Path Object that contains _this_ channel. 547 * @length: Channel length. Currently allocated number of descriptors. 548 * The channel length "grows" when more descriptors get allocated. 549 * See _hw_mempool_grow. 550 * @reserve_arr: Reserve array. Contains descriptors that can be reserved 551 * by driver for the subsequent send or receive operation. 552 * See vxge_hw_fifo_txdl_reserve(), 553 * vxge_hw_ring_rxd_reserve(). 554 * @reserve_ptr: Current pointer in the resrve array 555 * @reserve_top: Reserve top gives the maximum number of dtrs available in 556 * reserve array. 557 * @work_arr: Work array. Contains descriptors posted to the channel. 558 * Note that at any point in time @work_arr contains 3 types of 559 * descriptors: 560 * 1) posted but not yet consumed by Titan device; 561 * 2) consumed but not yet completed; 562 * 3) completed but not yet freed 563 * (via vxge_hw_fifo_txdl_free() or vxge_hw_ring_rxd_free()) 564 * @post_index: Post index. At any point in time points on the 565 * position in the channel, which'll contain next to-be-posted 566 * descriptor. 567 * @compl_index: Completion index. At any point in time points on the 568 * position in the channel, which will contain next 569 * to-be-completed descriptor. 570 * @free_arr: Free array. Contains completed descriptors that were freed 571 * (i.e., handed over back to HW) by driver. 572 * See vxge_hw_fifo_txdl_free(), vxge_hw_ring_rxd_free(). 573 * @free_ptr: current pointer in free array 574 * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize 575 * to store per-operation control information. 576 * @stats: Pointer to common statistics 577 * @userdata: Per-channel opaque (void*) user-defined context, which may be 578 * driver object, ULP connection, etc. 579 * Once channel is open, @userdata is passed back to user via 580 * vxge_hw_channel_callback_f. 581 * 582 * HW channel object. 583 * 584 * See also: enum vxge_hw_channel_type{}, enum vxge_hw_channel_flag 585 */ 586struct __vxge_hw_channel { 587 struct list_head item; 588 enum __vxge_hw_channel_type type; 589 struct __vxge_hw_device *devh; 590 struct __vxge_hw_vpath_handle *vph; 591 u32 length; 592 u32 vp_id; 593 void **reserve_arr; 594 u32 reserve_ptr; 595 u32 reserve_top; 596 void **work_arr; 597 u32 post_index ____cacheline_aligned; 598 u32 compl_index ____cacheline_aligned; 599 void **free_arr; 600 u32 free_ptr; 601 void **orig_arr; 602 u32 per_dtr_space; 603 void *userdata; 604 struct vxge_hw_common_reg __iomem *common_reg; 605 u32 first_vp_id; 606 struct vxge_hw_vpath_stats_sw_common_info *stats; 607 608} ____cacheline_aligned; 609 610/* 611 * struct __vxge_hw_virtualpath - Virtual Path 612 * 613 * @vp_id: Virtual path id 614 * @vp_open: This flag specifies if vxge_hw_vp_open is called from LL Driver 615 * @hldev: Hal device 616 * @vp_config: Virtual Path Config 617 * @vp_reg: VPATH Register map address in BAR0 618 * @vpmgmt_reg: VPATH_MGMT register map address 619 * @max_mtu: Max mtu that can be supported 620 * @vsport_number: vsport attached to this vpath 621 * @max_kdfc_db: Maximum kernel mode doorbells 622 * @max_nofl_db: Maximum non offload doorbells 623 * @tx_intr_num: Interrupt Number associated with the TX 624 625 * @ringh: Ring Queue 626 * @fifoh: FIFO Queue 627 * @vpath_handles: Virtual Path handles list 628 * @stats_block: Memory for DMAing stats 629 * @stats: Vpath statistics 630 * 631 * Virtual path structure to encapsulate the data related to a virtual path. 632 * Virtual paths are allocated by the HW upon getting configuration from the 633 * driver and inserted into the list of virtual paths. 634 */ 635struct __vxge_hw_virtualpath { 636 u32 vp_id; 637 638 u32 vp_open; 639#define VXGE_HW_VP_NOT_OPEN 0 640#define VXGE_HW_VP_OPEN 1 641 642 struct __vxge_hw_device *hldev; 643 struct vxge_hw_vp_config *vp_config; 644 struct vxge_hw_vpath_reg __iomem *vp_reg; 645 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; 646 struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db; 647 648 u32 max_mtu; 649 u32 vsport_number; 650 u32 max_kdfc_db; 651 u32 max_nofl_db; 652 653 struct __vxge_hw_ring *____cacheline_aligned ringh; 654 struct __vxge_hw_fifo *____cacheline_aligned fifoh; 655 struct list_head vpath_handles; 656 struct __vxge_hw_blockpool_entry *stats_block; 657 struct vxge_hw_vpath_stats_hw_info *hw_stats; 658 struct vxge_hw_vpath_stats_hw_info *hw_stats_sav; 659 struct vxge_hw_vpath_stats_sw_info *sw_stats; 660}; 661 662/* 663 * struct __vxge_hw_vpath_handle - List item to store callback information 664 * @item: List head to keep the item in linked list 665 * @vpath: Virtual path to which this item belongs 666 * 667 * This structure is used to store the callback information. 668 */ 669struct __vxge_hw_vpath_handle{ 670 struct list_head item; 671 struct __vxge_hw_virtualpath *vpath; 672}; 673 674/* 675 * struct __vxge_hw_device 676 * 677 * HW device object. 678 */ 679/** 680 * struct __vxge_hw_device - Hal device object 681 * @magic: Magic Number 682 * @device_id: PCI Device Id of the adapter 683 * @major_revision: PCI Device major revision 684 * @minor_revision: PCI Device minor revision 685 * @bar0: BAR0 virtual address. 686 * @pdev: Physical device handle 687 * @config: Confguration passed by the LL driver at initialization 688 * @link_state: Link state 689 * 690 * HW device object. Represents Titan adapter 691 */ 692struct __vxge_hw_device { 693 u32 magic; 694#define VXGE_HW_DEVICE_MAGIC 0x12345678 695#define VXGE_HW_DEVICE_DEAD 0xDEADDEAD 696 u16 device_id; 697 u8 major_revision; 698 u8 minor_revision; 699 void __iomem *bar0; 700 struct pci_dev *pdev; 701 struct net_device *ndev; 702 struct vxge_hw_device_config config; 703 enum vxge_hw_device_link_state link_state; 704 705 struct vxge_hw_uld_cbs uld_callbacks; 706 707 u32 host_type; 708 u32 func_id; 709 u32 access_rights; 710#define VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH 0x1 711#define VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM 0x2 712#define VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM 0x4 713 struct vxge_hw_legacy_reg __iomem *legacy_reg; 714 struct vxge_hw_toc_reg __iomem *toc_reg; 715 struct vxge_hw_common_reg __iomem *common_reg; 716 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg; 717 struct vxge_hw_srpcim_reg __iomem *srpcim_reg \ 718 [VXGE_HW_TITAN_SRPCIM_REG_SPACES]; 719 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg \ 720 [VXGE_HW_TITAN_VPMGMT_REG_SPACES]; 721 struct vxge_hw_vpath_reg __iomem *vpath_reg \ 722 [VXGE_HW_TITAN_VPATH_REG_SPACES]; 723 u8 __iomem *kdfc; 724 u8 __iomem *usdc; 725 struct __vxge_hw_virtualpath virtual_paths \ 726 [VXGE_HW_MAX_VIRTUAL_PATHS]; 727 u64 vpath_assignments; 728 u64 vpaths_deployed; 729 u32 first_vp_id; 730 u64 tim_int_mask0[4]; 731 u32 tim_int_mask1[4]; 732 733 struct __vxge_hw_blockpool block_pool; 734 struct vxge_hw_device_stats stats; 735 u32 debug_module_mask; 736 u32 debug_level; 737 u32 level_err; 738 u32 level_trace; 739}; 740 741#define VXGE_HW_INFO_LEN 64 742/** 743 * struct vxge_hw_device_hw_info - Device information 744 * @host_type: Host Type 745 * @func_id: Function Id 746 * @vpath_mask: vpath bit mask 747 * @fw_version: Firmware version 748 * @fw_date: Firmware Date 749 * @flash_version: Firmware version 750 * @flash_date: Firmware Date 751 * @mac_addrs: Mac addresses for each vpath 752 * @mac_addr_masks: Mac address masks for each vpath 753 * 754 * Returns the vpath mask that has the bits set for each vpath allocated 755 * for the driver and the first mac address for each vpath 756 */ 757struct vxge_hw_device_hw_info { 758 u32 host_type; 759#define VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION 0 760#define VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION 1 761#define VXGE_HW_NO_MR_SR_VH0_FUNCTION0 2 762#define VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION 3 763#define VXGE_HW_MR_SR_VH0_INVALID_CONFIG 4 764#define VXGE_HW_SR_VH_FUNCTION0 5 765#define VXGE_HW_SR_VH_VIRTUAL_FUNCTION 6 766#define VXGE_HW_VH_NORMAL_FUNCTION 7 767 u64 function_mode; 768#define VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION 0 769#define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION 1 770#define VXGE_HW_FUNCTION_MODE_SRIOV 2 771#define VXGE_HW_FUNCTION_MODE_MRIOV 3 772#define VXGE_HW_FUNCTION_MODE_MRIOV_8 4 773#define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_17 5 774#define VXGE_HW_FUNCTION_MODE_SRIOV_8 6 775#define VXGE_HW_FUNCTION_MODE_SRIOV_4 7 776#define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_2 8 777#define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_4 9 778#define VXGE_HW_FUNCTION_MODE_MRIOV_4 10 779 780 u32 func_id; 781 u64 vpath_mask; 782 struct vxge_hw_device_version fw_version; 783 struct vxge_hw_device_date fw_date; 784 struct vxge_hw_device_version flash_version; 785 struct vxge_hw_device_date flash_date; 786 u8 serial_number[VXGE_HW_INFO_LEN]; 787 u8 part_number[VXGE_HW_INFO_LEN]; 788 u8 product_desc[VXGE_HW_INFO_LEN]; 789 u8 (mac_addrs)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN]; 790 u8 (mac_addr_masks)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN]; 791}; 792 793/** 794 * struct vxge_hw_device_attr - Device memory spaces. 795 * @bar0: BAR0 virtual address. 796 * @pdev: PCI device object. 797 * 798 * Device memory spaces. Includes configuration, BAR0 etc. per device 799 * mapped memories. Also, includes a pointer to OS-specific PCI device object. 800 */ 801struct vxge_hw_device_attr { 802 void __iomem *bar0; 803 struct pci_dev *pdev; 804 struct vxge_hw_uld_cbs uld_callbacks; 805}; 806 807#define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls) (hldev->link_state = ls) 808 809#define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i) { \ 810 if (i < 16) { \ 811 m0[0] |= vxge_vBIT(0x8, (i*4), 4); \ 812 m0[1] |= vxge_vBIT(0x4, (i*4), 4); \ 813 } \ 814 else { \ 815 m1[0] = 0x80000000; \ 816 m1[1] = 0x40000000; \ 817 } \ 818} 819 820#define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i) { \ 821 if (i < 16) { \ 822 m0[0] &= ~vxge_vBIT(0x8, (i*4), 4); \ 823 m0[1] &= ~vxge_vBIT(0x4, (i*4), 4); \ 824 } \ 825 else { \ 826 m1[0] = 0; \ 827 m1[1] = 0; \ 828 } \ 829} 830 831#define VXGE_HW_DEVICE_STATS_PIO_READ(loc, offset) { \ 832 status = vxge_hw_mrpcim_stats_access(hldev, \ 833 VXGE_HW_STATS_OP_READ, \ 834 loc, \ 835 offset, \ 836 &val64); \ 837 \ 838 if (status != VXGE_HW_OK) \ 839 return status; \ 840} 841 842#define VXGE_HW_VPATH_STATS_PIO_READ(offset) { \ 843 status = __vxge_hw_vpath_stats_access(vpath, \ 844 VXGE_HW_STATS_OP_READ, \ 845 offset, \ 846 &val64); \ 847 if (status != VXGE_HW_OK) \ 848 return status; \ 849} 850 851/* 852 * struct __vxge_hw_ring - Ring channel. 853 * @channel: Channel "base" of this ring, the common part of all HW 854 * channels. 855 * @mempool: Memory pool, the pool from which descriptors get allocated. 856 * (See vxge_hw_mm.h). 857 * @config: Ring configuration, part of device configuration 858 * (see struct vxge_hw_device_config{}). 859 * @ring_length: Length of the ring 860 * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, 861 * as per Titan User Guide. 862 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Titan spec, 863 * 1-buffer mode descriptor is 32 byte long, etc. 864 * @rxd_priv_size: Per RxD size reserved (by HW) for driver to keep 865 * per-descriptor data (e.g., DMA handle for Solaris) 866 * @per_rxd_space: Per rxd space requested by driver 867 * @rxds_per_block: Number of descriptors per hardware-defined RxD 868 * block. Depends on the (1-, 3-, 5-) buffer mode. 869 * @rxdblock_priv_size: Reserved at the end of each RxD block. HW internal 870 * usage. Not to confuse with @rxd_priv_size. 871 * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR. 872 * @callback: Channel completion callback. HW invokes the callback when there 873 * are new completions on that channel. In many implementations 874 * the @callback executes in the hw interrupt context. 875 * @rxd_init: Channel's descriptor-initialize callback. 876 * See vxge_hw_ring_rxd_init_f{}. 877 * If not NULL, HW invokes the callback when opening 878 * the ring. 879 * @rxd_term: Channel's descriptor-terminate callback. If not NULL, 880 * HW invokes the callback when closing the corresponding channel. 881 * See also vxge_hw_channel_rxd_term_f{}. 882 * @stats: Statistics for ring 883 * Ring channel. 884 * 885 * Note: The structure is cache line aligned to better utilize 886 * CPU cache performance. 887 */ 888struct __vxge_hw_ring { 889 struct __vxge_hw_channel channel; 890 struct vxge_hw_mempool *mempool; 891 struct vxge_hw_vpath_reg __iomem *vp_reg; 892 struct vxge_hw_common_reg __iomem *common_reg; 893 u32 ring_length; 894 u32 buffer_mode; 895 u32 rxd_size; 896 u32 rxd_priv_size; 897 u32 per_rxd_space; 898 u32 rxds_per_block; 899 u32 rxdblock_priv_size; 900 u32 cmpl_cnt; 901 u32 vp_id; 902 u32 doorbell_cnt; 903 u32 total_db_cnt; 904 u64 rxds_limit; 905 906 enum vxge_hw_status (*callback)( 907 struct __vxge_hw_ring *ringh, 908 void *rxdh, 909 u8 t_code, 910 void *userdata); 911 912 enum vxge_hw_status (*rxd_init)( 913 void *rxdh, 914 void *userdata); 915 916 void (*rxd_term)( 917 void *rxdh, 918 enum vxge_hw_rxd_state state, 919 void *userdata); 920 921 struct vxge_hw_vpath_stats_sw_ring_info *stats ____cacheline_aligned; 922 struct vxge_hw_ring_config *config; 923} ____cacheline_aligned; 924 925/** 926 * enum enum vxge_hw_txdl_state - Descriptor (TXDL) state. 927 * @VXGE_HW_TXDL_STATE_NONE: Invalid state. 928 * @VXGE_HW_TXDL_STATE_AVAIL: Descriptor is available for reservation. 929 * @VXGE_HW_TXDL_STATE_POSTED: Descriptor is posted for processing by the 930 * device. 931 * @VXGE_HW_TXDL_STATE_FREED: Descriptor is free and can be reused for 932 * filling-in and posting later. 933 * 934 * Titan/HW descriptor states. 935 * 936 */ 937enum vxge_hw_txdl_state { 938 VXGE_HW_TXDL_STATE_NONE = 0, 939 VXGE_HW_TXDL_STATE_AVAIL = 1, 940 VXGE_HW_TXDL_STATE_POSTED = 2, 941 VXGE_HW_TXDL_STATE_FREED = 3 942}; 943/* 944 * struct __vxge_hw_fifo - Fifo. 945 * @channel: Channel "base" of this fifo, the common part of all HW 946 * channels. 947 * @mempool: Memory pool, from which descriptors get allocated. 948 * @config: Fifo configuration, part of device configuration 949 * (see struct vxge_hw_device_config{}). 950 * @interrupt_type: Interrupt type to be used 951 * @no_snoop_bits: See struct vxge_hw_fifo_config{}. 952 * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock. 953 * on TxDL please refer to Titan UG. 954 * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus 955 * per-TxDL HW private space (struct __vxge_hw_fifo_txdl_priv). 956 * @priv_size: Per-Tx descriptor space reserved for driver 957 * usage. 958 * @per_txdl_space: Per txdl private space for the driver 959 * @callback: Fifo completion callback. HW invokes the callback when there 960 * are new completions on that fifo. In many implementations 961 * the @callback executes in the hw interrupt context. 962 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, 963 * HW invokes the callback when closing the corresponding fifo. 964 * See also vxge_hw_fifo_txdl_term_f{}. 965 * @stats: Statistics of this fifo 966 * 967 * Fifo channel. 968 * Note: The structure is cache line aligned. 969 */ 970struct __vxge_hw_fifo { 971 struct __vxge_hw_channel channel; 972 struct vxge_hw_mempool *mempool; 973 struct vxge_hw_fifo_config *config; 974 struct vxge_hw_vpath_reg __iomem *vp_reg; 975 struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db; 976 u64 interrupt_type; 977 u32 no_snoop_bits; 978 u32 txdl_per_memblock; 979 u32 txdl_size; 980 u32 priv_size; 981 u32 per_txdl_space; 982 u32 vp_id; 983 u32 tx_intr_num; 984 985 enum vxge_hw_status (*callback)( 986 struct __vxge_hw_fifo *fifo_handle, 987 void *txdlh, 988 enum vxge_hw_fifo_tcode t_code, 989 void *userdata, 990 struct sk_buff ***skb_ptr, 991 int nr_skb, 992 int *more); 993 994 void (*txdl_term)( 995 void *txdlh, 996 enum vxge_hw_txdl_state state, 997 void *userdata); 998 999 struct vxge_hw_vpath_stats_sw_fifo_info *stats ____cacheline_aligned; 1000} ____cacheline_aligned; 1001 1002/* 1003 * struct __vxge_hw_fifo_txdl_priv - Transmit descriptor HW-private data. 1004 * @dma_addr: DMA (mapped) address of _this_ descriptor. 1005 * @dma_handle: DMA handle used to map the descriptor onto device. 1006 * @dma_offset: Descriptor's offset in the memory block. HW allocates 1007 * descriptors in memory blocks (see struct vxge_hw_fifo_config{}) 1008 * Each memblock is a contiguous block of DMA-able memory. 1009 * @frags: Total number of fragments (that is, contiguous data buffers) 1010 * carried by this TxDL. 1011 * @align_vaddr_start: Aligned virtual address start 1012 * @align_vaddr: Virtual address of the per-TxDL area in memory used for 1013 * alignement. Used to place one or more mis-aligned fragments 1014 * @align_dma_addr: DMA address translated from the @align_vaddr. 1015 * @align_dma_handle: DMA handle that corresponds to @align_dma_addr. 1016 * @align_dma_acch: DMA access handle corresponds to @align_dma_addr. 1017 * @align_dma_offset: The current offset into the @align_vaddr area. 1018 * Grows while filling the descriptor, gets reset. 1019 * @align_used_frags: Number of fragments used. 1020 * @alloc_frags: Total number of fragments allocated. 1021 * @unused: TODO 1022 * @next_txdl_priv: (TODO). 1023 * @first_txdp: (TODO). 1024 * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous 1025 * TxDL list. 1026 * @txdlh: Corresponding txdlh to this TxDL. 1027 * @memblock: Pointer to the TxDL memory block or memory page. 1028 * on the next send operation. 1029 * @dma_object: DMA address and handle of the memory block that contains 1030 * the descriptor. This member is used only in the "checked" 1031 * version of the HW (to enforce certain assertions); 1032 * otherwise it gets compiled out. 1033 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 1034 * 1035 * Per-transmit decsriptor HW-private data. HW uses the space to keep DMA 1036 * information associated with the descriptor. Note that driver can ask HW 1037 * to allocate additional per-descriptor space for its own (driver-specific) 1038 * purposes. 1039 * 1040 * See also: struct vxge_hw_ring_rxd_priv{}. 1041 */ 1042struct __vxge_hw_fifo_txdl_priv { 1043 dma_addr_t dma_addr; 1044 struct pci_dev *dma_handle; 1045 ptrdiff_t dma_offset; 1046 u32 frags; 1047 u8 *align_vaddr_start; 1048 u8 *align_vaddr; 1049 dma_addr_t align_dma_addr; 1050 struct pci_dev *align_dma_handle; 1051 struct pci_dev *align_dma_acch; 1052 ptrdiff_t align_dma_offset; 1053 u32 align_used_frags; 1054 u32 alloc_frags; 1055 u32 unused; 1056 struct __vxge_hw_fifo_txdl_priv *next_txdl_priv; 1057 struct vxge_hw_fifo_txd *first_txdp; 1058 void *memblock; 1059}; 1060 1061/* 1062 * struct __vxge_hw_non_offload_db_wrapper - Non-offload Doorbell Wrapper 1063 * @control_0: Bits 0 to 7 - Doorbell type. 1064 * Bits 8 to 31 - Reserved. 1065 * Bits 32 to 39 - The highest TxD in this TxDL. 1066 * Bits 40 to 47 - Reserved. 1067 * Bits 48 to 55 - Reserved. 1068 * Bits 56 to 63 - No snoop flags. 1069 * @txdl_ptr: The starting location of the TxDL in host memory. 1070 * 1071 * Created by the host and written to the adapter via PIO to a Kernel Doorbell 1072 * FIFO. All non-offload doorbell wrapper fields must be written by the host as 1073 * part of a doorbell write. Consumed by the adapter but is not written by the 1074 * adapter. 1075 */ 1076struct __vxge_hw_non_offload_db_wrapper { 1077 u64 control_0; 1078#define VXGE_HW_NODBW_GET_TYPE(ctrl0) vxge_bVALn(ctrl0, 0, 8) 1079#define VXGE_HW_NODBW_TYPE(val) vxge_vBIT(val, 0, 8) 1080#define VXGE_HW_NODBW_TYPE_NODBW 0 1081 1082#define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0) vxge_bVALn(ctrl0, 32, 8) 1083#define VXGE_HW_NODBW_LAST_TXD_NUMBER(val) vxge_vBIT(val, 32, 8) 1084 1085#define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0) vxge_bVALn(ctrl0, 56, 8) 1086#define VXGE_HW_NODBW_LIST_NO_SNOOP(val) vxge_vBIT(val, 56, 8) 1087#define VXGE_HW_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE 0x2 1088#define VXGE_HW_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ 0x1 1089 1090 u64 txdl_ptr; 1091}; 1092 1093/* 1094 * TX Descriptor 1095 */ 1096 1097/** 1098 * struct vxge_hw_fifo_txd - Transmit Descriptor 1099 * @control_0: Bits 0 to 6 - Reserved. 1100 * Bit 7 - List Ownership. This field should be initialized 1101 * to '1' by the driver before the transmit list pointer is 1102 * written to the adapter. This field will be set to '0' by the 1103 * adapter once it has completed transmitting the frame or frames in 1104 * the list. Note - This field is only valid in TxD0. Additionally, 1105 * for multi-list sequences, the driver should not release any 1106 * buffers until the ownership of the last list in the multi-list 1107 * sequence has been returned to the host. 1108 * Bits 8 to 11 - Reserved 1109 * Bits 12 to 15 - Transfer_Code. This field is only valid in 1110 * TxD0. It is used to describe the status of the transmit data 1111 * buffer transfer. This field is always overwritten by the 1112 * adapter, so this field may be initialized to any value. 1113 * Bits 16 to 17 - Host steering. This field allows the host to 1114 * override the selection of the physical transmit port. 1115 * Attention: 1116 * Normal sounds as if learned from the switch rather than from 1117 * the aggregation algorythms. 1118 * 00: Normal. Use Destination/MAC Address 1119 * lookup to determine the transmit port. 1120 * 01: Send on physical Port1. 1121 * 10: Send on physical Port0. 1122 * 11: Send on both ports. 1123 * Bits 18 to 21 - Reserved 1124 * Bits 22 to 23 - Gather_Code. This field is set by the host and 1125 * is used to describe how individual buffers comprise a frame. 1126 * 10: First descriptor of a frame. 1127 * 00: Middle of a multi-descriptor frame. 1128 * 01: Last descriptor of a frame. 1129 * 11: First and last descriptor of a frame (the entire frame 1130 * resides in a single buffer). 1131 * For multi-descriptor frames, the only valid gather code sequence 1132 * is {10, [00], 01}. In other words, the descriptors must be placed 1133 * in the list in the correct order. 1134 * Bits 24 to 27 - Reserved 1135 * Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation 1136 * definition. Only valid in TxD0. This field allows the host to 1137 * indicate the Ethernet encapsulation of an outbound LSO packet. 1138 * 00 - classic mode (best guess) 1139 * 01 - LLC 1140 * 10 - SNAP 1141 * 11 - DIX 1142 * If "classic mode" is selected, the adapter will attempt to 1143 * decode the frame's Ethernet encapsulation by examining the L/T 1144 * field as follows: 1145 * <= 0x05DC LLC/SNAP encoding; must examine DSAP/SSAP to determine 1146 * if packet is IPv4 or IPv6. 1147 * 0x8870 Jumbo-SNAP encoding. 1148 * 0x0800 IPv4 DIX encoding 1149 * 0x86DD IPv6 DIX encoding 1150 * others illegal encapsulation 1151 * Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag. 1152 * Set to 1 to perform segmentation offload for TCP/UDP. 1153 * This field is valid only in TxD0. 1154 * Bits 31 to 33 - Reserved. 1155 * Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size 1156 * This field is meaningful only when LSO_Control is non-zero. 1157 * When LSO_Control is set to TCP_LSO, the single (possibly large) 1158 * TCP segment described by this TxDL will be sent as a series of 1159 * TCP segments each of which contains no more than LSO_MSS 1160 * payload bytes. 1161 * When LSO_Control is set to UDP_LSO, the single (possibly large) 1162 * UDP datagram described by this TxDL will be sent as a series of 1163 * UDP datagrams each of which contains no more than LSO_MSS 1164 * payload bytes. 1165 * All outgoing frames from this TxDL will have LSO_MSS bytes of UDP 1166 * or TCP payload, with the exception of the last, which will have 1167 * <= LSO_MSS bytes of payload. 1168 * Bits 48 to 63 - Buffer_Size. Number of valid bytes in the 1169 * buffer to be read by the adapter. This field is written by the 1170 * host. A value of 0 is illegal. 1171 * Bits 32 to 63 - This value is written by the adapter upon 1172 * completion of a UDP or TCP LSO operation and indicates the number 1173 * of UDP or TCP payload bytes that were transmitted. 0x0000 will be 1174 * returned for any non-LSO operation. 1175 * @control_1: Bits 0 to 4 - Reserved. 1176 * Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum 1177 * offload. This field is only valid in the first TxD of a frame. 1178 * Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload. 1179 * This field is only valid in the first TxD of a frame (the TxD's 1180 * gather code must be 10 or 11). The driver should only set this 1181 * bit if it can guarantee that TCP is present. 1182 * Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload. 1183 * This field is only valid in the first TxD of a frame (the TxD's 1184 * gather code must be 10 or 11). The driver should only set this 1185 * bit if it can guarantee that UDP is present. 1186 * Bits 8 to 14 - Reserved. 1187 * Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to 1188 * instruct the adapter to insert the VLAN tag specified by the 1189 * Tx_VLAN_Tag field. This field is only valid in the first TxD of 1190 * a frame. 1191 * Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag 1192 * to be inserted into the frame by the adapter (the first two bytes 1193 * of a VLAN tag are always 0x8100). This field is only valid if the 1194 * Tx_VLAN_Enable field is set to '1'. 1195 * Bits 32 to 33 - Reserved. 1196 * Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt 1197 * number the frame associated with. This field is written by the 1198 * host. It is only valid in the first TxD of a frame. 1199 * Bits 40 to 42 - Reserved. 1200 * Bit 43 - Set to 1 to exclude the frame from bandwidth metering 1201 * functions. This field is valid only in the first TxD 1202 * of a frame. 1203 * Bits 44 to 45 - Reserved. 1204 * Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to 1205 * generate an interrupt as soon as all of the frames in the list 1206 * have been transmitted. In order to have per-frame interrupts, 1207 * the driver should place a maximum of one frame per list. This 1208 * field is only valid in the first TxD of a frame. 1209 * Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter 1210 * to count the frame toward the utilization interrupt specified in 1211 * the Tx_Int_Number field. This field is only valid in the first 1212 * TxD of a frame. 1213 * Bits 48 to 63 - Reserved. 1214 * @buffer_pointer: Buffer start address. 1215 * @host_control: Host_Control.Opaque 64bit data stored by driver inside the 1216 * Titan descriptor prior to posting the latter on the fifo 1217 * via vxge_hw_fifo_txdl_post().The %host_control is returned as is 1218 * to the driver with each completed descriptor. 1219 * 1220 * Transmit descriptor (TxD).Fifo descriptor contains configured number 1221 * (list) of TxDs. * For more details please refer to Titan User Guide, 1222 * Section 5.4.2 "Transmit Descriptor (TxD) Format". 1223 */ 1224struct vxge_hw_fifo_txd { 1225 u64 control_0; 1226#define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER vxge_mBIT(7) 1227 1228#define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) 1229#define VXGE_HW_FIFO_TXD_T_CODE(val) vxge_vBIT(val, 12, 4) 1230#define VXGE_HW_FIFO_TXD_T_CODE_UNUSED VXGE_HW_FIFO_T_CODE_UNUSED 1231 1232 1233#define VXGE_HW_FIFO_TXD_GATHER_CODE(val) vxge_vBIT(val, 22, 2) 1234#define VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST VXGE_HW_FIFO_GATHER_CODE_FIRST 1235#define VXGE_HW_FIFO_TXD_GATHER_CODE_LAST VXGE_HW_FIFO_GATHER_CODE_LAST 1236 1237 1238#define VXGE_HW_FIFO_TXD_LSO_EN vxge_mBIT(30) 1239 1240#define VXGE_HW_FIFO_TXD_LSO_MSS(val) vxge_vBIT(val, 34, 14) 1241 1242#define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val) vxge_vBIT(val, 48, 16) 1243 1244 u64 control_1; 1245#define VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN vxge_mBIT(5) 1246#define VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN vxge_mBIT(6) 1247#define VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN vxge_mBIT(7) 1248#define VXGE_HW_FIFO_TXD_VLAN_ENABLE vxge_mBIT(15) 1249 1250#define VXGE_HW_FIFO_TXD_VLAN_TAG(val) vxge_vBIT(val, 16, 16) 1251 1252#define VXGE_HW_FIFO_TXD_INT_NUMBER(val) vxge_vBIT(val, 34, 6) 1253 1254#define VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST vxge_mBIT(46) 1255#define VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ vxge_mBIT(47) 1256 1257 u64 buffer_pointer; 1258 1259 u64 host_control; 1260}; 1261 1262/** 1263 * struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring 1264 * @host_control: This field is exclusively for host use and is "readonly" 1265 * from the adapter's perspective. 1266 * @control_0:Bits 0 to 6 - RTH_Bucket get 1267 * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 1268 * by the host, and is set to 0 by the adapter. 1269 * 0 - Host owns RxD and buffer. 1270 * 1 - The adapter owns RxD and buffer. 1271 * Bit 8 - Fast_Path_Eligible When set, indicates that the 1272 * received frame meets all of the criteria for fast path processing. 1273 * The required criteria are as follows: 1274 * !SYN & 1275 * (Transfer_Code == "Transfer OK") & 1276 * (!Is_IP_Fragment) & 1277 * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | 1278 * (Is_IPv6)) & 1279 * ((Is_TCP & computed_L4_checksum == 0xFFFF) | 1280 * (Is_UDP & (computed_L4_checksum == 0xFFFF | 1281 * computed _L4_checksum == 0x0000))) 1282 * (same meaning for all RxD buffer modes) 1283 * Bit 9 - L3 Checksum Correct 1284 * Bit 10 - L4 Checksum Correct 1285 * Bit 11 - Reserved 1286 * Bit 12 to 15 - This field is written by the adapter. It is 1287 * used to report the status of the frame transfer to the host. 1288 * 0x0 - Transfer OK 1289 * 0x4 - RDA Failure During Transfer 1290 * 0x5 - Unparseable Packet, such as unknown IPv6 header. 1291 * 0x6 - Frame integrity error (FCS or ECC). 1292 * 0x7 - Buffer Size Error. The provided buffer(s) were not 1293 * appropriately sized and data loss occurred. 1294 * 0x8 - Internal ECC Error. RxD corrupted. 1295 * 0x9 - IPv4 Checksum error 1296 * 0xA - TCP/UDP Checksum error 1297 * 0xF - Unknown Error or Multiple Error. Indicates an 1298 * unknown problem or that more than one of transfer codes is set. 1299 * Bit 16 - SYN The adapter sets this field to indicate that 1300 * the incoming frame contained a TCP segment with its SYN bit 1301 * set and its ACK bit NOT set. (same meaning for all RxD buffer 1302 * modes) 1303 * Bit 17 - Is ICMP 1304 * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the 1305 * Socket Pair Direct Match Table and the frame was steered based 1306 * on SPDM. 1307 * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the 1308 * Indirection Table and the frame was steered based on hash 1309 * indirection. 1310 * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash 1311 * type) that was used to calculate the hash. 1312 * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN 1313 * tagged. 1314 * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation 1315 * of the received frame. 1316 * 0x0 - Ethernet DIX 1317 * 0x1 - LLC 1318 * 0x2 - SNAP (includes Jumbo-SNAP) 1319 * 0x3 - IPX 1320 * Bit 27 - IS_IPV4 Set to '1' if the frame contains an IPv4 packet. 1321 * Bit 28 - IS_IPV6 Set to '1' if the frame contains an IPv6 packet. 1322 * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a fragmented 1323 * IP packet. 1324 * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. 1325 * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. 1326 * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that 1327 * arrived with the frame. If the resulting computed IPv4 header 1328 * checksum for the frame did not produce the expected 0xFFFF value, 1329 * then the transfer code would be set to 0x9. 1330 * Bit 48 to 63 - L4_Checksum[0:15] The TCP/UDP checksum value that 1331 * arrived with the frame. If the resulting computed TCP/UDP checksum 1332 * for the frame did not produce the expected 0xFFFF value, then the 1333 * transfer code would be set to 0xA. 1334 * @control_1:Bits 0 to 1 - Reserved 1335 * Bits 2 to 15 - Buffer0_Size.This field is set by the host and 1336 * eventually overwritten by the adapter. The host writes the 1337 * available buffer size in bytes when it passes the descriptor to 1338 * the adapter. When a frame is delivered the host, the adapter 1339 * populates this field with the number of bytes written into the 1340 * buffer. The largest supported buffer is 16, 383 bytes. 1341 * Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid if 1342 * RTH_HASH_TYPE (Control_0, bits 20:23) is nonzero. 1343 * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable portion 1344 * of the VLAN tag, if one was detected by the adapter. This field is 1345 * populated even if VLAN-tag stripping is enabled. 1346 * @buffer0_ptr: Pointer to buffer. This field is populated by the driver. 1347 * 1348 * One buffer mode RxD for ring structure 1349 */ 1350struct vxge_hw_ring_rxd_1 { 1351 u64 host_control; 1352 u64 control_0; 1353#define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0) vxge_bVALn(ctrl0, 0, 7) 1354 1355#define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER vxge_mBIT(7) 1356 1357#define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) vxge_bVALn(ctrl0, 8, 1) 1358 1359#define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 9, 1) 1360 1361#define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 10, 1) 1362 1363#define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) 1364#define VXGE_HW_RING_RXD_T_CODE(val) vxge_vBIT(val, 12, 4) 1365 1366#define VXGE_HW_RING_RXD_T_CODE_UNUSED VXGE_HW_RING_T_CODE_UNUSED 1367 1368#define VXGE_HW_RING_RXD_SYN_GET(ctrl0) vxge_bVALn(ctrl0, 16, 1) 1369 1370#define VXGE_HW_RING_RXD_IS_ICMP_GET(ctrl0) vxge_bVALn(ctrl0, 17, 1) 1371 1372#define VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 18, 1) 1373 1374#define VXGE_HW_RING_RXD_RTH_IT_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 19, 1) 1375 1376#define VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) vxge_bVALn(ctrl0, 20, 4) 1377 1378#define VXGE_HW_RING_RXD_IS_VLAN_GET(ctrl0) vxge_bVALn(ctrl0, 24, 1) 1379 1380#define VXGE_HW_RING_RXD_ETHER_ENCAP_GET(ctrl0) vxge_bVALn(ctrl0, 25, 2) 1381 1382#define VXGE_HW_RING_RXD_FRAME_PROTO_GET(ctrl0) vxge_bVALn(ctrl0, 27, 5) 1383 1384#define VXGE_HW_RING_RXD_L3_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 32, 16) 1385 1386#define VXGE_HW_RING_RXD_L4_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 48, 16) 1387 1388 u64 control_1; 1389 1390#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) vxge_bVALn(ctrl1, 2, 14) 1391#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val) vxge_vBIT(val, 2, 14) 1392#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK vxge_vBIT(0x3FFF, 2, 14) 1393 1394#define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) vxge_bVALn(ctrl1, 16, 32) 1395 1396#define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1) vxge_bVALn(ctrl1, 48, 16) 1397 1398 u64 buffer0_ptr; 1399}; 1400 1401enum vxge_hw_rth_algoritms { 1402 RTH_ALG_JENKINS = 0, 1403 RTH_ALG_MS_RSS = 1, 1404 RTH_ALG_CRC32C = 2 1405}; 1406 1407/** 1408 * struct vxge_hw_rth_hash_types - RTH hash types. 1409 * @hash_type_tcpipv4_en: Enables RTH field type HashTypeTcpIPv4 1410 * @hash_type_ipv4_en: Enables RTH field type HashTypeIPv4 1411 * @hash_type_tcpipv6_en: Enables RTH field type HashTypeTcpIPv6 1412 * @hash_type_ipv6_en: Enables RTH field type HashTypeIPv6 1413 * @hash_type_tcpipv6ex_en: Enables RTH field type HashTypeTcpIPv6Ex 1414 * @hash_type_ipv6ex_en: Enables RTH field type HashTypeIPv6Ex 1415 * 1416 * Used to pass RTH hash types to rts_rts_set. 1417 * 1418 * See also: vxge_hw_vpath_rts_rth_set(), vxge_hw_vpath_rts_rth_get(). 1419 */ 1420struct vxge_hw_rth_hash_types { 1421 u8 hash_type_tcpipv4_en; 1422 u8 hash_type_ipv4_en; 1423 u8 hash_type_tcpipv6_en; 1424 u8 hash_type_ipv6_en; 1425 u8 hash_type_tcpipv6ex_en; 1426 u8 hash_type_ipv6ex_en; 1427}; 1428 1429u32 1430vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh); 1431 1432void vxge_hw_device_debug_set( 1433 struct __vxge_hw_device *devh, 1434 enum vxge_debug_level level, 1435 u32 mask); 1436 1437u32 1438vxge_hw_device_error_level_get(struct __vxge_hw_device *devh); 1439 1440u32 1441vxge_hw_device_trace_level_get(struct __vxge_hw_device *devh); 1442 1443u32 1444vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh); 1445 1446/** 1447 * vxge_hw_ring_rxd_size_get - Get the size of ring descriptor. 1448 * @buf_mode: Buffer mode (1, 3 or 5) 1449 * 1450 * This function returns the size of RxD for given buffer mode 1451 */ 1452static inline u32 vxge_hw_ring_rxd_size_get(u32 buf_mode) 1453{ 1454 return sizeof(struct vxge_hw_ring_rxd_1); 1455} 1456 1457/** 1458 * vxge_hw_ring_rxds_per_block_get - Get the number of rxds per block. 1459 * @buf_mode: Buffer mode (1 buffer mode only) 1460 * 1461 * This function returns the number of RxD for RxD block for given buffer mode 1462 */ 1463static inline u32 vxge_hw_ring_rxds_per_block_get(u32 buf_mode) 1464{ 1465 return (u32)((VXGE_HW_BLOCK_SIZE-16) / 1466 sizeof(struct vxge_hw_ring_rxd_1)); 1467} 1468 1469/** 1470 * vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor. 1471 * @rxdh: Descriptor handle. 1472 * @dma_pointer: DMA address of a single receive buffer this descriptor 1473 * should carry. Note that by the time vxge_hw_ring_rxd_1b_set is called, 1474 * the receive buffer should be already mapped to the device 1475 * @size: Size of the receive @dma_pointer buffer. 1476 * 1477 * Prepare 1-buffer-mode Rx descriptor for posting 1478 * (via vxge_hw_ring_rxd_post()). 1479 * 1480 * This inline helper-function does not return any parameters and always 1481 * succeeds. 1482 * 1483 */ 1484static inline 1485void vxge_hw_ring_rxd_1b_set( 1486 void *rxdh, 1487 dma_addr_t dma_pointer, 1488 u32 size) 1489{ 1490 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; 1491 rxdp->buffer0_ptr = dma_pointer; 1492 rxdp->control_1 &= ~VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK; 1493 rxdp->control_1 |= VXGE_HW_RING_RXD_1_BUFFER0_SIZE(size); 1494} 1495 1496/** 1497 * vxge_hw_ring_rxd_1b_get - Get data from the completed 1-buf 1498 * descriptor. 1499 * @vpath_handle: Virtual Path handle. 1500 * @rxdh: Descriptor handle. 1501 * @dma_pointer: DMA address of a single receive buffer this descriptor 1502 * carries. Returned by HW. 1503 * @pkt_length: Length (in bytes) of the data in the buffer pointed by 1504 * 1505 * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor. 1506 * This inline helper-function uses completed descriptor to populate receive 1507 * buffer pointer and other "out" parameters. The function always succeeds. 1508 * 1509 */ 1510static inline 1511void vxge_hw_ring_rxd_1b_get( 1512 struct __vxge_hw_ring *ring_handle, 1513 void *rxdh, 1514 u32 *pkt_length) 1515{ 1516 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; 1517 1518 *pkt_length = 1519 (u32)VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1); 1520} 1521 1522/** 1523 * vxge_hw_ring_rxd_1b_info_get - Get extended information associated with 1524 * a completed receive descriptor for 1b mode. 1525 * @vpath_handle: Virtual Path handle. 1526 * @rxdh: Descriptor handle. 1527 * @rxd_info: Descriptor information 1528 * 1529 * Retrieve extended information associated with a completed receive descriptor. 1530 * 1531 */ 1532static inline 1533void vxge_hw_ring_rxd_1b_info_get( 1534 struct __vxge_hw_ring *ring_handle, 1535 void *rxdh, 1536 struct vxge_hw_ring_rxd_info *rxd_info) 1537{ 1538 1539 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; 1540 rxd_info->syn_flag = 1541 (u32)VXGE_HW_RING_RXD_SYN_GET(rxdp->control_0); 1542 rxd_info->is_icmp = 1543 (u32)VXGE_HW_RING_RXD_IS_ICMP_GET(rxdp->control_0); 1544 rxd_info->fast_path_eligible = 1545 (u32)VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0); 1546 rxd_info->l3_cksum_valid = 1547 (u32)VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0); 1548 rxd_info->l3_cksum = 1549 (u32)VXGE_HW_RING_RXD_L3_CKSUM_GET(rxdp->control_0); 1550 rxd_info->l4_cksum_valid = 1551 (u32)VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0); 1552 rxd_info->l4_cksum = 1553 (u32)VXGE_HW_RING_RXD_L4_CKSUM_GET(rxdp->control_0); 1554 rxd_info->frame = 1555 (u32)VXGE_HW_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0); 1556 rxd_info->proto = 1557 (u32)VXGE_HW_RING_RXD_FRAME_PROTO_GET(rxdp->control_0); 1558 rxd_info->is_vlan = 1559 (u32)VXGE_HW_RING_RXD_IS_VLAN_GET(rxdp->control_0); 1560 rxd_info->vlan = 1561 (u32)VXGE_HW_RING_RXD_VLAN_TAG_GET(rxdp->control_1); 1562 rxd_info->rth_bucket = 1563 (u32)VXGE_HW_RING_RXD_RTH_BUCKET_GET(rxdp->control_0); 1564 rxd_info->rth_it_hit = 1565 (u32)VXGE_HW_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0); 1566 rxd_info->rth_spdm_hit = 1567 (u32)VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0); 1568 rxd_info->rth_hash_type = 1569 (u32)VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0); 1570 rxd_info->rth_value = 1571 (u32)VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1); 1572} 1573 1574/** 1575 * vxge_hw_ring_rxd_private_get - Get driver private per-descriptor data 1576 * of 1b mode 3b mode ring. 1577 * @rxdh: Descriptor handle. 1578 * 1579 * Returns: private driver info associated with the descriptor. 1580 * driver requests per-descriptor space via vxge_hw_ring_attr. 1581 * 1582 */ 1583static inline void *vxge_hw_ring_rxd_private_get(void *rxdh) 1584{ 1585 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; 1586 return (void *)(size_t)rxdp->host_control; 1587} 1588 1589/** 1590 * vxge_hw_fifo_txdl_cksum_set_bits - Offload checksum. 1591 * @txdlh: Descriptor handle. 1592 * @cksum_bits: Specifies which checksums are to be offloaded: IPv4, 1593 * and/or TCP and/or UDP. 1594 * 1595 * Ask Titan to calculate IPv4 & transport checksums for _this_ transmit 1596 * descriptor. 1597 * This API is part of the preparation of the transmit descriptor for posting 1598 * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include 1599 * vxge_hw_fifo_txdl_mss_set(), vxge_hw_fifo_txdl_buffer_set_aligned(), 1600 * and vxge_hw_fifo_txdl_buffer_set(). 1601 * All these APIs fill in the fields of the fifo descriptor, 1602 * in accordance with the Titan specification. 1603 * 1604 */ 1605static inline void vxge_hw_fifo_txdl_cksum_set_bits(void *txdlh, u64 cksum_bits) 1606{ 1607 struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; 1608 txdp->control_1 |= cksum_bits; 1609} 1610 1611/** 1612 * vxge_hw_fifo_txdl_mss_set - Set MSS. 1613 * @txdlh: Descriptor handle. 1614 * @mss: MSS size for _this_ TCP connection. Passed by TCP stack down to the 1615 * driver, which in turn inserts the MSS into the @txdlh. 1616 * 1617 * This API is part of the preparation of the transmit descriptor for posting 1618 * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include 1619 * vxge_hw_fifo_txdl_buffer_set(), vxge_hw_fifo_txdl_buffer_set_aligned(), 1620 * and vxge_hw_fifo_txdl_cksum_set_bits(). 1621 * All these APIs fill in the fields of the fifo descriptor, 1622 * in accordance with the Titan specification. 1623 * 1624 */ 1625static inline void vxge_hw_fifo_txdl_mss_set(void *txdlh, int mss) 1626{ 1627 struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; 1628 1629 txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_EN; 1630 txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_MSS(mss); 1631} 1632 1633/** 1634 * vxge_hw_fifo_txdl_vlan_set - Set VLAN tag. 1635 * @txdlh: Descriptor handle. 1636 * @vlan_tag: 16bit VLAN tag. 1637 * 1638 * Insert VLAN tag into specified transmit descriptor. 1639 * The actual insertion of the tag into outgoing frame is done by the hardware. 1640 */ 1641static inline void vxge_hw_fifo_txdl_vlan_set(void *txdlh, u16 vlan_tag) 1642{ 1643 struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; 1644 1645 txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_ENABLE; 1646 txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_TAG(vlan_tag); 1647} 1648 1649/** 1650 * vxge_hw_fifo_txdl_private_get - Retrieve per-descriptor private data. 1651 * @txdlh: Descriptor handle. 1652 * 1653 * Retrieve per-descriptor private data. 1654 * Note that driver requests per-descriptor space via 1655 * struct vxge_hw_fifo_attr passed to 1656 * vxge_hw_vpath_open(). 1657 * 1658 * Returns: private driver data associated with the descriptor. 1659 */ 1660static inline void *vxge_hw_fifo_txdl_private_get(void *txdlh) 1661{ 1662 struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; 1663 1664 return (void *)(size_t)txdp->host_control; 1665} 1666 1667/** 1668 * struct vxge_hw_ring_attr - Ring open "template". 1669 * @callback: Ring completion callback. HW invokes the callback when there 1670 * are new completions on that ring. In many implementations 1671 * the @callback executes in the hw interrupt context. 1672 * @rxd_init: Ring's descriptor-initialize callback. 1673 * See vxge_hw_ring_rxd_init_f{}. 1674 * If not NULL, HW invokes the callback when opening 1675 * the ring. 1676 * @rxd_term: Ring's descriptor-terminate callback. If not NULL, 1677 * HW invokes the callback when closing the corresponding ring. 1678 * See also vxge_hw_ring_rxd_term_f{}. 1679 * @userdata: User-defined "context" of _that_ ring. Passed back to the 1680 * user as one of the @callback, @rxd_init, and @rxd_term arguments. 1681 * @per_rxd_space: If specified (i.e., greater than zero): extra space 1682 * reserved by HW per each receive descriptor. 1683 * Can be used to store 1684 * and retrieve on completion, information specific 1685 * to the driver. 1686 * 1687 * Ring open "template". User fills the structure with ring 1688 * attributes and passes it to vxge_hw_vpath_open(). 1689 */ 1690struct vxge_hw_ring_attr { 1691 enum vxge_hw_status (*callback)( 1692 struct __vxge_hw_ring *ringh, 1693 void *rxdh, 1694 u8 t_code, 1695 void *userdata); 1696 1697 enum vxge_hw_status (*rxd_init)( 1698 void *rxdh, 1699 void *userdata); 1700 1701 void (*rxd_term)( 1702 void *rxdh, 1703 enum vxge_hw_rxd_state state, 1704 void *userdata); 1705 1706 void *userdata; 1707 u32 per_rxd_space; 1708}; 1709 1710/** 1711 * function vxge_hw_fifo_callback_f - FIFO callback. 1712 * @vpath_handle: Virtual path whose Fifo "containing" 1 or more completed 1713 * descriptors. 1714 * @txdlh: First completed descriptor. 1715 * @txdl_priv: Pointer to per txdl space allocated 1716 * @t_code: Transfer code, as per Titan User Guide. 1717 * Returned by HW. 1718 * @host_control: Opaque 64bit data stored by driver inside the Titan 1719 * descriptor prior to posting the latter on the fifo 1720 * via vxge_hw_fifo_txdl_post(). The @host_control is returned 1721 * as is to the driver with each completed descriptor. 1722 * @userdata: Opaque per-fifo data specified at fifo open 1723 * time, via vxge_hw_vpath_open(). 1724 * 1725 * Fifo completion callback (type declaration). A single per-fifo 1726 * callback is specified at fifo open time, via 1727 * vxge_hw_vpath_open(). Typically gets called as part of the processing 1728 * of the Interrupt Service Routine. 1729 * 1730 * Fifo callback gets called by HW if, and only if, there is at least 1731 * one new completion on a given fifo. Upon processing the first @txdlh driver 1732 * is _supposed_ to continue consuming completions using: 1733 * - vxge_hw_fifo_txdl_next_completed() 1734 * 1735 * Note that failure to process new completions in a timely fashion 1736 * leads to VXGE_HW_INF_OUT_OF_DESCRIPTORS condition. 1737 * 1738 * Non-zero @t_code means failure to process transmit descriptor. 1739 * 1740 * In the "transmit" case the failure could happen, for instance, when the 1741 * link is down, in which case Titan completes the descriptor because it 1742 * is not able to send the data out. 1743 * 1744 * For details please refer to Titan User Guide. 1745 * 1746 * See also: vxge_hw_fifo_txdl_next_completed(), vxge_hw_fifo_txdl_term_f{}. 1747 */ 1748/** 1749 * function vxge_hw_fifo_txdl_term_f - Terminate descriptor callback. 1750 * @txdlh: First completed descriptor. 1751 * @txdl_priv: Pointer to per txdl space allocated 1752 * @state: One of the enum vxge_hw_txdl_state{} enumerated states. 1753 * @userdata: Per-fifo user data (a.k.a. context) specified at 1754 * fifo open time, via vxge_hw_vpath_open(). 1755 * 1756 * Terminate descriptor callback. Unless NULL is specified in the 1757 * struct vxge_hw_fifo_attr{} structure passed to vxge_hw_vpath_open()), 1758 * HW invokes the callback as part of closing fifo, prior to 1759 * de-allocating the ring and associated data structures 1760 * (including descriptors). 1761 * driver should utilize the callback to (for instance) unmap 1762 * and free DMA data buffers associated with the posted (state = 1763 * VXGE_HW_TXDL_STATE_POSTED) descriptors, 1764 * as well as other relevant cleanup functions. 1765 * 1766 * See also: struct vxge_hw_fifo_attr{} 1767 */ 1768/** 1769 * struct vxge_hw_fifo_attr - Fifo open "template". 1770 * @callback: Fifo completion callback. HW invokes the callback when there 1771 * are new completions on that fifo. In many implementations 1772 * the @callback executes in the hw interrupt context. 1773 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, 1774 * HW invokes the callback when closing the corresponding fifo. 1775 * See also vxge_hw_fifo_txdl_term_f{}. 1776 * @userdata: User-defined "context" of _that_ fifo. Passed back to the 1777 * user as one of the @callback, and @txdl_term arguments. 1778 * @per_txdl_space: If specified (i.e., greater than zero): extra space 1779 * reserved by HW per each transmit descriptor. Can be used to 1780 * store, and retrieve on completion, information specific 1781 * to the driver. 1782 * 1783 * Fifo open "template". User fills the structure with fifo 1784 * attributes and passes it to vxge_hw_vpath_open(). 1785 */ 1786struct vxge_hw_fifo_attr { 1787 1788 enum vxge_hw_status (*callback)( 1789 struct __vxge_hw_fifo *fifo_handle, 1790 void *txdlh, 1791 enum vxge_hw_fifo_tcode t_code, 1792 void *userdata, 1793 struct sk_buff ***skb_ptr, 1794 int nr_skb, int *more); 1795 1796 void (*txdl_term)( 1797 void *txdlh, 1798 enum vxge_hw_txdl_state state, 1799 void *userdata); 1800 1801 void *userdata; 1802 u32 per_txdl_space; 1803}; 1804 1805/** 1806 * struct vxge_hw_vpath_attr - Attributes of virtual path 1807 * @vp_id: Identifier of Virtual Path 1808 * @ring_attr: Attributes of ring for non-offload receive 1809 * @fifo_attr: Attributes of fifo for non-offload transmit 1810 * 1811 * Attributes of virtual path. This structure is passed as parameter 1812 * to the vxge_hw_vpath_open() routine to set the attributes of ring and fifo. 1813 */ 1814struct vxge_hw_vpath_attr { 1815 u32 vp_id; 1816 struct vxge_hw_ring_attr ring_attr; 1817 struct vxge_hw_fifo_attr fifo_attr; 1818}; 1819 1820enum vxge_hw_status 1821__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev, 1822 struct __vxge_hw_blockpool *blockpool, 1823 u32 pool_size, 1824 u32 pool_max); 1825 1826void 1827__vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool); 1828 1829struct __vxge_hw_blockpool_entry * 1830__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *hldev, 1831 u32 size); 1832 1833void 1834__vxge_hw_blockpool_block_free(struct __vxge_hw_device *hldev, 1835 struct __vxge_hw_blockpool_entry *entry); 1836 1837void * 1838__vxge_hw_blockpool_malloc(struct __vxge_hw_device *hldev, 1839 u32 size, 1840 struct vxge_hw_mempool_dma *dma_object); 1841 1842void 1843__vxge_hw_blockpool_free(struct __vxge_hw_device *hldev, 1844 void *memblock, 1845 u32 size, 1846 struct vxge_hw_mempool_dma *dma_object); 1847 1848enum vxge_hw_status 1849__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config); 1850 1851enum vxge_hw_status 1852__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config); 1853 1854enum vxge_hw_status 1855vxge_hw_mgmt_device_config(struct __vxge_hw_device *devh, 1856 struct vxge_hw_device_config *dev_config, int size); 1857 1858enum vxge_hw_status __devinit vxge_hw_device_hw_info_get( 1859 void __iomem *bar0, 1860 struct vxge_hw_device_hw_info *hw_info); 1861 1862enum vxge_hw_status 1863__vxge_hw_vpath_fw_ver_get( 1864 u32 vp_id, 1865 struct vxge_hw_vpath_reg __iomem *vpath_reg, 1866 struct vxge_hw_device_hw_info *hw_info); 1867 1868enum vxge_hw_status 1869__vxge_hw_vpath_card_info_get( 1870 u32 vp_id, 1871 struct vxge_hw_vpath_reg __iomem *vpath_reg, 1872 struct vxge_hw_device_hw_info *hw_info); 1873 1874enum vxge_hw_status __devinit vxge_hw_device_config_default_get( 1875 struct vxge_hw_device_config *device_config); 1876 1877/** 1878 * vxge_hw_device_link_state_get - Get link state. 1879 * @devh: HW device handle. 1880 * 1881 * Get link state. 1882 * Returns: link state. 1883 */ 1884static inline 1885enum vxge_hw_device_link_state vxge_hw_device_link_state_get( 1886 struct __vxge_hw_device *devh) 1887{ 1888 return devh->link_state; 1889} 1890 1891void vxge_hw_device_terminate(struct __vxge_hw_device *devh); 1892 1893const u8 * 1894vxge_hw_device_serial_number_get(struct __vxge_hw_device *devh); 1895 1896u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *devh); 1897 1898const u8 * 1899vxge_hw_device_product_name_get(struct __vxge_hw_device *devh); 1900 1901enum vxge_hw_status __devinit vxge_hw_device_initialize( 1902 struct __vxge_hw_device **devh, 1903 struct vxge_hw_device_attr *attr, 1904 struct vxge_hw_device_config *device_config); 1905 1906enum vxge_hw_status vxge_hw_device_getpause_data( 1907 struct __vxge_hw_device *devh, 1908 u32 port, 1909 u32 *tx, 1910 u32 *rx); 1911 1912enum vxge_hw_status vxge_hw_device_setpause_data( 1913 struct __vxge_hw_device *devh, 1914 u32 port, 1915 u32 tx, 1916 u32 rx); 1917 1918static inline void *vxge_os_dma_malloc(struct pci_dev *pdev, 1919 unsigned long size, 1920 struct pci_dev **p_dmah, 1921 struct pci_dev **p_dma_acch) 1922{ 1923 gfp_t flags; 1924 void *vaddr; 1925 unsigned long misaligned = 0; 1926 int realloc_flag = 0; 1927 *p_dma_acch = *p_dmah = NULL; 1928 1929 if (in_interrupt()) 1930 flags = GFP_ATOMIC | GFP_DMA; 1931 else 1932 flags = GFP_KERNEL | GFP_DMA; 1933realloc: 1934 vaddr = kmalloc((size), flags); 1935 if (vaddr == NULL) 1936 return vaddr; 1937 misaligned = (unsigned long)VXGE_ALIGN((unsigned long)vaddr, 1938 VXGE_CACHE_LINE_SIZE); 1939 if (realloc_flag) 1940 goto out; 1941 1942 if (misaligned) { 1943 /* misaligned, free current one and try allocating 1944 * size + VXGE_CACHE_LINE_SIZE memory 1945 */ 1946 kfree((void *) vaddr); 1947 size += VXGE_CACHE_LINE_SIZE; 1948 realloc_flag = 1; 1949 goto realloc; 1950 } 1951out: 1952 *(unsigned long *)p_dma_acch = misaligned; 1953 vaddr = (void *)((u8 *)vaddr + misaligned); 1954 return vaddr; 1955} 1956 1957extern void vxge_hw_blockpool_block_add( 1958 struct __vxge_hw_device *devh, 1959 void *block_addr, 1960 u32 length, 1961 struct pci_dev *dma_h, 1962 struct pci_dev *acc_handle); 1963 1964static inline void vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, 1965 unsigned long size) 1966{ 1967 gfp_t flags; 1968 void *vaddr; 1969 1970 if (in_interrupt()) 1971 flags = GFP_ATOMIC | GFP_DMA; 1972 else 1973 flags = GFP_KERNEL | GFP_DMA; 1974 1975 vaddr = kmalloc((size), flags); 1976 1977 vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev); 1978} 1979 1980static inline void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr, 1981 struct pci_dev **p_dma_acch) 1982{ 1983 unsigned long misaligned = *(unsigned long *)p_dma_acch; 1984 u8 *tmp = (u8 *)vaddr; 1985 tmp -= misaligned; 1986 kfree((void *)tmp); 1987} 1988 1989/* 1990 * __vxge_hw_mempool_item_priv - will return pointer on per item private space 1991 */ 1992static inline void* 1993__vxge_hw_mempool_item_priv( 1994 struct vxge_hw_mempool *mempool, 1995 u32 memblock_idx, 1996 void *item, 1997 u32 *memblock_item_idx) 1998{ 1999 ptrdiff_t offset; 2000 void *memblock = mempool->memblocks_arr[memblock_idx]; 2001 2002 2003 offset = (u32)((u8 *)item - (u8 *)memblock); 2004 vxge_assert(offset >= 0 && (u32)offset < mempool->memblock_size); 2005 2006 (*memblock_item_idx) = (u32) offset / mempool->item_size; 2007 vxge_assert((*memblock_item_idx) < mempool->items_per_memblock); 2008 2009 return (u8 *)mempool->memblocks_priv_arr[memblock_idx] + 2010 (*memblock_item_idx) * mempool->items_priv_size; 2011} 2012 2013enum vxge_hw_status 2014__vxge_hw_mempool_grow( 2015 struct vxge_hw_mempool *mempool, 2016 u32 num_allocate, 2017 u32 *num_allocated); 2018 2019struct vxge_hw_mempool* 2020__vxge_hw_mempool_create( 2021 struct __vxge_hw_device *devh, 2022 u32 memblock_size, 2023 u32 item_size, 2024 u32 private_size, 2025 u32 items_initial, 2026 u32 items_max, 2027 struct vxge_hw_mempool_cbs *mp_callback, 2028 void *userdata); 2029 2030struct __vxge_hw_channel* 2031__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph, 2032 enum __vxge_hw_channel_type type, u32 length, 2033 u32 per_dtr_space, void *userdata); 2034 2035void 2036__vxge_hw_channel_free( 2037 struct __vxge_hw_channel *channel); 2038 2039enum vxge_hw_status 2040__vxge_hw_channel_initialize( 2041 struct __vxge_hw_channel *channel); 2042 2043enum vxge_hw_status 2044__vxge_hw_channel_reset( 2045 struct __vxge_hw_channel *channel); 2046 2047/* 2048 * __vxge_hw_fifo_txdl_priv - Return the max fragments allocated 2049 * for the fifo. 2050 * @fifo: Fifo 2051 * @txdp: Poniter to a TxD 2052 */ 2053static inline struct __vxge_hw_fifo_txdl_priv * 2054__vxge_hw_fifo_txdl_priv( 2055 struct __vxge_hw_fifo *fifo, 2056 struct vxge_hw_fifo_txd *txdp) 2057{ 2058 return (struct __vxge_hw_fifo_txdl_priv *) 2059 (((char *)((ulong)txdp->host_control)) + 2060 fifo->per_txdl_space); 2061} 2062 2063enum vxge_hw_status vxge_hw_vpath_open( 2064 struct __vxge_hw_device *devh, 2065 struct vxge_hw_vpath_attr *attr, 2066 struct __vxge_hw_vpath_handle **vpath_handle); 2067 2068enum vxge_hw_status 2069__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog); 2070 2071enum vxge_hw_status vxge_hw_vpath_close( 2072 struct __vxge_hw_vpath_handle *vpath_handle); 2073 2074enum vxge_hw_status 2075vxge_hw_vpath_reset( 2076 struct __vxge_hw_vpath_handle *vpath_handle); 2077 2078enum vxge_hw_status 2079vxge_hw_vpath_recover_from_reset( 2080 struct __vxge_hw_vpath_handle *vpath_handle); 2081 2082void 2083vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp); 2084 2085enum vxge_hw_status 2086vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ringh); 2087 2088enum vxge_hw_status vxge_hw_vpath_mtu_set( 2089 struct __vxge_hw_vpath_handle *vpath_handle, 2090 u32 new_mtu); 2091 2092enum vxge_hw_status vxge_hw_vpath_stats_enable( 2093 struct __vxge_hw_vpath_handle *vpath_handle); 2094 2095enum vxge_hw_status 2096__vxge_hw_vpath_stats_access( 2097 struct __vxge_hw_virtualpath *vpath, 2098 u32 operation, 2099 u32 offset, 2100 u64 *stat); 2101 2102enum vxge_hw_status 2103__vxge_hw_vpath_xmac_tx_stats_get( 2104 struct __vxge_hw_virtualpath *vpath, 2105 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats); 2106 2107enum vxge_hw_status 2108__vxge_hw_vpath_xmac_rx_stats_get( 2109 struct __vxge_hw_virtualpath *vpath, 2110 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats); 2111 2112enum vxge_hw_status 2113__vxge_hw_vpath_stats_get( 2114 struct __vxge_hw_virtualpath *vpath, 2115 struct vxge_hw_vpath_stats_hw_info *hw_stats); 2116 2117void 2118vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp); 2119 2120enum vxge_hw_status 2121__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config); 2122 2123void 2124__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev); 2125 2126enum vxge_hw_status 2127__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg); 2128 2129enum vxge_hw_status 2130__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg); 2131 2132enum vxge_hw_status 2133__vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg, 2134 struct vxge_hw_vpath_reg __iomem *vpath_reg); 2135 2136enum vxge_hw_status 2137__vxge_hw_device_register_poll( 2138 void __iomem *reg, 2139 u64 mask, u32 max_millis); 2140 2141#ifndef readq 2142static inline u64 readq(void __iomem *addr) 2143{ 2144 u64 ret = 0; 2145 ret = readl(addr + 4); 2146 ret <<= 32; 2147 ret |= readl(addr); 2148 2149 return ret; 2150} 2151#endif 2152 2153#ifndef writeq 2154static inline void writeq(u64 val, void __iomem *addr) 2155{ 2156 writel((u32) (val), addr); 2157 writel((u32) (val >> 32), (addr + 4)); 2158} 2159#endif 2160 2161static inline void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr) 2162{ 2163 writel(val, addr + 4); 2164} 2165 2166static inline void __vxge_hw_pio_mem_write32_lower(u32 val, void __iomem *addr) 2167{ 2168 writel(val, addr); 2169} 2170 2171static inline enum vxge_hw_status 2172__vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr, 2173 u64 mask, u32 max_millis) 2174{ 2175 enum vxge_hw_status status = VXGE_HW_OK; 2176 2177 __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr); 2178 wmb(); 2179 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr); 2180 wmb(); 2181 2182 status = __vxge_hw_device_register_poll(addr, mask, max_millis); 2183 return status; 2184} 2185 2186struct vxge_hw_toc_reg __iomem * 2187__vxge_hw_device_toc_get(void __iomem *bar0); 2188 2189enum vxge_hw_status 2190__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev); 2191 2192void 2193__vxge_hw_device_id_get(struct __vxge_hw_device *hldev); 2194 2195void 2196__vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev); 2197 2198enum vxge_hw_status 2199vxge_hw_device_flick_link_led(struct __vxge_hw_device *devh, u64 on_off); 2200 2201enum vxge_hw_status 2202__vxge_hw_device_initialize(struct __vxge_hw_device *hldev); 2203 2204enum vxge_hw_status 2205__vxge_hw_vpath_pci_read( 2206 struct __vxge_hw_virtualpath *vpath, 2207 u32 phy_func_0, 2208 u32 offset, 2209 u32 *val); 2210 2211enum vxge_hw_status 2212__vxge_hw_vpath_addr_get( 2213 u32 vp_id, 2214 struct vxge_hw_vpath_reg __iomem *vpath_reg, 2215 u8 (macaddr)[ETH_ALEN], 2216 u8 (macaddr_mask)[ETH_ALEN]); 2217 2218u32 2219__vxge_hw_vpath_func_id_get( 2220 u32 vp_id, struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg); 2221 2222enum vxge_hw_status 2223__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath); 2224 2225enum vxge_hw_status 2226vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask); 2227/** 2228 * vxge_debug 2229 * @level: level of debug verbosity. 2230 * @mask: mask for the debug 2231 * @buf: Circular buffer for tracing 2232 * @fmt: printf like format string 2233 * 2234 * Provides logging facilities. Can be customized on per-module 2235 * basis or/and with debug levels. Input parameters, except 2236 * module and level, are the same as posix printf. This function 2237 * may be compiled out if DEBUG macro was never defined. 2238 * See also: enum vxge_debug_level{}. 2239 */ 2240 2241#define vxge_trace_aux(level, mask, fmt, ...) \ 2242{\ 2243 vxge_os_vaprintf(level, mask, fmt, __VA_ARGS__);\ 2244} 2245 2246#define vxge_debug(module, level, mask, fmt, ...) { \ 2247if ((level >= VXGE_TRACE && ((module & VXGE_DEBUG_TRACE_MASK) == module)) || \ 2248 (level >= VXGE_ERR && ((module & VXGE_DEBUG_ERR_MASK) == module))) {\ 2249 if ((mask & VXGE_DEBUG_MASK) == mask)\ 2250 vxge_trace_aux(level, mask, fmt, __VA_ARGS__); \ 2251} \ 2252} 2253 2254#if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK) 2255#define vxge_debug_ll(level, mask, fmt, ...) \ 2256{\ 2257 vxge_debug(VXGE_COMPONENT_LL, level, mask, fmt, __VA_ARGS__);\ 2258} 2259 2260#else 2261#define vxge_debug_ll(level, mask, fmt, ...) 2262#endif 2263 2264enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set( 2265 struct __vxge_hw_vpath_handle **vpath_handles, 2266 u32 vpath_count, 2267 u8 *mtable, 2268 u8 *itable, 2269 u32 itable_size); 2270 2271enum vxge_hw_status vxge_hw_vpath_rts_rth_set( 2272 struct __vxge_hw_vpath_handle *vpath_handle, 2273 enum vxge_hw_rth_algoritms algorithm, 2274 struct vxge_hw_rth_hash_types *hash_type, 2275 u16 bucket_size); 2276 2277enum vxge_hw_status 2278__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id); 2279#endif 2280