1/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 Exp $ 2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 3 * 4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) 6 * Copyright (C) 2004 Sun Microsystems Inc. 7 * Copyright (C) 2007-2010 Broadcom Corporation. 8 */ 9 10#ifndef _T3_H 11#define _T3_H 12 13#define TG3_64BIT_REG_HIGH 0x00UL 14#define TG3_64BIT_REG_LOW 0x04UL 15 16/* Descriptor block info. */ 17#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 18#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 19#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 20#define BDINFO_FLAGS_DISABLED 0x00000002 21#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 22#define BDINFO_FLAGS_MAXLEN_SHIFT 16 23#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 24#define TG3_BDINFO_SIZE 0x10UL 25 26#define TG3_RX_INTERNAL_RING_SZ_5906 32 27 28#define RX_STD_MAX_SIZE_5705 512 29#define RX_JUMBO_MAX_SIZE 0xdeadbeef 30 31/* First 256 bytes are a mirror of PCI config space. */ 32#define TG3PCI_VENDOR 0x00000000 33#define TG3PCI_VENDOR_BROADCOM 0x14e4 34#define TG3PCI_DEVICE 0x00000002 35#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 36#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 37#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 38#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 39#define TG3PCI_DEVICE_TIGON3_5761S 0x1688 40#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 41#define TG3PCI_DEVICE_TIGON3_57780 0x1692 42#define TG3PCI_DEVICE_TIGON3_57760 0x1690 43#define TG3PCI_DEVICE_TIGON3_57790 0x1694 44#define TG3PCI_DEVICE_TIGON3_57788 0x1691 45#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ 46#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ 47#define TG3PCI_DEVICE_TIGON3_5717 0x1655 48#define TG3PCI_DEVICE_TIGON3_5718 0x1656 49#define TG3PCI_DEVICE_TIGON3_5724 0x165c 50#define TG3PCI_DEVICE_TIGON3_57781 0x16b1 51#define TG3PCI_DEVICE_TIGON3_57785 0x16b5 52#define TG3PCI_DEVICE_TIGON3_57761 0x16b0 53#define TG3PCI_DEVICE_TIGON3_57765 0x16b4 54#define TG3PCI_DEVICE_TIGON3_57791 0x16b2 55#define TG3PCI_DEVICE_TIGON3_57795 0x16b6 56#define TG3PCI_DEVICE_TIGON3_5719 0x1657 57/* 0x04 --> 0x2c unused */ 58#define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM 59#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644 60#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001 61#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002 62#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003 63#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005 64#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006 65#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007 66#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008 67#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008 68#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009 69#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009 70#define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM 71#define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000 72#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006 73#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004 74#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007 75#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008 76#define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL 77#define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1 78#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106 79#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109 80#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a 81#define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ 82#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c 83#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a 84#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d 85#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085 86#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099 87#define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM 88#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281 89/* 0x30 --> 0x64 unused */ 90#define TG3PCI_MSI_DATA 0x00000064 91/* 0x66 --> 0x68 unused */ 92#define TG3PCI_MISC_HOST_CTRL 0x00000068 93#define MISC_HOST_CTRL_CLEAR_INT 0x00000001 94#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 95#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 96#define MISC_HOST_CTRL_WORD_SWAP 0x00000008 97#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 98#define MISC_HOST_CTRL_CLKREG_RW 0x00000020 99#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 100#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 101#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 102#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 103#define MISC_HOST_CTRL_CHIPREV 0xffff0000 104#define MISC_HOST_CTRL_CHIPREV_SHIFT 16 105#define GET_CHIP_REV_ID(MISC_HOST_CTRL) \ 106 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \ 107 MISC_HOST_CTRL_CHIPREV_SHIFT) 108#define CHIPREV_ID_5700_A0 0x7000 109#define CHIPREV_ID_5700_A1 0x7001 110#define CHIPREV_ID_5700_B0 0x7100 111#define CHIPREV_ID_5700_B1 0x7101 112#define CHIPREV_ID_5700_B3 0x7102 113#define CHIPREV_ID_5700_ALTIMA 0x7104 114#define CHIPREV_ID_5700_C0 0x7200 115#define CHIPREV_ID_5701_A0 0x0000 116#define CHIPREV_ID_5701_B0 0x0100 117#define CHIPREV_ID_5701_B2 0x0102 118#define CHIPREV_ID_5701_B5 0x0105 119#define CHIPREV_ID_5703_A0 0x1000 120#define CHIPREV_ID_5703_A1 0x1001 121#define CHIPREV_ID_5703_A2 0x1002 122#define CHIPREV_ID_5703_A3 0x1003 123#define CHIPREV_ID_5704_A0 0x2000 124#define CHIPREV_ID_5704_A1 0x2001 125#define CHIPREV_ID_5704_A2 0x2002 126#define CHIPREV_ID_5704_A3 0x2003 127#define CHIPREV_ID_5705_A0 0x3000 128#define CHIPREV_ID_5705_A1 0x3001 129#define CHIPREV_ID_5705_A2 0x3002 130#define CHIPREV_ID_5705_A3 0x3003 131#define CHIPREV_ID_5750_A0 0x4000 132#define CHIPREV_ID_5750_A1 0x4001 133#define CHIPREV_ID_5750_A3 0x4003 134#define CHIPREV_ID_5750_C2 0x4202 135#define CHIPREV_ID_5752_A0_HW 0x5000 136#define CHIPREV_ID_5752_A0 0x6000 137#define CHIPREV_ID_5752_A1 0x6001 138#define CHIPREV_ID_5714_A2 0x9002 139#define CHIPREV_ID_5906_A1 0xc001 140#define CHIPREV_ID_57780_A0 0x57780000 141#define CHIPREV_ID_57780_A1 0x57780001 142#define CHIPREV_ID_5717_A0 0x05717000 143#define CHIPREV_ID_57765_A0 0x57785000 144#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) 145#define ASIC_REV_5700 0x07 146#define ASIC_REV_5701 0x00 147#define ASIC_REV_5703 0x01 148#define ASIC_REV_5704 0x02 149#define ASIC_REV_5705 0x03 150#define ASIC_REV_5750 0x04 151#define ASIC_REV_5752 0x06 152#define ASIC_REV_5780 0x08 153#define ASIC_REV_5714 0x09 154#define ASIC_REV_5755 0x0a 155#define ASIC_REV_5787 0x0b 156#define ASIC_REV_5906 0x0c 157#define ASIC_REV_USE_PROD_ID_REG 0x0f 158#define ASIC_REV_5784 0x5784 159#define ASIC_REV_5761 0x5761 160#define ASIC_REV_5785 0x5785 161#define ASIC_REV_57780 0x57780 162#define ASIC_REV_5717 0x5717 163#define ASIC_REV_57765 0x57785 164#define ASIC_REV_5719 0x5719 165#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 166#define CHIPREV_5700_AX 0x70 167#define CHIPREV_5700_BX 0x71 168#define CHIPREV_5700_CX 0x72 169#define CHIPREV_5701_AX 0x00 170#define CHIPREV_5703_AX 0x10 171#define CHIPREV_5704_AX 0x20 172#define CHIPREV_5704_BX 0x21 173#define CHIPREV_5750_AX 0x40 174#define CHIPREV_5750_BX 0x41 175#define CHIPREV_5784_AX 0x57840 176#define CHIPREV_5761_AX 0x57610 177#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) 178#define METAL_REV_A0 0x00 179#define METAL_REV_A1 0x01 180#define METAL_REV_B0 0x00 181#define METAL_REV_B1 0x01 182#define METAL_REV_B2 0x02 183#define TG3PCI_DMA_RW_CTRL 0x0000006c 184#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 185#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 186#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 187#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 188#define DMA_RWCTRL_READ_BNDRY_16 0x00000100 189#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 190#define DMA_RWCTRL_READ_BNDRY_32 0x00000200 191#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 192#define DMA_RWCTRL_READ_BNDRY_64 0x00000300 193#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 194#define DMA_RWCTRL_READ_BNDRY_128 0x00000400 195#define DMA_RWCTRL_READ_BNDRY_256 0x00000500 196#define DMA_RWCTRL_READ_BNDRY_512 0x00000600 197#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 198#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 199#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 200#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 201#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 202#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 203#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 204#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 205#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 206#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 207#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 208#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 209#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 210#define DMA_RWCTRL_ONE_DMA 0x00004000 211#define DMA_RWCTRL_READ_WATER 0x00070000 212#define DMA_RWCTRL_READ_WATER_SHIFT 16 213#define DMA_RWCTRL_WRITE_WATER 0x00380000 214#define DMA_RWCTRL_WRITE_WATER_SHIFT 19 215#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 216#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 217#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 218#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 219#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 220#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 221#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 222#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 223#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 224#define TG3PCI_PCISTATE 0x00000070 225#define PCISTATE_FORCE_RESET 0x00000001 226#define PCISTATE_INT_NOT_ACTIVE 0x00000002 227#define PCISTATE_CONV_PCI_MODE 0x00000004 228#define PCISTATE_BUS_SPEED_HIGH 0x00000008 229#define PCISTATE_BUS_32BIT 0x00000010 230#define PCISTATE_ROM_ENABLE 0x00000020 231#define PCISTATE_ROM_RETRY_ENABLE 0x00000040 232#define PCISTATE_FLAT_VIEW 0x00000100 233#define PCISTATE_RETRY_SAME_DMA 0x00002000 234#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 235#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 236#define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 237#define TG3PCI_CLOCK_CTRL 0x00000074 238#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 239#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 240#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 241#define CLOCK_CTRL_ALTCLK 0x00001000 242#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 243#define CLOCK_CTRL_44MHZ_CORE 0x00040000 244#define CLOCK_CTRL_625_CORE 0x00100000 245#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 246#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 247#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 248#define TG3PCI_REG_BASE_ADDR 0x00000078 249#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 250#define TG3PCI_REG_DATA 0x00000080 251#define TG3PCI_MEM_WIN_DATA 0x00000084 252#define TG3PCI_MISC_LOCAL_CTRL 0x00000090 253/* 0x94 --> 0x98 unused */ 254#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 255#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 256/* 0xa8 --> 0xb8 unused */ 257#define TG3PCI_DUAL_MAC_CTRL 0x000000b8 258#define DUAL_MAC_CTRL_CH_MASK 0x00000003 259#define DUAL_MAC_CTRL_ID 0x00000004 260#define TG3PCI_PRODID_ASICREV 0x000000bc 261#define PROD_ID_ASIC_REV_MASK 0x0fffffff 262/* 0xc0 --> 0xf4 unused */ 263 264#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4 265#define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc 266/* 0xf8 --> 0x200 unused */ 267 268#define TG3_CORR_ERR_STAT 0x00000110 269#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff 270/* 0x114 --> 0x200 unused */ 271 272/* Mailbox registers */ 273#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 274#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 275#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 276#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 277#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 278#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 279#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 280#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 281#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 282#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 283#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 284#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 285#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 286#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 287#define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ 288 TG3_64BIT_REG_LOW) 289#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 290#define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ 291 TG3_64BIT_REG_LOW) 292#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 293#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 294#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 295#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 296#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 297#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 298#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 299#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 300#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 301#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 302#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 303#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 304#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 305#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 306#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 307#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 308#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 309#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 310#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 311#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 312#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 313#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 314#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 315#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 316#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 317#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 318#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 319#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 320#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 321#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 322#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 323#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 324#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 325#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 326#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 327#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 328#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 329#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 330#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 331#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 332#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 333#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 334#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 335#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 336#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 337#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 338#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 339#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 340#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 341 342/* MAC control registers */ 343#define MAC_MODE 0x00000400 344#define MAC_MODE_RESET 0x00000001 345#define MAC_MODE_HALF_DUPLEX 0x00000002 346#define MAC_MODE_PORT_MODE_MASK 0x0000000c 347#define MAC_MODE_PORT_MODE_TBI 0x0000000c 348#define MAC_MODE_PORT_MODE_GMII 0x00000008 349#define MAC_MODE_PORT_MODE_MII 0x00000004 350#define MAC_MODE_PORT_MODE_NONE 0x00000000 351#define MAC_MODE_PORT_INT_LPBACK 0x00000010 352#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 353#define MAC_MODE_TX_BURSTING 0x00000100 354#define MAC_MODE_MAX_DEFER 0x00000200 355#define MAC_MODE_LINK_POLARITY 0x00000400 356#define MAC_MODE_RXSTAT_ENABLE 0x00000800 357#define MAC_MODE_RXSTAT_CLEAR 0x00001000 358#define MAC_MODE_RXSTAT_FLUSH 0x00002000 359#define MAC_MODE_TXSTAT_ENABLE 0x00004000 360#define MAC_MODE_TXSTAT_CLEAR 0x00008000 361#define MAC_MODE_TXSTAT_FLUSH 0x00010000 362#define MAC_MODE_SEND_CONFIGS 0x00020000 363#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 364#define MAC_MODE_ACPI_ENABLE 0x00080000 365#define MAC_MODE_MIP_ENABLE 0x00100000 366#define MAC_MODE_TDE_ENABLE 0x00200000 367#define MAC_MODE_RDE_ENABLE 0x00400000 368#define MAC_MODE_FHDE_ENABLE 0x00800000 369#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 370#define MAC_MODE_APE_RX_EN 0x08000000 371#define MAC_MODE_APE_TX_EN 0x10000000 372#define MAC_STATUS 0x00000404 373#define MAC_STATUS_PCS_SYNCED 0x00000001 374#define MAC_STATUS_SIGNAL_DET 0x00000002 375#define MAC_STATUS_RCVD_CFG 0x00000004 376#define MAC_STATUS_CFG_CHANGED 0x00000008 377#define MAC_STATUS_SYNC_CHANGED 0x00000010 378#define MAC_STATUS_PORT_DEC_ERR 0x00000400 379#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 380#define MAC_STATUS_MI_COMPLETION 0x00400000 381#define MAC_STATUS_MI_INTERRUPT 0x00800000 382#define MAC_STATUS_AP_ERROR 0x01000000 383#define MAC_STATUS_ODI_ERROR 0x02000000 384#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 385#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 386#define MAC_EVENT 0x00000408 387#define MAC_EVENT_PORT_DECODE_ERR 0x00000400 388#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 389#define MAC_EVENT_MI_COMPLETION 0x00400000 390#define MAC_EVENT_MI_INTERRUPT 0x00800000 391#define MAC_EVENT_AP_ERROR 0x01000000 392#define MAC_EVENT_ODI_ERROR 0x02000000 393#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 394#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 395#define MAC_LED_CTRL 0x0000040c 396#define LED_CTRL_LNKLED_OVERRIDE 0x00000001 397#define LED_CTRL_1000MBPS_ON 0x00000002 398#define LED_CTRL_100MBPS_ON 0x00000004 399#define LED_CTRL_10MBPS_ON 0x00000008 400#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 401#define LED_CTRL_TRAFFIC_BLINK 0x00000020 402#define LED_CTRL_TRAFFIC_LED 0x00000040 403#define LED_CTRL_1000MBPS_STATUS 0x00000080 404#define LED_CTRL_100MBPS_STATUS 0x00000100 405#define LED_CTRL_10MBPS_STATUS 0x00000200 406#define LED_CTRL_TRAFFIC_STATUS 0x00000400 407#define LED_CTRL_MODE_MAC 0x00000000 408#define LED_CTRL_MODE_PHY_1 0x00000800 409#define LED_CTRL_MODE_PHY_2 0x00001000 410#define LED_CTRL_MODE_SHASTA_MAC 0x00002000 411#define LED_CTRL_MODE_SHARED 0x00004000 412#define LED_CTRL_MODE_COMBO 0x00008000 413#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 414#define LED_CTRL_BLINK_RATE_SHIFT 19 415#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 416#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 417#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 418#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 419#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 420#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 421#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 422#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 423#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 424#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 425#define MAC_ACPI_MBUF_PTR 0x00000430 426#define MAC_ACPI_LEN_OFFSET 0x00000434 427#define ACPI_LENOFF_LEN_MASK 0x0000ffff 428#define ACPI_LENOFF_LEN_SHIFT 0 429#define ACPI_LENOFF_OFF_MASK 0x0fff0000 430#define ACPI_LENOFF_OFF_SHIFT 16 431#define MAC_TX_BACKOFF_SEED 0x00000438 432#define TX_BACKOFF_SEED_MASK 0x000003ff 433#define MAC_RX_MTU_SIZE 0x0000043c 434#define RX_MTU_SIZE_MASK 0x0000ffff 435#define MAC_PCS_TEST 0x00000440 436#define PCS_TEST_PATTERN_MASK 0x000fffff 437#define PCS_TEST_PATTERN_SHIFT 0 438#define PCS_TEST_ENABLE 0x00100000 439#define MAC_TX_AUTO_NEG 0x00000444 440#define TX_AUTO_NEG_MASK 0x0000ffff 441#define TX_AUTO_NEG_SHIFT 0 442#define MAC_RX_AUTO_NEG 0x00000448 443#define RX_AUTO_NEG_MASK 0x0000ffff 444#define RX_AUTO_NEG_SHIFT 0 445#define MAC_MI_COM 0x0000044c 446#define MI_COM_CMD_MASK 0x0c000000 447#define MI_COM_CMD_WRITE 0x04000000 448#define MI_COM_CMD_READ 0x08000000 449#define MI_COM_READ_FAILED 0x10000000 450#define MI_COM_START 0x20000000 451#define MI_COM_BUSY 0x20000000 452#define MI_COM_PHY_ADDR_MASK 0x03e00000 453#define MI_COM_PHY_ADDR_SHIFT 21 454#define MI_COM_REG_ADDR_MASK 0x001f0000 455#define MI_COM_REG_ADDR_SHIFT 16 456#define MI_COM_DATA_MASK 0x0000ffff 457#define MAC_MI_STAT 0x00000450 458#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 459#define MAC_MI_STAT_10MBPS_MODE 0x00000002 460#define MAC_MI_MODE 0x00000454 461#define MAC_MI_MODE_CLK_10MHZ 0x00000001 462#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 463#define MAC_MI_MODE_AUTO_POLL 0x00000010 464#define MAC_MI_MODE_500KHZ_CONST 0x00008000 465#define MAC_MI_MODE_BASE 0x000c0000 466#define MAC_AUTO_POLL_STATUS 0x00000458 467#define MAC_AUTO_POLL_ERROR 0x00000001 468#define MAC_TX_MODE 0x0000045c 469#define TX_MODE_RESET 0x00000001 470#define TX_MODE_ENABLE 0x00000002 471#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 472#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 473#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 474#define TX_MODE_MBUF_LOCKUP_FIX 0x00000100 475#define MAC_TX_STATUS 0x00000460 476#define TX_STATUS_XOFFED 0x00000001 477#define TX_STATUS_SENT_XOFF 0x00000002 478#define TX_STATUS_SENT_XON 0x00000004 479#define TX_STATUS_LINK_UP 0x00000008 480#define TX_STATUS_ODI_UNDERRUN 0x00000010 481#define TX_STATUS_ODI_OVERRUN 0x00000020 482#define MAC_TX_LENGTHS 0x00000464 483#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 484#define TX_LENGTHS_SLOT_TIME_SHIFT 0 485#define TX_LENGTHS_IPG_MASK 0x00000f00 486#define TX_LENGTHS_IPG_SHIFT 8 487#define TX_LENGTHS_IPG_CRS_MASK 0x00003000 488#define TX_LENGTHS_IPG_CRS_SHIFT 12 489#define MAC_RX_MODE 0x00000468 490#define RX_MODE_RESET 0x00000001 491#define RX_MODE_ENABLE 0x00000002 492#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 493#define RX_MODE_KEEP_MAC_CTRL 0x00000008 494#define RX_MODE_KEEP_PAUSE 0x00000010 495#define RX_MODE_ACCEPT_OVERSIZED 0x00000020 496#define RX_MODE_ACCEPT_RUNTS 0x00000040 497#define RX_MODE_LEN_CHECK 0x00000080 498#define RX_MODE_PROMISC 0x00000100 499#define RX_MODE_NO_CRC_CHECK 0x00000200 500#define RX_MODE_KEEP_VLAN_TAG 0x00000400 501#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000 502#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000 503#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000 504#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000 505#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000 506#define RX_MODE_RSS_ENABLE 0x00800000 507#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 508#define MAC_RX_STATUS 0x0000046c 509#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 510#define RX_STATUS_XOFF_RCVD 0x00000002 511#define RX_STATUS_XON_RCVD 0x00000004 512#define MAC_HASH_REG_0 0x00000470 513#define MAC_HASH_REG_1 0x00000474 514#define MAC_HASH_REG_2 0x00000478 515#define MAC_HASH_REG_3 0x0000047c 516#define MAC_RCV_RULE_0 0x00000480 517#define MAC_RCV_VALUE_0 0x00000484 518#define MAC_RCV_RULE_1 0x00000488 519#define MAC_RCV_VALUE_1 0x0000048c 520#define MAC_RCV_RULE_2 0x00000490 521#define MAC_RCV_VALUE_2 0x00000494 522#define MAC_RCV_RULE_3 0x00000498 523#define MAC_RCV_VALUE_3 0x0000049c 524#define MAC_RCV_RULE_4 0x000004a0 525#define MAC_RCV_VALUE_4 0x000004a4 526#define MAC_RCV_RULE_5 0x000004a8 527#define MAC_RCV_VALUE_5 0x000004ac 528#define MAC_RCV_RULE_6 0x000004b0 529#define MAC_RCV_VALUE_6 0x000004b4 530#define MAC_RCV_RULE_7 0x000004b8 531#define MAC_RCV_VALUE_7 0x000004bc 532#define MAC_RCV_RULE_8 0x000004c0 533#define MAC_RCV_VALUE_8 0x000004c4 534#define MAC_RCV_RULE_9 0x000004c8 535#define MAC_RCV_VALUE_9 0x000004cc 536#define MAC_RCV_RULE_10 0x000004d0 537#define MAC_RCV_VALUE_10 0x000004d4 538#define MAC_RCV_RULE_11 0x000004d8 539#define MAC_RCV_VALUE_11 0x000004dc 540#define MAC_RCV_RULE_12 0x000004e0 541#define MAC_RCV_VALUE_12 0x000004e4 542#define MAC_RCV_RULE_13 0x000004e8 543#define MAC_RCV_VALUE_13 0x000004ec 544#define MAC_RCV_RULE_14 0x000004f0 545#define MAC_RCV_VALUE_14 0x000004f4 546#define MAC_RCV_RULE_15 0x000004f8 547#define MAC_RCV_VALUE_15 0x000004fc 548#define RCV_RULE_DISABLE_MASK 0x7fffffff 549#define MAC_RCV_RULE_CFG 0x00000500 550#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 551#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 552/* 0x508 --> 0x520 unused */ 553#define MAC_HASHREGU_0 0x00000520 554#define MAC_HASHREGU_1 0x00000524 555#define MAC_HASHREGU_2 0x00000528 556#define MAC_HASHREGU_3 0x0000052c 557#define MAC_EXTADDR_0_HIGH 0x00000530 558#define MAC_EXTADDR_0_LOW 0x00000534 559#define MAC_EXTADDR_1_HIGH 0x00000538 560#define MAC_EXTADDR_1_LOW 0x0000053c 561#define MAC_EXTADDR_2_HIGH 0x00000540 562#define MAC_EXTADDR_2_LOW 0x00000544 563#define MAC_EXTADDR_3_HIGH 0x00000548 564#define MAC_EXTADDR_3_LOW 0x0000054c 565#define MAC_EXTADDR_4_HIGH 0x00000550 566#define MAC_EXTADDR_4_LOW 0x00000554 567#define MAC_EXTADDR_5_HIGH 0x00000558 568#define MAC_EXTADDR_5_LOW 0x0000055c 569#define MAC_EXTADDR_6_HIGH 0x00000560 570#define MAC_EXTADDR_6_LOW 0x00000564 571#define MAC_EXTADDR_7_HIGH 0x00000568 572#define MAC_EXTADDR_7_LOW 0x0000056c 573#define MAC_EXTADDR_8_HIGH 0x00000570 574#define MAC_EXTADDR_8_LOW 0x00000574 575#define MAC_EXTADDR_9_HIGH 0x00000578 576#define MAC_EXTADDR_9_LOW 0x0000057c 577#define MAC_EXTADDR_10_HIGH 0x00000580 578#define MAC_EXTADDR_10_LOW 0x00000584 579#define MAC_EXTADDR_11_HIGH 0x00000588 580#define MAC_EXTADDR_11_LOW 0x0000058c 581#define MAC_SERDES_CFG 0x00000590 582#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 583#define MAC_SERDES_STAT 0x00000594 584/* 0x598 --> 0x5a0 unused */ 585#define MAC_PHYCFG1 0x000005a0 586#define MAC_PHYCFG1_RGMII_INT 0x00000001 587#define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0 588#define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000 589#define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000 590#define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000 591#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 592#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 593#define MAC_PHYCFG1_TXC_DRV 0x20000000 594#define MAC_PHYCFG2 0x000005a4 595#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 596#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 597#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 598#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 599#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 600#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 601#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 602#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 603#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 604#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 605#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 606#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 607#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 608#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 609#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 610#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 611#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 612#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 613#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 614#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 615#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 616#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 617#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 618#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 619#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 620#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 621#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 622#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 623#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 624#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 625#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 626#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 627#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 628#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 629#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 630#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 631#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 632#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 633#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 634#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 635#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 636#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 637#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 638#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 639#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 640#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 641#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 642#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 643#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 644#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 645#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 646#define MAC_PHYCFG2_50610_LED_MODES \ 647 (MAC_PHYCFG2_EMODE_MASK_50610 | \ 648 MAC_PHYCFG2_EMODE_COMP_50610 | \ 649 MAC_PHYCFG2_FMODE_MASK_50610 | \ 650 MAC_PHYCFG2_FMODE_COMP_50610 | \ 651 MAC_PHYCFG2_GMODE_MASK_50610 | \ 652 MAC_PHYCFG2_GMODE_COMP_50610 | \ 653 MAC_PHYCFG2_ACT_MASK_50610 | \ 654 MAC_PHYCFG2_ACT_COMP_50610 | \ 655 MAC_PHYCFG2_QUAL_MASK_50610 | \ 656 MAC_PHYCFG2_QUAL_COMP_50610) 657#define MAC_PHYCFG2_AC131_LED_MODES \ 658 (MAC_PHYCFG2_EMODE_MASK_AC131 | \ 659 MAC_PHYCFG2_EMODE_COMP_AC131 | \ 660 MAC_PHYCFG2_FMODE_MASK_AC131 | \ 661 MAC_PHYCFG2_FMODE_COMP_AC131 | \ 662 MAC_PHYCFG2_GMODE_MASK_AC131 | \ 663 MAC_PHYCFG2_GMODE_COMP_AC131 | \ 664 MAC_PHYCFG2_ACT_MASK_AC131 | \ 665 MAC_PHYCFG2_ACT_COMP_AC131 | \ 666 MAC_PHYCFG2_QUAL_MASK_AC131 | \ 667 MAC_PHYCFG2_QUAL_COMP_AC131) 668#define MAC_PHYCFG2_RTL8211C_LED_MODES \ 669 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ 670 MAC_PHYCFG2_EMODE_COMP_RT8211 | \ 671 MAC_PHYCFG2_FMODE_MASK_RT8211 | \ 672 MAC_PHYCFG2_FMODE_COMP_RT8211 | \ 673 MAC_PHYCFG2_GMODE_MASK_RT8211 | \ 674 MAC_PHYCFG2_GMODE_COMP_RT8211 | \ 675 MAC_PHYCFG2_ACT_MASK_RT8211 | \ 676 MAC_PHYCFG2_ACT_COMP_RT8211 | \ 677 MAC_PHYCFG2_QUAL_MASK_RT8211 | \ 678 MAC_PHYCFG2_QUAL_COMP_RT8211) 679#define MAC_PHYCFG2_RTL8201E_LED_MODES \ 680 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ 681 MAC_PHYCFG2_EMODE_COMP_RT8201 | \ 682 MAC_PHYCFG2_FMODE_MASK_RT8201 | \ 683 MAC_PHYCFG2_FMODE_COMP_RT8201 | \ 684 MAC_PHYCFG2_GMODE_MASK_RT8201 | \ 685 MAC_PHYCFG2_GMODE_COMP_RT8201 | \ 686 MAC_PHYCFG2_ACT_MASK_RT8201 | \ 687 MAC_PHYCFG2_ACT_COMP_RT8201 | \ 688 MAC_PHYCFG2_QUAL_MASK_RT8201 | \ 689 MAC_PHYCFG2_QUAL_COMP_RT8201) 690#define MAC_EXT_RGMII_MODE 0x000005a8 691#define MAC_RGMII_MODE_TX_ENABLE 0x00000001 692#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 693#define MAC_RGMII_MODE_TX_RESET 0x00000004 694#define MAC_RGMII_MODE_RX_INT_B 0x00000100 695#define MAC_RGMII_MODE_RX_QUALITY 0x00000200 696#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 697#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 698/* 0x5ac --> 0x5b0 unused */ 699#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 700#define SERDES_RX_SIG_DETECT 0x00000400 701#define SG_DIG_CTRL 0x000005b0 702#define SG_DIG_USING_HW_AUTONEG 0x80000000 703#define SG_DIG_SOFT_RESET 0x40000000 704#define SG_DIG_DISABLE_LINKRDY 0x20000000 705#define SG_DIG_CRC16_CLEAR_N 0x01000000 706#define SG_DIG_EN10B 0x00800000 707#define SG_DIG_CLEAR_STATUS 0x00400000 708#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 709#define SG_DIG_LOCAL_LINK_STATUS 0x00100000 710#define SG_DIG_SPEED_STATUS_MASK 0x000c0000 711#define SG_DIG_SPEED_STATUS_SHIFT 18 712#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 713#define SG_DIG_RESTART_AUTONEG 0x00010000 714#define SG_DIG_FIBER_MODE 0x00008000 715#define SG_DIG_REMOTE_FAULT_MASK 0x00006000 716#define SG_DIG_PAUSE_MASK 0x00001800 717#define SG_DIG_PAUSE_CAP 0x00000800 718#define SG_DIG_ASYM_PAUSE 0x00001000 719#define SG_DIG_GBIC_ENABLE 0x00000400 720#define SG_DIG_CHECK_END_ENABLE 0x00000200 721#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 722#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 723#define SG_DIG_GMII_INPUT_SELECT 0x00000040 724#define SG_DIG_MRADV_CRC16_SELECT 0x00000020 725#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 726#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 727#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 728#define SG_DIG_REMOTE_LOOPBACK 0x00000002 729#define SG_DIG_LOOPBACK 0x00000001 730#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ 731 SG_DIG_LOCAL_DUPLEX_STATUS | \ 732 SG_DIG_LOCAL_LINK_STATUS | \ 733 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ 734 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) 735#define SG_DIG_STATUS 0x000005b4 736#define SG_DIG_CRC16_BUS_MASK 0xffff0000 737#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ 738#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ 739#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ 740#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ 741#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ 742#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ 743#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 744#define SG_DIG_IS_SERDES 0x00000100 745#define SG_DIG_COMMA_DETECTOR 0x00000008 746#define SG_DIG_MAC_ACK_STATUS 0x00000004 747#define SG_DIG_AUTONEG_COMPLETE 0x00000002 748#define SG_DIG_AUTONEG_ERROR 0x00000001 749/* 0x5b8 --> 0x600 unused */ 750#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 751#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 752/* 0x624 --> 0x670 unused */ 753 754#define MAC_RSS_INDIR_TBL_0 0x00000630 755 756#define MAC_RSS_HASH_KEY_0 0x00000670 757#define MAC_RSS_HASH_KEY_1 0x00000674 758#define MAC_RSS_HASH_KEY_2 0x00000678 759#define MAC_RSS_HASH_KEY_3 0x0000067c 760#define MAC_RSS_HASH_KEY_4 0x00000680 761#define MAC_RSS_HASH_KEY_5 0x00000684 762#define MAC_RSS_HASH_KEY_6 0x00000688 763#define MAC_RSS_HASH_KEY_7 0x0000068c 764#define MAC_RSS_HASH_KEY_8 0x00000690 765#define MAC_RSS_HASH_KEY_9 0x00000694 766/* 0x698 --> 0x800 unused */ 767 768#define MAC_TX_STATS_OCTETS 0x00000800 769#define MAC_TX_STATS_RESV1 0x00000804 770#define MAC_TX_STATS_COLLISIONS 0x00000808 771#define MAC_TX_STATS_XON_SENT 0x0000080c 772#define MAC_TX_STATS_XOFF_SENT 0x00000810 773#define MAC_TX_STATS_RESV2 0x00000814 774#define MAC_TX_STATS_MAC_ERRORS 0x00000818 775#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 776#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 777#define MAC_TX_STATS_DEFERRED 0x00000824 778#define MAC_TX_STATS_RESV3 0x00000828 779#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 780#define MAC_TX_STATS_LATE_COL 0x00000830 781#define MAC_TX_STATS_RESV4_1 0x00000834 782#define MAC_TX_STATS_RESV4_2 0x00000838 783#define MAC_TX_STATS_RESV4_3 0x0000083c 784#define MAC_TX_STATS_RESV4_4 0x00000840 785#define MAC_TX_STATS_RESV4_5 0x00000844 786#define MAC_TX_STATS_RESV4_6 0x00000848 787#define MAC_TX_STATS_RESV4_7 0x0000084c 788#define MAC_TX_STATS_RESV4_8 0x00000850 789#define MAC_TX_STATS_RESV4_9 0x00000854 790#define MAC_TX_STATS_RESV4_10 0x00000858 791#define MAC_TX_STATS_RESV4_11 0x0000085c 792#define MAC_TX_STATS_RESV4_12 0x00000860 793#define MAC_TX_STATS_RESV4_13 0x00000864 794#define MAC_TX_STATS_RESV4_14 0x00000868 795#define MAC_TX_STATS_UCAST 0x0000086c 796#define MAC_TX_STATS_MCAST 0x00000870 797#define MAC_TX_STATS_BCAST 0x00000874 798#define MAC_TX_STATS_RESV5_1 0x00000878 799#define MAC_TX_STATS_RESV5_2 0x0000087c 800#define MAC_RX_STATS_OCTETS 0x00000880 801#define MAC_RX_STATS_RESV1 0x00000884 802#define MAC_RX_STATS_FRAGMENTS 0x00000888 803#define MAC_RX_STATS_UCAST 0x0000088c 804#define MAC_RX_STATS_MCAST 0x00000890 805#define MAC_RX_STATS_BCAST 0x00000894 806#define MAC_RX_STATS_FCS_ERRORS 0x00000898 807#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 808#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 809#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 810#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 811#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 812#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 813#define MAC_RX_STATS_JABBERS 0x000008b4 814#define MAC_RX_STATS_UNDERSIZE 0x000008b8 815/* 0x8bc --> 0xc00 unused */ 816 817/* Send data initiator control registers */ 818#define SNDDATAI_MODE 0x00000c00 819#define SNDDATAI_MODE_RESET 0x00000001 820#define SNDDATAI_MODE_ENABLE 0x00000002 821#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 822#define SNDDATAI_STATUS 0x00000c04 823#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 824#define SNDDATAI_STATSCTRL 0x00000c08 825#define SNDDATAI_SCTRL_ENABLE 0x00000001 826#define SNDDATAI_SCTRL_FASTUPD 0x00000002 827#define SNDDATAI_SCTRL_CLEAR 0x00000004 828#define SNDDATAI_SCTRL_FLUSH 0x00000008 829#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 830#define SNDDATAI_STATSENAB 0x00000c0c 831#define SNDDATAI_STATSINCMASK 0x00000c10 832#define ISO_PKT_TX 0x00000c20 833/* 0xc24 --> 0xc80 unused */ 834#define SNDDATAI_COS_CNT_0 0x00000c80 835#define SNDDATAI_COS_CNT_1 0x00000c84 836#define SNDDATAI_COS_CNT_2 0x00000c88 837#define SNDDATAI_COS_CNT_3 0x00000c8c 838#define SNDDATAI_COS_CNT_4 0x00000c90 839#define SNDDATAI_COS_CNT_5 0x00000c94 840#define SNDDATAI_COS_CNT_6 0x00000c98 841#define SNDDATAI_COS_CNT_7 0x00000c9c 842#define SNDDATAI_COS_CNT_8 0x00000ca0 843#define SNDDATAI_COS_CNT_9 0x00000ca4 844#define SNDDATAI_COS_CNT_10 0x00000ca8 845#define SNDDATAI_COS_CNT_11 0x00000cac 846#define SNDDATAI_COS_CNT_12 0x00000cb0 847#define SNDDATAI_COS_CNT_13 0x00000cb4 848#define SNDDATAI_COS_CNT_14 0x00000cb8 849#define SNDDATAI_COS_CNT_15 0x00000cbc 850#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 851#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 852#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 853#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 854#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 855#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 856#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 857#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 858/* 0xce0 --> 0x1000 unused */ 859 860/* Send data completion control registers */ 861#define SNDDATAC_MODE 0x00001000 862#define SNDDATAC_MODE_RESET 0x00000001 863#define SNDDATAC_MODE_ENABLE 0x00000002 864#define SNDDATAC_MODE_CDELAY 0x00000010 865/* 0x1004 --> 0x1400 unused */ 866 867/* Send BD ring selector */ 868#define SNDBDS_MODE 0x00001400 869#define SNDBDS_MODE_RESET 0x00000001 870#define SNDBDS_MODE_ENABLE 0x00000002 871#define SNDBDS_MODE_ATTN_ENABLE 0x00000004 872#define SNDBDS_STATUS 0x00001404 873#define SNDBDS_STATUS_ERROR_ATTN 0x00000004 874#define SNDBDS_HWDIAG 0x00001408 875/* 0x140c --> 0x1440 */ 876#define SNDBDS_SEL_CON_IDX_0 0x00001440 877#define SNDBDS_SEL_CON_IDX_1 0x00001444 878#define SNDBDS_SEL_CON_IDX_2 0x00001448 879#define SNDBDS_SEL_CON_IDX_3 0x0000144c 880#define SNDBDS_SEL_CON_IDX_4 0x00001450 881#define SNDBDS_SEL_CON_IDX_5 0x00001454 882#define SNDBDS_SEL_CON_IDX_6 0x00001458 883#define SNDBDS_SEL_CON_IDX_7 0x0000145c 884#define SNDBDS_SEL_CON_IDX_8 0x00001460 885#define SNDBDS_SEL_CON_IDX_9 0x00001464 886#define SNDBDS_SEL_CON_IDX_10 0x00001468 887#define SNDBDS_SEL_CON_IDX_11 0x0000146c 888#define SNDBDS_SEL_CON_IDX_12 0x00001470 889#define SNDBDS_SEL_CON_IDX_13 0x00001474 890#define SNDBDS_SEL_CON_IDX_14 0x00001478 891#define SNDBDS_SEL_CON_IDX_15 0x0000147c 892/* 0x1480 --> 0x1800 unused */ 893 894/* Send BD initiator control registers */ 895#define SNDBDI_MODE 0x00001800 896#define SNDBDI_MODE_RESET 0x00000001 897#define SNDBDI_MODE_ENABLE 0x00000002 898#define SNDBDI_MODE_ATTN_ENABLE 0x00000004 899#define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020 900#define SNDBDI_STATUS 0x00001804 901#define SNDBDI_STATUS_ERROR_ATTN 0x00000004 902#define SNDBDI_IN_PROD_IDX_0 0x00001808 903#define SNDBDI_IN_PROD_IDX_1 0x0000180c 904#define SNDBDI_IN_PROD_IDX_2 0x00001810 905#define SNDBDI_IN_PROD_IDX_3 0x00001814 906#define SNDBDI_IN_PROD_IDX_4 0x00001818 907#define SNDBDI_IN_PROD_IDX_5 0x0000181c 908#define SNDBDI_IN_PROD_IDX_6 0x00001820 909#define SNDBDI_IN_PROD_IDX_7 0x00001824 910#define SNDBDI_IN_PROD_IDX_8 0x00001828 911#define SNDBDI_IN_PROD_IDX_9 0x0000182c 912#define SNDBDI_IN_PROD_IDX_10 0x00001830 913#define SNDBDI_IN_PROD_IDX_11 0x00001834 914#define SNDBDI_IN_PROD_IDX_12 0x00001838 915#define SNDBDI_IN_PROD_IDX_13 0x0000183c 916#define SNDBDI_IN_PROD_IDX_14 0x00001840 917#define SNDBDI_IN_PROD_IDX_15 0x00001844 918/* 0x1848 --> 0x1c00 unused */ 919 920/* Send BD completion control registers */ 921#define SNDBDC_MODE 0x00001c00 922#define SNDBDC_MODE_RESET 0x00000001 923#define SNDBDC_MODE_ENABLE 0x00000002 924#define SNDBDC_MODE_ATTN_ENABLE 0x00000004 925/* 0x1c04 --> 0x2000 unused */ 926 927/* Receive list placement control registers */ 928#define RCVLPC_MODE 0x00002000 929#define RCVLPC_MODE_RESET 0x00000001 930#define RCVLPC_MODE_ENABLE 0x00000002 931#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 932#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 933#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 934#define RCVLPC_STATUS 0x00002004 935#define RCVLPC_STATUS_CLASS0 0x00000004 936#define RCVLPC_STATUS_MAPOOR 0x00000008 937#define RCVLPC_STATUS_STAT_OFLOW 0x00000010 938#define RCVLPC_LOCK 0x00002008 939#define RCVLPC_LOCK_REQ_MASK 0x0000ffff 940#define RCVLPC_LOCK_REQ_SHIFT 0 941#define RCVLPC_LOCK_GRANT_MASK 0xffff0000 942#define RCVLPC_LOCK_GRANT_SHIFT 16 943#define RCVLPC_NON_EMPTY_BITS 0x0000200c 944#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 945#define RCVLPC_CONFIG 0x00002010 946#define RCVLPC_STATSCTRL 0x00002014 947#define RCVLPC_STATSCTRL_ENABLE 0x00000001 948#define RCVLPC_STATSCTRL_FASTUPD 0x00000002 949#define RCVLPC_STATS_ENABLE 0x00002018 950#define RCVLPC_STATSENAB_ASF_FIX 0x00000002 951#define RCVLPC_STATSENAB_DACK_FIX 0x00040000 952#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 953#define RCVLPC_STATS_INCMASK 0x0000201c 954/* 0x2020 --> 0x2100 unused */ 955#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 956#define SELLST_TAIL 0x00000004 957#define SELLST_CONT 0x00000008 958#define SELLST_UNUSED 0x0000000c 959#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 960#define RCVLPC_DROP_FILTER_CNT 0x00002240 961#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 962#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 963#define RCVLPC_NO_RCV_BD_CNT 0x0000224c 964#define RCVLPC_IN_DISCARDS_CNT 0x00002250 965#define RCVLPC_IN_ERRORS_CNT 0x00002254 966#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 967/* 0x225c --> 0x2400 unused */ 968 969/* Receive Data and Receive BD Initiator Control */ 970#define RCVDBDI_MODE 0x00002400 971#define RCVDBDI_MODE_RESET 0x00000001 972#define RCVDBDI_MODE_ENABLE 0x00000002 973#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 974#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 975#define RCVDBDI_MODE_INV_RING_SZ 0x00000010 976#define RCVDBDI_STATUS 0x00002404 977#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 978#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 979#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 980#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 981/* 0x240c --> 0x2440 unused */ 982#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 983#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 984#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 985#define RCVDBDI_JUMBO_CON_IDX 0x00002470 986#define RCVDBDI_STD_CON_IDX 0x00002474 987#define RCVDBDI_MINI_CON_IDX 0x00002478 988/* 0x247c --> 0x2480 unused */ 989#define RCVDBDI_BD_PROD_IDX_0 0x00002480 990#define RCVDBDI_BD_PROD_IDX_1 0x00002484 991#define RCVDBDI_BD_PROD_IDX_2 0x00002488 992#define RCVDBDI_BD_PROD_IDX_3 0x0000248c 993#define RCVDBDI_BD_PROD_IDX_4 0x00002490 994#define RCVDBDI_BD_PROD_IDX_5 0x00002494 995#define RCVDBDI_BD_PROD_IDX_6 0x00002498 996#define RCVDBDI_BD_PROD_IDX_7 0x0000249c 997#define RCVDBDI_BD_PROD_IDX_8 0x000024a0 998#define RCVDBDI_BD_PROD_IDX_9 0x000024a4 999#define RCVDBDI_BD_PROD_IDX_10 0x000024a8 1000#define RCVDBDI_BD_PROD_IDX_11 0x000024ac 1001#define RCVDBDI_BD_PROD_IDX_12 0x000024b0 1002#define RCVDBDI_BD_PROD_IDX_13 0x000024b4 1003#define RCVDBDI_BD_PROD_IDX_14 0x000024b8 1004#define RCVDBDI_BD_PROD_IDX_15 0x000024bc 1005#define RCVDBDI_HWDIAG 0x000024c0 1006/* 0x24c4 --> 0x2800 unused */ 1007 1008/* Receive Data Completion Control */ 1009#define RCVDCC_MODE 0x00002800 1010#define RCVDCC_MODE_RESET 0x00000001 1011#define RCVDCC_MODE_ENABLE 0x00000002 1012#define RCVDCC_MODE_ATTN_ENABLE 0x00000004 1013/* 0x2804 --> 0x2c00 unused */ 1014 1015/* Receive BD Initiator Control Registers */ 1016#define RCVBDI_MODE 0x00002c00 1017#define RCVBDI_MODE_RESET 0x00000001 1018#define RCVBDI_MODE_ENABLE 0x00000002 1019#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 1020#define RCVBDI_STATUS 0x00002c04 1021#define RCVBDI_STATUS_RCB_ATTN 0x00000004 1022#define RCVBDI_JUMBO_PROD_IDX 0x00002c08 1023#define RCVBDI_STD_PROD_IDX 0x00002c0c 1024#define RCVBDI_MINI_PROD_IDX 0x00002c10 1025#define RCVBDI_MINI_THRESH 0x00002c14 1026#define RCVBDI_STD_THRESH 0x00002c18 1027#define RCVBDI_JUMBO_THRESH 0x00002c1c 1028/* 0x2c20 --> 0x2d00 unused */ 1029 1030#define STD_REPLENISH_LWM 0x00002d00 1031#define JMB_REPLENISH_LWM 0x00002d04 1032/* 0x2d08 --> 0x3000 unused */ 1033 1034/* Receive BD Completion Control Registers */ 1035#define RCVCC_MODE 0x00003000 1036#define RCVCC_MODE_RESET 0x00000001 1037#define RCVCC_MODE_ENABLE 0x00000002 1038#define RCVCC_MODE_ATTN_ENABLE 0x00000004 1039#define RCVCC_STATUS 0x00003004 1040#define RCVCC_STATUS_ERROR_ATTN 0x00000004 1041#define RCVCC_JUMP_PROD_IDX 0x00003008 1042#define RCVCC_STD_PROD_IDX 0x0000300c 1043#define RCVCC_MINI_PROD_IDX 0x00003010 1044/* 0x3014 --> 0x3400 unused */ 1045 1046/* Receive list selector control registers */ 1047#define RCVLSC_MODE 0x00003400 1048#define RCVLSC_MODE_RESET 0x00000001 1049#define RCVLSC_MODE_ENABLE 0x00000002 1050#define RCVLSC_MODE_ATTN_ENABLE 0x00000004 1051#define RCVLSC_STATUS 0x00003404 1052#define RCVLSC_STATUS_ERROR_ATTN 0x00000004 1053/* 0x3408 --> 0x3600 unused */ 1054 1055/* CPMU registers */ 1056#define TG3_CPMU_CTRL 0x00003600 1057#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1058#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1059#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1060#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1061#define TG3_CPMU_LSPD_10MB_CLK 0x00003604 1062#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 1063#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1064/* 0x3608 --> 0x360c unused */ 1065 1066#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c 1067#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1068#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1069#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 1070#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 1071#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 1072#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1073/* 0x3614 --> 0x361c unused */ 1074 1075#define TG3_CPMU_HST_ACC 0x0000361c 1076#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 1077#define CPMU_HST_ACC_MACCLK_6_25 0x00130000 1078/* 0x3620 --> 0x3630 unused */ 1079 1080#define TG3_CPMU_CLCK_STAT 0x00003630 1081#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 1082#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1083#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1084#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1085/* 0x3634 --> 0x365c unused */ 1086 1087#define TG3_CPMU_MUTEX_REQ 0x0000365c 1088#define CPMU_MUTEX_REQ_DRIVER 0x00001000 1089#define TG3_CPMU_MUTEX_GNT 0x00003660 1090#define CPMU_MUTEX_GNT_DRIVER 0x00001000 1091#define TG3_CPMU_PHY_STRAP 0x00003664 1092#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1093/* 0x3664 --> 0x3800 unused */ 1094 1095/* Mbuf cluster free registers */ 1096#define MBFREE_MODE 0x00003800 1097#define MBFREE_MODE_RESET 0x00000001 1098#define MBFREE_MODE_ENABLE 0x00000002 1099#define MBFREE_STATUS 0x00003804 1100/* 0x3808 --> 0x3c00 unused */ 1101 1102/* Host coalescing control registers */ 1103#define HOSTCC_MODE 0x00003c00 1104#define HOSTCC_MODE_RESET 0x00000001 1105#define HOSTCC_MODE_ENABLE 0x00000002 1106#define HOSTCC_MODE_ATTN 0x00000004 1107#define HOSTCC_MODE_NOW 0x00000008 1108#define HOSTCC_MODE_FULL_STATUS 0x00000000 1109#define HOSTCC_MODE_64BYTE 0x00000080 1110#define HOSTCC_MODE_32BYTE 0x00000100 1111#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 1112#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 1113#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 1114#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 1115#define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000 1116#define HOSTCC_STATUS 0x00003c04 1117#define HOSTCC_STATUS_ERROR_ATTN 0x00000004 1118#define HOSTCC_RXCOL_TICKS 0x00003c08 1119#define LOW_RXCOL_TICKS 0x00000032 1120#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 1121#define DEFAULT_RXCOL_TICKS 0x00000048 1122#define HIGH_RXCOL_TICKS 0x00000096 1123#define MAX_RXCOL_TICKS 0x000003ff 1124#define HOSTCC_TXCOL_TICKS 0x00003c0c 1125#define LOW_TXCOL_TICKS 0x00000096 1126#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 1127#define DEFAULT_TXCOL_TICKS 0x0000012c 1128#define HIGH_TXCOL_TICKS 0x00000145 1129#define MAX_TXCOL_TICKS 0x000003ff 1130#define HOSTCC_RXMAX_FRAMES 0x00003c10 1131#define LOW_RXMAX_FRAMES 0x00000005 1132#define DEFAULT_RXMAX_FRAMES 0x00000008 1133#define HIGH_RXMAX_FRAMES 0x00000012 1134#define MAX_RXMAX_FRAMES 0x000000ff 1135#define HOSTCC_TXMAX_FRAMES 0x00003c14 1136#define LOW_TXMAX_FRAMES 0x00000035 1137#define DEFAULT_TXMAX_FRAMES 0x0000004b 1138#define HIGH_TXMAX_FRAMES 0x00000052 1139#define MAX_TXMAX_FRAMES 0x000000ff 1140#define HOSTCC_RXCOAL_TICK_INT 0x00003c18 1141#define DEFAULT_RXCOAL_TICK_INT 0x00000019 1142#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 1143#define MAX_RXCOAL_TICK_INT 0x000003ff 1144#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 1145#define DEFAULT_TXCOAL_TICK_INT 0x00000019 1146#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 1147#define MAX_TXCOAL_TICK_INT 0x000003ff 1148#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 1149#define DEFAULT_RXCOAL_MAXF_INT 0x00000005 1150#define MAX_RXCOAL_MAXF_INT 0x000000ff 1151#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 1152#define DEFAULT_TXCOAL_MAXF_INT 0x00000005 1153#define MAX_TXCOAL_MAXF_INT 0x000000ff 1154#define HOSTCC_STAT_COAL_TICKS 0x00003c28 1155#define DEFAULT_STAT_COAL_TICKS 0x000f4240 1156#define MAX_STAT_COAL_TICKS 0xd693d400 1157#define MIN_STAT_COAL_TICKS 0x00000064 1158/* 0x3c2c --> 0x3c30 unused */ 1159#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 1160#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 1161#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 1162#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 1163#define HOSTCC_FLOW_ATTN 0x00003c48 1164/* 0x3c4c --> 0x3c50 unused */ 1165#define HOSTCC_JUMBO_CON_IDX 0x00003c50 1166#define HOSTCC_STD_CON_IDX 0x00003c54 1167#define HOSTCC_MINI_CON_IDX 0x00003c58 1168/* 0x3c5c --> 0x3c80 unused */ 1169#define HOSTCC_RET_PROD_IDX_0 0x00003c80 1170#define HOSTCC_RET_PROD_IDX_1 0x00003c84 1171#define HOSTCC_RET_PROD_IDX_2 0x00003c88 1172#define HOSTCC_RET_PROD_IDX_3 0x00003c8c 1173#define HOSTCC_RET_PROD_IDX_4 0x00003c90 1174#define HOSTCC_RET_PROD_IDX_5 0x00003c94 1175#define HOSTCC_RET_PROD_IDX_6 0x00003c98 1176#define HOSTCC_RET_PROD_IDX_7 0x00003c9c 1177#define HOSTCC_RET_PROD_IDX_8 0x00003ca0 1178#define HOSTCC_RET_PROD_IDX_9 0x00003ca4 1179#define HOSTCC_RET_PROD_IDX_10 0x00003ca8 1180#define HOSTCC_RET_PROD_IDX_11 0x00003cac 1181#define HOSTCC_RET_PROD_IDX_12 0x00003cb0 1182#define HOSTCC_RET_PROD_IDX_13 0x00003cb4 1183#define HOSTCC_RET_PROD_IDX_14 0x00003cb8 1184#define HOSTCC_RET_PROD_IDX_15 0x00003cbc 1185#define HOSTCC_SND_CON_IDX_0 0x00003cc0 1186#define HOSTCC_SND_CON_IDX_1 0x00003cc4 1187#define HOSTCC_SND_CON_IDX_2 0x00003cc8 1188#define HOSTCC_SND_CON_IDX_3 0x00003ccc 1189#define HOSTCC_SND_CON_IDX_4 0x00003cd0 1190#define HOSTCC_SND_CON_IDX_5 0x00003cd4 1191#define HOSTCC_SND_CON_IDX_6 0x00003cd8 1192#define HOSTCC_SND_CON_IDX_7 0x00003cdc 1193#define HOSTCC_SND_CON_IDX_8 0x00003ce0 1194#define HOSTCC_SND_CON_IDX_9 0x00003ce4 1195#define HOSTCC_SND_CON_IDX_10 0x00003ce8 1196#define HOSTCC_SND_CON_IDX_11 0x00003cec 1197#define HOSTCC_SND_CON_IDX_12 0x00003cf0 1198#define HOSTCC_SND_CON_IDX_13 0x00003cf4 1199#define HOSTCC_SND_CON_IDX_14 0x00003cf8 1200#define HOSTCC_SND_CON_IDX_15 0x00003cfc 1201#define HOSTCC_STATBLCK_RING1 0x00003d00 1202/* 0x3d00 --> 0x3d80 unused */ 1203 1204#define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80 1205#define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84 1206#define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88 1207#define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c 1208#define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90 1209#define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94 1210/* 0x3d98 --> 0x4000 unused */ 1211 1212/* Memory arbiter control registers */ 1213#define MEMARB_MODE 0x00004000 1214#define MEMARB_MODE_RESET 0x00000001 1215#define MEMARB_MODE_ENABLE 0x00000002 1216#define MEMARB_STATUS 0x00004004 1217#define MEMARB_TRAP_ADDR_LOW 0x00004008 1218#define MEMARB_TRAP_ADDR_HIGH 0x0000400c 1219/* 0x4010 --> 0x4400 unused */ 1220 1221/* Buffer manager control registers */ 1222#define BUFMGR_MODE 0x00004400 1223#define BUFMGR_MODE_RESET 0x00000001 1224#define BUFMGR_MODE_ENABLE 0x00000002 1225#define BUFMGR_MODE_ATTN_ENABLE 0x00000004 1226#define BUFMGR_MODE_BM_TEST 0x00000008 1227#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 1228#define BUFMGR_STATUS 0x00004404 1229#define BUFMGR_STATUS_ERROR 0x00000004 1230#define BUFMGR_STATUS_MBLOW 0x00000010 1231#define BUFMGR_MB_POOL_ADDR 0x00004408 1232#define BUFMGR_MB_POOL_SIZE 0x0000440c 1233#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 1234#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 1235#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 1236#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 1237#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 1238#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 1239#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 1240#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 1241#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 1242#define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a 1243#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 1244#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b 1245#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e 1246#define BUFMGR_MB_HIGH_WATER 0x00004418 1247#define DEFAULT_MB_HIGH_WATER 0x00000060 1248#define DEFAULT_MB_HIGH_WATER_5705 0x00000060 1249#define DEFAULT_MB_HIGH_WATER_5906 0x00000010 1250#define DEFAULT_MB_HIGH_WATER_57765 0x000000a0 1251#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 1252#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 1253#define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea 1254#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 1255#define BUFMGR_MB_ALLOC_BIT 0x10000000 1256#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1257#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 1258#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 1259#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 1260#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 1261#define BUFMGR_DMA_LOW_WATER 0x00004434 1262#define DEFAULT_DMA_LOW_WATER 0x00000005 1263#define BUFMGR_DMA_HIGH_WATER 0x00004438 1264#define DEFAULT_DMA_HIGH_WATER 0x0000000a 1265#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 1266#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 1267#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 1268#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 1269#define BUFMGR_HWDIAG_0 0x0000444c 1270#define BUFMGR_HWDIAG_1 0x00004450 1271#define BUFMGR_HWDIAG_2 0x00004454 1272/* 0x4458 --> 0x4800 unused */ 1273 1274/* Read DMA control registers */ 1275#define RDMAC_MODE 0x00004800 1276#define RDMAC_MODE_RESET 0x00000001 1277#define RDMAC_MODE_ENABLE 0x00000002 1278#define RDMAC_MODE_TGTABORT_ENAB 0x00000004 1279#define RDMAC_MODE_MSTABORT_ENAB 0x00000008 1280#define RDMAC_MODE_PARITYERR_ENAB 0x00000010 1281#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1282#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1283#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 1284#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1285#define RDMAC_MODE_LNGREAD_ENAB 0x00000200 1286#define RDMAC_MODE_SPLIT_ENABLE 0x00000800 1287#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 1288#define RDMAC_MODE_SPLIT_RESET 0x00001000 1289#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 1290#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 1291#define RDMAC_MODE_FIFO_SIZE_128 0x00020000 1292#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 1293#define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000 1294#define RDMAC_MODE_IPV4_LSO_EN 0x08000000 1295#define RDMAC_MODE_IPV6_LSO_EN 0x10000000 1296#define RDMAC_STATUS 0x00004804 1297#define RDMAC_STATUS_TGTABORT 0x00000004 1298#define RDMAC_STATUS_MSTABORT 0x00000008 1299#define RDMAC_STATUS_PARITYERR 0x00000010 1300#define RDMAC_STATUS_ADDROFLOW 0x00000020 1301#define RDMAC_STATUS_FIFOOFLOW 0x00000040 1302#define RDMAC_STATUS_FIFOURUN 0x00000080 1303#define RDMAC_STATUS_FIFOOREAD 0x00000100 1304#define RDMAC_STATUS_LNGREAD 0x00000200 1305/* 0x4808 --> 0x4c00 unused */ 1306 1307/* Write DMA control registers */ 1308#define WDMAC_MODE 0x00004c00 1309#define WDMAC_MODE_RESET 0x00000001 1310#define WDMAC_MODE_ENABLE 0x00000002 1311#define WDMAC_MODE_TGTABORT_ENAB 0x00000004 1312#define WDMAC_MODE_MSTABORT_ENAB 0x00000008 1313#define WDMAC_MODE_PARITYERR_ENAB 0x00000010 1314#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1315#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1316#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 1317#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1318#define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1319#define WDMAC_MODE_RX_ACCEL 0x00000400 1320#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 1321#define WDMAC_MODE_BURST_ALL_DATA 0xc0000000 1322#define WDMAC_STATUS 0x00004c04 1323#define WDMAC_STATUS_TGTABORT 0x00000004 1324#define WDMAC_STATUS_MSTABORT 0x00000008 1325#define WDMAC_STATUS_PARITYERR 0x00000010 1326#define WDMAC_STATUS_ADDROFLOW 0x00000020 1327#define WDMAC_STATUS_FIFOOFLOW 0x00000040 1328#define WDMAC_STATUS_FIFOURUN 0x00000080 1329#define WDMAC_STATUS_FIFOOREAD 0x00000100 1330#define WDMAC_STATUS_LNGREAD 0x00000200 1331/* 0x4c08 --> 0x5000 unused */ 1332 1333/* Per-cpu register offsets (arm9) */ 1334#define CPU_MODE 0x00000000 1335#define CPU_MODE_RESET 0x00000001 1336#define CPU_MODE_HALT 0x00000400 1337#define CPU_STATE 0x00000004 1338#define CPU_EVTMASK 0x00000008 1339/* 0xc --> 0x1c reserved */ 1340#define CPU_PC 0x0000001c 1341#define CPU_INSN 0x00000020 1342#define CPU_SPAD_UFLOW 0x00000024 1343#define CPU_WDOG_CLEAR 0x00000028 1344#define CPU_WDOG_VECTOR 0x0000002c 1345#define CPU_WDOG_PC 0x00000030 1346#define CPU_HW_BP 0x00000034 1347/* 0x38 --> 0x44 unused */ 1348#define CPU_WDOG_SAVED_STATE 0x00000044 1349#define CPU_LAST_BRANCH_ADDR 0x00000048 1350#define CPU_SPAD_UFLOW_SET 0x0000004c 1351/* 0x50 --> 0x200 unused */ 1352#define CPU_R0 0x00000200 1353#define CPU_R1 0x00000204 1354#define CPU_R2 0x00000208 1355#define CPU_R3 0x0000020c 1356#define CPU_R4 0x00000210 1357#define CPU_R5 0x00000214 1358#define CPU_R6 0x00000218 1359#define CPU_R7 0x0000021c 1360#define CPU_R8 0x00000220 1361#define CPU_R9 0x00000224 1362#define CPU_R10 0x00000228 1363#define CPU_R11 0x0000022c 1364#define CPU_R12 0x00000230 1365#define CPU_R13 0x00000234 1366#define CPU_R14 0x00000238 1367#define CPU_R15 0x0000023c 1368#define CPU_R16 0x00000240 1369#define CPU_R17 0x00000244 1370#define CPU_R18 0x00000248 1371#define CPU_R19 0x0000024c 1372#define CPU_R20 0x00000250 1373#define CPU_R21 0x00000254 1374#define CPU_R22 0x00000258 1375#define CPU_R23 0x0000025c 1376#define CPU_R24 0x00000260 1377#define CPU_R25 0x00000264 1378#define CPU_R26 0x00000268 1379#define CPU_R27 0x0000026c 1380#define CPU_R28 0x00000270 1381#define CPU_R29 0x00000274 1382#define CPU_R30 0x00000278 1383#define CPU_R31 0x0000027c 1384/* 0x280 --> 0x400 unused */ 1385 1386#define RX_CPU_BASE 0x00005000 1387#define RX_CPU_MODE 0x00005000 1388#define RX_CPU_STATE 0x00005004 1389#define RX_CPU_PGMCTR 0x0000501c 1390#define RX_CPU_HWBKPT 0x00005034 1391#define TX_CPU_BASE 0x00005400 1392#define TX_CPU_MODE 0x00005400 1393#define TX_CPU_STATE 0x00005404 1394#define TX_CPU_PGMCTR 0x0000541c 1395 1396#define VCPU_STATUS 0x00005100 1397#define VCPU_STATUS_INIT_DONE 0x04000000 1398#define VCPU_STATUS_DRV_RESET 0x08000000 1399 1400#define VCPU_CFGSHDW 0x00005104 1401#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001 1402#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004 1403#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 1404 1405/* Mailboxes */ 1406#define GRCMBOX_BASE 0x00005600 1407#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1408#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 1409#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 1410#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 1411#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 1412#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 1413#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 1414#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 1415#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 1416#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 1417#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 1418#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 1419#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 1420#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 1421#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 1422#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 1423#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 1424#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 1425#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 1426#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 1427#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 1428#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 1429#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 1430#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 1431#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 1432#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 1433#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 1434#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 1435#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 1436#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 1437#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 1438#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 1439#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 1440#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 1441#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 1442#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 1443#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 1444#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 1445#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 1446#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 1447#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 1448#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 1449#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 1450#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 1451#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 1452#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 1453#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 1454#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 1455#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 1456#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 1457#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 1458#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 1459#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 1460#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 1461#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 1462#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 1463#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 1464#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 1465#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 1466#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 1467#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 1468#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 1469#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 1470#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 1471#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 1472#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 1473#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 1474#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 1475/* 0x5a10 --> 0x5c00 */ 1476 1477/* Flow Through queues */ 1478#define FTQ_RESET 0x00005c00 1479/* 0x5c04 --> 0x5c10 unused */ 1480#define FTQ_DMA_NORM_READ_CTL 0x00005c10 1481#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 1482#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 1483#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 1484#define FTQ_DMA_HIGH_READ_CTL 0x00005c20 1485#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 1486#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 1487#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 1488#define FTQ_DMA_COMP_DISC_CTL 0x00005c30 1489#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 1490#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 1491#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 1492#define FTQ_SEND_BD_COMP_CTL 0x00005c40 1493#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 1494#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 1495#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 1496#define FTQ_SEND_DATA_INIT_CTL 0x00005c50 1497#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 1498#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 1499#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 1500#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 1501#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 1502#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 1503#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 1504#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 1505#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 1506#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 1507#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 1508#define FTQ_SWTYPE1_CTL 0x00005c80 1509#define FTQ_SWTYPE1_FULL_CNT 0x00005c84 1510#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 1511#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 1512#define FTQ_SEND_DATA_COMP_CTL 0x00005c90 1513#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 1514#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 1515#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 1516#define FTQ_HOST_COAL_CTL 0x00005ca0 1517#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 1518#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 1519#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 1520#define FTQ_MAC_TX_CTL 0x00005cb0 1521#define FTQ_MAC_TX_FULL_CNT 0x00005cb4 1522#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 1523#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 1524#define FTQ_MB_FREE_CTL 0x00005cc0 1525#define FTQ_MB_FREE_FULL_CNT 0x00005cc4 1526#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 1527#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 1528#define FTQ_RCVBD_COMP_CTL 0x00005cd0 1529#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 1530#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 1531#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 1532#define FTQ_RCVLST_PLMT_CTL 0x00005ce0 1533#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 1534#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 1535#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 1536#define FTQ_RCVDATA_INI_CTL 0x00005cf0 1537#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 1538#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 1539#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 1540#define FTQ_RCVDATA_COMP_CTL 0x00005d00 1541#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 1542#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 1543#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 1544#define FTQ_SWTYPE2_CTL 0x00005d10 1545#define FTQ_SWTYPE2_FULL_CNT 0x00005d14 1546#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 1547#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 1548/* 0x5d20 --> 0x6000 unused */ 1549 1550/* Message signaled interrupt registers */ 1551#define MSGINT_MODE 0x00006000 1552#define MSGINT_MODE_RESET 0x00000001 1553#define MSGINT_MODE_ENABLE 0x00000002 1554#define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020 1555#define MSGINT_MODE_MULTIVEC_EN 0x00000080 1556#define MSGINT_STATUS 0x00006004 1557#define MSGINT_FIFO 0x00006008 1558/* 0x600c --> 0x6400 unused */ 1559 1560/* DMA completion registers */ 1561#define DMAC_MODE 0x00006400 1562#define DMAC_MODE_RESET 0x00000001 1563#define DMAC_MODE_ENABLE 0x00000002 1564/* 0x6404 --> 0x6800 unused */ 1565 1566/* GRC registers */ 1567#define GRC_MODE 0x00006800 1568#define GRC_MODE_UPD_ON_COAL 0x00000001 1569#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 1570#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 1571#define GRC_MODE_BSWAP_DATA 0x00000010 1572#define GRC_MODE_WSWAP_DATA 0x00000020 1573#define GRC_MODE_SPLITHDR 0x00000100 1574#define GRC_MODE_NOFRM_CRACKING 0x00000200 1575#define GRC_MODE_INCL_CRC 0x00000400 1576#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 1577#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 1578#define GRC_MODE_NOIRQ_ON_RCV 0x00004000 1579#define GRC_MODE_FORCE_PCI32BIT 0x00008000 1580#define GRC_MODE_HOST_STACKUP 0x00010000 1581#define GRC_MODE_HOST_SENDBDS 0x00020000 1582#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1583#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 1584#define GRC_MODE_PCIE_TL_SEL 0x00000000 1585#define GRC_MODE_PCIE_PL_SEL 0x00400000 1586#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1587#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1588#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1589#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 1590#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1591#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1592#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1593#define GRC_MODE_PCIE_DL_SEL 0x20000000 1594#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1595#define GRC_MODE_PCIE_HI_1K_EN 0x80000000 1596#define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \ 1597 GRC_MODE_PCIE_PL_SEL | \ 1598 GRC_MODE_PCIE_DL_SEL | \ 1599 GRC_MODE_PCIE_HI_1K_EN) 1600#define GRC_MISC_CFG 0x00006804 1601#define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1602#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1603#define GRC_MISC_CFG_PRESCALAR_SHIFT 1 1604#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 1605#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 1606#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 1607#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 1608#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 1609#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 1610#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 1611#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 1612#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 1613#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1614#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1615#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1616#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 1617#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1618#define GRC_LOCAL_CTRL 0x00006808 1619#define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1620#define GRC_LCLCTRL_CLEARINT 0x00000002 1621#define GRC_LCLCTRL_SETINT 0x00000004 1622#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1623#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1624#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1625#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1626#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 1627#define GRC_LCLCTRL_GPIO_OE3 0x00000040 1628#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 1629#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1630#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1631#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1632#define GRC_LCLCTRL_GPIO_OE0 0x00000800 1633#define GRC_LCLCTRL_GPIO_OE1 0x00001000 1634#define GRC_LCLCTRL_GPIO_OE2 0x00002000 1635#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 1636#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 1637#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 1638#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 1639#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 1640#define GRC_LCLCTRL_MEMSZ_256K 0x00000000 1641#define GRC_LCLCTRL_MEMSZ_512K 0x00040000 1642#define GRC_LCLCTRL_MEMSZ_1M 0x00080000 1643#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 1644#define GRC_LCLCTRL_MEMSZ_4M 0x00100000 1645#define GRC_LCLCTRL_MEMSZ_8M 0x00140000 1646#define GRC_LCLCTRL_MEMSZ_16M 0x00180000 1647#define GRC_LCLCTRL_BANK_SELECT 0x00200000 1648#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 1649#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1650#define GRC_TIMER 0x0000680c 1651#define GRC_RX_CPU_EVENT 0x00006810 1652#define GRC_RX_CPU_DRIVER_EVENT 0x00004000 1653#define GRC_RX_TIMER_REF 0x00006814 1654#define GRC_RX_CPU_SEM 0x00006818 1655#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1656#define GRC_TX_CPU_EVENT 0x00006820 1657#define GRC_TX_TIMER_REF 0x00006824 1658#define GRC_TX_CPU_SEM 0x00006828 1659#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 1660#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 1661#define GRC_EEPROM_ADDR 0x00006838 1662#define EEPROM_ADDR_WRITE 0x00000000 1663#define EEPROM_ADDR_READ 0x80000000 1664#define EEPROM_ADDR_COMPLETE 0x40000000 1665#define EEPROM_ADDR_FSM_RESET 0x20000000 1666#define EEPROM_ADDR_DEVID_MASK 0x1c000000 1667#define EEPROM_ADDR_DEVID_SHIFT 26 1668#define EEPROM_ADDR_START 0x02000000 1669#define EEPROM_ADDR_CLKPERD_SHIFT 16 1670#define EEPROM_ADDR_ADDR_MASK 0x0000ffff 1671#define EEPROM_ADDR_ADDR_SHIFT 0 1672#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 1673#define EEPROM_CHIP_SIZE (64 * 1024) 1674#define GRC_EEPROM_DATA 0x0000683c 1675#define GRC_EEPROM_CTRL 0x00006840 1676#define GRC_MDI_CTRL 0x00006844 1677#define GRC_SEEPROM_DELAY 0x00006848 1678/* 0x684c --> 0x6890 unused */ 1679#define GRC_VCPU_EXT_CTRL 0x00006890 1680#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1681#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1682#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ 1683 1684/* 0x6c00 --> 0x7000 unused */ 1685 1686/* NVRAM Control registers */ 1687#define NVRAM_CMD 0x00007000 1688#define NVRAM_CMD_RESET 0x00000001 1689#define NVRAM_CMD_DONE 0x00000008 1690#define NVRAM_CMD_GO 0x00000010 1691#define NVRAM_CMD_WR 0x00000020 1692#define NVRAM_CMD_RD 0x00000000 1693#define NVRAM_CMD_ERASE 0x00000040 1694#define NVRAM_CMD_FIRST 0x00000080 1695#define NVRAM_CMD_LAST 0x00000100 1696#define NVRAM_CMD_WREN 0x00010000 1697#define NVRAM_CMD_WRDI 0x00020000 1698#define NVRAM_STAT 0x00007004 1699#define NVRAM_WRDATA 0x00007008 1700#define NVRAM_ADDR 0x0000700c 1701#define NVRAM_ADDR_MSK 0x00ffffff 1702#define NVRAM_RDDATA 0x00007010 1703#define NVRAM_CFG1 0x00007014 1704#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 1705#define NVRAM_CFG1_BUFFERED_MODE 0x00000002 1706#define NVRAM_CFG1_PASS_THRU 0x00000004 1707#define NVRAM_CFG1_STATUS_BITS 0x00000070 1708#define NVRAM_CFG1_BIT_BANG 0x00000008 1709#define NVRAM_CFG1_FLASH_SIZE 0x02000000 1710#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 1711#define NVRAM_CFG1_VENDOR_MASK 0x03000003 1712#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 1713#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1714#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 1715#define FLASH_VENDOR_ST 0x03000001 1716#define FLASH_VENDOR_SAIFUN 0x01000003 1717#define FLASH_VENDOR_SST_SMALL 0x00000001 1718#define FLASH_VENDOR_SST_LARGE 0x02000001 1719#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 1720#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 1721#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 1722#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1723#define FLASH_5752VENDOR_ST_M45PE10 0x02400000 1724#define FLASH_5752VENDOR_ST_M45PE20 0x02400002 1725#define FLASH_5752VENDOR_ST_M45PE40 0x02400001 1726#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 1727#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 1728#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 1729#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 1730#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003 1731#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 1732#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 1733#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 1734#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 1735#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 1736#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 1737#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003 1738#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000 1739#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002 1740#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001 1741#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003 1742#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000 1743#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002 1744#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001 1745#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001 1746#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000 1747#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002 1748#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003 1749#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001 1750#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 1751#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 1752#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 1753#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000 1754#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000 1755#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002 1756#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 1757#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 1758#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 1759#define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001 1760#define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003 1761#define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001 1762#define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003 1763#define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000 1764#define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002 1765#define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001 1766#define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003 1767#define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000 1768#define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002 1769#define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001 1770#define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003 1771#define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000 1772#define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002 1773#define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001 1774#define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003 1775#define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000 1776#define FLASH_5717VENDOR_ST_25USPT 0x03400002 1777#define FLASH_5717VENDOR_ST_45USPT 0x03400001 1778#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1779#define FLASH_5752PAGE_SIZE_256 0x00000000 1780#define FLASH_5752PAGE_SIZE_512 0x10000000 1781#define FLASH_5752PAGE_SIZE_1K 0x20000000 1782#define FLASH_5752PAGE_SIZE_2K 0x30000000 1783#define FLASH_5752PAGE_SIZE_4K 0x40000000 1784#define FLASH_5752PAGE_SIZE_264 0x50000000 1785#define FLASH_5752PAGE_SIZE_528 0x60000000 1786#define NVRAM_CFG2 0x00007018 1787#define NVRAM_CFG3 0x0000701c 1788#define NVRAM_SWARB 0x00007020 1789#define SWARB_REQ_SET0 0x00000001 1790#define SWARB_REQ_SET1 0x00000002 1791#define SWARB_REQ_SET2 0x00000004 1792#define SWARB_REQ_SET3 0x00000008 1793#define SWARB_REQ_CLR0 0x00000010 1794#define SWARB_REQ_CLR1 0x00000020 1795#define SWARB_REQ_CLR2 0x00000040 1796#define SWARB_REQ_CLR3 0x00000080 1797#define SWARB_GNT0 0x00000100 1798#define SWARB_GNT1 0x00000200 1799#define SWARB_GNT2 0x00000400 1800#define SWARB_GNT3 0x00000800 1801#define SWARB_REQ0 0x00001000 1802#define SWARB_REQ1 0x00002000 1803#define SWARB_REQ2 0x00004000 1804#define SWARB_REQ3 0x00008000 1805#define NVRAM_ACCESS 0x00007024 1806#define ACCESS_ENABLE 0x00000001 1807#define ACCESS_WR_ENABLE 0x00000002 1808#define NVRAM_WRITE1 0x00007028 1809/* 0x702c unused */ 1810 1811#define NVRAM_ADDR_LOCKOUT 0x00007030 1812/* 0x7034 --> 0x7500 unused */ 1813 1814#define OTP_MODE 0x00007500 1815#define OTP_MODE_OTP_THRU_GRC 0x00000001 1816#define OTP_CTRL 0x00007504 1817#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000 1818#define OTP_CTRL_OTP_CMD_READ 0x00000000 1819#define OTP_CTRL_OTP_CMD_INIT 0x00000008 1820#define OTP_CTRL_OTP_CMD_START 0x00000001 1821#define OTP_STATUS 0x00007508 1822#define OTP_STATUS_CMD_DONE 0x00000001 1823#define OTP_ADDRESS 0x0000750c 1824#define OTP_ADDRESS_MAGIC1 0x000000a0 1825#define OTP_ADDRESS_MAGIC2 0x00000080 1826/* 0x7510 unused */ 1827 1828#define OTP_READ_DATA 0x00007514 1829/* 0x7518 --> 0x7c04 unused */ 1830 1831#define PCIE_TRANSACTION_CFG 0x00007c04 1832#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 1833#define PCIE_TRANS_CFG_LOM 0x00000020 1834/* 0x7c08 --> 0x7d28 unused */ 1835 1836#define PCIE_PWR_MGMT_THRESH 0x00007d28 1837#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 1838#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 1839#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 1840/* 0x7d2c --> 0x7d54 unused */ 1841 1842#define TG3_PCIE_LNKCTL 0x00007d54 1843#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 1844#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 1845/* 0x7d58 --> 0x7e70 unused */ 1846 1847#define TG3_PCIE_PHY_TSTCTL 0x00007e2c 1848#define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040 1849#define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 1850 1851#define TG3_PCIE_EIDLE_DELAY 0x00007e70 1852#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f 1853#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c 1854/* 0x7e74 --> 0x8000 unused */ 1855 1856 1857/* Alternate PCIE definitions */ 1858#define TG3_PCIE_TLDLPL_PORT 0x00007c00 1859#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 1860#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 1861#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 1862#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 1863 1864/* OTP bit definitions */ 1865#define TG3_OTP_AGCTGT_MASK 0x000000e0 1866#define TG3_OTP_AGCTGT_SHIFT 1 1867#define TG3_OTP_HPFFLTR_MASK 0x00000300 1868#define TG3_OTP_HPFFLTR_SHIFT 1 1869#define TG3_OTP_HPFOVER_MASK 0x00000400 1870#define TG3_OTP_HPFOVER_SHIFT 1 1871#define TG3_OTP_LPFDIS_MASK 0x00000800 1872#define TG3_OTP_LPFDIS_SHIFT 11 1873#define TG3_OTP_VDAC_MASK 0xff000000 1874#define TG3_OTP_VDAC_SHIFT 24 1875#define TG3_OTP_10BTAMP_MASK 0x0000f000 1876#define TG3_OTP_10BTAMP_SHIFT 8 1877#define TG3_OTP_ROFF_MASK 0x00e00000 1878#define TG3_OTP_ROFF_SHIFT 11 1879#define TG3_OTP_RCOFF_MASK 0x001c0000 1880#define TG3_OTP_RCOFF_SHIFT 16 1881 1882#define TG3_OTP_DEFAULT 0x286c1640 1883 1884 1885/* Hardware Legacy NVRAM layout */ 1886#define TG3_NVM_VPD_OFF 0x100 1887#define TG3_NVM_VPD_LEN 256 1888 1889/* Hardware Selfboot NVRAM layout */ 1890#define TG3_NVM_HWSB_CFG1 0x00000004 1891#define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 1892#define TG3_NVM_HWSB_CFG1_MAJSFT 27 1893#define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 1894#define TG3_NVM_HWSB_CFG1_MINSFT 22 1895 1896#define TG3_EEPROM_MAGIC 0x669955aa 1897#define TG3_EEPROM_MAGIC_FW 0xa5000000 1898#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 1899#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 1900#define TG3_EEPROM_SB_FORMAT_1 0x00200000 1901#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 1902#define TG3_EEPROM_SB_REVISION_0 0x00000000 1903#define TG3_EEPROM_SB_REVISION_2 0x00020000 1904#define TG3_EEPROM_SB_REVISION_3 0x00030000 1905#define TG3_EEPROM_SB_REVISION_4 0x00040000 1906#define TG3_EEPROM_SB_REVISION_5 0x00050000 1907#define TG3_EEPROM_MAGIC_HW 0xabcd 1908#define TG3_EEPROM_MAGIC_HW_MSK 0xffff 1909 1910#define TG3_NVM_DIR_START 0x18 1911#define TG3_NVM_DIR_END 0x78 1912#define TG3_NVM_DIRENT_SIZE 0xc 1913#define TG3_NVM_DIRTYPE_SHIFT 24 1914#define TG3_NVM_DIRTYPE_ASFINI 1 1915#define TG3_NVM_PTREV_BCVER 0x94 1916#define TG3_NVM_BCVER_MAJMSK 0x0000ff00 1917#define TG3_NVM_BCVER_MAJSFT 8 1918#define TG3_NVM_BCVER_MINMSK 0x000000ff 1919 1920#define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 1921#define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 1922#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 1923#define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 1924#define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c 1925#define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20 1926#define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 1927#define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 1928#define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff 1929#define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800 1930#define TG3_EEPROM_SB_EDH_BLD_SHFT 11 1931 1932 1933/* 32K Window into NIC internal memory */ 1934#define NIC_SRAM_WIN_BASE 0x00008000 1935 1936/* Offsets into first 32k of NIC internal memory. */ 1937#define NIC_SRAM_PAGE_ZERO 0x00000000 1938#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 1939#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 1940#define NIC_SRAM_STATS_BLK 0x00000300 1941#define NIC_SRAM_STATUS_BLK 0x00000b00 1942 1943#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 1944#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 1945#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 1946 1947#define NIC_SRAM_DATA_SIG 0x00000b54 1948#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 1949 1950#define NIC_SRAM_DATA_CFG 0x00000b58 1951#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 1952#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 1953#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 1954#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 1955#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 1956#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 1957#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 1958#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 1959#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 1960#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 1961#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 1962#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 1963#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 1964#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 1965#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000 1966 1967#define NIC_SRAM_DATA_VER 0x00000b5c 1968#define NIC_SRAM_DATA_VER_SHIFT 16 1969 1970#define NIC_SRAM_DATA_PHY_ID 0x00000b74 1971#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 1972#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 1973 1974#define NIC_SRAM_FW_CMD_MBOX 0x00000b78 1975#define FWCMD_NICDRV_ALIVE 0x00000001 1976#define FWCMD_NICDRV_PAUSE_FW 0x00000002 1977#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 1978#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 1979#define FWCMD_NICDRV_FIX_DMAR 0x00000005 1980#define FWCMD_NICDRV_FIX_DMAW 0x00000006 1981#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c 1982#define FWCMD_NICDRV_ALIVE2 0x0000000d 1983#define FWCMD_NICDRV_ALIVE3 0x0000000e 1984#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 1985#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 1986#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 1987#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 1988#define DRV_STATE_START 0x00000001 1989#define DRV_STATE_START_DONE 0x80000001 1990#define DRV_STATE_UNLOAD 0x00000002 1991#define DRV_STATE_UNLOAD_DONE 0x80000002 1992#define DRV_STATE_WOL 0x00000003 1993#define DRV_STATE_SUSPEND 0x00000004 1994 1995#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 1996 1997#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 1998#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 1999 2000#define NIC_SRAM_WOL_MBOX 0x00000d30 2001#define WOL_SIGNATURE 0x474c0000 2002#define WOL_DRV_STATE_SHUTDOWN 0x00000001 2003#define WOL_DRV_WOL 0x00000002 2004#define WOL_SET_MAGIC_PKT 0x00000004 2005 2006#define NIC_SRAM_DATA_CFG_2 0x00000d38 2007 2008#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400 2009#define SHASTA_EXT_LED_MODE_MASK 0x00018000 2010#define SHASTA_EXT_LED_LEGACY 0x00000000 2011#define SHASTA_EXT_LED_SHARED 0x00008000 2012#define SHASTA_EXT_LED_MAC 0x00010000 2013#define SHASTA_EXT_LED_COMBO 0x00018000 2014 2015#define NIC_SRAM_DATA_CFG_3 0x00000d3c 2016#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 2017 2018#define NIC_SRAM_DATA_CFG_4 0x00000d60 2019#define NIC_SRAM_GMII_MODE 0x00000002 2020#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004 2021#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 2022#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 2023 2024#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 2025 2026#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 2027#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 2028#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 2029#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 2030#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 2031#define NIC_SRAM_MBUF_POOL_BASE 0x00008000 2032#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 2033#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 2034#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 2035#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 2036 2037 2038/* Currently this is fixed. */ 2039#define TG3_PHY_MII_ADDR 0x01 2040 2041 2042/*** Tigon3 specific PHY MII registers. ***/ 2043#define TG3_BMCR_SPEED1000 0x0040 2044 2045#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ 2046#define MII_TG3_CTRL_ADV_1000_HALF 0x0100 2047#define MII_TG3_CTRL_ADV_1000_FULL 0x0200 2048#define MII_TG3_CTRL_AS_MASTER 0x0800 2049#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 2050 2051#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 2052#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 2053#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 2054#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 2055#define MII_TG3_EXT_CTRL_TBI 0x8000 2056 2057#define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 2058#define MII_TG3_EXT_STAT_LPASS 0x0100 2059 2060#define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */ 2061#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 2062#define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ 2063#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 2064 2065#define MII_TG3_DSP_TAP1 0x0001 2066#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007 2067#define MII_TG3_DSP_AADJ1CH0 0x001f 2068#define MII_TG3_DSP_AADJ1CH3 0x601f 2069#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 2070#define MII_TG3_DSP_EXP1_INT_STAT 0x0f01 2071#define MII_TG3_DSP_EXP8 0x0f08 2072#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 2073#define MII_TG3_DSP_EXP8_AEDW 0x0200 2074#define MII_TG3_DSP_EXP75 0x0f75 2075#define MII_TG3_DSP_EXP96 0x0f96 2076#define MII_TG3_DSP_EXP97 0x0f97 2077 2078#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ 2079 2080#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 2081#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 2082#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 2083#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 2084 2085#define MII_TG3_AUXCTL_MISC_WREN 0x8000 2086#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 2087#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000 2088#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 2089 2090#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 2091#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 2092#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 2093 2094#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ 2095#define MII_TG3_AUX_STAT_LPASS 0x0004 2096#define MII_TG3_AUX_STAT_SPDMASK 0x0700 2097#define MII_TG3_AUX_STAT_10HALF 0x0100 2098#define MII_TG3_AUX_STAT_10FULL 0x0200 2099#define MII_TG3_AUX_STAT_100HALF 0x0300 2100#define MII_TG3_AUX_STAT_100_4 0x0400 2101#define MII_TG3_AUX_STAT_100FULL 0x0500 2102#define MII_TG3_AUX_STAT_1000HALF 0x0600 2103#define MII_TG3_AUX_STAT_1000FULL 0x0700 2104#define MII_TG3_AUX_STAT_100 0x0008 2105#define MII_TG3_AUX_STAT_FULL 0x0001 2106 2107#define MII_TG3_ISTAT 0x1a /* IRQ status register */ 2108#define MII_TG3_IMASK 0x1b /* IRQ mask register */ 2109 2110/* ISTAT/IMASK event bits */ 2111#define MII_TG3_INT_LINKCHG 0x0002 2112#define MII_TG3_INT_SPEEDCHG 0x0004 2113#define MII_TG3_INT_DUPLEXCHG 0x0008 2114#define MII_TG3_INT_ANEG_PAGE_RX 0x0400 2115 2116#define MII_TG3_MISC_SHDW 0x1c 2117#define MII_TG3_MISC_SHDW_WREN 0x8000 2118 2119#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 2120#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 2121#define MII_TG3_MISC_SHDW_APD_SEL 0x2800 2122 2123#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 2124#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002 2125#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 2126#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 2127#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 2128#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 2129 2130#define MII_TG3_TEST1 0x1e 2131#define MII_TG3_TEST1_TRIM_EN 0x0010 2132#define MII_TG3_TEST1_CRC_EN 0x8000 2133 2134 2135/* Fast Ethernet Tranceiver definitions */ 2136#define MII_TG3_FET_PTEST 0x17 2137#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000 2138#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800 2139 2140#define MII_TG3_FET_TEST 0x1f 2141#define MII_TG3_FET_SHADOW_EN 0x0080 2142 2143#define MII_TG3_FET_SHDW_MISCCTRL 0x10 2144#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 2145 2146#define MII_TG3_FET_SHDW_AUXMODE4 0x1a 2147#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 2148 2149#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b 2150#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 2151 2152 2153/* APE registers. Accessible through BAR1 */ 2154#define TG3_APE_EVENT 0x000c 2155#define APE_EVENT_1 0x00000001 2156#define TG3_APE_LOCK_REQ 0x002c 2157#define APE_LOCK_REQ_DRIVER 0x00001000 2158#define TG3_APE_LOCK_GRANT 0x004c 2159#define APE_LOCK_GRANT_DRIVER 0x00001000 2160#define TG3_APE_SEG_SIG 0x4000 2161#define APE_SEG_SIG_MAGIC 0x41504521 2162 2163/* APE shared memory. Accessible through BAR1 */ 2164#define TG3_APE_FW_STATUS 0x400c 2165#define APE_FW_STATUS_READY 0x00000100 2166#define TG3_APE_FW_FEATURES 0x4010 2167#define TG3_APE_FW_FEATURE_NCSI 0x00000002 2168#define TG3_APE_FW_VERSION 0x4018 2169#define APE_FW_VERSION_MAJMSK 0xff000000 2170#define APE_FW_VERSION_MAJSFT 24 2171#define APE_FW_VERSION_MINMSK 0x00ff0000 2172#define APE_FW_VERSION_MINSFT 16 2173#define APE_FW_VERSION_REVMSK 0x0000ff00 2174#define APE_FW_VERSION_REVSFT 8 2175#define APE_FW_VERSION_BLDMSK 0x000000ff 2176#define TG3_APE_HOST_SEG_SIG 0x4200 2177#define APE_HOST_SEG_SIG_MAGIC 0x484f5354 2178#define TG3_APE_HOST_SEG_LEN 0x4204 2179#define APE_HOST_SEG_LEN_MAGIC 0x0000001c 2180#define TG3_APE_HOST_INIT_COUNT 0x4208 2181#define TG3_APE_HOST_DRIVER_ID 0x420c 2182#define APE_HOST_DRIVER_ID_LINUX 0xf0000000 2183#define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2184 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8) 2185#define TG3_APE_HOST_BEHAVIOR 0x4210 2186#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2187#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214 2188#define APE_HOST_HEARTBEAT_INT_DISABLE 0 2189#define APE_HOST_HEARTBEAT_INT_5SEC 5000 2190#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218 2191 2192#define TG3_APE_EVENT_STATUS 0x4300 2193 2194#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2195#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2196#define APE_EVENT_STATUS_STATE_START 0x00010000 2197#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2198#define APE_EVENT_STATUS_STATE_WOL 0x00030000 2199#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2200#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2201 2202#define TG3_APE_PER_LOCK_REQ 0x8400 2203#define APE_LOCK_PER_REQ_DRIVER 0x00001000 2204#define TG3_APE_PER_LOCK_GRANT 0x8420 2205#define APE_PER_LOCK_GRANT_DRIVER 0x00001000 2206 2207/* APE convenience enumerations. */ 2208#define TG3_APE_LOCK_GRC 1 2209#define TG3_APE_LOCK_MEM 4 2210 2211#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2212 2213 2214/* There are two ways to manage the TX descriptors on the tigon3. 2215 * Either the descriptors are in host DMA'able memory, or they 2216 * exist only in the cards on-chip SRAM. All 16 send bds are under 2217 * the same mode, they may not be configured individually. 2218 * 2219 * This driver always uses host memory TX descriptors. 2220 * 2221 * To use host memory TX descriptors: 2222 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 2223 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 2224 * 2) Allocate DMA'able memory. 2225 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2226 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 2227 * obtained in step 2 2228 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 2229 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 2230 * of TX descriptors. Leave flags field clear. 2231 * 4) Access TX descriptors via host memory. The chip 2232 * will refetch into local SRAM as needed when producer 2233 * index mailboxes are updated. 2234 * 2235 * To use on-chip TX descriptors: 2236 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 2237 * Make sure GRC_MODE_HOST_SENDBDS is clear. 2238 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2239 * a) Set TG3_BDINFO_HOST_ADDR to zero. 2240 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 2241 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 2242 * 3) Access TX descriptors directly in on-chip SRAM 2243 * using normal {read,write}l(). (and not using 2244 * pointer dereferencing of ioremap()'d memory like 2245 * the broken Broadcom driver does) 2246 * 2247 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 2248 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 2249 */ 2250struct tg3_tx_buffer_desc { 2251 u32 addr_hi; 2252 u32 addr_lo; 2253 2254 u32 len_flags; 2255#define TXD_FLAG_TCPUDP_CSUM 0x0001 2256#define TXD_FLAG_IP_CSUM 0x0002 2257#define TXD_FLAG_END 0x0004 2258#define TXD_FLAG_IP_FRAG 0x0008 2259#define TXD_FLAG_JMB_PKT 0x0008 2260#define TXD_FLAG_IP_FRAG_END 0x0010 2261#define TXD_FLAG_VLAN 0x0040 2262#define TXD_FLAG_COAL_NOW 0x0080 2263#define TXD_FLAG_CPU_PRE_DMA 0x0100 2264#define TXD_FLAG_CPU_POST_DMA 0x0200 2265#define TXD_FLAG_ADD_SRC_ADDR 0x1000 2266#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 2267#define TXD_FLAG_NO_CRC 0x8000 2268#define TXD_LEN_SHIFT 16 2269 2270 u32 vlan_tag; 2271#define TXD_VLAN_TAG_SHIFT 0 2272#define TXD_MSS_SHIFT 16 2273}; 2274 2275#define TXD_ADDR 0x00UL /* 64-bit */ 2276#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 2277#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 2278#define TXD_SIZE 0x10UL 2279 2280struct tg3_rx_buffer_desc { 2281 u32 addr_hi; 2282 u32 addr_lo; 2283 2284 u32 idx_len; 2285#define RXD_IDX_MASK 0xffff0000 2286#define RXD_IDX_SHIFT 16 2287#define RXD_LEN_MASK 0x0000ffff 2288#define RXD_LEN_SHIFT 0 2289 2290 u32 type_flags; 2291#define RXD_TYPE_SHIFT 16 2292#define RXD_FLAGS_SHIFT 0 2293 2294#define RXD_FLAG_END 0x0004 2295#define RXD_FLAG_MINI 0x0800 2296#define RXD_FLAG_JUMBO 0x0020 2297#define RXD_FLAG_VLAN 0x0040 2298#define RXD_FLAG_ERROR 0x0400 2299#define RXD_FLAG_IP_CSUM 0x1000 2300#define RXD_FLAG_TCPUDP_CSUM 0x2000 2301#define RXD_FLAG_IS_TCP 0x4000 2302 2303 u32 ip_tcp_csum; 2304#define RXD_IPCSUM_MASK 0xffff0000 2305#define RXD_IPCSUM_SHIFT 16 2306#define RXD_TCPCSUM_MASK 0x0000ffff 2307#define RXD_TCPCSUM_SHIFT 0 2308 2309 u32 err_vlan; 2310 2311#define RXD_VLAN_MASK 0x0000ffff 2312 2313#define RXD_ERR_BAD_CRC 0x00010000 2314#define RXD_ERR_COLLISION 0x00020000 2315#define RXD_ERR_LINK_LOST 0x00040000 2316#define RXD_ERR_PHY_DECODE 0x00080000 2317#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 2318#define RXD_ERR_MAC_ABRT 0x00200000 2319#define RXD_ERR_TOO_SMALL 0x00400000 2320#define RXD_ERR_NO_RESOURCES 0x00800000 2321#define RXD_ERR_HUGE_FRAME 0x01000000 2322#define RXD_ERR_MASK 0xffff0000 2323 2324 u32 reserved; 2325 u32 opaque; 2326#define RXD_OPAQUE_INDEX_MASK 0x0000ffff 2327#define RXD_OPAQUE_INDEX_SHIFT 0 2328#define RXD_OPAQUE_RING_STD 0x00010000 2329#define RXD_OPAQUE_RING_JUMBO 0x00020000 2330#define RXD_OPAQUE_RING_MINI 0x00040000 2331#define RXD_OPAQUE_RING_MASK 0x00070000 2332}; 2333 2334struct tg3_ext_rx_buffer_desc { 2335 struct { 2336 u32 addr_hi; 2337 u32 addr_lo; 2338 } addrlist[3]; 2339 u32 len2_len1; 2340 u32 resv_len3; 2341 struct tg3_rx_buffer_desc std; 2342}; 2343 2344/* We only use this when testing out the DMA engine 2345 * at probe time. This is the internal format of buffer 2346 * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 2347 */ 2348struct tg3_internal_buffer_desc { 2349 u32 addr_hi; 2350 u32 addr_lo; 2351 u32 nic_mbuf; 2352#ifdef __BIG_ENDIAN 2353 u16 cqid_sqid; 2354 u16 len; 2355#else 2356 u16 len; 2357 u16 cqid_sqid; 2358#endif 2359 u32 flags; 2360 u32 __cookie1; 2361 u32 __cookie2; 2362 u32 __cookie3; 2363}; 2364 2365#define TG3_HW_STATUS_SIZE 0x50 2366struct tg3_hw_status { 2367 u32 status; 2368#define SD_STATUS_UPDATED 0x00000001 2369#define SD_STATUS_LINK_CHG 0x00000002 2370#define SD_STATUS_ERROR 0x00000004 2371 2372 u32 status_tag; 2373 2374#ifdef __BIG_ENDIAN 2375 u16 rx_consumer; 2376 u16 rx_jumbo_consumer; 2377#else 2378 u16 rx_jumbo_consumer; 2379 u16 rx_consumer; 2380#endif 2381 2382#ifdef __BIG_ENDIAN 2383 u16 reserved; 2384 u16 rx_mini_consumer; 2385#else 2386 u16 rx_mini_consumer; 2387 u16 reserved; 2388#endif 2389 struct { 2390#ifdef __BIG_ENDIAN 2391 u16 tx_consumer; 2392 u16 rx_producer; 2393#else 2394 u16 rx_producer; 2395 u16 tx_consumer; 2396#endif 2397 } idx[16]; 2398}; 2399 2400typedef struct { 2401 u32 high, low; 2402} tg3_stat64_t; 2403 2404struct tg3_hw_stats { 2405 u8 __reserved0[0x400-0x300]; 2406 2407 /* Statistics maintained by Receive MAC. */ 2408 tg3_stat64_t rx_octets; 2409 u64 __reserved1; 2410 tg3_stat64_t rx_fragments; 2411 tg3_stat64_t rx_ucast_packets; 2412 tg3_stat64_t rx_mcast_packets; 2413 tg3_stat64_t rx_bcast_packets; 2414 tg3_stat64_t rx_fcs_errors; 2415 tg3_stat64_t rx_align_errors; 2416 tg3_stat64_t rx_xon_pause_rcvd; 2417 tg3_stat64_t rx_xoff_pause_rcvd; 2418 tg3_stat64_t rx_mac_ctrl_rcvd; 2419 tg3_stat64_t rx_xoff_entered; 2420 tg3_stat64_t rx_frame_too_long_errors; 2421 tg3_stat64_t rx_jabbers; 2422 tg3_stat64_t rx_undersize_packets; 2423 tg3_stat64_t rx_in_length_errors; 2424 tg3_stat64_t rx_out_length_errors; 2425 tg3_stat64_t rx_64_or_less_octet_packets; 2426 tg3_stat64_t rx_65_to_127_octet_packets; 2427 tg3_stat64_t rx_128_to_255_octet_packets; 2428 tg3_stat64_t rx_256_to_511_octet_packets; 2429 tg3_stat64_t rx_512_to_1023_octet_packets; 2430 tg3_stat64_t rx_1024_to_1522_octet_packets; 2431 tg3_stat64_t rx_1523_to_2047_octet_packets; 2432 tg3_stat64_t rx_2048_to_4095_octet_packets; 2433 tg3_stat64_t rx_4096_to_8191_octet_packets; 2434 tg3_stat64_t rx_8192_to_9022_octet_packets; 2435 2436 u64 __unused0[37]; 2437 2438 /* Statistics maintained by Transmit MAC. */ 2439 tg3_stat64_t tx_octets; 2440 u64 __reserved2; 2441 tg3_stat64_t tx_collisions; 2442 tg3_stat64_t tx_xon_sent; 2443 tg3_stat64_t tx_xoff_sent; 2444 tg3_stat64_t tx_flow_control; 2445 tg3_stat64_t tx_mac_errors; 2446 tg3_stat64_t tx_single_collisions; 2447 tg3_stat64_t tx_mult_collisions; 2448 tg3_stat64_t tx_deferred; 2449 u64 __reserved3; 2450 tg3_stat64_t tx_excessive_collisions; 2451 tg3_stat64_t tx_late_collisions; 2452 tg3_stat64_t tx_collide_2times; 2453 tg3_stat64_t tx_collide_3times; 2454 tg3_stat64_t tx_collide_4times; 2455 tg3_stat64_t tx_collide_5times; 2456 tg3_stat64_t tx_collide_6times; 2457 tg3_stat64_t tx_collide_7times; 2458 tg3_stat64_t tx_collide_8times; 2459 tg3_stat64_t tx_collide_9times; 2460 tg3_stat64_t tx_collide_10times; 2461 tg3_stat64_t tx_collide_11times; 2462 tg3_stat64_t tx_collide_12times; 2463 tg3_stat64_t tx_collide_13times; 2464 tg3_stat64_t tx_collide_14times; 2465 tg3_stat64_t tx_collide_15times; 2466 tg3_stat64_t tx_ucast_packets; 2467 tg3_stat64_t tx_mcast_packets; 2468 tg3_stat64_t tx_bcast_packets; 2469 tg3_stat64_t tx_carrier_sense_errors; 2470 tg3_stat64_t tx_discards; 2471 tg3_stat64_t tx_errors; 2472 2473 u64 __unused1[31]; 2474 2475 /* Statistics maintained by Receive List Placement. */ 2476 tg3_stat64_t COS_rx_packets[16]; 2477 tg3_stat64_t COS_rx_filter_dropped; 2478 tg3_stat64_t dma_writeq_full; 2479 tg3_stat64_t dma_write_prioq_full; 2480 tg3_stat64_t rxbds_empty; 2481 tg3_stat64_t rx_discards; 2482 tg3_stat64_t rx_errors; 2483 tg3_stat64_t rx_threshold_hit; 2484 2485 u64 __unused2[9]; 2486 2487 /* Statistics maintained by Send Data Initiator. */ 2488 tg3_stat64_t COS_out_packets[16]; 2489 tg3_stat64_t dma_readq_full; 2490 tg3_stat64_t dma_read_prioq_full; 2491 tg3_stat64_t tx_comp_queue_full; 2492 2493 /* Statistics maintained by Host Coalescing. */ 2494 tg3_stat64_t ring_set_send_prod_index; 2495 tg3_stat64_t ring_status_update; 2496 tg3_stat64_t nic_irqs; 2497 tg3_stat64_t nic_avoided_irqs; 2498 tg3_stat64_t nic_tx_threshold_hit; 2499 2500 u8 __reserved4[0xb00-0x9c0]; 2501}; 2502 2503/* 'mapping' is superfluous as the chip does not write into 2504 * the tx/rx post rings so we could just fetch it from there. 2505 * But the cache behavior is better how we are doing it now. 2506 */ 2507struct ring_info { 2508 struct sk_buff *skb; 2509 DEFINE_DMA_UNMAP_ADDR(mapping); 2510}; 2511 2512struct tg3_config_info { 2513 u32 flags; 2514}; 2515 2516struct tg3_link_config { 2517 /* Describes what we're trying to get. */ 2518 u32 advertising; 2519 u16 speed; 2520 u8 duplex; 2521 u8 autoneg; 2522 u8 flowctrl; 2523 2524 /* Describes what we actually have. */ 2525 u8 active_flowctrl; 2526 2527 u8 active_duplex; 2528#define SPEED_INVALID 0xffff 2529#define DUPLEX_INVALID 0xff 2530#define AUTONEG_INVALID 0xff 2531 u16 active_speed; 2532 2533 /* When we go in and out of low power mode we need 2534 * to swap with this state. 2535 */ 2536 u16 orig_speed; 2537 u8 orig_duplex; 2538 u8 orig_autoneg; 2539 u32 orig_advertising; 2540}; 2541 2542struct tg3_bufmgr_config { 2543 u32 mbuf_read_dma_low_water; 2544 u32 mbuf_mac_rx_low_water; 2545 u32 mbuf_high_water; 2546 2547 u32 mbuf_read_dma_low_water_jumbo; 2548 u32 mbuf_mac_rx_low_water_jumbo; 2549 u32 mbuf_high_water_jumbo; 2550 2551 u32 dma_low_water; 2552 u32 dma_high_water; 2553}; 2554 2555struct tg3_ethtool_stats { 2556 /* Statistics maintained by Receive MAC. */ 2557 u64 rx_octets; 2558 u64 rx_fragments; 2559 u64 rx_ucast_packets; 2560 u64 rx_mcast_packets; 2561 u64 rx_bcast_packets; 2562 u64 rx_fcs_errors; 2563 u64 rx_align_errors; 2564 u64 rx_xon_pause_rcvd; 2565 u64 rx_xoff_pause_rcvd; 2566 u64 rx_mac_ctrl_rcvd; 2567 u64 rx_xoff_entered; 2568 u64 rx_frame_too_long_errors; 2569 u64 rx_jabbers; 2570 u64 rx_undersize_packets; 2571 u64 rx_in_length_errors; 2572 u64 rx_out_length_errors; 2573 u64 rx_64_or_less_octet_packets; 2574 u64 rx_65_to_127_octet_packets; 2575 u64 rx_128_to_255_octet_packets; 2576 u64 rx_256_to_511_octet_packets; 2577 u64 rx_512_to_1023_octet_packets; 2578 u64 rx_1024_to_1522_octet_packets; 2579 u64 rx_1523_to_2047_octet_packets; 2580 u64 rx_2048_to_4095_octet_packets; 2581 u64 rx_4096_to_8191_octet_packets; 2582 u64 rx_8192_to_9022_octet_packets; 2583 2584 /* Statistics maintained by Transmit MAC. */ 2585 u64 tx_octets; 2586 u64 tx_collisions; 2587 u64 tx_xon_sent; 2588 u64 tx_xoff_sent; 2589 u64 tx_flow_control; 2590 u64 tx_mac_errors; 2591 u64 tx_single_collisions; 2592 u64 tx_mult_collisions; 2593 u64 tx_deferred; 2594 u64 tx_excessive_collisions; 2595 u64 tx_late_collisions; 2596 u64 tx_collide_2times; 2597 u64 tx_collide_3times; 2598 u64 tx_collide_4times; 2599 u64 tx_collide_5times; 2600 u64 tx_collide_6times; 2601 u64 tx_collide_7times; 2602 u64 tx_collide_8times; 2603 u64 tx_collide_9times; 2604 u64 tx_collide_10times; 2605 u64 tx_collide_11times; 2606 u64 tx_collide_12times; 2607 u64 tx_collide_13times; 2608 u64 tx_collide_14times; 2609 u64 tx_collide_15times; 2610 u64 tx_ucast_packets; 2611 u64 tx_mcast_packets; 2612 u64 tx_bcast_packets; 2613 u64 tx_carrier_sense_errors; 2614 u64 tx_discards; 2615 u64 tx_errors; 2616 2617 /* Statistics maintained by Receive List Placement. */ 2618 u64 dma_writeq_full; 2619 u64 dma_write_prioq_full; 2620 u64 rxbds_empty; 2621 u64 rx_discards; 2622 u64 rx_errors; 2623 u64 rx_threshold_hit; 2624 2625 /* Statistics maintained by Send Data Initiator. */ 2626 u64 dma_readq_full; 2627 u64 dma_read_prioq_full; 2628 u64 tx_comp_queue_full; 2629 2630 /* Statistics maintained by Host Coalescing. */ 2631 u64 ring_set_send_prod_index; 2632 u64 ring_status_update; 2633 u64 nic_irqs; 2634 u64 nic_avoided_irqs; 2635 u64 nic_tx_threshold_hit; 2636}; 2637 2638struct tg3_rx_prodring_set { 2639 u32 rx_std_prod_idx; 2640 u32 rx_std_cons_idx; 2641 u32 rx_jmb_prod_idx; 2642 u32 rx_jmb_cons_idx; 2643 struct tg3_rx_buffer_desc *rx_std; 2644 struct tg3_ext_rx_buffer_desc *rx_jmb; 2645 struct ring_info *rx_std_buffers; 2646 struct ring_info *rx_jmb_buffers; 2647 dma_addr_t rx_std_mapping; 2648 dma_addr_t rx_jmb_mapping; 2649}; 2650 2651#define TG3_IRQ_MAX_VECS 5 2652 2653struct tg3_napi { 2654 struct napi_struct napi ____cacheline_aligned; 2655 struct tg3 *tp; 2656 struct tg3_hw_status *hw_status; 2657 2658 u32 last_tag; 2659 u32 last_irq_tag; 2660 u32 int_mbox; 2661 u32 coal_now; 2662 u32 tx_prod; 2663 u32 tx_cons; 2664 u32 tx_pending; 2665 u32 prodmbox; 2666 2667 u32 consmbox; 2668 u32 rx_rcb_ptr; 2669 u16 *rx_rcb_prod_idx; 2670 struct tg3_rx_prodring_set *prodring; 2671 2672 struct tg3_rx_buffer_desc *rx_rcb; 2673 struct tg3_tx_buffer_desc *tx_ring; 2674 struct ring_info *tx_buffers; 2675 2676 dma_addr_t status_mapping; 2677 dma_addr_t rx_rcb_mapping; 2678 dma_addr_t tx_desc_mapping; 2679 2680 char irq_lbl[IFNAMSIZ]; 2681 unsigned int irq_vec; 2682}; 2683 2684struct tg3 { 2685 /* begin "general, frequently-used members" cacheline section */ 2686 2687 /* If the IRQ handler (which runs lockless) needs to be 2688 * quiesced, the following bitmask state is used. The 2689 * SYNC flag is set by non-IRQ context code to initiate 2690 * the quiescence. 2691 * 2692 * When the IRQ handler notices that SYNC is set, it 2693 * disables interrupts and returns. 2694 * 2695 * When all outstanding IRQ handlers have returned after 2696 * the SYNC flag has been set, the setter can be assured 2697 * that interrupts will no longer get run. 2698 * 2699 * In this way all SMP driver locks are never acquired 2700 * in hw IRQ context, only sw IRQ context or lower. 2701 */ 2702 unsigned int irq_sync; 2703 2704 /* SMP locking strategy: 2705 * 2706 * lock: Held during reset, PHY access, timer, and when 2707 * updating tg3_flags and tg3_flags2. 2708 * 2709 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds 2710 * netif_tx_lock when it needs to call 2711 * netif_wake_queue. 2712 * 2713 * Both of these locks are to be held with BH safety. 2714 * 2715 * Because the IRQ handler, tg3_poll, and tg3_start_xmit 2716 * are running lockless, it is necessary to completely 2717 * quiesce the chip with tg3_netif_stop and tg3_full_lock 2718 * before reconfiguring the device. 2719 * 2720 * indirect_lock: Held when accessing registers indirectly 2721 * with IRQ disabling. 2722 */ 2723 spinlock_t lock; 2724 spinlock_t indirect_lock; 2725 2726 u32 (*read32) (struct tg3 *, u32); 2727 void (*write32) (struct tg3 *, u32, u32); 2728 u32 (*read32_mbox) (struct tg3 *, u32); 2729 void (*write32_mbox) (struct tg3 *, u32, 2730 u32); 2731 void __iomem *regs; 2732 void __iomem *aperegs; 2733 struct net_device *dev; 2734 struct pci_dev *pdev; 2735 2736 u32 coal_now; 2737 u32 msg_enable; 2738 2739 /* begin "tx thread" cacheline section */ 2740 void (*write32_tx_mbox) (struct tg3 *, u32, 2741 u32); 2742 2743 /* begin "rx thread" cacheline section */ 2744 struct tg3_napi napi[TG3_IRQ_MAX_VECS]; 2745 void (*write32_rx_mbox) (struct tg3 *, u32, 2746 u32); 2747 u32 rx_copy_thresh; 2748 u32 rx_pending; 2749 u32 rx_jumbo_pending; 2750 u32 rx_std_max_post; 2751 u32 rx_offset; 2752 u32 rx_pkt_map_sz; 2753#if TG3_VLAN_TAG_USED 2754 struct vlan_group *vlgrp; 2755#endif 2756 2757 struct tg3_rx_prodring_set prodring[TG3_IRQ_MAX_VECS]; 2758 2759 2760 /* begin "everything else" cacheline(s) section */ 2761 unsigned long rx_dropped; 2762 struct rtnl_link_stats64 net_stats_prev; 2763 struct tg3_ethtool_stats estats; 2764 struct tg3_ethtool_stats estats_prev; 2765 2766 union { 2767 unsigned long phy_crc_errors; 2768 unsigned long last_event_jiffies; 2769 }; 2770 2771 u32 tg3_flags; 2772#define TG3_FLAG_TAGGED_STATUS 0x00000001 2773#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 2774#define TG3_FLAG_RX_CHECKSUMS 0x00000004 2775#define TG3_FLAG_USE_LINKCHG_REG 0x00000008 2776#define TG3_FLAG_ENABLE_ASF 0x00000020 2777#define TG3_FLAG_ASPM_WORKAROUND 0x00000040 2778#define TG3_FLAG_POLL_SERDES 0x00000080 2779#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 2780#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 2781#define TG3_FLAG_WOL_SPEED_100MB 0x00000400 2782#define TG3_FLAG_WOL_ENABLE 0x00000800 2783#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000 2784#define TG3_FLAG_NVRAM 0x00002000 2785#define TG3_FLAG_NVRAM_BUFFERED 0x00004000 2786#define TG3_FLAG_SUPPORT_MSI 0x00008000 2787#define TG3_FLAG_SUPPORT_MSIX 0x00010000 2788#define TG3_FLAG_SUPPORT_MSI_OR_MSIX (TG3_FLAG_SUPPORT_MSI | \ 2789 TG3_FLAG_SUPPORT_MSIX) 2790#define TG3_FLAG_PCIX_MODE 0x00020000 2791#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 2792#define TG3_FLAG_PCI_32BIT 0x00080000 2793#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 2794#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000 2795#define TG3_FLAG_WOL_CAP 0x00400000 2796#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 2797#define TG3_FLAG_PAUSE_AUTONEG 0x02000000 2798#define TG3_FLAG_CPMU_PRESENT 0x04000000 2799#define TG3_FLAG_40BIT_DMA_BUG 0x08000000 2800#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 2801#define TG3_FLAG_JUMBO_CAPABLE 0x20000000 2802#define TG3_FLAG_CHIP_RESETTING 0x40000000 2803#define TG3_FLAG_INIT_COMPLETE 0x80000000 2804 u32 tg3_flags2; 2805#define TG3_FLG2_RESTART_TIMER 0x00000001 2806#define TG3_FLG2_TSO_BUG 0x00000002 2807#define TG3_FLG2_IS_5788 0x00000008 2808#define TG3_FLG2_MAX_RXPEND_64 0x00000010 2809#define TG3_FLG2_TSO_CAPABLE 0x00000020 2810#define TG3_FLG2_PCI_EXPRESS 0x00000200 2811#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400 2812#define TG3_FLG2_HW_AUTONEG 0x00000800 2813#define TG3_FLG2_IS_NIC 0x00001000 2814#define TG3_FLG2_FLASH 0x00008000 2815#define TG3_FLG2_HW_TSO_1 0x00010000 2816#define TG3_FLG2_5705_PLUS 0x00040000 2817#define TG3_FLG2_5750_PLUS 0x00080000 2818#define TG3_FLG2_HW_TSO_3 0x00100000 2819#define TG3_FLG2_USING_MSI 0x00200000 2820#define TG3_FLG2_USING_MSIX 0x00400000 2821#define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \ 2822 TG3_FLG2_USING_MSIX) 2823#define TG3_FLG2_ICH_WORKAROUND 0x02000000 2824#define TG3_FLG2_5780_CLASS 0x04000000 2825#define TG3_FLG2_HW_TSO_2 0x08000000 2826#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \ 2827 TG3_FLG2_HW_TSO_2 | \ 2828 TG3_FLG2_HW_TSO_3) 2829#define TG3_FLG2_1SHOT_MSI 0x10000000 2830#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 2831 u32 tg3_flags3; 2832#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001 2833#define TG3_FLG3_ENABLE_APE 0x00000002 2834#define TG3_FLG3_PROTECTED_NVRAM 0x00000004 2835#define TG3_FLG3_5701_DMA_BUG 0x00000008 2836#define TG3_FLG3_USE_PHYLIB 0x00000010 2837#define TG3_FLG3_MDIOBUS_INITED 0x00000020 2838#define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100 2839#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200 2840#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400 2841#define TG3_FLG3_CLKREQ_BUG 0x00000800 2842#define TG3_FLG3_5755_PLUS 0x00002000 2843#define TG3_FLG3_NO_NVRAM 0x00004000 2844#define TG3_FLG3_ENABLE_RSS 0x00020000 2845#define TG3_FLG3_ENABLE_TSS 0x00040000 2846#define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000 2847#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000 2848#define TG3_FLG3_SHORT_DMA_BUG 0x00200000 2849#define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000 2850#define TG3_FLG3_L1PLLPD_EN 0x00800000 2851#define TG3_FLG3_5717_PLUS 0x01000000 2852 2853 struct timer_list timer; 2854 u16 timer_counter; 2855 u16 timer_multiplier; 2856 u32 timer_offset; 2857 u16 asf_counter; 2858 u16 asf_multiplier; 2859 2860 /* 1 second counter for transient serdes link events */ 2861 u32 serdes_counter; 2862#define SERDES_AN_TIMEOUT_5704S 2 2863#define SERDES_PARALLEL_DET_TIMEOUT 1 2864#define SERDES_AN_TIMEOUT_5714S 1 2865 2866 struct tg3_link_config link_config; 2867 struct tg3_bufmgr_config bufmgr_config; 2868 2869 /* cache h/w values, often passed straight to h/w */ 2870 u32 rx_mode; 2871 u32 tx_mode; 2872 u32 mac_mode; 2873 u32 mi_mode; 2874 u32 misc_host_ctrl; 2875 u32 grc_mode; 2876 u32 grc_local_ctrl; 2877 u32 dma_rwctrl; 2878 u32 coalesce_mode; 2879 u32 pwrmgmt_thresh; 2880 2881 /* PCI block */ 2882 u32 pci_chip_rev_id; 2883 u16 pci_cmd; 2884 u8 pci_cacheline_sz; 2885 u8 pci_lat_timer; 2886 2887 int pm_cap; 2888 int msi_cap; 2889 union { 2890 int pcix_cap; 2891 int pcie_cap; 2892 }; 2893 2894 struct mii_bus *mdio_bus; 2895 int mdio_irq[PHY_MAX_ADDR]; 2896 2897 u8 phy_addr; 2898 2899 /* PHY info */ 2900 u32 phy_id; 2901#define TG3_PHY_ID_MASK 0xfffffff0 2902#define TG3_PHY_ID_BCM5400 0x60008040 2903#define TG3_PHY_ID_BCM5401 0x60008050 2904#define TG3_PHY_ID_BCM5411 0x60008070 2905#define TG3_PHY_ID_BCM5701 0x60008110 2906#define TG3_PHY_ID_BCM5703 0x60008160 2907#define TG3_PHY_ID_BCM5704 0x60008190 2908#define TG3_PHY_ID_BCM5705 0x600081a0 2909#define TG3_PHY_ID_BCM5750 0x60008180 2910#define TG3_PHY_ID_BCM5752 0x60008100 2911#define TG3_PHY_ID_BCM5714 0x60008340 2912#define TG3_PHY_ID_BCM5780 0x60008350 2913#define TG3_PHY_ID_BCM5755 0xbc050cc0 2914#define TG3_PHY_ID_BCM5787 0xbc050ce0 2915#define TG3_PHY_ID_BCM5756 0xbc050ed0 2916#define TG3_PHY_ID_BCM5784 0xbc050fa0 2917#define TG3_PHY_ID_BCM5761 0xbc050fd0 2918#define TG3_PHY_ID_BCM5718C 0x5c0d8a00 2919#define TG3_PHY_ID_BCM5718S 0xbc050ff0 2920#define TG3_PHY_ID_BCM57765 0x5c0d8a40 2921#define TG3_PHY_ID_BCM5719C 0x5c0d8a20 2922#define TG3_PHY_ID_BCM5906 0xdc00ac40 2923#define TG3_PHY_ID_BCM8002 0x60010140 2924#define TG3_PHY_ID_INVALID 0xffffffff 2925 2926#define PHY_ID_RTL8211C 0x001cc910 2927#define PHY_ID_RTL8201E 0x00008200 2928 2929#define TG3_PHY_ID_REV_MASK 0x0000000f 2930#define TG3_PHY_REV_BCM5401_B0 0x1 2931 2932 /* This macro assumes the passed PHY ID is 2933 * already masked with TG3_PHY_ID_MASK. 2934 */ 2935#define TG3_KNOWN_PHY_ID(X) \ 2936 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \ 2937 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \ 2938 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \ 2939 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \ 2940 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \ 2941 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \ 2942 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \ 2943 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \ 2944 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \ 2945 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \ 2946 (X) == TG3_PHY_ID_BCM8002) 2947 2948 u32 phy_flags; 2949#define TG3_PHYFLG_IS_LOW_POWER 0x00000001 2950#define TG3_PHYFLG_IS_CONNECTED 0x00000002 2951#define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 2952#define TG3_PHYFLG_PHY_SERDES 0x00000010 2953#define TG3_PHYFLG_MII_SERDES 0x00000020 2954#define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ 2955 TG3_PHYFLG_MII_SERDES) 2956#define TG3_PHYFLG_IS_FET 0x00000040 2957#define TG3_PHYFLG_10_100_ONLY 0x00000080 2958#define TG3_PHYFLG_ENABLE_APD 0x00000100 2959#define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200 2960#define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400 2961#define TG3_PHYFLG_JITTER_BUG 0x00000800 2962#define TG3_PHYFLG_ADJUST_TRIM 0x00001000 2963#define TG3_PHYFLG_ADC_BUG 0x00002000 2964#define TG3_PHYFLG_5704_A0_BUG 0x00004000 2965#define TG3_PHYFLG_BER_BUG 0x00008000 2966#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 2967#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 2968 2969 u32 led_ctrl; 2970 u32 phy_otp; 2971 2972#define TG3_BPN_SIZE 24 2973 char board_part_number[TG3_BPN_SIZE]; 2974#define TG3_VER_SIZE ETHTOOL_FWVERS_LEN 2975 char fw_ver[TG3_VER_SIZE]; 2976 u32 nic_sram_data_cfg; 2977 u32 pci_clock_ctrl; 2978 struct pci_dev *pdev_peer; 2979 2980 struct tg3_hw_stats *hw_stats; 2981 dma_addr_t stats_mapping; 2982 struct work_struct reset_task; 2983 2984 int nvram_lock_cnt; 2985 u32 nvram_size; 2986#define TG3_NVRAM_SIZE_64KB 0x00010000 2987#define TG3_NVRAM_SIZE_128KB 0x00020000 2988#define TG3_NVRAM_SIZE_256KB 0x00040000 2989#define TG3_NVRAM_SIZE_512KB 0x00080000 2990#define TG3_NVRAM_SIZE_1MB 0x00100000 2991#define TG3_NVRAM_SIZE_2MB 0x00200000 2992 2993 u32 nvram_pagesize; 2994 u32 nvram_jedecnum; 2995 2996#define JEDEC_ATMEL 0x1f 2997#define JEDEC_ST 0x20 2998#define JEDEC_SAIFUN 0x4f 2999#define JEDEC_SST 0xbf 3000 3001#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB 3002#define ATMEL_AT24C64_PAGE_SIZE (32) 3003 3004#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB 3005#define ATMEL_AT24C512_PAGE_SIZE (128) 3006 3007#define ATMEL_AT45DB0X1B_PAGE_POS 9 3008#define ATMEL_AT45DB0X1B_PAGE_SIZE 264 3009 3010#define ATMEL_AT25F512_PAGE_SIZE 256 3011 3012#define ST_M45PEX0_PAGE_SIZE 256 3013 3014#define SAIFUN_SA25F0XX_PAGE_SIZE 256 3015 3016#define SST_25VF0X0_PAGE_SIZE 4098 3017 3018 unsigned int irq_max; 3019 unsigned int irq_cnt; 3020 3021 struct ethtool_coalesce coal; 3022 3023 /* firmware info */ 3024 const char *fw_needed; 3025 const struct firmware *fw; 3026 u32 fw_len; /* includes BSS */ 3027}; 3028 3029#endif /* !(_T3_H) */ 3030