1/* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2009 Renesas Solutions Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 */ 22 23#ifndef __SH_ETH_H__ 24#define __SH_ETH_H__ 25 26#include <linux/module.h> 27#include <linux/kernel.h> 28#include <linux/spinlock.h> 29#include <linux/workqueue.h> 30#include <linux/netdevice.h> 31#include <linux/phy.h> 32 33#include <asm/sh_eth.h> 34 35#define CARDNAME "sh-eth" 36#define TX_TIMEOUT (5*HZ) 37#define TX_RING_SIZE 64 /* Tx ring size */ 38#define RX_RING_SIZE 64 /* Rx ring size */ 39#define ETHERSMALL 60 40#define PKT_BUF_SZ 1538 41 42#if defined(CONFIG_CPU_SUBTYPE_SH7763) 43/* This CPU register maps is very difference by other SH4 CPU */ 44 45/* Chip Base Address */ 46# define SH_TSU_ADDR 0xFEE01800 47# define ARSTR SH_TSU_ADDR 48 49/* Chip Registers */ 50/* E-DMAC */ 51# define EDSR 0x000 52# define EDMR 0x400 53# define EDTRR 0x408 54# define EDRRR 0x410 55# define EESR 0x428 56# define EESIPR 0x430 57# define TDLAR 0x010 58# define TDFAR 0x014 59# define TDFXR 0x018 60# define TDFFR 0x01C 61# define RDLAR 0x030 62# define RDFAR 0x034 63# define RDFXR 0x038 64# define RDFFR 0x03C 65# define TRSCER 0x438 66# define RMFCR 0x440 67# define TFTR 0x448 68# define FDR 0x450 69# define RMCR 0x458 70# define RPADIR 0x460 71# define FCFTR 0x468 72 73/* Ether Register */ 74# define ECMR 0x500 75# define ECSR 0x510 76# define ECSIPR 0x518 77# define PIR 0x520 78# define PSR 0x528 79# define PIPR 0x52C 80# define RFLR 0x508 81# define APR 0x554 82# define MPR 0x558 83# define PFTCR 0x55C 84# define PFRCR 0x560 85# define TPAUSER 0x564 86# define GECMR 0x5B0 87# define BCULR 0x5B4 88# define MAHR 0x5C0 89# define MALR 0x5C8 90# define TROCR 0x700 91# define CDCR 0x708 92# define LCCR 0x710 93# define CEFCR 0x740 94# define FRECR 0x748 95# define TSFRCR 0x750 96# define TLFRCR 0x758 97# define RFCR 0x760 98# define CERCR 0x768 99# define CEECR 0x770 100# define MAFCR 0x778 101 102/* TSU Absolute Address */ 103# define TSU_CTRST 0x004 104# define TSU_FWEN0 0x010 105# define TSU_FWEN1 0x014 106# define TSU_FCM 0x18 107# define TSU_BSYSL0 0x20 108# define TSU_BSYSL1 0x24 109# define TSU_PRISL0 0x28 110# define TSU_PRISL1 0x2C 111# define TSU_FWSL0 0x30 112# define TSU_FWSL1 0x34 113# define TSU_FWSLC 0x38 114# define TSU_QTAG0 0x40 115# define TSU_QTAG1 0x44 116# define TSU_FWSR 0x50 117# define TSU_FWINMK 0x54 118# define TSU_ADQT0 0x48 119# define TSU_ADQT1 0x4C 120# define TSU_VTAG0 0x58 121# define TSU_VTAG1 0x5C 122# define TSU_ADSBSY 0x60 123# define TSU_TEN 0x64 124# define TSU_POST1 0x70 125# define TSU_POST2 0x74 126# define TSU_POST3 0x78 127# define TSU_POST4 0x7C 128# define TSU_ADRH0 0x100 129# define TSU_ADRL0 0x104 130# define TSU_ADRH31 0x1F8 131# define TSU_ADRL31 0x1FC 132 133# define TXNLCR0 0x80 134# define TXALCR0 0x84 135# define RXNLCR0 0x88 136# define RXALCR0 0x8C 137# define FWNLCR0 0x90 138# define FWALCR0 0x94 139# define TXNLCR1 0xA0 140# define TXALCR1 0xA4 141# define RXNLCR1 0xA8 142# define RXALCR1 0xAC 143# define FWNLCR1 0xB0 144# define FWALCR1 0x40 145 146#elif defined(CONFIG_CPU_SH4) /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */ 147/* EtherC */ 148#define ECMR 0x100 149#define RFLR 0x108 150#define ECSR 0x110 151#define ECSIPR 0x118 152#define PIR 0x120 153#define PSR 0x128 154#define RDMLR 0x140 155#define IPGR 0x150 156#define APR 0x154 157#define MPR 0x158 158#define TPAUSER 0x164 159#define RFCF 0x160 160#define TPAUSECR 0x168 161#define BCFRR 0x16c 162#define MAHR 0x1c0 163#define MALR 0x1c8 164#define TROCR 0x1d0 165#define CDCR 0x1d4 166#define LCCR 0x1d8 167#define CNDCR 0x1dc 168#define CEFCR 0x1e4 169#define FRECR 0x1e8 170#define TSFRCR 0x1ec 171#define TLFRCR 0x1f0 172#define RFCR 0x1f4 173#define MAFCR 0x1f8 174#define RTRATE 0x1fc 175 176/* E-DMAC */ 177#define EDMR 0x000 178#define EDTRR 0x008 179#define EDRRR 0x010 180#define TDLAR 0x018 181#define RDLAR 0x020 182#define EESR 0x028 183#define EESIPR 0x030 184#define TRSCER 0x038 185#define RMFCR 0x040 186#define TFTR 0x048 187#define FDR 0x050 188#define RMCR 0x058 189#define TFUCR 0x064 190#define RFOCR 0x068 191#define FCFTR 0x070 192#define RPADIR 0x078 193#define TRIMD 0x07c 194#define RBWAR 0x0c8 195#define RDFAR 0x0cc 196#define TBRAR 0x0d4 197#define TDFAR 0x0d8 198#else /* #elif defined(CONFIG_CPU_SH4) */ 199/* This section is SH3 or SH2 */ 200#ifndef CONFIG_CPU_SUBTYPE_SH7619 201/* Chip base address */ 202# define SH_TSU_ADDR 0xA7000804 203# define ARSTR 0xA7000800 204#endif 205/* Chip Registers */ 206/* E-DMAC */ 207# define EDMR 0x0000 208# define EDTRR 0x0004 209# define EDRRR 0x0008 210# define TDLAR 0x000C 211# define RDLAR 0x0010 212# define EESR 0x0014 213# define EESIPR 0x0018 214# define TRSCER 0x001C 215# define RMFCR 0x0020 216# define TFTR 0x0024 217# define FDR 0x0028 218# define RMCR 0x002C 219# define EDOCR 0x0030 220# define FCFTR 0x0034 221# define RPADIR 0x0038 222# define TRIMD 0x003C 223# define RBWAR 0x0040 224# define RDFAR 0x0044 225# define TBRAR 0x004C 226# define TDFAR 0x0050 227 228/* Ether Register */ 229# define ECMR 0x0160 230# define ECSR 0x0164 231# define ECSIPR 0x0168 232# define PIR 0x016C 233# define MAHR 0x0170 234# define MALR 0x0174 235# define RFLR 0x0178 236# define PSR 0x017C 237# define TROCR 0x0180 238# define CDCR 0x0184 239# define LCCR 0x0188 240# define CNDCR 0x018C 241# define CEFCR 0x0194 242# define FRECR 0x0198 243# define TSFRCR 0x019C 244# define TLFRCR 0x01A0 245# define RFCR 0x01A4 246# define MAFCR 0x01A8 247# define IPGR 0x01B4 248# if defined(CONFIG_CPU_SUBTYPE_SH7710) 249# define APR 0x01B8 250# define MPR 0x01BC 251# define TPAUSER 0x1C4 252# define BCFR 0x1CC 253# endif /* CONFIG_CPU_SH7710 */ 254 255/* TSU */ 256# define TSU_CTRST 0x004 257# define TSU_FWEN0 0x010 258# define TSU_FWEN1 0x014 259# define TSU_FCM 0x018 260# define TSU_BSYSL0 0x020 261# define TSU_BSYSL1 0x024 262# define TSU_PRISL0 0x028 263# define TSU_PRISL1 0x02C 264# define TSU_FWSL0 0x030 265# define TSU_FWSL1 0x034 266# define TSU_FWSLC 0x038 267# define TSU_QTAGM0 0x040 268# define TSU_QTAGM1 0x044 269# define TSU_ADQT0 0x048 270# define TSU_ADQT1 0x04C 271# define TSU_FWSR 0x050 272# define TSU_FWINMK 0x054 273# define TSU_ADSBSY 0x060 274# define TSU_TEN 0x064 275# define TSU_POST1 0x070 276# define TSU_POST2 0x074 277# define TSU_POST3 0x078 278# define TSU_POST4 0x07C 279# define TXNLCR0 0x080 280# define TXALCR0 0x084 281# define RXNLCR0 0x088 282# define RXALCR0 0x08C 283# define FWNLCR0 0x090 284# define FWALCR0 0x094 285# define TXNLCR1 0x0A0 286# define TXALCR1 0x0A4 287# define RXNLCR1 0x0A8 288# define RXALCR1 0x0AC 289# define FWNLCR1 0x0B0 290# define FWALCR1 0x0B4 291 292#define TSU_ADRH0 0x0100 293#define TSU_ADRL0 0x0104 294#define TSU_ADRL31 0x01FC 295 296#endif /* CONFIG_CPU_SUBTYPE_SH7763 */ 297 298/* There are avoid compile error... */ 299#if !defined(BCULR) 300#define BCULR 0x0fc 301#endif 302#if !defined(TRIMD) 303#define TRIMD 0x0fc 304#endif 305#if !defined(APR) 306#define APR 0x0fc 307#endif 308#if !defined(MPR) 309#define MPR 0x0fc 310#endif 311#if !defined(TPAUSER) 312#define TPAUSER 0x0fc 313#endif 314 315/* Driver's parameters */ 316#if defined(CONFIG_CPU_SH4) 317#define SH4_SKB_RX_ALIGN 32 318#else 319#define SH2_SH3_SKB_RX_ALIGN 2 320#endif 321 322/* 323 * Register's bits 324 */ 325#ifdef CONFIG_CPU_SUBTYPE_SH7763 326/* EDSR */ 327enum EDSR_BIT { 328 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 329}; 330#define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 331 332/* GECMR */ 333enum GECMR_BIT { 334 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01, 335}; 336#endif 337 338/* EDMR */ 339enum DMAC_M_BIT { 340 EDMR_EL = 0x40, /* Litte endian */ 341 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 342#ifdef CONFIG_CPU_SUBTYPE_SH7763 343 EDMR_SRST = 0x03, 344#else /* CONFIG_CPU_SUBTYPE_SH7763 */ 345 EDMR_SRST = 0x01, 346#endif 347}; 348 349/* EDTRR */ 350enum DMAC_T_BIT { 351#ifdef CONFIG_CPU_SUBTYPE_SH7763 352 EDTRR_TRNS = 0x03, 353#else 354 EDTRR_TRNS = 0x01, 355#endif 356}; 357 358/* EDRRR*/ 359enum EDRRR_R_BIT { 360 EDRRR_R = 0x01, 361}; 362 363/* TPAUSER */ 364enum TPAUSER_BIT { 365 TPAUSER_TPAUSE = 0x0000ffff, 366 TPAUSER_UNLIMITED = 0, 367}; 368 369/* BCFR */ 370enum BCFR_BIT { 371 BCFR_RPAUSE = 0x0000ffff, 372 BCFR_UNLIMITED = 0, 373}; 374 375/* PIR */ 376enum PIR_BIT { 377 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 378}; 379 380/* PSR */ 381enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 382 383/* EESR */ 384enum EESR_BIT { 385 EESR_TWB1 = 0x80000000, 386 EESR_TWB = 0x40000000, /* same as TWB0 */ 387 EESR_TC1 = 0x20000000, 388 EESR_TUC = 0x10000000, 389 EESR_ROC = 0x08000000, 390 EESR_TABT = 0x04000000, 391 EESR_RABT = 0x02000000, 392 EESR_RFRMER = 0x01000000, /* same as RFCOF */ 393 EESR_ADE = 0x00800000, 394 EESR_ECI = 0x00400000, 395 EESR_FTC = 0x00200000, /* same as TC or TC0 */ 396 EESR_TDE = 0x00100000, 397 EESR_TFE = 0x00080000, /* same as TFUF */ 398 EESR_FRC = 0x00040000, /* same as FR */ 399 EESR_RDE = 0x00020000, 400 EESR_RFE = 0x00010000, 401 EESR_CND = 0x00000800, 402 EESR_DLC = 0x00000400, 403 EESR_CD = 0x00000200, 404 EESR_RTO = 0x00000100, 405 EESR_RMAF = 0x00000080, 406 EESR_CEEF = 0x00000040, 407 EESR_CELF = 0x00000020, 408 EESR_RRF = 0x00000010, 409 EESR_RTLF = 0x00000008, 410 EESR_RTSF = 0x00000004, 411 EESR_PRE = 0x00000002, 412 EESR_CERF = 0x00000001, 413}; 414 415#define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \ 416 EESR_RTO) 417#define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \ 418 EESR_RDE | EESR_RFRMER | EESR_ADE | \ 419 EESR_TFE | EESR_TDE | EESR_ECI) 420#define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \ 421 EESR_TFE) 422 423/* EESIPR */ 424enum DMAC_IM_BIT { 425 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 426 DMAC_M_RABT = 0x02000000, 427 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 428 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 429 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 430 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 431 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 432 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 433 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 434 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 435 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 436 DMAC_M_RINT1 = 0x00000001, 437}; 438 439/* Receive descriptor bit */ 440enum RD_STS_BIT { 441 RD_RACT = 0x80000000, RD_RDEL = 0x40000000, 442 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 443 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 444 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 445 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 446 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 447 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 448 RD_RFS1 = 0x00000001, 449}; 450#define RDF1ST RD_RFP1 451#define RDFEND RD_RFP0 452#define RD_RFP (RD_RFP1|RD_RFP0) 453 454/* FCFTR */ 455enum FCFTR_BIT { 456 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 457 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 458 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 459}; 460#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) 461#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) 462 463/* Transfer descriptor bit */ 464enum TD_STS_BIT { 465 TD_TACT = 0x80000000, 466 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 467 TD_TFP0 = 0x10000000, 468}; 469#define TDF1ST TD_TFP1 470#define TDFEND TD_TFP0 471#define TD_TFP (TD_TFP1|TD_TFP0) 472 473/* RMCR */ 474#define DEFAULT_RMCR_VALUE 0x00000000 475 476/* ECMR */ 477enum FELIC_MODE_BIT { 478 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, 479 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, 480 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 481 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 482 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 483 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, 484 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001, 485}; 486 487/* ECSR */ 488enum ECSR_STATUS_BIT { 489 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 490 ECSR_LCHNG = 0x04, 491 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 492}; 493 494#define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \ 495 ECSR_ICD | ECSIPR_MPDIP) 496 497/* ECSIPR */ 498enum ECSIPR_STATUS_MASK_BIT { 499 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, 500 ECSIPR_LCHNGIP = 0x04, 501 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 502}; 503 504#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \ 505 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 506 507/* APR */ 508enum APR_BIT { 509 APR_AP = 0x00000001, 510}; 511 512/* MPR */ 513enum MPR_BIT { 514 MPR_MP = 0x00000001, 515}; 516 517/* TRSCER */ 518enum DESC_I_BIT { 519 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 520 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 521 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 522 DESC_I_RINT1 = 0x0001, 523}; 524 525/* RPADIR */ 526enum RPADIR_BIT { 527 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 528 RPADIR_PADR = 0x0003f, 529}; 530 531/* RFLR */ 532#define RFLR_VALUE 0x1000 533 534/* FDR */ 535#define DEFAULT_FDR_INIT 0x00000707 536 537enum phy_offsets { 538 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, 539 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6, 540 PHY_16 = 16, 541}; 542 543/* PHY_CTRL */ 544enum PHY_CTRL_BIT { 545 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000, 546 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400, 547 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080, 548}; 549#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */ 550 551/* PHY_STAT */ 552enum PHY_STAT_BIT { 553 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000, 554 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020, 555 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004, 556 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001, 557}; 558 559/* PHY_ANA */ 560enum PHY_ANA_BIT { 561 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000, 562 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100, 563 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020, 564 PHY_A_SEL = 0x001e, 565}; 566/* PHY_ANL */ 567enum PHY_ANL_BIT { 568 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000, 569 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100, 570 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020, 571 PHY_L_SEL = 0x001f, 572}; 573 574/* PHY_ANE */ 575enum PHY_ANE_BIT { 576 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004, 577 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001, 578}; 579 580/* DM9161 */ 581enum PHY_16_BIT { 582 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000, 583 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800, 584 PHY_16_TXselect = 0x0400, 585 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100, 586 PHY_16_Force100LNK = 0x0080, 587 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020, 588 PHY_16_RPDCTR_EN = 0x0010, 589 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004, 590 PHY_16_Sleepmode = 0x0002, 591 PHY_16_RemoteLoopOut = 0x0001, 592}; 593 594#define POST_RX 0x08 595#define POST_FW 0x04 596#define POST0_RX (POST_RX) 597#define POST0_FW (POST_FW) 598#define POST1_RX (POST_RX >> 2) 599#define POST1_FW (POST_FW >> 2) 600#define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW) 601 602/* ARSTR */ 603enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, }; 604 605/* TSU_FWEN0 */ 606enum TSU_FWEN0_BIT { 607 TSU_FWEN0_0 = 0x00000001, 608}; 609 610/* TSU_ADSBSY */ 611enum TSU_ADSBSY_BIT { 612 TSU_ADSBSY_0 = 0x00000001, 613}; 614 615/* TSU_TEN */ 616enum TSU_TEN_BIT { 617 TSU_TEN_0 = 0x80000000, 618}; 619 620/* TSU_FWSL0 */ 621enum TSU_FWSL0_BIT { 622 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800, 623 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200, 624 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010, 625}; 626 627/* TSU_FWSLC */ 628enum TSU_FWSLC_BIT { 629 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000, 630 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040, 631 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010, 632 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004, 633 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001, 634}; 635 636/* 637 * The sh ether Tx buffer descriptors. 638 * This structure should be 20 bytes. 639 */ 640struct sh_eth_txdesc { 641 u32 status; /* TD0 */ 642#if defined(CONFIG_CPU_LITTLE_ENDIAN) 643 u16 pad0; /* TD1 */ 644 u16 buffer_length; /* TD1 */ 645#else 646 u16 buffer_length; /* TD1 */ 647 u16 pad0; /* TD1 */ 648#endif 649 u32 addr; /* TD2 */ 650 u32 pad1; /* padding data */ 651} __attribute__((aligned(2), packed)); 652 653/* 654 * The sh ether Rx buffer descriptors. 655 * This structure should be 20 bytes. 656 */ 657struct sh_eth_rxdesc { 658 u32 status; /* RD0 */ 659#if defined(CONFIG_CPU_LITTLE_ENDIAN) 660 u16 frame_length; /* RD1 */ 661 u16 buffer_length; /* RD1 */ 662#else 663 u16 buffer_length; /* RD1 */ 664 u16 frame_length; /* RD1 */ 665#endif 666 u32 addr; /* RD2 */ 667 u32 pad0; /* padding data */ 668} __attribute__((aligned(2), packed)); 669 670/* This structure is used by each CPU dependency handling. */ 671struct sh_eth_cpu_data { 672 /* optional functions */ 673 void (*chip_reset)(struct net_device *ndev); 674 void (*set_duplex)(struct net_device *ndev); 675 void (*set_rate)(struct net_device *ndev); 676 677 /* mandatory initialize value */ 678 unsigned long eesipr_value; 679 680 /* optional initialize value */ 681 unsigned long ecsr_value; 682 unsigned long ecsipr_value; 683 unsigned long fdr_value; 684 unsigned long fcftr_value; 685 unsigned long rpadir_value; 686 unsigned long rmcr_value; 687 688 /* interrupt checking mask */ 689 unsigned long tx_check; 690 unsigned long eesr_err_check; 691 unsigned long tx_error_check; 692 693 /* hardware features */ 694 unsigned no_psr:1; /* EtherC DO NOT have PSR */ 695 unsigned apr:1; /* EtherC have APR */ 696 unsigned mpr:1; /* EtherC have MPR */ 697 unsigned tpauser:1; /* EtherC have TPAUSER */ 698 unsigned bculr:1; /* EtherC have BCULR */ 699 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */ 700 unsigned rpadir:1; /* E-DMAC have RPADIR */ 701 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ 702 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ 703}; 704 705struct sh_eth_private { 706 struct platform_device *pdev; 707 struct sh_eth_cpu_data *cd; 708 dma_addr_t rx_desc_dma; 709 dma_addr_t tx_desc_dma; 710 struct sh_eth_rxdesc *rx_ring; 711 struct sh_eth_txdesc *tx_ring; 712 struct sk_buff **rx_skbuff; 713 struct sk_buff **tx_skbuff; 714 struct net_device_stats stats; 715 struct timer_list timer; 716 spinlock_t lock; 717 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ 718 u32 cur_tx, dirty_tx; 719 u32 rx_buf_sz; /* Based on MTU+slack. */ 720 int edmac_endian; 721 /* MII transceiver section. */ 722 u32 phy_id; /* PHY ID */ 723 struct mii_bus *mii_bus; /* MDIO bus control */ 724 struct phy_device *phydev; /* PHY device control */ 725 enum phy_state link; 726 int msg_enable; 727 int speed; 728 int duplex; 729 u32 rx_int_var, tx_int_var; /* interrupt control variables */ 730 char post_rx; /* POST receive */ 731 char post_fw; /* POST forward */ 732 struct net_device_stats tsu_stats; /* TSU forward status */ 733 734 unsigned no_ether_link:1; 735 unsigned ether_link_active_low:1; 736}; 737 738static inline void sh_eth_soft_swap(char *src, int len) 739{ 740#ifdef __LITTLE_ENDIAN__ 741 u32 *p = (u32 *)src; 742 u32 *maxp; 743 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32)); 744 745 for (; p < maxp; p++) 746 *p = swab32(*p); 747#endif 748} 749 750#endif /* #ifndef __SH_ETH_H__ */ 751