1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ 2/* 3 * Copyright 1996-1999 Thomas Bogendoerfer 4 * 5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker. 6 * 7 * Copyright 1993 United States Government as represented by the 8 * Director, National Security Agency. 9 * 10 * This software may be used and distributed according to the terms 11 * of the GNU General Public License, incorporated herein by reference. 12 * 13 * This driver is for PCnet32 and PCnetPCI based ethercards 14 */ 15/************************************************************************** 16 * 23 Oct, 2000. 17 * Fixed a few bugs, related to running the controller in 32bit mode. 18 * 19 * Carsten Langgaard, carstenl@mips.com 20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 21 * 22 *************************************************************************/ 23 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26#define DRV_NAME "pcnet32" 27#define DRV_VERSION "1.35" 28#define DRV_RELDATE "21.Apr.2008" 29#define PFX DRV_NAME ": " 30 31static const char *const version = 32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; 33 34#include <linux/module.h> 35#include <linux/kernel.h> 36#include <linux/sched.h> 37#include <linux/string.h> 38#include <linux/errno.h> 39#include <linux/ioport.h> 40#include <linux/slab.h> 41#include <linux/interrupt.h> 42#include <linux/pci.h> 43#include <linux/delay.h> 44#include <linux/init.h> 45#include <linux/ethtool.h> 46#include <linux/mii.h> 47#include <linux/crc32.h> 48#include <linux/netdevice.h> 49#include <linux/etherdevice.h> 50#include <linux/if_ether.h> 51#include <linux/skbuff.h> 52#include <linux/spinlock.h> 53#include <linux/moduleparam.h> 54#include <linux/bitops.h> 55#include <linux/io.h> 56#include <linux/uaccess.h> 57 58#include <asm/dma.h> 59#include <asm/irq.h> 60 61/* 62 * PCI device identifiers for "new style" Linux PCI Device Drivers 63 */ 64static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = { 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), }, 66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), }, 67 68 /* 69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have 70 * the incorrect vendor id. 71 */ 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE), 73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, }, 74 75 { } /* terminate list */ 76}; 77 78MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); 79 80static int cards_found; 81 82/* 83 * VLB I/O addresses 84 */ 85static unsigned int pcnet32_portlist[] __initdata = 86 { 0x300, 0x320, 0x340, 0x360, 0 }; 87 88static int pcnet32_debug; 89static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ 90static int pcnet32vlb; /* check for VLB cards ? */ 91 92static struct net_device *pcnet32_dev; 93 94static int max_interrupt_work = 2; 95static int rx_copybreak = 200; 96 97#define PCNET32_PORT_AUI 0x00 98#define PCNET32_PORT_10BT 0x01 99#define PCNET32_PORT_GPSI 0x02 100#define PCNET32_PORT_MII 0x03 101 102#define PCNET32_PORT_PORTSEL 0x03 103#define PCNET32_PORT_ASEL 0x04 104#define PCNET32_PORT_100 0x40 105#define PCNET32_PORT_FD 0x80 106 107#define PCNET32_DMA_MASK 0xffffffff 108 109#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) 110#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) 111 112/* 113 * table to translate option values from tulip 114 * to internal options 115 */ 116static const unsigned char options_mapping[] = { 117 PCNET32_PORT_ASEL, /* 0 Auto-select */ 118 PCNET32_PORT_AUI, /* 1 BNC/AUI */ 119 PCNET32_PORT_AUI, /* 2 AUI/BNC */ 120 PCNET32_PORT_ASEL, /* 3 not supported */ 121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ 122 PCNET32_PORT_ASEL, /* 5 not supported */ 123 PCNET32_PORT_ASEL, /* 6 not supported */ 124 PCNET32_PORT_ASEL, /* 7 not supported */ 125 PCNET32_PORT_ASEL, /* 8 not supported */ 126 PCNET32_PORT_MII, /* 9 MII 10baseT */ 127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ 128 PCNET32_PORT_MII, /* 11 MII (autosel) */ 129 PCNET32_PORT_10BT, /* 12 10BaseT */ 130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ 131 /* 14 MII 100BaseTx-FD */ 132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, 133 PCNET32_PORT_ASEL /* 15 not supported */ 134}; 135 136static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { 137 "Loopback test (offline)" 138}; 139 140#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test) 141 142#define PCNET32_NUM_REGS 136 143 144#define MAX_UNITS 8 /* More are supported, limit only on options */ 145static int options[MAX_UNITS]; 146static int full_duplex[MAX_UNITS]; 147static int homepna[MAX_UNITS]; 148 149/* 150 * Theory of Operation 151 * 152 * This driver uses the same software structure as the normal lance 153 * driver. So look for a verbose description in lance.c. The differences 154 * to the normal lance driver is the use of the 32bit mode of PCnet32 155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no 156 * 16MB limitation and we don't need bounce buffers. 157 */ 158 159/* 160 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 163 */ 164#ifndef PCNET32_LOG_TX_BUFFERS 165#define PCNET32_LOG_TX_BUFFERS 4 166#define PCNET32_LOG_RX_BUFFERS 5 167#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ 168#define PCNET32_LOG_MAX_RX_BUFFERS 9 169#endif 170 171#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) 172#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) 173 174#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) 175#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) 176 177#define PKT_BUF_SKB 1544 178/* actual buffer length after being aligned */ 179#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN) 180/* chip wants twos complement of the (aligned) buffer length */ 181#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB) 182 183/* Offsets from base I/O address. */ 184#define PCNET32_WIO_RDP 0x10 185#define PCNET32_WIO_RAP 0x12 186#define PCNET32_WIO_RESET 0x14 187#define PCNET32_WIO_BDP 0x16 188 189#define PCNET32_DWIO_RDP 0x10 190#define PCNET32_DWIO_RAP 0x14 191#define PCNET32_DWIO_RESET 0x18 192#define PCNET32_DWIO_BDP 0x1C 193 194#define PCNET32_TOTAL_SIZE 0x20 195 196#define CSR0 0 197#define CSR0_INIT 0x1 198#define CSR0_START 0x2 199#define CSR0_STOP 0x4 200#define CSR0_TXPOLL 0x8 201#define CSR0_INTEN 0x40 202#define CSR0_IDON 0x0100 203#define CSR0_NORMAL (CSR0_START | CSR0_INTEN) 204#define PCNET32_INIT_LOW 1 205#define PCNET32_INIT_HIGH 2 206#define CSR3 3 207#define CSR4 4 208#define CSR5 5 209#define CSR5_SUSPEND 0x0001 210#define CSR15 15 211#define PCNET32_MC_FILTER 8 212 213#define PCNET32_79C970A 0x2621 214 215/* The PCNET32 Rx and Tx ring descriptors. */ 216struct pcnet32_rx_head { 217 __le32 base; 218 __le16 buf_length; /* two`s complement of length */ 219 __le16 status; 220 __le32 msg_length; 221 __le32 reserved; 222}; 223 224struct pcnet32_tx_head { 225 __le32 base; 226 __le16 length; /* two`s complement of length */ 227 __le16 status; 228 __le32 misc; 229 __le32 reserved; 230}; 231 232/* The PCNET32 32-Bit initialization block, described in databook. */ 233struct pcnet32_init_block { 234 __le16 mode; 235 __le16 tlen_rlen; 236 u8 phys_addr[6]; 237 __le16 reserved; 238 __le32 filter[2]; 239 /* Receive and transmit ring base, along with extra bits. */ 240 __le32 rx_ring; 241 __le32 tx_ring; 242}; 243 244/* PCnet32 access functions */ 245struct pcnet32_access { 246 u16 (*read_csr) (unsigned long, int); 247 void (*write_csr) (unsigned long, int, u16); 248 u16 (*read_bcr) (unsigned long, int); 249 void (*write_bcr) (unsigned long, int, u16); 250 u16 (*read_rap) (unsigned long); 251 void (*write_rap) (unsigned long, u16); 252 void (*reset) (unsigned long); 253}; 254 255/* 256 * The first field of pcnet32_private is read by the ethernet device 257 * so the structure should be allocated using pci_alloc_consistent(). 258 */ 259struct pcnet32_private { 260 struct pcnet32_init_block *init_block; 261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ 262 struct pcnet32_rx_head *rx_ring; 263 struct pcnet32_tx_head *tx_ring; 264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block, 265 returned by pci_alloc_consistent */ 266 struct pci_dev *pci_dev; 267 const char *name; 268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 269 struct sk_buff **tx_skbuff; 270 struct sk_buff **rx_skbuff; 271 dma_addr_t *tx_dma_addr; 272 dma_addr_t *rx_dma_addr; 273 struct pcnet32_access a; 274 spinlock_t lock; /* Guard lock */ 275 unsigned int cur_rx, cur_tx; /* The next free ring entry */ 276 unsigned int rx_ring_size; /* current rx ring size */ 277 unsigned int tx_ring_size; /* current tx ring size */ 278 unsigned int rx_mod_mask; /* rx ring modular mask */ 279 unsigned int tx_mod_mask; /* tx ring modular mask */ 280 unsigned short rx_len_bits; 281 unsigned short tx_len_bits; 282 dma_addr_t rx_ring_dma_addr; 283 dma_addr_t tx_ring_dma_addr; 284 unsigned int dirty_rx, /* ring entries to be freed. */ 285 dirty_tx; 286 287 struct net_device *dev; 288 struct napi_struct napi; 289 char tx_full; 290 char phycount; /* number of phys found */ 291 int options; 292 unsigned int shared_irq:1, /* shared irq possible */ 293 dxsuflo:1, /* disable transmit stop on uflo */ 294 mii:1; /* mii port available */ 295 struct net_device *next; 296 struct mii_if_info mii_if; 297 struct timer_list watchdog_timer; 298 struct timer_list blink_timer; 299 u32 msg_enable; /* debug message level */ 300 301 /* each bit indicates an available PHY */ 302 u32 phymask; 303 unsigned short chip_version; /* which variant this is */ 304}; 305 306static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); 307static int pcnet32_probe1(unsigned long, int, struct pci_dev *); 308static int pcnet32_open(struct net_device *); 309static int pcnet32_init_ring(struct net_device *); 310static netdev_tx_t pcnet32_start_xmit(struct sk_buff *, 311 struct net_device *); 312static void pcnet32_tx_timeout(struct net_device *dev); 313static irqreturn_t pcnet32_interrupt(int, void *); 314static int pcnet32_close(struct net_device *); 315static struct net_device_stats *pcnet32_get_stats(struct net_device *); 316static void pcnet32_load_multicast(struct net_device *dev); 317static void pcnet32_set_multicast_list(struct net_device *); 318static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); 319static void pcnet32_watchdog(struct net_device *); 320static int mdio_read(struct net_device *dev, int phy_id, int reg_num); 321static void mdio_write(struct net_device *dev, int phy_id, int reg_num, 322 int val); 323static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); 324static void pcnet32_ethtool_test(struct net_device *dev, 325 struct ethtool_test *eth_test, u64 * data); 326static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); 327static int pcnet32_phys_id(struct net_device *dev, u32 data); 328static void pcnet32_led_blink_callback(struct net_device *dev); 329static int pcnet32_get_regs_len(struct net_device *dev); 330static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 331 void *ptr); 332static void pcnet32_purge_tx_ring(struct net_device *dev); 333static int pcnet32_alloc_ring(struct net_device *dev, const char *name); 334static void pcnet32_free_ring(struct net_device *dev); 335static void pcnet32_check_media(struct net_device *dev, int verbose); 336 337static u16 pcnet32_wio_read_csr(unsigned long addr, int index) 338{ 339 outw(index, addr + PCNET32_WIO_RAP); 340 return inw(addr + PCNET32_WIO_RDP); 341} 342 343static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) 344{ 345 outw(index, addr + PCNET32_WIO_RAP); 346 outw(val, addr + PCNET32_WIO_RDP); 347} 348 349static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) 350{ 351 outw(index, addr + PCNET32_WIO_RAP); 352 return inw(addr + PCNET32_WIO_BDP); 353} 354 355static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) 356{ 357 outw(index, addr + PCNET32_WIO_RAP); 358 outw(val, addr + PCNET32_WIO_BDP); 359} 360 361static u16 pcnet32_wio_read_rap(unsigned long addr) 362{ 363 return inw(addr + PCNET32_WIO_RAP); 364} 365 366static void pcnet32_wio_write_rap(unsigned long addr, u16 val) 367{ 368 outw(val, addr + PCNET32_WIO_RAP); 369} 370 371static void pcnet32_wio_reset(unsigned long addr) 372{ 373 inw(addr + PCNET32_WIO_RESET); 374} 375 376static int pcnet32_wio_check(unsigned long addr) 377{ 378 outw(88, addr + PCNET32_WIO_RAP); 379 return (inw(addr + PCNET32_WIO_RAP) == 88); 380} 381 382static struct pcnet32_access pcnet32_wio = { 383 .read_csr = pcnet32_wio_read_csr, 384 .write_csr = pcnet32_wio_write_csr, 385 .read_bcr = pcnet32_wio_read_bcr, 386 .write_bcr = pcnet32_wio_write_bcr, 387 .read_rap = pcnet32_wio_read_rap, 388 .write_rap = pcnet32_wio_write_rap, 389 .reset = pcnet32_wio_reset 390}; 391 392static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) 393{ 394 outl(index, addr + PCNET32_DWIO_RAP); 395 return inl(addr + PCNET32_DWIO_RDP) & 0xffff; 396} 397 398static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) 399{ 400 outl(index, addr + PCNET32_DWIO_RAP); 401 outl(val, addr + PCNET32_DWIO_RDP); 402} 403 404static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) 405{ 406 outl(index, addr + PCNET32_DWIO_RAP); 407 return inl(addr + PCNET32_DWIO_BDP) & 0xffff; 408} 409 410static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) 411{ 412 outl(index, addr + PCNET32_DWIO_RAP); 413 outl(val, addr + PCNET32_DWIO_BDP); 414} 415 416static u16 pcnet32_dwio_read_rap(unsigned long addr) 417{ 418 return inl(addr + PCNET32_DWIO_RAP) & 0xffff; 419} 420 421static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) 422{ 423 outl(val, addr + PCNET32_DWIO_RAP); 424} 425 426static void pcnet32_dwio_reset(unsigned long addr) 427{ 428 inl(addr + PCNET32_DWIO_RESET); 429} 430 431static int pcnet32_dwio_check(unsigned long addr) 432{ 433 outl(88, addr + PCNET32_DWIO_RAP); 434 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88); 435} 436 437static struct pcnet32_access pcnet32_dwio = { 438 .read_csr = pcnet32_dwio_read_csr, 439 .write_csr = pcnet32_dwio_write_csr, 440 .read_bcr = pcnet32_dwio_read_bcr, 441 .write_bcr = pcnet32_dwio_write_bcr, 442 .read_rap = pcnet32_dwio_read_rap, 443 .write_rap = pcnet32_dwio_write_rap, 444 .reset = pcnet32_dwio_reset 445}; 446 447static void pcnet32_netif_stop(struct net_device *dev) 448{ 449 struct pcnet32_private *lp = netdev_priv(dev); 450 451 dev->trans_start = jiffies; /* prevent tx timeout */ 452 napi_disable(&lp->napi); 453 netif_tx_disable(dev); 454} 455 456static void pcnet32_netif_start(struct net_device *dev) 457{ 458 struct pcnet32_private *lp = netdev_priv(dev); 459 ulong ioaddr = dev->base_addr; 460 u16 val; 461 462 netif_wake_queue(dev); 463 val = lp->a.read_csr(ioaddr, CSR3); 464 val &= 0x00ff; 465 lp->a.write_csr(ioaddr, CSR3, val); 466 napi_enable(&lp->napi); 467} 468 469/* 470 * Allocate space for the new sized tx ring. 471 * Free old resources 472 * Save new resources. 473 * Any failure keeps old resources. 474 * Must be called with lp->lock held. 475 */ 476static void pcnet32_realloc_tx_ring(struct net_device *dev, 477 struct pcnet32_private *lp, 478 unsigned int size) 479{ 480 dma_addr_t new_ring_dma_addr; 481 dma_addr_t *new_dma_addr_list; 482 struct pcnet32_tx_head *new_tx_ring; 483 struct sk_buff **new_skb_list; 484 485 pcnet32_purge_tx_ring(dev); 486 487 new_tx_ring = pci_alloc_consistent(lp->pci_dev, 488 sizeof(struct pcnet32_tx_head) * 489 (1 << size), 490 &new_ring_dma_addr); 491 if (new_tx_ring == NULL) { 492 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 493 return; 494 } 495 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size)); 496 497 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t), 498 GFP_ATOMIC); 499 if (!new_dma_addr_list) { 500 netif_err(lp, drv, dev, "Memory allocation failed\n"); 501 goto free_new_tx_ring; 502 } 503 504 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *), 505 GFP_ATOMIC); 506 if (!new_skb_list) { 507 netif_err(lp, drv, dev, "Memory allocation failed\n"); 508 goto free_new_lists; 509 } 510 511 kfree(lp->tx_skbuff); 512 kfree(lp->tx_dma_addr); 513 pci_free_consistent(lp->pci_dev, 514 sizeof(struct pcnet32_tx_head) * 515 lp->tx_ring_size, lp->tx_ring, 516 lp->tx_ring_dma_addr); 517 518 lp->tx_ring_size = (1 << size); 519 lp->tx_mod_mask = lp->tx_ring_size - 1; 520 lp->tx_len_bits = (size << 12); 521 lp->tx_ring = new_tx_ring; 522 lp->tx_ring_dma_addr = new_ring_dma_addr; 523 lp->tx_dma_addr = new_dma_addr_list; 524 lp->tx_skbuff = new_skb_list; 525 return; 526 527free_new_lists: 528 kfree(new_dma_addr_list); 529free_new_tx_ring: 530 pci_free_consistent(lp->pci_dev, 531 sizeof(struct pcnet32_tx_head) * 532 (1 << size), 533 new_tx_ring, 534 new_ring_dma_addr); 535} 536 537/* 538 * Allocate space for the new sized rx ring. 539 * Re-use old receive buffers. 540 * alloc extra buffers 541 * free unneeded buffers 542 * free unneeded buffers 543 * Save new resources. 544 * Any failure keeps old resources. 545 * Must be called with lp->lock held. 546 */ 547static void pcnet32_realloc_rx_ring(struct net_device *dev, 548 struct pcnet32_private *lp, 549 unsigned int size) 550{ 551 dma_addr_t new_ring_dma_addr; 552 dma_addr_t *new_dma_addr_list; 553 struct pcnet32_rx_head *new_rx_ring; 554 struct sk_buff **new_skb_list; 555 int new, overlap; 556 557 new_rx_ring = pci_alloc_consistent(lp->pci_dev, 558 sizeof(struct pcnet32_rx_head) * 559 (1 << size), 560 &new_ring_dma_addr); 561 if (new_rx_ring == NULL) { 562 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 563 return; 564 } 565 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size)); 566 567 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t), 568 GFP_ATOMIC); 569 if (!new_dma_addr_list) { 570 netif_err(lp, drv, dev, "Memory allocation failed\n"); 571 goto free_new_rx_ring; 572 } 573 574 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *), 575 GFP_ATOMIC); 576 if (!new_skb_list) { 577 netif_err(lp, drv, dev, "Memory allocation failed\n"); 578 goto free_new_lists; 579 } 580 581 /* first copy the current receive buffers */ 582 overlap = min(size, lp->rx_ring_size); 583 for (new = 0; new < overlap; new++) { 584 new_rx_ring[new] = lp->rx_ring[new]; 585 new_dma_addr_list[new] = lp->rx_dma_addr[new]; 586 new_skb_list[new] = lp->rx_skbuff[new]; 587 } 588 /* now allocate any new buffers needed */ 589 for (; new < size; new++) { 590 struct sk_buff *rx_skbuff; 591 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB); 592 rx_skbuff = new_skb_list[new]; 593 if (!rx_skbuff) { 594 /* keep the original lists and buffers */ 595 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n", 596 __func__); 597 goto free_all_new; 598 } 599 skb_reserve(rx_skbuff, NET_IP_ALIGN); 600 601 new_dma_addr_list[new] = 602 pci_map_single(lp->pci_dev, rx_skbuff->data, 603 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 604 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); 605 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE); 606 new_rx_ring[new].status = cpu_to_le16(0x8000); 607 } 608 /* and free any unneeded buffers */ 609 for (; new < lp->rx_ring_size; new++) { 610 if (lp->rx_skbuff[new]) { 611 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new], 612 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 613 dev_kfree_skb(lp->rx_skbuff[new]); 614 } 615 } 616 617 kfree(lp->rx_skbuff); 618 kfree(lp->rx_dma_addr); 619 pci_free_consistent(lp->pci_dev, 620 sizeof(struct pcnet32_rx_head) * 621 lp->rx_ring_size, lp->rx_ring, 622 lp->rx_ring_dma_addr); 623 624 lp->rx_ring_size = (1 << size); 625 lp->rx_mod_mask = lp->rx_ring_size - 1; 626 lp->rx_len_bits = (size << 4); 627 lp->rx_ring = new_rx_ring; 628 lp->rx_ring_dma_addr = new_ring_dma_addr; 629 lp->rx_dma_addr = new_dma_addr_list; 630 lp->rx_skbuff = new_skb_list; 631 return; 632 633free_all_new: 634 while (--new >= lp->rx_ring_size) { 635 if (new_skb_list[new]) { 636 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new], 637 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 638 dev_kfree_skb(new_skb_list[new]); 639 } 640 } 641 kfree(new_skb_list); 642free_new_lists: 643 kfree(new_dma_addr_list); 644free_new_rx_ring: 645 pci_free_consistent(lp->pci_dev, 646 sizeof(struct pcnet32_rx_head) * 647 (1 << size), 648 new_rx_ring, 649 new_ring_dma_addr); 650} 651 652static void pcnet32_purge_rx_ring(struct net_device *dev) 653{ 654 struct pcnet32_private *lp = netdev_priv(dev); 655 int i; 656 657 /* free all allocated skbuffs */ 658 for (i = 0; i < lp->rx_ring_size; i++) { 659 lp->rx_ring[i].status = 0; /* CPU owns buffer */ 660 wmb(); /* Make sure adapter sees owner change */ 661 if (lp->rx_skbuff[i]) { 662 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], 663 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 664 dev_kfree_skb_any(lp->rx_skbuff[i]); 665 } 666 lp->rx_skbuff[i] = NULL; 667 lp->rx_dma_addr[i] = 0; 668 } 669} 670 671#ifdef CONFIG_NET_POLL_CONTROLLER 672static void pcnet32_poll_controller(struct net_device *dev) 673{ 674 disable_irq(dev->irq); 675 pcnet32_interrupt(0, dev); 676 enable_irq(dev->irq); 677} 678#endif 679 680static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 681{ 682 struct pcnet32_private *lp = netdev_priv(dev); 683 unsigned long flags; 684 int r = -EOPNOTSUPP; 685 686 if (lp->mii) { 687 spin_lock_irqsave(&lp->lock, flags); 688 mii_ethtool_gset(&lp->mii_if, cmd); 689 spin_unlock_irqrestore(&lp->lock, flags); 690 r = 0; 691 } 692 return r; 693} 694 695static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 696{ 697 struct pcnet32_private *lp = netdev_priv(dev); 698 unsigned long flags; 699 int r = -EOPNOTSUPP; 700 701 if (lp->mii) { 702 spin_lock_irqsave(&lp->lock, flags); 703 r = mii_ethtool_sset(&lp->mii_if, cmd); 704 spin_unlock_irqrestore(&lp->lock, flags); 705 } 706 return r; 707} 708 709static void pcnet32_get_drvinfo(struct net_device *dev, 710 struct ethtool_drvinfo *info) 711{ 712 struct pcnet32_private *lp = netdev_priv(dev); 713 714 strcpy(info->driver, DRV_NAME); 715 strcpy(info->version, DRV_VERSION); 716 if (lp->pci_dev) 717 strcpy(info->bus_info, pci_name(lp->pci_dev)); 718 else 719 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr); 720} 721 722static u32 pcnet32_get_link(struct net_device *dev) 723{ 724 struct pcnet32_private *lp = netdev_priv(dev); 725 unsigned long flags; 726 int r; 727 728 spin_lock_irqsave(&lp->lock, flags); 729 if (lp->mii) { 730 r = mii_link_ok(&lp->mii_if); 731 } else if (lp->chip_version >= PCNET32_79C970A) { 732 ulong ioaddr = dev->base_addr; /* card base I/O address */ 733 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0); 734 } else { /* can not detect link on really old chips */ 735 r = 1; 736 } 737 spin_unlock_irqrestore(&lp->lock, flags); 738 739 return r; 740} 741 742static u32 pcnet32_get_msglevel(struct net_device *dev) 743{ 744 struct pcnet32_private *lp = netdev_priv(dev); 745 return lp->msg_enable; 746} 747 748static void pcnet32_set_msglevel(struct net_device *dev, u32 value) 749{ 750 struct pcnet32_private *lp = netdev_priv(dev); 751 lp->msg_enable = value; 752} 753 754static int pcnet32_nway_reset(struct net_device *dev) 755{ 756 struct pcnet32_private *lp = netdev_priv(dev); 757 unsigned long flags; 758 int r = -EOPNOTSUPP; 759 760 if (lp->mii) { 761 spin_lock_irqsave(&lp->lock, flags); 762 r = mii_nway_restart(&lp->mii_if); 763 spin_unlock_irqrestore(&lp->lock, flags); 764 } 765 return r; 766} 767 768static void pcnet32_get_ringparam(struct net_device *dev, 769 struct ethtool_ringparam *ering) 770{ 771 struct pcnet32_private *lp = netdev_priv(dev); 772 773 ering->tx_max_pending = TX_MAX_RING_SIZE; 774 ering->tx_pending = lp->tx_ring_size; 775 ering->rx_max_pending = RX_MAX_RING_SIZE; 776 ering->rx_pending = lp->rx_ring_size; 777} 778 779static int pcnet32_set_ringparam(struct net_device *dev, 780 struct ethtool_ringparam *ering) 781{ 782 struct pcnet32_private *lp = netdev_priv(dev); 783 unsigned long flags; 784 unsigned int size; 785 ulong ioaddr = dev->base_addr; 786 int i; 787 788 if (ering->rx_mini_pending || ering->rx_jumbo_pending) 789 return -EINVAL; 790 791 if (netif_running(dev)) 792 pcnet32_netif_stop(dev); 793 794 spin_lock_irqsave(&lp->lock, flags); 795 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 796 797 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); 798 799 /* set the minimum ring size to 4, to allow the loopback test to work 800 * unchanged. 801 */ 802 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { 803 if (size <= (1 << i)) 804 break; 805 } 806 if ((1 << i) != lp->tx_ring_size) 807 pcnet32_realloc_tx_ring(dev, lp, i); 808 809 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); 810 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { 811 if (size <= (1 << i)) 812 break; 813 } 814 if ((1 << i) != lp->rx_ring_size) 815 pcnet32_realloc_rx_ring(dev, lp, i); 816 817 lp->napi.weight = lp->rx_ring_size / 2; 818 819 if (netif_running(dev)) { 820 pcnet32_netif_start(dev); 821 pcnet32_restart(dev, CSR0_NORMAL); 822 } 823 824 spin_unlock_irqrestore(&lp->lock, flags); 825 826 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n", 827 lp->rx_ring_size, lp->tx_ring_size); 828 829 return 0; 830} 831 832static void pcnet32_get_strings(struct net_device *dev, u32 stringset, 833 u8 *data) 834{ 835 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); 836} 837 838static int pcnet32_get_sset_count(struct net_device *dev, int sset) 839{ 840 switch (sset) { 841 case ETH_SS_TEST: 842 return PCNET32_TEST_LEN; 843 default: 844 return -EOPNOTSUPP; 845 } 846} 847 848static void pcnet32_ethtool_test(struct net_device *dev, 849 struct ethtool_test *test, u64 * data) 850{ 851 struct pcnet32_private *lp = netdev_priv(dev); 852 int rc; 853 854 if (test->flags == ETH_TEST_FL_OFFLINE) { 855 rc = pcnet32_loopback_test(dev, data); 856 if (rc) { 857 netif_printk(lp, hw, KERN_DEBUG, dev, 858 "Loopback test failed\n"); 859 test->flags |= ETH_TEST_FL_FAILED; 860 } else 861 netif_printk(lp, hw, KERN_DEBUG, dev, 862 "Loopback test passed\n"); 863 } else 864 netif_printk(lp, hw, KERN_DEBUG, dev, 865 "No tests to run (specify 'Offline' on ethtool)\n"); 866} /* end pcnet32_ethtool_test */ 867 868static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) 869{ 870 struct pcnet32_private *lp = netdev_priv(dev); 871 struct pcnet32_access *a = &lp->a; /* access to registers */ 872 ulong ioaddr = dev->base_addr; /* card base I/O address */ 873 struct sk_buff *skb; /* sk buff */ 874 int x, i; /* counters */ 875 int numbuffs = 4; /* number of TX/RX buffers and descs */ 876 u16 status = 0x8300; /* TX ring status */ 877 __le16 teststatus; /* test of ring status */ 878 int rc; /* return code */ 879 int size; /* size of packets */ 880 unsigned char *packet; /* source packet data */ 881 static const int data_len = 60; /* length of source packets */ 882 unsigned long flags; 883 unsigned long ticks; 884 885 rc = 1; /* default to fail */ 886 887 if (netif_running(dev)) 888 pcnet32_netif_stop(dev); 889 890 spin_lock_irqsave(&lp->lock, flags); 891 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 892 893 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size)); 894 895 /* Reset the PCNET32 */ 896 lp->a.reset(ioaddr); 897 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 898 899 /* switch pcnet32 to 32bit mode */ 900 lp->a.write_bcr(ioaddr, 20, 2); 901 902 /* purge & init rings but don't actually restart */ 903 pcnet32_restart(dev, 0x0000); 904 905 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 906 907 /* Initialize Transmit buffers. */ 908 size = data_len + 15; 909 for (x = 0; x < numbuffs; x++) { 910 skb = dev_alloc_skb(size); 911 if (!skb) { 912 netif_printk(lp, hw, KERN_DEBUG, dev, 913 "Cannot allocate skb at line: %d!\n", 914 __LINE__); 915 goto clean_up; 916 } 917 packet = skb->data; 918 skb_put(skb, size); /* create space for data */ 919 lp->tx_skbuff[x] = skb; 920 lp->tx_ring[x].length = cpu_to_le16(-skb->len); 921 lp->tx_ring[x].misc = 0; 922 923 /* put DA and SA into the skb */ 924 for (i = 0; i < 6; i++) 925 *packet++ = dev->dev_addr[i]; 926 for (i = 0; i < 6; i++) 927 *packet++ = dev->dev_addr[i]; 928 /* type */ 929 *packet++ = 0x08; 930 *packet++ = 0x06; 931 /* packet number */ 932 *packet++ = x; 933 /* fill packet with data */ 934 for (i = 0; i < data_len; i++) 935 *packet++ = i; 936 937 lp->tx_dma_addr[x] = 938 pci_map_single(lp->pci_dev, skb->data, skb->len, 939 PCI_DMA_TODEVICE); 940 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); 941 wmb(); /* Make sure owner changes after all others are visible */ 942 lp->tx_ring[x].status = cpu_to_le16(status); 943 } 944 945 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */ 946 a->write_bcr(ioaddr, 32, x | 0x0002); 947 948 /* set int loopback in CSR15 */ 949 x = a->read_csr(ioaddr, CSR15) & 0xfffc; 950 lp->a.write_csr(ioaddr, CSR15, x | 0x0044); 951 952 teststatus = cpu_to_le16(0x8000); 953 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ 954 955 /* Check status of descriptors */ 956 for (x = 0; x < numbuffs; x++) { 957 ticks = 0; 958 rmb(); 959 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { 960 spin_unlock_irqrestore(&lp->lock, flags); 961 msleep(1); 962 spin_lock_irqsave(&lp->lock, flags); 963 rmb(); 964 ticks++; 965 } 966 if (ticks == 200) { 967 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x); 968 break; 969 } 970 } 971 972 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 973 wmb(); 974 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { 975 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n"); 976 977 for (x = 0; x < numbuffs; x++) { 978 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x); 979 skb = lp->rx_skbuff[x]; 980 for (i = 0; i < size; i++) 981 pr_cont(" %02x", *(skb->data + i)); 982 pr_cont("\n"); 983 } 984 } 985 986 x = 0; 987 rc = 0; 988 while (x < numbuffs && !rc) { 989 skb = lp->rx_skbuff[x]; 990 packet = lp->tx_skbuff[x]->data; 991 for (i = 0; i < size; i++) { 992 if (*(skb->data + i) != packet[i]) { 993 netif_printk(lp, hw, KERN_DEBUG, dev, 994 "Error in compare! %2x - %02x %02x\n", 995 i, *(skb->data + i), packet[i]); 996 rc = 1; 997 break; 998 } 999 } 1000 x++; 1001 } 1002 1003clean_up: 1004 *data1 = rc; 1005 pcnet32_purge_tx_ring(dev); 1006 1007 x = a->read_csr(ioaddr, CSR15); 1008 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ 1009 1010 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ 1011 a->write_bcr(ioaddr, 32, (x & ~0x0002)); 1012 1013 if (netif_running(dev)) { 1014 pcnet32_netif_start(dev); 1015 pcnet32_restart(dev, CSR0_NORMAL); 1016 } else { 1017 pcnet32_purge_rx_ring(dev); 1018 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ 1019 } 1020 spin_unlock_irqrestore(&lp->lock, flags); 1021 1022 return rc; 1023} /* end pcnet32_loopback_test */ 1024 1025static void pcnet32_led_blink_callback(struct net_device *dev) 1026{ 1027 struct pcnet32_private *lp = netdev_priv(dev); 1028 struct pcnet32_access *a = &lp->a; 1029 ulong ioaddr = dev->base_addr; 1030 unsigned long flags; 1031 int i; 1032 1033 spin_lock_irqsave(&lp->lock, flags); 1034 for (i = 4; i < 8; i++) 1035 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); 1036 spin_unlock_irqrestore(&lp->lock, flags); 1037 1038 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT); 1039} 1040 1041static int pcnet32_phys_id(struct net_device *dev, u32 data) 1042{ 1043 struct pcnet32_private *lp = netdev_priv(dev); 1044 struct pcnet32_access *a = &lp->a; 1045 ulong ioaddr = dev->base_addr; 1046 unsigned long flags; 1047 int i, regs[4]; 1048 1049 if (!lp->blink_timer.function) { 1050 init_timer(&lp->blink_timer); 1051 lp->blink_timer.function = (void *)pcnet32_led_blink_callback; 1052 lp->blink_timer.data = (unsigned long)dev; 1053 } 1054 1055 /* Save the current value of the bcrs */ 1056 spin_lock_irqsave(&lp->lock, flags); 1057 for (i = 4; i < 8; i++) 1058 regs[i - 4] = a->read_bcr(ioaddr, i); 1059 spin_unlock_irqrestore(&lp->lock, flags); 1060 1061 mod_timer(&lp->blink_timer, jiffies); 1062 set_current_state(TASK_INTERRUPTIBLE); 1063 1064 /* AV: the limit here makes no sense whatsoever */ 1065 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))) 1066 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ); 1067 1068 msleep_interruptible(data * 1000); 1069 del_timer_sync(&lp->blink_timer); 1070 1071 /* Restore the original value of the bcrs */ 1072 spin_lock_irqsave(&lp->lock, flags); 1073 for (i = 4; i < 8; i++) 1074 a->write_bcr(ioaddr, i, regs[i - 4]); 1075 spin_unlock_irqrestore(&lp->lock, flags); 1076 1077 return 0; 1078} 1079 1080/* 1081 * lp->lock must be held. 1082 */ 1083static int pcnet32_suspend(struct net_device *dev, unsigned long *flags, 1084 int can_sleep) 1085{ 1086 int csr5; 1087 struct pcnet32_private *lp = netdev_priv(dev); 1088 struct pcnet32_access *a = &lp->a; 1089 ulong ioaddr = dev->base_addr; 1090 int ticks; 1091 1092 /* really old chips have to be stopped. */ 1093 if (lp->chip_version < PCNET32_79C970A) 1094 return 0; 1095 1096 /* set SUSPEND (SPND) - CSR5 bit 0 */ 1097 csr5 = a->read_csr(ioaddr, CSR5); 1098 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); 1099 1100 /* poll waiting for bit to be set */ 1101 ticks = 0; 1102 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { 1103 spin_unlock_irqrestore(&lp->lock, *flags); 1104 if (can_sleep) 1105 msleep(1); 1106 else 1107 mdelay(1); 1108 spin_lock_irqsave(&lp->lock, *flags); 1109 ticks++; 1110 if (ticks > 200) { 1111 netif_printk(lp, hw, KERN_DEBUG, dev, 1112 "Error getting into suspend!\n"); 1113 return 0; 1114 } 1115 } 1116 return 1; 1117} 1118 1119/* 1120 * process one receive descriptor entry 1121 */ 1122 1123static void pcnet32_rx_entry(struct net_device *dev, 1124 struct pcnet32_private *lp, 1125 struct pcnet32_rx_head *rxp, 1126 int entry) 1127{ 1128 int status = (short)le16_to_cpu(rxp->status) >> 8; 1129 int rx_in_place = 0; 1130 struct sk_buff *skb; 1131 short pkt_len; 1132 1133 if (status != 0x03) { /* There was an error. */ 1134 /* 1135 * There is a tricky error noted by John Murphy, 1136 * <murf@perftech.com> to Russ Nelson: Even with full-sized 1137 * buffers it's possible for a jabber packet to use two 1138 * buffers, with only the last correctly noting the error. 1139 */ 1140 if (status & 0x01) /* Only count a general error at the */ 1141 dev->stats.rx_errors++; /* end of a packet. */ 1142 if (status & 0x20) 1143 dev->stats.rx_frame_errors++; 1144 if (status & 0x10) 1145 dev->stats.rx_over_errors++; 1146 if (status & 0x08) 1147 dev->stats.rx_crc_errors++; 1148 if (status & 0x04) 1149 dev->stats.rx_fifo_errors++; 1150 return; 1151 } 1152 1153 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4; 1154 1155 /* Discard oversize frames. */ 1156 if (unlikely(pkt_len > PKT_BUF_SIZE)) { 1157 netif_err(lp, drv, dev, "Impossible packet size %d!\n", 1158 pkt_len); 1159 dev->stats.rx_errors++; 1160 return; 1161 } 1162 if (pkt_len < 60) { 1163 netif_err(lp, rx_err, dev, "Runt packet!\n"); 1164 dev->stats.rx_errors++; 1165 return; 1166 } 1167 1168 if (pkt_len > rx_copybreak) { 1169 struct sk_buff *newskb; 1170 1171 newskb = dev_alloc_skb(PKT_BUF_SKB); 1172 if (newskb) { 1173 skb_reserve(newskb, NET_IP_ALIGN); 1174 skb = lp->rx_skbuff[entry]; 1175 pci_unmap_single(lp->pci_dev, 1176 lp->rx_dma_addr[entry], 1177 PKT_BUF_SIZE, 1178 PCI_DMA_FROMDEVICE); 1179 skb_put(skb, pkt_len); 1180 lp->rx_skbuff[entry] = newskb; 1181 lp->rx_dma_addr[entry] = 1182 pci_map_single(lp->pci_dev, 1183 newskb->data, 1184 PKT_BUF_SIZE, 1185 PCI_DMA_FROMDEVICE); 1186 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]); 1187 rx_in_place = 1; 1188 } else 1189 skb = NULL; 1190 } else 1191 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN); 1192 1193 if (skb == NULL) { 1194 netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n"); 1195 dev->stats.rx_dropped++; 1196 return; 1197 } 1198 if (!rx_in_place) { 1199 skb_reserve(skb, NET_IP_ALIGN); 1200 skb_put(skb, pkt_len); /* Make room */ 1201 pci_dma_sync_single_for_cpu(lp->pci_dev, 1202 lp->rx_dma_addr[entry], 1203 pkt_len, 1204 PCI_DMA_FROMDEVICE); 1205 skb_copy_to_linear_data(skb, 1206 (unsigned char *)(lp->rx_skbuff[entry]->data), 1207 pkt_len); 1208 pci_dma_sync_single_for_device(lp->pci_dev, 1209 lp->rx_dma_addr[entry], 1210 pkt_len, 1211 PCI_DMA_FROMDEVICE); 1212 } 1213 dev->stats.rx_bytes += skb->len; 1214 skb->protocol = eth_type_trans(skb, dev); 1215 netif_receive_skb(skb); 1216 dev->stats.rx_packets++; 1217} 1218 1219static int pcnet32_rx(struct net_device *dev, int budget) 1220{ 1221 struct pcnet32_private *lp = netdev_priv(dev); 1222 int entry = lp->cur_rx & lp->rx_mod_mask; 1223 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry]; 1224 int npackets = 0; 1225 1226 /* If we own the next entry, it's a new packet. Send it up. */ 1227 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) { 1228 pcnet32_rx_entry(dev, lp, rxp, entry); 1229 npackets += 1; 1230 /* 1231 * The docs say that the buffer length isn't touched, but Andrew 1232 * Boyd of QNX reports that some revs of the 79C965 clear it. 1233 */ 1234 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE); 1235 wmb(); /* Make sure owner changes after others are visible */ 1236 rxp->status = cpu_to_le16(0x8000); 1237 entry = (++lp->cur_rx) & lp->rx_mod_mask; 1238 rxp = &lp->rx_ring[entry]; 1239 } 1240 1241 return npackets; 1242} 1243 1244static int pcnet32_tx(struct net_device *dev) 1245{ 1246 struct pcnet32_private *lp = netdev_priv(dev); 1247 unsigned int dirty_tx = lp->dirty_tx; 1248 int delta; 1249 int must_restart = 0; 1250 1251 while (dirty_tx != lp->cur_tx) { 1252 int entry = dirty_tx & lp->tx_mod_mask; 1253 int status = (short)le16_to_cpu(lp->tx_ring[entry].status); 1254 1255 if (status < 0) 1256 break; /* It still hasn't been Txed */ 1257 1258 lp->tx_ring[entry].base = 0; 1259 1260 if (status & 0x4000) { 1261 /* There was a major error, log it. */ 1262 int err_status = le32_to_cpu(lp->tx_ring[entry].misc); 1263 dev->stats.tx_errors++; 1264 netif_err(lp, tx_err, dev, 1265 "Tx error status=%04x err_status=%08x\n", 1266 status, err_status); 1267 if (err_status & 0x04000000) 1268 dev->stats.tx_aborted_errors++; 1269 if (err_status & 0x08000000) 1270 dev->stats.tx_carrier_errors++; 1271 if (err_status & 0x10000000) 1272 dev->stats.tx_window_errors++; 1273#ifndef DO_DXSUFLO 1274 if (err_status & 0x40000000) { 1275 dev->stats.tx_fifo_errors++; 1276 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1277 /* Remove this verbosity later! */ 1278 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1279 must_restart = 1; 1280 } 1281#else 1282 if (err_status & 0x40000000) { 1283 dev->stats.tx_fifo_errors++; 1284 if (!lp->dxsuflo) { /* If controller doesn't recover ... */ 1285 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1286 /* Remove this verbosity later! */ 1287 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1288 must_restart = 1; 1289 } 1290 } 1291#endif 1292 } else { 1293 if (status & 0x1800) 1294 dev->stats.collisions++; 1295 dev->stats.tx_packets++; 1296 } 1297 1298 /* We must free the original skb */ 1299 if (lp->tx_skbuff[entry]) { 1300 pci_unmap_single(lp->pci_dev, 1301 lp->tx_dma_addr[entry], 1302 lp->tx_skbuff[entry]-> 1303 len, PCI_DMA_TODEVICE); 1304 dev_kfree_skb_any(lp->tx_skbuff[entry]); 1305 lp->tx_skbuff[entry] = NULL; 1306 lp->tx_dma_addr[entry] = 0; 1307 } 1308 dirty_tx++; 1309 } 1310 1311 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); 1312 if (delta > lp->tx_ring_size) { 1313 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n", 1314 dirty_tx, lp->cur_tx, lp->tx_full); 1315 dirty_tx += lp->tx_ring_size; 1316 delta -= lp->tx_ring_size; 1317 } 1318 1319 if (lp->tx_full && 1320 netif_queue_stopped(dev) && 1321 delta < lp->tx_ring_size - 2) { 1322 /* The ring is no longer full, clear tbusy. */ 1323 lp->tx_full = 0; 1324 netif_wake_queue(dev); 1325 } 1326 lp->dirty_tx = dirty_tx; 1327 1328 return must_restart; 1329} 1330 1331static int pcnet32_poll(struct napi_struct *napi, int budget) 1332{ 1333 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); 1334 struct net_device *dev = lp->dev; 1335 unsigned long ioaddr = dev->base_addr; 1336 unsigned long flags; 1337 int work_done; 1338 u16 val; 1339 1340 work_done = pcnet32_rx(dev, budget); 1341 1342 spin_lock_irqsave(&lp->lock, flags); 1343 if (pcnet32_tx(dev)) { 1344 /* reset the chip to clear the error condition, then restart */ 1345 lp->a.reset(ioaddr); 1346 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 1347 pcnet32_restart(dev, CSR0_START); 1348 netif_wake_queue(dev); 1349 } 1350 spin_unlock_irqrestore(&lp->lock, flags); 1351 1352 if (work_done < budget) { 1353 spin_lock_irqsave(&lp->lock, flags); 1354 1355 __napi_complete(napi); 1356 1357 /* clear interrupt masks */ 1358 val = lp->a.read_csr(ioaddr, CSR3); 1359 val &= 0x00ff; 1360 lp->a.write_csr(ioaddr, CSR3, val); 1361 1362 /* Set interrupt enable. */ 1363 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN); 1364 1365 spin_unlock_irqrestore(&lp->lock, flags); 1366 } 1367 return work_done; 1368} 1369 1370#define PCNET32_REGS_PER_PHY 32 1371#define PCNET32_MAX_PHYS 32 1372static int pcnet32_get_regs_len(struct net_device *dev) 1373{ 1374 struct pcnet32_private *lp = netdev_priv(dev); 1375 int j = lp->phycount * PCNET32_REGS_PER_PHY; 1376 1377 return (PCNET32_NUM_REGS + j) * sizeof(u16); 1378} 1379 1380static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1381 void *ptr) 1382{ 1383 int i, csr0; 1384 u16 *buff = ptr; 1385 struct pcnet32_private *lp = netdev_priv(dev); 1386 struct pcnet32_access *a = &lp->a; 1387 ulong ioaddr = dev->base_addr; 1388 unsigned long flags; 1389 1390 spin_lock_irqsave(&lp->lock, flags); 1391 1392 csr0 = a->read_csr(ioaddr, CSR0); 1393 if (!(csr0 & CSR0_STOP)) /* If not stopped */ 1394 pcnet32_suspend(dev, &flags, 1); 1395 1396 /* read address PROM */ 1397 for (i = 0; i < 16; i += 2) 1398 *buff++ = inw(ioaddr + i); 1399 1400 /* read control and status registers */ 1401 for (i = 0; i < 90; i++) 1402 *buff++ = a->read_csr(ioaddr, i); 1403 1404 *buff++ = a->read_csr(ioaddr, 112); 1405 *buff++ = a->read_csr(ioaddr, 114); 1406 1407 /* read bus configuration registers */ 1408 for (i = 0; i < 30; i++) 1409 *buff++ = a->read_bcr(ioaddr, i); 1410 1411 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ 1412 1413 for (i = 31; i < 36; i++) 1414 *buff++ = a->read_bcr(ioaddr, i); 1415 1416 /* read mii phy registers */ 1417 if (lp->mii) { 1418 int j; 1419 for (j = 0; j < PCNET32_MAX_PHYS; j++) { 1420 if (lp->phymask & (1 << j)) { 1421 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { 1422 lp->a.write_bcr(ioaddr, 33, 1423 (j << 5) | i); 1424 *buff++ = lp->a.read_bcr(ioaddr, 34); 1425 } 1426 } 1427 } 1428 } 1429 1430 if (!(csr0 & CSR0_STOP)) { /* If not stopped */ 1431 int csr5; 1432 1433 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 1434 csr5 = a->read_csr(ioaddr, CSR5); 1435 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 1436 } 1437 1438 spin_unlock_irqrestore(&lp->lock, flags); 1439} 1440 1441static const struct ethtool_ops pcnet32_ethtool_ops = { 1442 .get_settings = pcnet32_get_settings, 1443 .set_settings = pcnet32_set_settings, 1444 .get_drvinfo = pcnet32_get_drvinfo, 1445 .get_msglevel = pcnet32_get_msglevel, 1446 .set_msglevel = pcnet32_set_msglevel, 1447 .nway_reset = pcnet32_nway_reset, 1448 .get_link = pcnet32_get_link, 1449 .get_ringparam = pcnet32_get_ringparam, 1450 .set_ringparam = pcnet32_set_ringparam, 1451 .get_strings = pcnet32_get_strings, 1452 .self_test = pcnet32_ethtool_test, 1453 .phys_id = pcnet32_phys_id, 1454 .get_regs_len = pcnet32_get_regs_len, 1455 .get_regs = pcnet32_get_regs, 1456 .get_sset_count = pcnet32_get_sset_count, 1457}; 1458 1459/* only probes for non-PCI devices, the rest are handled by 1460 * pci_register_driver via pcnet32_probe_pci */ 1461 1462static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) 1463{ 1464 unsigned int *port, ioaddr; 1465 1466 /* search for PCnet32 VLB cards at known addresses */ 1467 for (port = pcnet32_portlist; (ioaddr = *port); port++) { 1468 if (request_region 1469 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { 1470 /* check if there is really a pcnet chip on that ioaddr */ 1471 if ((inb(ioaddr + 14) == 0x57) && 1472 (inb(ioaddr + 15) == 0x57)) { 1473 pcnet32_probe1(ioaddr, 0, NULL); 1474 } else { 1475 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1476 } 1477 } 1478 } 1479} 1480 1481static int __devinit 1482pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) 1483{ 1484 unsigned long ioaddr; 1485 int err; 1486 1487 err = pci_enable_device(pdev); 1488 if (err < 0) { 1489 if (pcnet32_debug & NETIF_MSG_PROBE) 1490 pr_err("failed to enable device -- err=%d\n", err); 1491 return err; 1492 } 1493 pci_set_master(pdev); 1494 1495 ioaddr = pci_resource_start(pdev, 0); 1496 if (!ioaddr) { 1497 if (pcnet32_debug & NETIF_MSG_PROBE) 1498 pr_err("card has no PCI IO resources, aborting\n"); 1499 return -ENODEV; 1500 } 1501 1502 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) { 1503 if (pcnet32_debug & NETIF_MSG_PROBE) 1504 pr_err("architecture does not support 32bit PCI busmaster DMA\n"); 1505 return -ENODEV; 1506 } 1507 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) { 1508 if (pcnet32_debug & NETIF_MSG_PROBE) 1509 pr_err("io address range already allocated\n"); 1510 return -EBUSY; 1511 } 1512 1513 err = pcnet32_probe1(ioaddr, 1, pdev); 1514 if (err < 0) 1515 pci_disable_device(pdev); 1516 1517 return err; 1518} 1519 1520static const struct net_device_ops pcnet32_netdev_ops = { 1521 .ndo_open = pcnet32_open, 1522 .ndo_stop = pcnet32_close, 1523 .ndo_start_xmit = pcnet32_start_xmit, 1524 .ndo_tx_timeout = pcnet32_tx_timeout, 1525 .ndo_get_stats = pcnet32_get_stats, 1526 .ndo_set_multicast_list = pcnet32_set_multicast_list, 1527 .ndo_do_ioctl = pcnet32_ioctl, 1528 .ndo_change_mtu = eth_change_mtu, 1529 .ndo_set_mac_address = eth_mac_addr, 1530 .ndo_validate_addr = eth_validate_addr, 1531#ifdef CONFIG_NET_POLL_CONTROLLER 1532 .ndo_poll_controller = pcnet32_poll_controller, 1533#endif 1534}; 1535 1536/* pcnet32_probe1 1537 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. 1538 * pdev will be NULL when called from pcnet32_probe_vlbus. 1539 */ 1540static int __devinit 1541pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) 1542{ 1543 struct pcnet32_private *lp; 1544 int i, media; 1545 int fdx, mii, fset, dxsuflo; 1546 int chip_version; 1547 char *chipname; 1548 struct net_device *dev; 1549 struct pcnet32_access *a = NULL; 1550 u8 promaddr[6]; 1551 int ret = -ENODEV; 1552 1553 /* reset the chip */ 1554 pcnet32_wio_reset(ioaddr); 1555 1556 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ 1557 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { 1558 a = &pcnet32_wio; 1559 } else { 1560 pcnet32_dwio_reset(ioaddr); 1561 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && 1562 pcnet32_dwio_check(ioaddr)) { 1563 a = &pcnet32_dwio; 1564 } else { 1565 if (pcnet32_debug & NETIF_MSG_PROBE) 1566 pr_err("No access methods\n"); 1567 goto err_release_region; 1568 } 1569 } 1570 1571 chip_version = 1572 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); 1573 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) 1574 pr_info(" PCnet chip version is %#x\n", chip_version); 1575 if ((chip_version & 0xfff) != 0x003) { 1576 if (pcnet32_debug & NETIF_MSG_PROBE) 1577 pr_info("Unsupported chip version\n"); 1578 goto err_release_region; 1579 } 1580 1581 /* initialize variables */ 1582 fdx = mii = fset = dxsuflo = 0; 1583 chip_version = (chip_version >> 12) & 0xffff; 1584 1585 switch (chip_version) { 1586 case 0x2420: 1587 chipname = "PCnet/PCI 79C970"; /* PCI */ 1588 break; 1589 case 0x2430: 1590 if (shared) 1591 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ 1592 else 1593 chipname = "PCnet/32 79C965"; /* 486/VL bus */ 1594 break; 1595 case 0x2621: 1596 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 1597 fdx = 1; 1598 break; 1599 case 0x2623: 1600 chipname = "PCnet/FAST 79C971"; /* PCI */ 1601 fdx = 1; 1602 mii = 1; 1603 fset = 1; 1604 break; 1605 case 0x2624: 1606 chipname = "PCnet/FAST+ 79C972"; /* PCI */ 1607 fdx = 1; 1608 mii = 1; 1609 fset = 1; 1610 break; 1611 case 0x2625: 1612 chipname = "PCnet/FAST III 79C973"; /* PCI */ 1613 fdx = 1; 1614 mii = 1; 1615 break; 1616 case 0x2626: 1617 chipname = "PCnet/Home 79C978"; /* PCI */ 1618 fdx = 1; 1619 /* 1620 * This is based on specs published at www.amd.com. This section 1621 * assumes that a card with a 79C978 wants to go into standard 1622 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, 1623 * and the module option homepna=1 can select this instead. 1624 */ 1625 media = a->read_bcr(ioaddr, 49); 1626 media &= ~3; /* default to 10Mb ethernet */ 1627 if (cards_found < MAX_UNITS && homepna[cards_found]) 1628 media |= 1; /* switch to home wiring mode */ 1629 if (pcnet32_debug & NETIF_MSG_PROBE) 1630 printk(KERN_DEBUG PFX "media set to %sMbit mode\n", 1631 (media & 1) ? "1" : "10"); 1632 a->write_bcr(ioaddr, 49, media); 1633 break; 1634 case 0x2627: 1635 chipname = "PCnet/FAST III 79C975"; /* PCI */ 1636 fdx = 1; 1637 mii = 1; 1638 break; 1639 case 0x2628: 1640 chipname = "PCnet/PRO 79C976"; 1641 fdx = 1; 1642 mii = 1; 1643 break; 1644 default: 1645 if (pcnet32_debug & NETIF_MSG_PROBE) 1646 pr_info("PCnet version %#x, no PCnet32 chip\n", 1647 chip_version); 1648 goto err_release_region; 1649 } 1650 1651 /* 1652 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit 1653 * starting until the packet is loaded. Strike one for reliability, lose 1654 * one for latency - although on PCI this isnt a big loss. Older chips 1655 * have FIFO's smaller than a packet, so you can't do this. 1656 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. 1657 */ 1658 1659 if (fset) { 1660 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); 1661 a->write_csr(ioaddr, 80, 1662 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); 1663 dxsuflo = 1; 1664 } 1665 1666 dev = alloc_etherdev(sizeof(*lp)); 1667 if (!dev) { 1668 if (pcnet32_debug & NETIF_MSG_PROBE) 1669 pr_err("Memory allocation failed\n"); 1670 ret = -ENOMEM; 1671 goto err_release_region; 1672 } 1673 1674 if (pdev) 1675 SET_NETDEV_DEV(dev, &pdev->dev); 1676 1677 if (pcnet32_debug & NETIF_MSG_PROBE) 1678 pr_info("%s at %#3lx,", chipname, ioaddr); 1679 1680 /* In most chips, after a chip reset, the ethernet address is read from the 1681 * station address PROM at the base address and programmed into the 1682 * "Physical Address Registers" CSR12-14. 1683 * As a precautionary measure, we read the PROM values and complain if 1684 * they disagree with the CSRs. If they miscompare, and the PROM addr 1685 * is valid, then the PROM addr is used. 1686 */ 1687 for (i = 0; i < 3; i++) { 1688 unsigned int val; 1689 val = a->read_csr(ioaddr, i + 12) & 0x0ffff; 1690 /* There may be endianness issues here. */ 1691 dev->dev_addr[2 * i] = val & 0x0ff; 1692 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; 1693 } 1694 1695 /* read PROM address and compare with CSR address */ 1696 for (i = 0; i < 6; i++) 1697 promaddr[i] = inb(ioaddr + i); 1698 1699 if (memcmp(promaddr, dev->dev_addr, 6) || 1700 !is_valid_ether_addr(dev->dev_addr)) { 1701 if (is_valid_ether_addr(promaddr)) { 1702 if (pcnet32_debug & NETIF_MSG_PROBE) { 1703 pr_cont(" warning: CSR address invalid,\n"); 1704 pr_info(" using instead PROM address of"); 1705 } 1706 memcpy(dev->dev_addr, promaddr, 6); 1707 } 1708 } 1709 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 1710 1711 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ 1712 if (!is_valid_ether_addr(dev->perm_addr)) 1713 memset(dev->dev_addr, 0, ETH_ALEN); 1714 1715 if (pcnet32_debug & NETIF_MSG_PROBE) { 1716 pr_cont(" %pM", dev->dev_addr); 1717 1718 /* Version 0x2623 and 0x2624 */ 1719 if (((chip_version + 1) & 0xfffe) == 0x2624) { 1720 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ 1721 pr_info(" tx_start_pt(0x%04x):", i); 1722 switch (i >> 10) { 1723 case 0: 1724 pr_cont(" 20 bytes,"); 1725 break; 1726 case 1: 1727 pr_cont(" 64 bytes,"); 1728 break; 1729 case 2: 1730 pr_cont(" 128 bytes,"); 1731 break; 1732 case 3: 1733 pr_cont("~220 bytes,"); 1734 break; 1735 } 1736 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ 1737 pr_cont(" BCR18(%x):", i & 0xffff); 1738 if (i & (1 << 5)) 1739 pr_cont("BurstWrEn "); 1740 if (i & (1 << 6)) 1741 pr_cont("BurstRdEn "); 1742 if (i & (1 << 7)) 1743 pr_cont("DWordIO "); 1744 if (i & (1 << 11)) 1745 pr_cont("NoUFlow "); 1746 i = a->read_bcr(ioaddr, 25); 1747 pr_info(" SRAMSIZE=0x%04x,", i << 8); 1748 i = a->read_bcr(ioaddr, 26); 1749 pr_cont(" SRAM_BND=0x%04x,", i << 8); 1750 i = a->read_bcr(ioaddr, 27); 1751 if (i & (1 << 14)) 1752 pr_cont("LowLatRx"); 1753 } 1754 } 1755 1756 dev->base_addr = ioaddr; 1757 lp = netdev_priv(dev); 1758 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ 1759 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block), 1760 &lp->init_dma_addr); 1761 if (!lp->init_block) { 1762 if (pcnet32_debug & NETIF_MSG_PROBE) 1763 pr_err("Consistent memory allocation failed\n"); 1764 ret = -ENOMEM; 1765 goto err_free_netdev; 1766 } 1767 lp->pci_dev = pdev; 1768 1769 lp->dev = dev; 1770 1771 spin_lock_init(&lp->lock); 1772 1773 lp->name = chipname; 1774 lp->shared_irq = shared; 1775 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ 1776 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ 1777 lp->tx_mod_mask = lp->tx_ring_size - 1; 1778 lp->rx_mod_mask = lp->rx_ring_size - 1; 1779 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); 1780 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); 1781 lp->mii_if.full_duplex = fdx; 1782 lp->mii_if.phy_id_mask = 0x1f; 1783 lp->mii_if.reg_num_mask = 0x1f; 1784 lp->dxsuflo = dxsuflo; 1785 lp->mii = mii; 1786 lp->chip_version = chip_version; 1787 lp->msg_enable = pcnet32_debug; 1788 if ((cards_found >= MAX_UNITS) || 1789 (options[cards_found] >= sizeof(options_mapping))) 1790 lp->options = PCNET32_PORT_ASEL; 1791 else 1792 lp->options = options_mapping[options[cards_found]]; 1793 lp->mii_if.dev = dev; 1794 lp->mii_if.mdio_read = mdio_read; 1795 lp->mii_if.mdio_write = mdio_write; 1796 1797 /* napi.weight is used in both the napi and non-napi cases */ 1798 lp->napi.weight = lp->rx_ring_size / 2; 1799 1800 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2); 1801 1802 if (fdx && !(lp->options & PCNET32_PORT_ASEL) && 1803 ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) 1804 lp->options |= PCNET32_PORT_FD; 1805 1806 lp->a = *a; 1807 1808 /* prior to register_netdev, dev->name is not yet correct */ 1809 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { 1810 ret = -ENOMEM; 1811 goto err_free_ring; 1812 } 1813 /* detect special T1/E1 WAN card by checking for MAC address */ 1814 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && 1815 dev->dev_addr[2] == 0x75) 1816 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; 1817 1818 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */ 1819 lp->init_block->tlen_rlen = 1820 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 1821 for (i = 0; i < 6; i++) 1822 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 1823 lp->init_block->filter[0] = 0x00000000; 1824 lp->init_block->filter[1] = 0x00000000; 1825 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 1826 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 1827 1828 /* switch pcnet32 to 32bit mode */ 1829 a->write_bcr(ioaddr, 20, 2); 1830 1831 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 1832 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 1833 1834 if (pdev) { /* use the IRQ provided by PCI */ 1835 dev->irq = pdev->irq; 1836 if (pcnet32_debug & NETIF_MSG_PROBE) 1837 pr_cont(" assigned IRQ %d\n", dev->irq); 1838 } else { 1839 unsigned long irq_mask = probe_irq_on(); 1840 1841 /* 1842 * To auto-IRQ we enable the initialization-done and DMA error 1843 * interrupts. For ISA boards we get a DMA error, but VLB and PCI 1844 * boards will work. 1845 */ 1846 /* Trigger an initialization just for the interrupt. */ 1847 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); 1848 mdelay(1); 1849 1850 dev->irq = probe_irq_off(irq_mask); 1851 if (!dev->irq) { 1852 if (pcnet32_debug & NETIF_MSG_PROBE) 1853 pr_cont(", failed to detect IRQ line\n"); 1854 ret = -ENODEV; 1855 goto err_free_ring; 1856 } 1857 if (pcnet32_debug & NETIF_MSG_PROBE) 1858 pr_cont(", probed IRQ %d\n", dev->irq); 1859 } 1860 1861 /* Set the mii phy_id so that we can query the link state */ 1862 if (lp->mii) { 1863 /* lp->phycount and lp->phymask are set to 0 by memset above */ 1864 1865 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f; 1866 /* scan for PHYs */ 1867 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 1868 unsigned short id1, id2; 1869 1870 id1 = mdio_read(dev, i, MII_PHYSID1); 1871 if (id1 == 0xffff) 1872 continue; 1873 id2 = mdio_read(dev, i, MII_PHYSID2); 1874 if (id2 == 0xffff) 1875 continue; 1876 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) 1877 continue; /* 79C971 & 79C972 have phantom phy at id 31 */ 1878 lp->phycount++; 1879 lp->phymask |= (1 << i); 1880 lp->mii_if.phy_id = i; 1881 if (pcnet32_debug & NETIF_MSG_PROBE) 1882 pr_info("Found PHY %04x:%04x at address %d\n", 1883 id1, id2, i); 1884 } 1885 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); 1886 if (lp->phycount > 1) 1887 lp->options |= PCNET32_PORT_MII; 1888 } 1889 1890 init_timer(&lp->watchdog_timer); 1891 lp->watchdog_timer.data = (unsigned long)dev; 1892 lp->watchdog_timer.function = (void *)&pcnet32_watchdog; 1893 1894 /* The PCNET32-specific entries in the device structure. */ 1895 dev->netdev_ops = &pcnet32_netdev_ops; 1896 dev->ethtool_ops = &pcnet32_ethtool_ops; 1897 dev->watchdog_timeo = (5 * HZ); 1898 1899 /* Fill in the generic fields of the device structure. */ 1900 if (register_netdev(dev)) 1901 goto err_free_ring; 1902 1903 if (pdev) { 1904 pci_set_drvdata(pdev, dev); 1905 } else { 1906 lp->next = pcnet32_dev; 1907 pcnet32_dev = dev; 1908 } 1909 1910 if (pcnet32_debug & NETIF_MSG_PROBE) 1911 pr_info("%s: registered as %s\n", dev->name, lp->name); 1912 cards_found++; 1913 1914 /* enable LED writes */ 1915 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); 1916 1917 return 0; 1918 1919err_free_ring: 1920 pcnet32_free_ring(dev); 1921 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 1922 lp->init_block, lp->init_dma_addr); 1923err_free_netdev: 1924 free_netdev(dev); 1925err_release_region: 1926 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1927 return ret; 1928} 1929 1930/* if any allocation fails, caller must also call pcnet32_free_ring */ 1931static int pcnet32_alloc_ring(struct net_device *dev, const char *name) 1932{ 1933 struct pcnet32_private *lp = netdev_priv(dev); 1934 1935 lp->tx_ring = pci_alloc_consistent(lp->pci_dev, 1936 sizeof(struct pcnet32_tx_head) * 1937 lp->tx_ring_size, 1938 &lp->tx_ring_dma_addr); 1939 if (lp->tx_ring == NULL) { 1940 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 1941 return -ENOMEM; 1942 } 1943 1944 lp->rx_ring = pci_alloc_consistent(lp->pci_dev, 1945 sizeof(struct pcnet32_rx_head) * 1946 lp->rx_ring_size, 1947 &lp->rx_ring_dma_addr); 1948 if (lp->rx_ring == NULL) { 1949 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 1950 return -ENOMEM; 1951 } 1952 1953 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t), 1954 GFP_ATOMIC); 1955 if (!lp->tx_dma_addr) { 1956 netif_err(lp, drv, dev, "Memory allocation failed\n"); 1957 return -ENOMEM; 1958 } 1959 1960 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t), 1961 GFP_ATOMIC); 1962 if (!lp->rx_dma_addr) { 1963 netif_err(lp, drv, dev, "Memory allocation failed\n"); 1964 return -ENOMEM; 1965 } 1966 1967 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *), 1968 GFP_ATOMIC); 1969 if (!lp->tx_skbuff) { 1970 netif_err(lp, drv, dev, "Memory allocation failed\n"); 1971 return -ENOMEM; 1972 } 1973 1974 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *), 1975 GFP_ATOMIC); 1976 if (!lp->rx_skbuff) { 1977 netif_err(lp, drv, dev, "Memory allocation failed\n"); 1978 return -ENOMEM; 1979 } 1980 1981 return 0; 1982} 1983 1984static void pcnet32_free_ring(struct net_device *dev) 1985{ 1986 struct pcnet32_private *lp = netdev_priv(dev); 1987 1988 kfree(lp->tx_skbuff); 1989 lp->tx_skbuff = NULL; 1990 1991 kfree(lp->rx_skbuff); 1992 lp->rx_skbuff = NULL; 1993 1994 kfree(lp->tx_dma_addr); 1995 lp->tx_dma_addr = NULL; 1996 1997 kfree(lp->rx_dma_addr); 1998 lp->rx_dma_addr = NULL; 1999 2000 if (lp->tx_ring) { 2001 pci_free_consistent(lp->pci_dev, 2002 sizeof(struct pcnet32_tx_head) * 2003 lp->tx_ring_size, lp->tx_ring, 2004 lp->tx_ring_dma_addr); 2005 lp->tx_ring = NULL; 2006 } 2007 2008 if (lp->rx_ring) { 2009 pci_free_consistent(lp->pci_dev, 2010 sizeof(struct pcnet32_rx_head) * 2011 lp->rx_ring_size, lp->rx_ring, 2012 lp->rx_ring_dma_addr); 2013 lp->rx_ring = NULL; 2014 } 2015} 2016 2017static int pcnet32_open(struct net_device *dev) 2018{ 2019 struct pcnet32_private *lp = netdev_priv(dev); 2020 struct pci_dev *pdev = lp->pci_dev; 2021 unsigned long ioaddr = dev->base_addr; 2022 u16 val; 2023 int i; 2024 int rc; 2025 unsigned long flags; 2026 2027 if (request_irq(dev->irq, pcnet32_interrupt, 2028 lp->shared_irq ? IRQF_SHARED : 0, dev->name, 2029 (void *)dev)) { 2030 return -EAGAIN; 2031 } 2032 2033 spin_lock_irqsave(&lp->lock, flags); 2034 /* Check for a valid station address */ 2035 if (!is_valid_ether_addr(dev->dev_addr)) { 2036 rc = -EINVAL; 2037 goto err_free_irq; 2038 } 2039 2040 /* Reset the PCNET32 */ 2041 lp->a.reset(ioaddr); 2042 2043 /* switch pcnet32 to 32bit mode */ 2044 lp->a.write_bcr(ioaddr, 20, 2); 2045 2046 netif_printk(lp, ifup, KERN_DEBUG, dev, 2047 "%s() irq %d tx/rx rings %#x/%#x init %#x\n", 2048 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr), 2049 (u32) (lp->rx_ring_dma_addr), 2050 (u32) (lp->init_dma_addr)); 2051 2052 /* set/reset autoselect bit */ 2053 val = lp->a.read_bcr(ioaddr, 2) & ~2; 2054 if (lp->options & PCNET32_PORT_ASEL) 2055 val |= 2; 2056 lp->a.write_bcr(ioaddr, 2, val); 2057 2058 /* handle full duplex setting */ 2059 if (lp->mii_if.full_duplex) { 2060 val = lp->a.read_bcr(ioaddr, 9) & ~3; 2061 if (lp->options & PCNET32_PORT_FD) { 2062 val |= 1; 2063 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) 2064 val |= 2; 2065 } else if (lp->options & PCNET32_PORT_ASEL) { 2066 if (lp->chip_version == 0x2627) 2067 val |= 3; 2068 } 2069 lp->a.write_bcr(ioaddr, 9, val); 2070 } 2071 2072 /* set/reset GPSI bit in test register */ 2073 val = lp->a.read_csr(ioaddr, 124) & ~0x10; 2074 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) 2075 val |= 0x10; 2076 lp->a.write_csr(ioaddr, 124, val); 2077 2078 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ 2079 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT && 2080 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || 2081 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { 2082 if (lp->options & PCNET32_PORT_ASEL) { 2083 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; 2084 netif_printk(lp, link, KERN_DEBUG, dev, 2085 "Setting 100Mb-Full Duplex\n"); 2086 } 2087 } 2088 if (lp->phycount < 2) { 2089 /* 2090 * 24 Jun 2004 according AMD, in order to change the PHY, 2091 * DANAS (or DISPM for 79C976) must be set; then select the speed, 2092 * duplex, and/or enable auto negotiation, and clear DANAS 2093 */ 2094 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { 2095 lp->a.write_bcr(ioaddr, 32, 2096 lp->a.read_bcr(ioaddr, 32) | 0x0080); 2097 /* disable Auto Negotiation, set 10Mpbs, HD */ 2098 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8; 2099 if (lp->options & PCNET32_PORT_FD) 2100 val |= 0x10; 2101 if (lp->options & PCNET32_PORT_100) 2102 val |= 0x08; 2103 lp->a.write_bcr(ioaddr, 32, val); 2104 } else { 2105 if (lp->options & PCNET32_PORT_ASEL) { 2106 lp->a.write_bcr(ioaddr, 32, 2107 lp->a.read_bcr(ioaddr, 2108 32) | 0x0080); 2109 /* enable auto negotiate, setup, disable fd */ 2110 val = lp->a.read_bcr(ioaddr, 32) & ~0x98; 2111 val |= 0x20; 2112 lp->a.write_bcr(ioaddr, 32, val); 2113 } 2114 } 2115 } else { 2116 int first_phy = -1; 2117 u16 bmcr; 2118 u32 bcr9; 2119 struct ethtool_cmd ecmd; 2120 2121 /* 2122 * There is really no good other way to handle multiple PHYs 2123 * other than turning off all automatics 2124 */ 2125 val = lp->a.read_bcr(ioaddr, 2); 2126 lp->a.write_bcr(ioaddr, 2, val & ~2); 2127 val = lp->a.read_bcr(ioaddr, 32); 2128 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ 2129 2130 if (!(lp->options & PCNET32_PORT_ASEL)) { 2131 /* setup ecmd */ 2132 ecmd.port = PORT_MII; 2133 ecmd.transceiver = XCVR_INTERNAL; 2134 ecmd.autoneg = AUTONEG_DISABLE; 2135 ecmd.speed = 2136 lp-> 2137 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10; 2138 bcr9 = lp->a.read_bcr(ioaddr, 9); 2139 2140 if (lp->options & PCNET32_PORT_FD) { 2141 ecmd.duplex = DUPLEX_FULL; 2142 bcr9 |= (1 << 0); 2143 } else { 2144 ecmd.duplex = DUPLEX_HALF; 2145 bcr9 |= ~(1 << 0); 2146 } 2147 lp->a.write_bcr(ioaddr, 9, bcr9); 2148 } 2149 2150 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2151 if (lp->phymask & (1 << i)) { 2152 /* isolate all but the first PHY */ 2153 bmcr = mdio_read(dev, i, MII_BMCR); 2154 if (first_phy == -1) { 2155 first_phy = i; 2156 mdio_write(dev, i, MII_BMCR, 2157 bmcr & ~BMCR_ISOLATE); 2158 } else { 2159 mdio_write(dev, i, MII_BMCR, 2160 bmcr | BMCR_ISOLATE); 2161 } 2162 /* use mii_ethtool_sset to setup PHY */ 2163 lp->mii_if.phy_id = i; 2164 ecmd.phy_address = i; 2165 if (lp->options & PCNET32_PORT_ASEL) { 2166 mii_ethtool_gset(&lp->mii_if, &ecmd); 2167 ecmd.autoneg = AUTONEG_ENABLE; 2168 } 2169 mii_ethtool_sset(&lp->mii_if, &ecmd); 2170 } 2171 } 2172 lp->mii_if.phy_id = first_phy; 2173 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy); 2174 } 2175 2176#ifdef DO_DXSUFLO 2177 if (lp->dxsuflo) { /* Disable transmit stop on underflow */ 2178 val = lp->a.read_csr(ioaddr, CSR3); 2179 val |= 0x40; 2180 lp->a.write_csr(ioaddr, CSR3, val); 2181 } 2182#endif 2183 2184 lp->init_block->mode = 2185 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2186 pcnet32_load_multicast(dev); 2187 2188 if (pcnet32_init_ring(dev)) { 2189 rc = -ENOMEM; 2190 goto err_free_ring; 2191 } 2192 2193 napi_enable(&lp->napi); 2194 2195 /* Re-initialize the PCNET32, and start it when done. */ 2196 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 2197 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 2198 2199 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 2200 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT); 2201 2202 netif_start_queue(dev); 2203 2204 if (lp->chip_version >= PCNET32_79C970A) { 2205 /* Print the link status and start the watchdog */ 2206 pcnet32_check_media(dev, 1); 2207 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT); 2208 } 2209 2210 i = 0; 2211 while (i++ < 100) 2212 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON) 2213 break; 2214 /* 2215 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton 2216 * reports that doing so triggers a bug in the '974. 2217 */ 2218 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL); 2219 2220 netif_printk(lp, ifup, KERN_DEBUG, dev, 2221 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", 2222 i, 2223 (u32) (lp->init_dma_addr), 2224 lp->a.read_csr(ioaddr, CSR0)); 2225 2226 spin_unlock_irqrestore(&lp->lock, flags); 2227 2228 return 0; /* Always succeed */ 2229 2230err_free_ring: 2231 /* free any allocated skbuffs */ 2232 pcnet32_purge_rx_ring(dev); 2233 2234 /* 2235 * Switch back to 16bit mode to avoid problems with dumb 2236 * DOS packet driver after a warm reboot 2237 */ 2238 lp->a.write_bcr(ioaddr, 20, 4); 2239 2240err_free_irq: 2241 spin_unlock_irqrestore(&lp->lock, flags); 2242 free_irq(dev->irq, dev); 2243 return rc; 2244} 2245 2246/* 2247 * The LANCE has been halted for one reason or another (busmaster memory 2248 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, 2249 * etc.). Modern LANCE variants always reload their ring-buffer 2250 * configuration when restarted, so we must reinitialize our ring 2251 * context before restarting. As part of this reinitialization, 2252 * find all packets still on the Tx ring and pretend that they had been 2253 * sent (in effect, drop the packets on the floor) - the higher-level 2254 * protocols will time out and retransmit. It'd be better to shuffle 2255 * these skbs to a temp list and then actually re-Tx them after 2256 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com 2257 */ 2258 2259static void pcnet32_purge_tx_ring(struct net_device *dev) 2260{ 2261 struct pcnet32_private *lp = netdev_priv(dev); 2262 int i; 2263 2264 for (i = 0; i < lp->tx_ring_size; i++) { 2265 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2266 wmb(); /* Make sure adapter sees owner change */ 2267 if (lp->tx_skbuff[i]) { 2268 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], 2269 lp->tx_skbuff[i]->len, 2270 PCI_DMA_TODEVICE); 2271 dev_kfree_skb_any(lp->tx_skbuff[i]); 2272 } 2273 lp->tx_skbuff[i] = NULL; 2274 lp->tx_dma_addr[i] = 0; 2275 } 2276} 2277 2278/* Initialize the PCNET32 Rx and Tx rings. */ 2279static int pcnet32_init_ring(struct net_device *dev) 2280{ 2281 struct pcnet32_private *lp = netdev_priv(dev); 2282 int i; 2283 2284 lp->tx_full = 0; 2285 lp->cur_rx = lp->cur_tx = 0; 2286 lp->dirty_rx = lp->dirty_tx = 0; 2287 2288 for (i = 0; i < lp->rx_ring_size; i++) { 2289 struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; 2290 if (rx_skbuff == NULL) { 2291 lp->rx_skbuff[i] = dev_alloc_skb(PKT_BUF_SKB); 2292 rx_skbuff = lp->rx_skbuff[i]; 2293 if (!rx_skbuff) { 2294 /* there is not much we can do at this point */ 2295 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n", 2296 __func__); 2297 return -1; 2298 } 2299 skb_reserve(rx_skbuff, NET_IP_ALIGN); 2300 } 2301 2302 rmb(); 2303 if (lp->rx_dma_addr[i] == 0) 2304 lp->rx_dma_addr[i] = 2305 pci_map_single(lp->pci_dev, rx_skbuff->data, 2306 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 2307 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); 2308 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE); 2309 wmb(); /* Make sure owner changes after all others are visible */ 2310 lp->rx_ring[i].status = cpu_to_le16(0x8000); 2311 } 2312 /* The Tx buffer address is filled in as needed, but we do need to clear 2313 * the upper ownership bit. */ 2314 for (i = 0; i < lp->tx_ring_size; i++) { 2315 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2316 wmb(); /* Make sure adapter sees owner change */ 2317 lp->tx_ring[i].base = 0; 2318 lp->tx_dma_addr[i] = 0; 2319 } 2320 2321 lp->init_block->tlen_rlen = 2322 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 2323 for (i = 0; i < 6; i++) 2324 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 2325 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 2326 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 2327 wmb(); /* Make sure all changes are visible */ 2328 return 0; 2329} 2330 2331/* the pcnet32 has been issued a stop or reset. Wait for the stop bit 2332 * then flush the pending transmit operations, re-initialize the ring, 2333 * and tell the chip to initialize. 2334 */ 2335static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) 2336{ 2337 struct pcnet32_private *lp = netdev_priv(dev); 2338 unsigned long ioaddr = dev->base_addr; 2339 int i; 2340 2341 /* wait for stop */ 2342 for (i = 0; i < 100; i++) 2343 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP) 2344 break; 2345 2346 if (i >= 100) 2347 netif_err(lp, drv, dev, "%s timed out waiting for stop\n", 2348 __func__); 2349 2350 pcnet32_purge_tx_ring(dev); 2351 if (pcnet32_init_ring(dev)) 2352 return; 2353 2354 /* ReInit Ring */ 2355 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT); 2356 i = 0; 2357 while (i++ < 1000) 2358 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON) 2359 break; 2360 2361 lp->a.write_csr(ioaddr, CSR0, csr0_bits); 2362} 2363 2364static void pcnet32_tx_timeout(struct net_device *dev) 2365{ 2366 struct pcnet32_private *lp = netdev_priv(dev); 2367 unsigned long ioaddr = dev->base_addr, flags; 2368 2369 spin_lock_irqsave(&lp->lock, flags); 2370 /* Transmitter timeout, serious problems. */ 2371 if (pcnet32_debug & NETIF_MSG_DRV) 2372 pr_err("%s: transmit timed out, status %4.4x, resetting\n", 2373 dev->name, lp->a.read_csr(ioaddr, CSR0)); 2374 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); 2375 dev->stats.tx_errors++; 2376 if (netif_msg_tx_err(lp)) { 2377 int i; 2378 printk(KERN_DEBUG 2379 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", 2380 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", 2381 lp->cur_rx); 2382 for (i = 0; i < lp->rx_ring_size; i++) 2383 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2384 le32_to_cpu(lp->rx_ring[i].base), 2385 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 2386 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), 2387 le16_to_cpu(lp->rx_ring[i].status)); 2388 for (i = 0; i < lp->tx_ring_size; i++) 2389 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2390 le32_to_cpu(lp->tx_ring[i].base), 2391 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, 2392 le32_to_cpu(lp->tx_ring[i].misc), 2393 le16_to_cpu(lp->tx_ring[i].status)); 2394 printk("\n"); 2395 } 2396 pcnet32_restart(dev, CSR0_NORMAL); 2397 2398 dev->trans_start = jiffies; /* prevent tx timeout */ 2399 netif_wake_queue(dev); 2400 2401 spin_unlock_irqrestore(&lp->lock, flags); 2402} 2403 2404static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb, 2405 struct net_device *dev) 2406{ 2407 struct pcnet32_private *lp = netdev_priv(dev); 2408 unsigned long ioaddr = dev->base_addr; 2409 u16 status; 2410 int entry; 2411 unsigned long flags; 2412 2413 spin_lock_irqsave(&lp->lock, flags); 2414 2415 netif_printk(lp, tx_queued, KERN_DEBUG, dev, 2416 "%s() called, csr0 %4.4x\n", 2417 __func__, lp->a.read_csr(ioaddr, CSR0)); 2418 2419 /* Default status -- will not enable Successful-TxDone 2420 * interrupt when that option is available to us. 2421 */ 2422 status = 0x8300; 2423 2424 /* Fill in a Tx ring entry */ 2425 2426 /* Mask to ring buffer boundary. */ 2427 entry = lp->cur_tx & lp->tx_mod_mask; 2428 2429 /* Caution: the write order is important here, set the status 2430 * with the "ownership" bits last. */ 2431 2432 lp->tx_ring[entry].length = cpu_to_le16(-skb->len); 2433 2434 lp->tx_ring[entry].misc = 0x00000000; 2435 2436 lp->tx_skbuff[entry] = skb; 2437 lp->tx_dma_addr[entry] = 2438 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 2439 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); 2440 wmb(); /* Make sure owner changes after all others are visible */ 2441 lp->tx_ring[entry].status = cpu_to_le16(status); 2442 2443 lp->cur_tx++; 2444 dev->stats.tx_bytes += skb->len; 2445 2446 /* Trigger an immediate send poll. */ 2447 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); 2448 2449 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { 2450 lp->tx_full = 1; 2451 netif_stop_queue(dev); 2452 } 2453 spin_unlock_irqrestore(&lp->lock, flags); 2454 return NETDEV_TX_OK; 2455} 2456 2457/* The PCNET32 interrupt handler. */ 2458static irqreturn_t 2459pcnet32_interrupt(int irq, void *dev_id) 2460{ 2461 struct net_device *dev = dev_id; 2462 struct pcnet32_private *lp; 2463 unsigned long ioaddr; 2464 u16 csr0; 2465 int boguscnt = max_interrupt_work; 2466 2467 ioaddr = dev->base_addr; 2468 lp = netdev_priv(dev); 2469 2470 spin_lock(&lp->lock); 2471 2472 csr0 = lp->a.read_csr(ioaddr, CSR0); 2473 while ((csr0 & 0x8f00) && --boguscnt >= 0) { 2474 if (csr0 == 0xffff) 2475 break; /* PCMCIA remove happened */ 2476 /* Acknowledge all of the current interrupt sources ASAP. */ 2477 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f); 2478 2479 netif_printk(lp, intr, KERN_DEBUG, dev, 2480 "interrupt csr0=%#2.2x new csr=%#2.2x\n", 2481 csr0, lp->a.read_csr(ioaddr, CSR0)); 2482 2483 /* Log misc errors. */ 2484 if (csr0 & 0x4000) 2485 dev->stats.tx_errors++; /* Tx babble. */ 2486 if (csr0 & 0x1000) { 2487 /* 2488 * This happens when our receive ring is full. This 2489 * shouldn't be a problem as we will see normal rx 2490 * interrupts for the frames in the receive ring. But 2491 * there are some PCI chipsets (I can reproduce this 2492 * on SP3G with Intel saturn chipset) which have 2493 * sometimes problems and will fill up the receive 2494 * ring with error descriptors. In this situation we 2495 * don't get a rx interrupt, but a missed frame 2496 * interrupt sooner or later. 2497 */ 2498 dev->stats.rx_errors++; /* Missed a Rx frame. */ 2499 } 2500 if (csr0 & 0x0800) { 2501 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n", 2502 csr0); 2503 /* unlike for the lance, there is no restart needed */ 2504 } 2505 if (napi_schedule_prep(&lp->napi)) { 2506 u16 val; 2507 /* set interrupt masks */ 2508 val = lp->a.read_csr(ioaddr, CSR3); 2509 val |= 0x5f00; 2510 lp->a.write_csr(ioaddr, CSR3, val); 2511 2512 __napi_schedule(&lp->napi); 2513 break; 2514 } 2515 csr0 = lp->a.read_csr(ioaddr, CSR0); 2516 } 2517 2518 netif_printk(lp, intr, KERN_DEBUG, dev, 2519 "exiting interrupt, csr0=%#4.4x\n", 2520 lp->a.read_csr(ioaddr, CSR0)); 2521 2522 spin_unlock(&lp->lock); 2523 2524 return IRQ_HANDLED; 2525} 2526 2527static int pcnet32_close(struct net_device *dev) 2528{ 2529 unsigned long ioaddr = dev->base_addr; 2530 struct pcnet32_private *lp = netdev_priv(dev); 2531 unsigned long flags; 2532 2533 del_timer_sync(&lp->watchdog_timer); 2534 2535 netif_stop_queue(dev); 2536 napi_disable(&lp->napi); 2537 2538 spin_lock_irqsave(&lp->lock, flags); 2539 2540 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112); 2541 2542 netif_printk(lp, ifdown, KERN_DEBUG, dev, 2543 "Shutting down ethercard, status was %2.2x\n", 2544 lp->a.read_csr(ioaddr, CSR0)); 2545 2546 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ 2547 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); 2548 2549 /* 2550 * Switch back to 16bit mode to avoid problems with dumb 2551 * DOS packet driver after a warm reboot 2552 */ 2553 lp->a.write_bcr(ioaddr, 20, 4); 2554 2555 spin_unlock_irqrestore(&lp->lock, flags); 2556 2557 free_irq(dev->irq, dev); 2558 2559 spin_lock_irqsave(&lp->lock, flags); 2560 2561 pcnet32_purge_rx_ring(dev); 2562 pcnet32_purge_tx_ring(dev); 2563 2564 spin_unlock_irqrestore(&lp->lock, flags); 2565 2566 return 0; 2567} 2568 2569static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) 2570{ 2571 struct pcnet32_private *lp = netdev_priv(dev); 2572 unsigned long ioaddr = dev->base_addr; 2573 unsigned long flags; 2574 2575 spin_lock_irqsave(&lp->lock, flags); 2576 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112); 2577 spin_unlock_irqrestore(&lp->lock, flags); 2578 2579 return &dev->stats; 2580} 2581 2582/* taken from the sunlance driver, which it took from the depca driver */ 2583static void pcnet32_load_multicast(struct net_device *dev) 2584{ 2585 struct pcnet32_private *lp = netdev_priv(dev); 2586 volatile struct pcnet32_init_block *ib = lp->init_block; 2587 volatile __le16 *mcast_table = (__le16 *)ib->filter; 2588 struct netdev_hw_addr *ha; 2589 unsigned long ioaddr = dev->base_addr; 2590 char *addrs; 2591 int i; 2592 u32 crc; 2593 2594 /* set all multicast bits */ 2595 if (dev->flags & IFF_ALLMULTI) { 2596 ib->filter[0] = cpu_to_le32(~0U); 2597 ib->filter[1] = cpu_to_le32(~0U); 2598 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); 2599 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); 2600 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); 2601 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); 2602 return; 2603 } 2604 /* clear the multicast filter */ 2605 ib->filter[0] = 0; 2606 ib->filter[1] = 0; 2607 2608 /* Add addresses */ 2609 netdev_for_each_mc_addr(ha, dev) { 2610 addrs = ha->addr; 2611 2612 /* multicast address? */ 2613 if (!(*addrs & 1)) 2614 continue; 2615 2616 crc = ether_crc_le(6, addrs); 2617 crc = crc >> 26; 2618 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf)); 2619 } 2620 for (i = 0; i < 4; i++) 2621 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i, 2622 le16_to_cpu(mcast_table[i])); 2623} 2624 2625/* 2626 * Set or clear the multicast filter for this adaptor. 2627 */ 2628static void pcnet32_set_multicast_list(struct net_device *dev) 2629{ 2630 unsigned long ioaddr = dev->base_addr, flags; 2631 struct pcnet32_private *lp = netdev_priv(dev); 2632 int csr15, suspended; 2633 2634 spin_lock_irqsave(&lp->lock, flags); 2635 suspended = pcnet32_suspend(dev, &flags, 0); 2636 csr15 = lp->a.read_csr(ioaddr, CSR15); 2637 if (dev->flags & IFF_PROMISC) { 2638 /* Log any net taps. */ 2639 netif_info(lp, hw, dev, "Promiscuous mode enabled\n"); 2640 lp->init_block->mode = 2641 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 2642 7); 2643 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000); 2644 } else { 2645 lp->init_block->mode = 2646 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2647 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff); 2648 pcnet32_load_multicast(dev); 2649 } 2650 2651 if (suspended) { 2652 int csr5; 2653 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 2654 csr5 = lp->a.read_csr(ioaddr, CSR5); 2655 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 2656 } else { 2657 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); 2658 pcnet32_restart(dev, CSR0_NORMAL); 2659 netif_wake_queue(dev); 2660 } 2661 2662 spin_unlock_irqrestore(&lp->lock, flags); 2663} 2664 2665/* This routine assumes that the lp->lock is held */ 2666static int mdio_read(struct net_device *dev, int phy_id, int reg_num) 2667{ 2668 struct pcnet32_private *lp = netdev_priv(dev); 2669 unsigned long ioaddr = dev->base_addr; 2670 u16 val_out; 2671 2672 if (!lp->mii) 2673 return 0; 2674 2675 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2676 val_out = lp->a.read_bcr(ioaddr, 34); 2677 2678 return val_out; 2679} 2680 2681/* This routine assumes that the lp->lock is held */ 2682static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) 2683{ 2684 struct pcnet32_private *lp = netdev_priv(dev); 2685 unsigned long ioaddr = dev->base_addr; 2686 2687 if (!lp->mii) 2688 return; 2689 2690 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2691 lp->a.write_bcr(ioaddr, 34, val); 2692} 2693 2694static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2695{ 2696 struct pcnet32_private *lp = netdev_priv(dev); 2697 int rc; 2698 unsigned long flags; 2699 2700 /* SIOC[GS]MIIxxx ioctls */ 2701 if (lp->mii) { 2702 spin_lock_irqsave(&lp->lock, flags); 2703 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); 2704 spin_unlock_irqrestore(&lp->lock, flags); 2705 } else { 2706 rc = -EOPNOTSUPP; 2707 } 2708 2709 return rc; 2710} 2711 2712static int pcnet32_check_otherphy(struct net_device *dev) 2713{ 2714 struct pcnet32_private *lp = netdev_priv(dev); 2715 struct mii_if_info mii = lp->mii_if; 2716 u16 bmcr; 2717 int i; 2718 2719 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2720 if (i == lp->mii_if.phy_id) 2721 continue; /* skip active phy */ 2722 if (lp->phymask & (1 << i)) { 2723 mii.phy_id = i; 2724 if (mii_link_ok(&mii)) { 2725 /* found PHY with active link */ 2726 netif_info(lp, link, dev, "Using PHY number %d\n", 2727 i); 2728 2729 /* isolate inactive phy */ 2730 bmcr = 2731 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); 2732 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, 2733 bmcr | BMCR_ISOLATE); 2734 2735 /* de-isolate new phy */ 2736 bmcr = mdio_read(dev, i, MII_BMCR); 2737 mdio_write(dev, i, MII_BMCR, 2738 bmcr & ~BMCR_ISOLATE); 2739 2740 /* set new phy address */ 2741 lp->mii_if.phy_id = i; 2742 return 1; 2743 } 2744 } 2745 } 2746 return 0; 2747} 2748 2749/* 2750 * Show the status of the media. Similar to mii_check_media however it 2751 * correctly shows the link speed for all (tested) pcnet32 variants. 2752 * Devices with no mii just report link state without speed. 2753 * 2754 * Caller is assumed to hold and release the lp->lock. 2755 */ 2756 2757static void pcnet32_check_media(struct net_device *dev, int verbose) 2758{ 2759 struct pcnet32_private *lp = netdev_priv(dev); 2760 int curr_link; 2761 int prev_link = netif_carrier_ok(dev) ? 1 : 0; 2762 u32 bcr9; 2763 2764 if (lp->mii) { 2765 curr_link = mii_link_ok(&lp->mii_if); 2766 } else { 2767 ulong ioaddr = dev->base_addr; /* card base I/O address */ 2768 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0); 2769 } 2770 if (!curr_link) { 2771 if (prev_link || verbose) { 2772 netif_carrier_off(dev); 2773 netif_info(lp, link, dev, "link down\n"); 2774 } 2775 if (lp->phycount > 1) { 2776 curr_link = pcnet32_check_otherphy(dev); 2777 prev_link = 0; 2778 } 2779 } else if (verbose || !prev_link) { 2780 netif_carrier_on(dev); 2781 if (lp->mii) { 2782 if (netif_msg_link(lp)) { 2783 struct ethtool_cmd ecmd; 2784 mii_ethtool_gset(&lp->mii_if, &ecmd); 2785 netdev_info(dev, "link up, %sMbps, %s-duplex\n", 2786 (ecmd.speed == SPEED_100) 2787 ? "100" : "10", 2788 (ecmd.duplex == DUPLEX_FULL) 2789 ? "full" : "half"); 2790 } 2791 bcr9 = lp->a.read_bcr(dev->base_addr, 9); 2792 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { 2793 if (lp->mii_if.full_duplex) 2794 bcr9 |= (1 << 0); 2795 else 2796 bcr9 &= ~(1 << 0); 2797 lp->a.write_bcr(dev->base_addr, 9, bcr9); 2798 } 2799 } else { 2800 netif_info(lp, link, dev, "link up\n"); 2801 } 2802 } 2803} 2804 2805/* 2806 * Check for loss of link and link establishment. 2807 * Can not use mii_check_media because it does nothing if mode is forced. 2808 */ 2809 2810static void pcnet32_watchdog(struct net_device *dev) 2811{ 2812 struct pcnet32_private *lp = netdev_priv(dev); 2813 unsigned long flags; 2814 2815 /* Print the link status if it has changed */ 2816 spin_lock_irqsave(&lp->lock, flags); 2817 pcnet32_check_media(dev, 0); 2818 spin_unlock_irqrestore(&lp->lock, flags); 2819 2820 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT)); 2821} 2822 2823static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state) 2824{ 2825 struct net_device *dev = pci_get_drvdata(pdev); 2826 2827 if (netif_running(dev)) { 2828 netif_device_detach(dev); 2829 pcnet32_close(dev); 2830 } 2831 pci_save_state(pdev); 2832 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 2833 return 0; 2834} 2835 2836static int pcnet32_pm_resume(struct pci_dev *pdev) 2837{ 2838 struct net_device *dev = pci_get_drvdata(pdev); 2839 2840 pci_set_power_state(pdev, PCI_D0); 2841 pci_restore_state(pdev); 2842 2843 if (netif_running(dev)) { 2844 pcnet32_open(dev); 2845 netif_device_attach(dev); 2846 } 2847 return 0; 2848} 2849 2850static void __devexit pcnet32_remove_one(struct pci_dev *pdev) 2851{ 2852 struct net_device *dev = pci_get_drvdata(pdev); 2853 2854 if (dev) { 2855 struct pcnet32_private *lp = netdev_priv(dev); 2856 2857 unregister_netdev(dev); 2858 pcnet32_free_ring(dev); 2859 release_region(dev->base_addr, PCNET32_TOTAL_SIZE); 2860 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2861 lp->init_block, lp->init_dma_addr); 2862 free_netdev(dev); 2863 pci_disable_device(pdev); 2864 pci_set_drvdata(pdev, NULL); 2865 } 2866} 2867 2868static struct pci_driver pcnet32_driver = { 2869 .name = DRV_NAME, 2870 .probe = pcnet32_probe_pci, 2871 .remove = __devexit_p(pcnet32_remove_one), 2872 .id_table = pcnet32_pci_tbl, 2873 .suspend = pcnet32_pm_suspend, 2874 .resume = pcnet32_pm_resume, 2875}; 2876 2877/* An additional parameter that may be passed in... */ 2878static int debug = -1; 2879static int tx_start_pt = -1; 2880static int pcnet32_have_pci; 2881 2882module_param(debug, int, 0); 2883MODULE_PARM_DESC(debug, DRV_NAME " debug level"); 2884module_param(max_interrupt_work, int, 0); 2885MODULE_PARM_DESC(max_interrupt_work, 2886 DRV_NAME " maximum events handled per interrupt"); 2887module_param(rx_copybreak, int, 0); 2888MODULE_PARM_DESC(rx_copybreak, 2889 DRV_NAME " copy breakpoint for copy-only-tiny-frames"); 2890module_param(tx_start_pt, int, 0); 2891MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); 2892module_param(pcnet32vlb, int, 0); 2893MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); 2894module_param_array(options, int, NULL, 0); 2895MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); 2896module_param_array(full_duplex, int, NULL, 0); 2897MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); 2898/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ 2899module_param_array(homepna, int, NULL, 0); 2900MODULE_PARM_DESC(homepna, 2901 DRV_NAME 2902 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); 2903 2904MODULE_AUTHOR("Thomas Bogendoerfer"); 2905MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); 2906MODULE_LICENSE("GPL"); 2907 2908#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 2909 2910static int __init pcnet32_init_module(void) 2911{ 2912 pr_info("%s", version); 2913 2914 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); 2915 2916 if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) 2917 tx_start = tx_start_pt; 2918 2919 /* find the PCI devices */ 2920 if (!pci_register_driver(&pcnet32_driver)) 2921 pcnet32_have_pci = 1; 2922 2923 /* should we find any remaining VLbus devices ? */ 2924 if (pcnet32vlb) 2925 pcnet32_probe_vlbus(pcnet32_portlist); 2926 2927 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) 2928 pr_info("%d cards_found\n", cards_found); 2929 2930 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; 2931} 2932 2933static void __exit pcnet32_cleanup_module(void) 2934{ 2935 struct net_device *next_dev; 2936 2937 while (pcnet32_dev) { 2938 struct pcnet32_private *lp = netdev_priv(pcnet32_dev); 2939 next_dev = lp->next; 2940 unregister_netdev(pcnet32_dev); 2941 pcnet32_free_ring(pcnet32_dev); 2942 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); 2943 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2944 lp->init_block, lp->init_dma_addr); 2945 free_netdev(pcnet32_dev); 2946 pcnet32_dev = next_dev; 2947 } 2948 2949 if (pcnet32_have_pci) 2950 pci_unregister_driver(&pcnet32_driver); 2951} 2952 2953module_init(pcnet32_init_module); 2954module_exit(pcnet32_cleanup_module); 2955 2956/* 2957 * Local variables: 2958 * c-indent-level: 4 2959 * tab-width: 8 2960 * End: 2961 */ 2962