1/* ---------------------------------------------------------------------------- 2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN. 3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao 4 5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media 6 Access Controller for Ethernet (MACE). It is essentially the Am2150 7 PCMCIA Ethernet card contained in the Am2150 Demo Kit. 8 9Written by Roger C. Pao <rpao@paonet.org> 10 Copyright 1995 Roger C. Pao 11 Linux 2.5 cleanups Copyright Red Hat 2003 12 13 This software may be used and distributed according to the terms of 14 the GNU General Public License. 15 16Ported to Linux 1.3.* network driver environment by 17 Matti Aarnio <mea@utu.fi> 18 19References 20 21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993 22 Am79C940 (MACE) Data Sheet, 1994 23 Am79C90 (C-LANCE) Data Sheet, 1994 24 Linux PCMCIA Programmer's Guide v1.17 25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8 26 27 Eric Mears, New Media Corporation 28 Tom Pollard, New Media Corporation 29 Dean Siasoyco, New Media Corporation 30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com> 31 Donald Becker <becker@scyld.com> 32 David Hinds <dahinds@users.sourceforge.net> 33 34 The Linux client driver is based on the 3c589_cs.c client driver by 35 David Hinds. 36 37 The Linux network driver outline is based on the 3c589_cs.c driver, 38 the 8390.c driver, and the example skeleton.c kernel code, which are 39 by Donald Becker. 40 41 The Am2150 network driver hardware interface code is based on the 42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears. 43 44 Special thanks for testing and help in debugging this driver goes 45 to Ken Lesniak. 46 47------------------------------------------------------------------------------- 48Driver Notes and Issues 49------------------------------------------------------------------------------- 50 511. Developed on a Dell 320SLi 52 PCMCIA Card Services 2.6.2 53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386 54 552. rc.pcmcia may require loading pcmcia_core with io_speed=300: 56 'insmod pcmcia_core.o io_speed=300'. 57 This will avoid problems with fast systems which causes rx_framecnt 58 to return random values. 59 603. If hot extraction does not work for you, use 'ifconfig eth0 down' 61 before extraction. 62 634. There is a bad slow-down problem in this driver. 64 655. Future: Multicast processing. In the meantime, do _not_ compile your 66 kernel with multicast ip enabled. 67 68------------------------------------------------------------------------------- 69History 70------------------------------------------------------------------------------- 71Log: nmclan_cs.c,v 72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk> 73 * Fixed hang on card eject as we probe it 74 * Cleaned up to use new style locking. 75 * 76 * Revision 0.16 1995/07/01 06:42:17 rpao 77 * Bug fix: nmclan_reset() called CardServices incorrectly. 78 * 79 * Revision 0.15 1995/05/24 08:09:47 rpao 80 * Re-implement MULTI_TX dev->tbusy handling. 81 * 82 * Revision 0.14 1995/05/23 03:19:30 rpao 83 * Added, in nmclan_config(), "tuple.Attributes = 0;". 84 * Modified MACE ID check to ignore chip revision level. 85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt. 86 * 87 * Revision 0.13 1995/05/18 05:56:34 rpao 88 * Statistics changes. 89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list. 90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup. 91 * 92 * Revision 0.12 1995/05/14 00:12:23 rpao 93 * Statistics overhaul. 94 * 95 9695/05/13 rpao V0.10a 97 Bug fix: MACE statistics counters used wrong I/O ports. 98 Bug fix: mace_interrupt() needed to allow statistics to be 99 processed without RX or TX interrupts pending. 10095/05/11 rpao V0.10 101 Multiple transmit request processing. 102 Modified statistics to use MACE counters where possible. 10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO. 104 *Released 10595/05/10 rpao V0.08 106 Bug fix: Make all non-exported functions private by using 107 static keyword. 108 Bug fix: Test IntrCnt _before_ reading MACE_IR. 10995/05/10 rpao V0.07 Statistics. 11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states. 111 112---------------------------------------------------------------------------- */ 113 114#define DRV_NAME "nmclan_cs" 115#define DRV_VERSION "0.16" 116 117 118/* ---------------------------------------------------------------------------- 119Conditional Compilation Options 120---------------------------------------------------------------------------- */ 121 122#define MULTI_TX 0 123#define RESET_ON_TIMEOUT 1 124#define TX_INTERRUPTABLE 1 125#define RESET_XILINX 0 126 127/* ---------------------------------------------------------------------------- 128Include Files 129---------------------------------------------------------------------------- */ 130 131#include <linux/module.h> 132#include <linux/kernel.h> 133#include <linux/init.h> 134#include <linux/ptrace.h> 135#include <linux/slab.h> 136#include <linux/string.h> 137#include <linux/timer.h> 138#include <linux/interrupt.h> 139#include <linux/in.h> 140#include <linux/delay.h> 141#include <linux/ethtool.h> 142#include <linux/netdevice.h> 143#include <linux/etherdevice.h> 144#include <linux/skbuff.h> 145#include <linux/if_arp.h> 146#include <linux/ioport.h> 147#include <linux/bitops.h> 148 149#include <pcmcia/cs.h> 150#include <pcmcia/cisreg.h> 151#include <pcmcia/cistpl.h> 152#include <pcmcia/ds.h> 153 154#include <asm/uaccess.h> 155#include <asm/io.h> 156#include <asm/system.h> 157 158/* ---------------------------------------------------------------------------- 159Defines 160---------------------------------------------------------------------------- */ 161 162#define ETHER_ADDR_LEN ETH_ALEN 163 /* 6 bytes in an Ethernet Address */ 164#define MACE_LADRF_LEN 8 165 /* 8 bytes in Logical Address Filter */ 166 167/* Loop Control Defines */ 168#define MACE_MAX_IR_ITERATIONS 10 169#define MACE_MAX_RX_ITERATIONS 12 170 /* 171 TBD: Dean brought this up, and I assumed the hardware would 172 handle it: 173 174 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be 175 non-zero when the isr exits. We may not get another interrupt 176 to process the remaining packets for some time. 177 */ 178 179/* 180The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA) 181which manages the interface between the MACE and the PCMCIA bus. It 182also includes buffer management for the 32K x 8 SRAM to control up to 183four transmit and 12 receive frames at a time. 184*/ 185#define AM2150_MAX_TX_FRAMES 4 186#define AM2150_MAX_RX_FRAMES 12 187 188/* Am2150 Ethernet Card I/O Mapping */ 189#define AM2150_RCV 0x00 190#define AM2150_XMT 0x04 191#define AM2150_XMT_SKIP 0x09 192#define AM2150_RCV_NEXT 0x0A 193#define AM2150_RCV_FRAME_COUNT 0x0B 194#define AM2150_MACE_BANK 0x0C 195#define AM2150_MACE_BASE 0x10 196 197/* MACE Registers */ 198#define MACE_RCVFIFO 0 199#define MACE_XMTFIFO 1 200#define MACE_XMTFC 2 201#define MACE_XMTFS 3 202#define MACE_XMTRC 4 203#define MACE_RCVFC 5 204#define MACE_RCVFS 6 205#define MACE_FIFOFC 7 206#define MACE_IR 8 207#define MACE_IMR 9 208#define MACE_PR 10 209#define MACE_BIUCC 11 210#define MACE_FIFOCC 12 211#define MACE_MACCC 13 212#define MACE_PLSCC 14 213#define MACE_PHYCC 15 214#define MACE_CHIPIDL 16 215#define MACE_CHIPIDH 17 216#define MACE_IAC 18 217/* Reserved */ 218#define MACE_LADRF 20 219#define MACE_PADR 21 220/* Reserved */ 221/* Reserved */ 222#define MACE_MPC 24 223/* Reserved */ 224#define MACE_RNTPC 26 225#define MACE_RCVCC 27 226/* Reserved */ 227#define MACE_UTR 29 228#define MACE_RTR1 30 229#define MACE_RTR2 31 230 231/* MACE Bit Masks */ 232#define MACE_XMTRC_EXDEF 0x80 233#define MACE_XMTRC_XMTRC 0x0F 234 235#define MACE_XMTFS_XMTSV 0x80 236#define MACE_XMTFS_UFLO 0x40 237#define MACE_XMTFS_LCOL 0x20 238#define MACE_XMTFS_MORE 0x10 239#define MACE_XMTFS_ONE 0x08 240#define MACE_XMTFS_DEFER 0x04 241#define MACE_XMTFS_LCAR 0x02 242#define MACE_XMTFS_RTRY 0x01 243 244#define MACE_RCVFS_RCVSTS 0xF000 245#define MACE_RCVFS_OFLO 0x8000 246#define MACE_RCVFS_CLSN 0x4000 247#define MACE_RCVFS_FRAM 0x2000 248#define MACE_RCVFS_FCS 0x1000 249 250#define MACE_FIFOFC_RCVFC 0xF0 251#define MACE_FIFOFC_XMTFC 0x0F 252 253#define MACE_IR_JAB 0x80 254#define MACE_IR_BABL 0x40 255#define MACE_IR_CERR 0x20 256#define MACE_IR_RCVCCO 0x10 257#define MACE_IR_RNTPCO 0x08 258#define MACE_IR_MPCO 0x04 259#define MACE_IR_RCVINT 0x02 260#define MACE_IR_XMTINT 0x01 261 262#define MACE_MACCC_PROM 0x80 263#define MACE_MACCC_DXMT2PD 0x40 264#define MACE_MACCC_EMBA 0x20 265#define MACE_MACCC_RESERVED 0x10 266#define MACE_MACCC_DRCVPA 0x08 267#define MACE_MACCC_DRCVBC 0x04 268#define MACE_MACCC_ENXMT 0x02 269#define MACE_MACCC_ENRCV 0x01 270 271#define MACE_PHYCC_LNKFL 0x80 272#define MACE_PHYCC_DLNKTST 0x40 273#define MACE_PHYCC_REVPOL 0x20 274#define MACE_PHYCC_DAPC 0x10 275#define MACE_PHYCC_LRT 0x08 276#define MACE_PHYCC_ASEL 0x04 277#define MACE_PHYCC_RWAKE 0x02 278#define MACE_PHYCC_AWAKE 0x01 279 280#define MACE_IAC_ADDRCHG 0x80 281#define MACE_IAC_PHYADDR 0x04 282#define MACE_IAC_LOGADDR 0x02 283 284#define MACE_UTR_RTRE 0x80 285#define MACE_UTR_RTRD 0x40 286#define MACE_UTR_RPA 0x20 287#define MACE_UTR_FCOLL 0x10 288#define MACE_UTR_RCVFCSE 0x08 289#define MACE_UTR_LOOP_INCL_MENDEC 0x06 290#define MACE_UTR_LOOP_NO_MENDEC 0x04 291#define MACE_UTR_LOOP_EXTERNAL 0x02 292#define MACE_UTR_LOOP_NONE 0x00 293#define MACE_UTR_RESERVED 0x01 294 295/* Switch MACE register bank (only 0 and 1 are valid) */ 296#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK) 297 298#define MACE_IMR_DEFAULT \ 299 (0xFF - \ 300 ( \ 301 MACE_IR_CERR | \ 302 MACE_IR_RCVCCO | \ 303 MACE_IR_RNTPCO | \ 304 MACE_IR_MPCO | \ 305 MACE_IR_RCVINT | \ 306 MACE_IR_XMTINT \ 307 ) \ 308 ) 309#undef MACE_IMR_DEFAULT 310#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */ 311 312#define TX_TIMEOUT ((400*HZ)/1000) 313 314/* ---------------------------------------------------------------------------- 315Type Definitions 316---------------------------------------------------------------------------- */ 317 318typedef struct _mace_statistics { 319 /* MACE_XMTFS */ 320 int xmtsv; 321 int uflo; 322 int lcol; 323 int more; 324 int one; 325 int defer; 326 int lcar; 327 int rtry; 328 329 /* MACE_XMTRC */ 330 int exdef; 331 int xmtrc; 332 333 /* RFS1--Receive Status (RCVSTS) */ 334 int oflo; 335 int clsn; 336 int fram; 337 int fcs; 338 339 /* RFS2--Runt Packet Count (RNTPC) */ 340 int rfs_rntpc; 341 342 /* RFS3--Receive Collision Count (RCVCC) */ 343 int rfs_rcvcc; 344 345 /* MACE_IR */ 346 int jab; 347 int babl; 348 int cerr; 349 int rcvcco; 350 int rntpco; 351 int mpco; 352 353 /* MACE_MPC */ 354 int mpc; 355 356 /* MACE_RNTPC */ 357 int rntpc; 358 359 /* MACE_RCVCC */ 360 int rcvcc; 361} mace_statistics; 362 363typedef struct _mace_private { 364 struct pcmcia_device *p_dev; 365 struct net_device_stats linux_stats; /* Linux statistics counters */ 366 mace_statistics mace_stats; /* MACE chip statistics counters */ 367 368 /* restore_multicast_list() state variables */ 369 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */ 370 int multicast_num_addrs; 371 372 char tx_free_frames; /* Number of free transmit frame buffers */ 373 char tx_irq_disabled; /* MACE TX interrupt disabled */ 374 375 spinlock_t bank_lock; /* Must be held if you step off bank 0 */ 376} mace_private; 377 378/* ---------------------------------------------------------------------------- 379Private Global Variables 380---------------------------------------------------------------------------- */ 381 382static const char *if_names[]={ 383 "Auto", "10baseT", "BNC", 384}; 385 386/* ---------------------------------------------------------------------------- 387Parameters 388 These are the parameters that can be set during loading with 389 'insmod'. 390---------------------------------------------------------------------------- */ 391 392MODULE_DESCRIPTION("New Media PCMCIA ethernet driver"); 393MODULE_LICENSE("GPL"); 394 395#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) 396 397/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */ 398INT_MODULE_PARM(if_port, 0); 399 400 401/* ---------------------------------------------------------------------------- 402Function Prototypes 403---------------------------------------------------------------------------- */ 404 405static int nmclan_config(struct pcmcia_device *link); 406static void nmclan_release(struct pcmcia_device *link); 407 408static void nmclan_reset(struct net_device *dev); 409static int mace_config(struct net_device *dev, struct ifmap *map); 410static int mace_open(struct net_device *dev); 411static int mace_close(struct net_device *dev); 412static netdev_tx_t mace_start_xmit(struct sk_buff *skb, 413 struct net_device *dev); 414static void mace_tx_timeout(struct net_device *dev); 415static irqreturn_t mace_interrupt(int irq, void *dev_id); 416static struct net_device_stats *mace_get_stats(struct net_device *dev); 417static int mace_rx(struct net_device *dev, unsigned char RxCnt); 418static void restore_multicast_list(struct net_device *dev); 419static void set_multicast_list(struct net_device *dev); 420static const struct ethtool_ops netdev_ethtool_ops; 421 422 423static void nmclan_detach(struct pcmcia_device *p_dev); 424 425static const struct net_device_ops mace_netdev_ops = { 426 .ndo_open = mace_open, 427 .ndo_stop = mace_close, 428 .ndo_start_xmit = mace_start_xmit, 429 .ndo_tx_timeout = mace_tx_timeout, 430 .ndo_set_config = mace_config, 431 .ndo_get_stats = mace_get_stats, 432 .ndo_set_multicast_list = set_multicast_list, 433 .ndo_change_mtu = eth_change_mtu, 434 .ndo_set_mac_address = eth_mac_addr, 435 .ndo_validate_addr = eth_validate_addr, 436}; 437 438/* ---------------------------------------------------------------------------- 439nmclan_attach 440 Creates an "instance" of the driver, allocating local data 441 structures for one device. The device is registered with Card 442 Services. 443---------------------------------------------------------------------------- */ 444 445static int nmclan_probe(struct pcmcia_device *link) 446{ 447 mace_private *lp; 448 struct net_device *dev; 449 450 dev_dbg(&link->dev, "nmclan_attach()\n"); 451 452 /* Create new ethernet device */ 453 dev = alloc_etherdev(sizeof(mace_private)); 454 if (!dev) 455 return -ENOMEM; 456 lp = netdev_priv(dev); 457 lp->p_dev = link; 458 link->priv = dev; 459 460 spin_lock_init(&lp->bank_lock); 461 link->resource[0]->end = 32; 462 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO; 463 link->conf.Attributes = CONF_ENABLE_IRQ; 464 link->conf.IntType = INT_MEMORY_AND_IO; 465 link->conf.ConfigIndex = 1; 466 link->conf.Present = PRESENT_OPTION; 467 468 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 469 470 dev->netdev_ops = &mace_netdev_ops; 471 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); 472 dev->watchdog_timeo = TX_TIMEOUT; 473 474 return nmclan_config(link); 475} /* nmclan_attach */ 476 477/* ---------------------------------------------------------------------------- 478nmclan_detach 479 This deletes a driver "instance". The device is de-registered 480 with Card Services. If it has been released, all local data 481 structures are freed. Otherwise, the structures will be freed 482 when the device is released. 483---------------------------------------------------------------------------- */ 484 485static void nmclan_detach(struct pcmcia_device *link) 486{ 487 struct net_device *dev = link->priv; 488 489 dev_dbg(&link->dev, "nmclan_detach\n"); 490 491 unregister_netdev(dev); 492 493 nmclan_release(link); 494 495 free_netdev(dev); 496} /* nmclan_detach */ 497 498/* ---------------------------------------------------------------------------- 499mace_read 500 Reads a MACE register. This is bank independent; however, the 501 caller must ensure that this call is not interruptable. We are 502 assuming that during normal operation, the MACE is always in 503 bank 0. 504---------------------------------------------------------------------------- */ 505static int mace_read(mace_private *lp, unsigned int ioaddr, int reg) 506{ 507 int data = 0xFF; 508 unsigned long flags; 509 510 switch (reg >> 4) { 511 case 0: /* register 0-15 */ 512 data = inb(ioaddr + AM2150_MACE_BASE + reg); 513 break; 514 case 1: /* register 16-31 */ 515 spin_lock_irqsave(&lp->bank_lock, flags); 516 MACEBANK(1); 517 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); 518 MACEBANK(0); 519 spin_unlock_irqrestore(&lp->bank_lock, flags); 520 break; 521 } 522 return (data & 0xFF); 523} /* mace_read */ 524 525/* ---------------------------------------------------------------------------- 526mace_write 527 Writes to a MACE register. This is bank independent; however, 528 the caller must ensure that this call is not interruptable. We 529 are assuming that during normal operation, the MACE is always in 530 bank 0. 531---------------------------------------------------------------------------- */ 532static void mace_write(mace_private *lp, unsigned int ioaddr, int reg, 533 int data) 534{ 535 unsigned long flags; 536 537 switch (reg >> 4) { 538 case 0: /* register 0-15 */ 539 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg); 540 break; 541 case 1: /* register 16-31 */ 542 spin_lock_irqsave(&lp->bank_lock, flags); 543 MACEBANK(1); 544 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); 545 MACEBANK(0); 546 spin_unlock_irqrestore(&lp->bank_lock, flags); 547 break; 548 } 549} /* mace_write */ 550 551/* ---------------------------------------------------------------------------- 552mace_init 553 Resets the MACE chip. 554---------------------------------------------------------------------------- */ 555static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr) 556{ 557 int i; 558 int ct = 0; 559 560 /* MACE Software reset */ 561 mace_write(lp, ioaddr, MACE_BIUCC, 1); 562 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) { 563 /* Wait for reset bit to be cleared automatically after <= 200ns */; 564 if(++ct > 500) 565 { 566 printk(KERN_ERR "mace: reset failed, card removed ?\n"); 567 return -1; 568 } 569 udelay(1); 570 } 571 mace_write(lp, ioaddr, MACE_BIUCC, 0); 572 573 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */ 574 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F); 575 576 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */ 577 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */ 578 579 /* 580 * Bit 2-1 PORTSEL[1-0] Port Select. 581 * 00 AUI/10Base-2 582 * 01 10Base-T 583 * 10 DAI Port (reserved in Am2150) 584 * 11 GPSI 585 * For this card, only the first two are valid. 586 * So, PLSCC should be set to 587 * 0x00 for 10Base-2 588 * 0x02 for 10Base-T 589 * Or just set ASEL in PHYCC below! 590 */ 591 switch (if_port) { 592 case 1: 593 mace_write(lp, ioaddr, MACE_PLSCC, 0x02); 594 break; 595 case 2: 596 mace_write(lp, ioaddr, MACE_PLSCC, 0x00); 597 break; 598 default: 599 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4); 600 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden, 601 and the MACE device will automatically select the operating media 602 interface port. */ 603 break; 604 } 605 606 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR); 607 /* Poll ADDRCHG bit */ 608 ct = 0; 609 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) 610 { 611 if(++ ct > 500) 612 { 613 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n"); 614 return -1; 615 } 616 } 617 /* Set PADR register */ 618 for (i = 0; i < ETHER_ADDR_LEN; i++) 619 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]); 620 621 /* MAC Configuration Control Register should be written last */ 622 /* Let set_multicast_list set this. */ 623 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */ 624 mace_write(lp, ioaddr, MACE_MACCC, 0x00); 625 return 0; 626} /* mace_init */ 627 628/* ---------------------------------------------------------------------------- 629nmclan_config 630 This routine is scheduled to run after a CARD_INSERTION event 631 is received, to configure the PCMCIA socket, and to make the 632 ethernet device available to the system. 633---------------------------------------------------------------------------- */ 634 635static int nmclan_config(struct pcmcia_device *link) 636{ 637 struct net_device *dev = link->priv; 638 mace_private *lp = netdev_priv(dev); 639 u8 *buf; 640 size_t len; 641 int i, ret; 642 unsigned int ioaddr; 643 644 dev_dbg(&link->dev, "nmclan_config\n"); 645 646 link->io_lines = 5; 647 ret = pcmcia_request_io(link); 648 if (ret) 649 goto failed; 650 ret = pcmcia_request_exclusive_irq(link, mace_interrupt); 651 if (ret) 652 goto failed; 653 ret = pcmcia_request_configuration(link, &link->conf); 654 if (ret) 655 goto failed; 656 657 dev->irq = link->irq; 658 dev->base_addr = link->resource[0]->start; 659 660 ioaddr = dev->base_addr; 661 662 /* Read the ethernet address from the CIS. */ 663 len = pcmcia_get_tuple(link, 0x80, &buf); 664 if (!buf || len < ETHER_ADDR_LEN) { 665 kfree(buf); 666 goto failed; 667 } 668 memcpy(dev->dev_addr, buf, ETHER_ADDR_LEN); 669 kfree(buf); 670 671 /* Verify configuration by reading the MACE ID. */ 672 { 673 char sig[2]; 674 675 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL); 676 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH); 677 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) { 678 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n", 679 sig[0], sig[1]); 680 } else { 681 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should" 682 " be 0x40 0x?9\n", sig[0], sig[1]); 683 return -ENODEV; 684 } 685 } 686 687 if(mace_init(lp, ioaddr, dev->dev_addr) == -1) 688 goto failed; 689 690 /* The if_port symbol can be set when the module is loaded */ 691 if (if_port <= 2) 692 dev->if_port = if_port; 693 else 694 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n"); 695 696 SET_NETDEV_DEV(dev, &link->dev); 697 698 i = register_netdev(dev); 699 if (i != 0) { 700 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n"); 701 goto failed; 702 } 703 704 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port," 705 " hw_addr %pM\n", 706 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port], 707 dev->dev_addr); 708 return 0; 709 710failed: 711 nmclan_release(link); 712 return -ENODEV; 713} /* nmclan_config */ 714 715/* ---------------------------------------------------------------------------- 716nmclan_release 717 After a card is removed, nmclan_release() will unregister the 718 net device, and release the PCMCIA configuration. If the device 719 is still open, this will be postponed until it is closed. 720---------------------------------------------------------------------------- */ 721static void nmclan_release(struct pcmcia_device *link) 722{ 723 dev_dbg(&link->dev, "nmclan_release\n"); 724 pcmcia_disable_device(link); 725} 726 727static int nmclan_suspend(struct pcmcia_device *link) 728{ 729 struct net_device *dev = link->priv; 730 731 if (link->open) 732 netif_device_detach(dev); 733 734 return 0; 735} 736 737static int nmclan_resume(struct pcmcia_device *link) 738{ 739 struct net_device *dev = link->priv; 740 741 if (link->open) { 742 nmclan_reset(dev); 743 netif_device_attach(dev); 744 } 745 746 return 0; 747} 748 749 750/* ---------------------------------------------------------------------------- 751nmclan_reset 752 Reset and restore all of the Xilinx and MACE registers. 753---------------------------------------------------------------------------- */ 754static void nmclan_reset(struct net_device *dev) 755{ 756 mace_private *lp = netdev_priv(dev); 757 758#if RESET_XILINX 759 struct pcmcia_device *link = &lp->link; 760 u8 OrigCorValue; 761 762 /* Save original COR value */ 763 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue); 764 765 /* Reset Xilinx */ 766 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n", 767 OrigCorValue); 768 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET); 769 /* Need to wait for 20 ms for PCMCIA to finish reset. */ 770 771 /* Restore original COR configuration index */ 772 pcmcia_write_config_byte(link, CISREG_COR, 773 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK))); 774 /* Xilinx is now completely reset along with the MACE chip. */ 775 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 776 777#endif /* #if RESET_XILINX */ 778 779 /* Xilinx is now completely reset along with the MACE chip. */ 780 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 781 782 /* Reinitialize the MACE chip for operation. */ 783 mace_init(lp, dev->base_addr, dev->dev_addr); 784 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT); 785 786 /* Restore the multicast list and enable TX and RX. */ 787 restore_multicast_list(dev); 788} /* nmclan_reset */ 789 790/* ---------------------------------------------------------------------------- 791mace_config 792 [Someone tell me what this is supposed to do? Is if_port a defined 793 standard? If so, there should be defines to indicate 1=10Base-T, 794 2=10Base-2, etc. including limited automatic detection.] 795---------------------------------------------------------------------------- */ 796static int mace_config(struct net_device *dev, struct ifmap *map) 797{ 798 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) { 799 if (map->port <= 2) { 800 dev->if_port = map->port; 801 printk(KERN_INFO "%s: switched to %s port\n", dev->name, 802 if_names[dev->if_port]); 803 } else 804 return -EINVAL; 805 } 806 return 0; 807} /* mace_config */ 808 809/* ---------------------------------------------------------------------------- 810mace_open 811 Open device driver. 812---------------------------------------------------------------------------- */ 813static int mace_open(struct net_device *dev) 814{ 815 unsigned int ioaddr = dev->base_addr; 816 mace_private *lp = netdev_priv(dev); 817 struct pcmcia_device *link = lp->p_dev; 818 819 if (!pcmcia_dev_present(link)) 820 return -ENODEV; 821 822 link->open++; 823 824 MACEBANK(0); 825 826 netif_start_queue(dev); 827 nmclan_reset(dev); 828 829 return 0; /* Always succeed */ 830} /* mace_open */ 831 832/* ---------------------------------------------------------------------------- 833mace_close 834 Closes device driver. 835---------------------------------------------------------------------------- */ 836static int mace_close(struct net_device *dev) 837{ 838 unsigned int ioaddr = dev->base_addr; 839 mace_private *lp = netdev_priv(dev); 840 struct pcmcia_device *link = lp->p_dev; 841 842 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name); 843 844 /* Mask off all interrupts from the MACE chip. */ 845 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR); 846 847 link->open--; 848 netif_stop_queue(dev); 849 850 return 0; 851} /* mace_close */ 852 853static void netdev_get_drvinfo(struct net_device *dev, 854 struct ethtool_drvinfo *info) 855{ 856 strcpy(info->driver, DRV_NAME); 857 strcpy(info->version, DRV_VERSION); 858 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr); 859} 860 861static const struct ethtool_ops netdev_ethtool_ops = { 862 .get_drvinfo = netdev_get_drvinfo, 863}; 864 865/* ---------------------------------------------------------------------------- 866mace_start_xmit 867 This routine begins the packet transmit function. When completed, 868 it will generate a transmit interrupt. 869 870 According to /usr/src/linux/net/inet/dev.c, if _start_xmit 871 returns 0, the "packet is now solely the responsibility of the 872 driver." If _start_xmit returns non-zero, the "transmission 873 failed, put skb back into a list." 874---------------------------------------------------------------------------- */ 875 876static void mace_tx_timeout(struct net_device *dev) 877{ 878 mace_private *lp = netdev_priv(dev); 879 struct pcmcia_device *link = lp->p_dev; 880 881 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name); 882#if RESET_ON_TIMEOUT 883 printk("resetting card\n"); 884 pcmcia_reset_card(link->socket); 885#else /* #if RESET_ON_TIMEOUT */ 886 printk("NOT resetting card\n"); 887#endif /* #if RESET_ON_TIMEOUT */ 888 dev->trans_start = jiffies; /* prevent tx timeout */ 889 netif_wake_queue(dev); 890} 891 892static netdev_tx_t mace_start_xmit(struct sk_buff *skb, 893 struct net_device *dev) 894{ 895 mace_private *lp = netdev_priv(dev); 896 unsigned int ioaddr = dev->base_addr; 897 898 netif_stop_queue(dev); 899 900 pr_debug("%s: mace_start_xmit(length = %ld) called.\n", 901 dev->name, (long)skb->len); 902 903#if !TX_INTERRUPTABLE 904 /* Disable MACE TX interrupts. */ 905 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT, 906 ioaddr + AM2150_MACE_BASE + MACE_IMR); 907 lp->tx_irq_disabled=1; 908#endif /* #if (!TX_INTERRUPTABLE) */ 909 910 { 911 /* This block must not be interrupted by another transmit request! 912 mace_tx_timeout will take care of timer-based retransmissions from 913 the upper layers. The interrupt handler is guaranteed never to 914 service a transmit interrupt while we are in here. 915 */ 916 917 lp->linux_stats.tx_bytes += skb->len; 918 lp->tx_free_frames--; 919 920 /* WARNING: Write the _exact_ number of bytes written in the header! */ 921 /* Put out the word header [must be an outw()] . . . */ 922 outw(skb->len, ioaddr + AM2150_XMT); 923 /* . . . and the packet [may be any combination of outw() and outb()] */ 924 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1); 925 if (skb->len & 1) { 926 /* Odd byte transfer */ 927 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT); 928 } 929 930#if MULTI_TX 931 if (lp->tx_free_frames > 0) 932 netif_start_queue(dev); 933#endif /* #if MULTI_TX */ 934 } 935 936#if !TX_INTERRUPTABLE 937 /* Re-enable MACE TX interrupts. */ 938 lp->tx_irq_disabled=0; 939 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR); 940#endif /* #if (!TX_INTERRUPTABLE) */ 941 942 dev_kfree_skb(skb); 943 944 return NETDEV_TX_OK; 945} /* mace_start_xmit */ 946 947/* ---------------------------------------------------------------------------- 948mace_interrupt 949 The interrupt handler. 950---------------------------------------------------------------------------- */ 951static irqreturn_t mace_interrupt(int irq, void *dev_id) 952{ 953 struct net_device *dev = (struct net_device *) dev_id; 954 mace_private *lp = netdev_priv(dev); 955 unsigned int ioaddr; 956 int status; 957 int IntrCnt = MACE_MAX_IR_ITERATIONS; 958 959 if (dev == NULL) { 960 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n", 961 irq); 962 return IRQ_NONE; 963 } 964 965 ioaddr = dev->base_addr; 966 967 if (lp->tx_irq_disabled) { 968 printk( 969 (lp->tx_irq_disabled? 970 KERN_NOTICE "%s: Interrupt with tx_irq_disabled " 971 "[isr=%02X, imr=%02X]\n": 972 KERN_NOTICE "%s: Re-entering the interrupt handler " 973 "[isr=%02X, imr=%02X]\n"), 974 dev->name, 975 inb(ioaddr + AM2150_MACE_BASE + MACE_IR), 976 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR) 977 ); 978 /* WARNING: MACE_IR has been read! */ 979 return IRQ_NONE; 980 } 981 982 if (!netif_device_present(dev)) { 983 pr_debug("%s: interrupt from dead card\n", dev->name); 984 return IRQ_NONE; 985 } 986 987 do { 988 /* WARNING: MACE_IR is a READ/CLEAR port! */ 989 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR); 990 991 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status); 992 993 if (status & MACE_IR_RCVINT) { 994 mace_rx(dev, MACE_MAX_RX_ITERATIONS); 995 } 996 997 if (status & MACE_IR_XMTINT) { 998 unsigned char fifofc; 999 unsigned char xmtrc; 1000 unsigned char xmtfs; 1001 1002 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC); 1003 if ((fifofc & MACE_FIFOFC_XMTFC)==0) { 1004 lp->linux_stats.tx_errors++; 1005 outb(0xFF, ioaddr + AM2150_XMT_SKIP); 1006 } 1007 1008 /* Transmit Retry Count (XMTRC, reg 4) */ 1009 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC); 1010 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++; 1011 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC); 1012 1013 if ( 1014 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) & 1015 MACE_XMTFS_XMTSV /* Transmit Status Valid */ 1016 ) { 1017 lp->mace_stats.xmtsv++; 1018 1019 if (xmtfs & ~MACE_XMTFS_XMTSV) { 1020 if (xmtfs & MACE_XMTFS_UFLO) { 1021 /* Underflow. Indicates that the Transmit FIFO emptied before 1022 the end of frame was reached. */ 1023 lp->mace_stats.uflo++; 1024 } 1025 if (xmtfs & MACE_XMTFS_LCOL) { 1026 /* Late Collision */ 1027 lp->mace_stats.lcol++; 1028 } 1029 if (xmtfs & MACE_XMTFS_MORE) { 1030 /* MORE than one retry was needed */ 1031 lp->mace_stats.more++; 1032 } 1033 if (xmtfs & MACE_XMTFS_ONE) { 1034 /* Exactly ONE retry occurred */ 1035 lp->mace_stats.one++; 1036 } 1037 if (xmtfs & MACE_XMTFS_DEFER) { 1038 /* Transmission was defered */ 1039 lp->mace_stats.defer++; 1040 } 1041 if (xmtfs & MACE_XMTFS_LCAR) { 1042 /* Loss of carrier */ 1043 lp->mace_stats.lcar++; 1044 } 1045 if (xmtfs & MACE_XMTFS_RTRY) { 1046 /* Retry error: transmit aborted after 16 attempts */ 1047 lp->mace_stats.rtry++; 1048 } 1049 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */ 1050 1051 } /* if (xmtfs & MACE_XMTFS_XMTSV) */ 1052 1053 lp->linux_stats.tx_packets++; 1054 lp->tx_free_frames++; 1055 netif_wake_queue(dev); 1056 } /* if (status & MACE_IR_XMTINT) */ 1057 1058 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) { 1059 if (status & MACE_IR_JAB) { 1060 /* Jabber Error. Excessive transmit duration (20-150ms). */ 1061 lp->mace_stats.jab++; 1062 } 1063 if (status & MACE_IR_BABL) { 1064 /* Babble Error. >1518 bytes transmitted. */ 1065 lp->mace_stats.babl++; 1066 } 1067 if (status & MACE_IR_CERR) { 1068 /* Collision Error. CERR indicates the absence of the 1069 Signal Quality Error Test message after a packet 1070 transmission. */ 1071 lp->mace_stats.cerr++; 1072 } 1073 if (status & MACE_IR_RCVCCO) { 1074 /* Receive Collision Count Overflow; */ 1075 lp->mace_stats.rcvcco++; 1076 } 1077 if (status & MACE_IR_RNTPCO) { 1078 /* Runt Packet Count Overflow */ 1079 lp->mace_stats.rntpco++; 1080 } 1081 if (status & MACE_IR_MPCO) { 1082 /* Missed Packet Count Overflow */ 1083 lp->mace_stats.mpco++; 1084 } 1085 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */ 1086 1087 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt)); 1088 1089 return IRQ_HANDLED; 1090} /* mace_interrupt */ 1091 1092/* ---------------------------------------------------------------------------- 1093mace_rx 1094 Receives packets. 1095---------------------------------------------------------------------------- */ 1096static int mace_rx(struct net_device *dev, unsigned char RxCnt) 1097{ 1098 mace_private *lp = netdev_priv(dev); 1099 unsigned int ioaddr = dev->base_addr; 1100 unsigned char rx_framecnt; 1101 unsigned short rx_status; 1102 1103 while ( 1104 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) && 1105 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */ 1106 (RxCnt--) 1107 ) { 1108 rx_status = inw(ioaddr + AM2150_RCV); 1109 1110 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status" 1111 " 0x%X.\n", dev->name, rx_framecnt, rx_status); 1112 1113 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */ 1114 lp->linux_stats.rx_errors++; 1115 if (rx_status & MACE_RCVFS_OFLO) { 1116 lp->mace_stats.oflo++; 1117 } 1118 if (rx_status & MACE_RCVFS_CLSN) { 1119 lp->mace_stats.clsn++; 1120 } 1121 if (rx_status & MACE_RCVFS_FRAM) { 1122 lp->mace_stats.fram++; 1123 } 1124 if (rx_status & MACE_RCVFS_FCS) { 1125 lp->mace_stats.fcs++; 1126 } 1127 } else { 1128 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4; 1129 /* Auto Strip is off, always subtract 4 */ 1130 struct sk_buff *skb; 1131 1132 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV); 1133 /* runt packet count */ 1134 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV); 1135 /* rcv collision count */ 1136 1137 pr_debug(" receiving packet size 0x%X rx_status" 1138 " 0x%X.\n", pkt_len, rx_status); 1139 1140 skb = dev_alloc_skb(pkt_len+2); 1141 1142 if (skb != NULL) { 1143 skb_reserve(skb, 2); 1144 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1); 1145 if (pkt_len & 1) 1146 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV); 1147 skb->protocol = eth_type_trans(skb, dev); 1148 1149 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */ 1150 1151 lp->linux_stats.rx_packets++; 1152 lp->linux_stats.rx_bytes += pkt_len; 1153 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ 1154 continue; 1155 } else { 1156 pr_debug("%s: couldn't allocate a sk_buff of size" 1157 " %d.\n", dev->name, pkt_len); 1158 lp->linux_stats.rx_dropped++; 1159 } 1160 } 1161 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ 1162 } /* while */ 1163 1164 return 0; 1165} /* mace_rx */ 1166 1167/* ---------------------------------------------------------------------------- 1168pr_linux_stats 1169---------------------------------------------------------------------------- */ 1170static void pr_linux_stats(struct net_device_stats *pstats) 1171{ 1172 pr_debug("pr_linux_stats\n"); 1173 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n", 1174 (long)pstats->rx_packets, (long)pstats->tx_packets); 1175 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n", 1176 (long)pstats->rx_errors, (long)pstats->tx_errors); 1177 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n", 1178 (long)pstats->rx_dropped, (long)pstats->tx_dropped); 1179 pr_debug(" multicast=%-7ld collisions=%ld\n", 1180 (long)pstats->multicast, (long)pstats->collisions); 1181 1182 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n", 1183 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors); 1184 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n", 1185 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors); 1186 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n", 1187 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors); 1188 1189 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n", 1190 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors); 1191 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n", 1192 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors); 1193 pr_debug(" tx_window_errors=%ld\n", 1194 (long)pstats->tx_window_errors); 1195} /* pr_linux_stats */ 1196 1197/* ---------------------------------------------------------------------------- 1198pr_mace_stats 1199---------------------------------------------------------------------------- */ 1200static void pr_mace_stats(mace_statistics *pstats) 1201{ 1202 pr_debug("pr_mace_stats\n"); 1203 1204 pr_debug(" xmtsv=%-7d uflo=%d\n", 1205 pstats->xmtsv, pstats->uflo); 1206 pr_debug(" lcol=%-7d more=%d\n", 1207 pstats->lcol, pstats->more); 1208 pr_debug(" one=%-7d defer=%d\n", 1209 pstats->one, pstats->defer); 1210 pr_debug(" lcar=%-7d rtry=%d\n", 1211 pstats->lcar, pstats->rtry); 1212 1213 /* MACE_XMTRC */ 1214 pr_debug(" exdef=%-7d xmtrc=%d\n", 1215 pstats->exdef, pstats->xmtrc); 1216 1217 /* RFS1--Receive Status (RCVSTS) */ 1218 pr_debug(" oflo=%-7d clsn=%d\n", 1219 pstats->oflo, pstats->clsn); 1220 pr_debug(" fram=%-7d fcs=%d\n", 1221 pstats->fram, pstats->fcs); 1222 1223 /* RFS2--Runt Packet Count (RNTPC) */ 1224 /* RFS3--Receive Collision Count (RCVCC) */ 1225 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n", 1226 pstats->rfs_rntpc, pstats->rfs_rcvcc); 1227 1228 /* MACE_IR */ 1229 pr_debug(" jab=%-7d babl=%d\n", 1230 pstats->jab, pstats->babl); 1231 pr_debug(" cerr=%-7d rcvcco=%d\n", 1232 pstats->cerr, pstats->rcvcco); 1233 pr_debug(" rntpco=%-7d mpco=%d\n", 1234 pstats->rntpco, pstats->mpco); 1235 1236 /* MACE_MPC */ 1237 pr_debug(" mpc=%d\n", pstats->mpc); 1238 1239 /* MACE_RNTPC */ 1240 pr_debug(" rntpc=%d\n", pstats->rntpc); 1241 1242 /* MACE_RCVCC */ 1243 pr_debug(" rcvcc=%d\n", pstats->rcvcc); 1244 1245} /* pr_mace_stats */ 1246 1247/* ---------------------------------------------------------------------------- 1248update_stats 1249 Update statistics. We change to register window 1, so this 1250 should be run single-threaded if the device is active. This is 1251 expected to be a rare operation, and it's simpler for the rest 1252 of the driver to assume that window 0 is always valid rather 1253 than use a special window-state variable. 1254 1255 oflo & uflo should _never_ occur since it would mean the Xilinx 1256 was not able to transfer data between the MACE FIFO and the 1257 card's SRAM fast enough. If this happens, something is 1258 seriously wrong with the hardware. 1259---------------------------------------------------------------------------- */ 1260static void update_stats(unsigned int ioaddr, struct net_device *dev) 1261{ 1262 mace_private *lp = netdev_priv(dev); 1263 1264 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC); 1265 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC); 1266 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC); 1267 /* At this point, mace_stats is fully updated for this call. 1268 We may now update the linux_stats. */ 1269 1270 /* The MACE has no equivalent for linux_stats field which are commented 1271 out. */ 1272 1273 /* lp->linux_stats.multicast; */ 1274 lp->linux_stats.collisions = 1275 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc; 1276 /* Collision: The MACE may retry sending a packet 15 times 1277 before giving up. The retry count is in XMTRC. 1278 Does each retry constitute a collision? 1279 If so, why doesn't the RCVCC record these collisions? */ 1280 1281 /* detailed rx_errors: */ 1282 lp->linux_stats.rx_length_errors = 1283 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc; 1284 /* lp->linux_stats.rx_over_errors */ 1285 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs; 1286 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram; 1287 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo; 1288 lp->linux_stats.rx_missed_errors = 1289 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc; 1290 1291 /* detailed tx_errors */ 1292 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry; 1293 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar; 1294 /* LCAR usually results from bad cabling. */ 1295 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo; 1296 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr; 1297 /* lp->linux_stats.tx_window_errors; */ 1298} /* update_stats */ 1299 1300/* ---------------------------------------------------------------------------- 1301mace_get_stats 1302 Gathers ethernet statistics from the MACE chip. 1303---------------------------------------------------------------------------- */ 1304static struct net_device_stats *mace_get_stats(struct net_device *dev) 1305{ 1306 mace_private *lp = netdev_priv(dev); 1307 1308 update_stats(dev->base_addr, dev); 1309 1310 pr_debug("%s: updating the statistics.\n", dev->name); 1311 pr_linux_stats(&lp->linux_stats); 1312 pr_mace_stats(&lp->mace_stats); 1313 1314 return &lp->linux_stats; 1315} /* net_device_stats */ 1316 1317/* ---------------------------------------------------------------------------- 1318updateCRC 1319 Modified from Am79C90 data sheet. 1320---------------------------------------------------------------------------- */ 1321 1322#ifdef BROKEN_MULTICAST 1323 1324static void updateCRC(int *CRC, int bit) 1325{ 1326 int poly[]={ 1327 1,1,1,0, 1,1,0,1, 1328 1,0,1,1, 1,0,0,0, 1329 1,0,0,0, 0,0,1,1, 1330 0,0,1,0, 0,0,0,0 1331 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the 1332 CRC generator polynomial. */ 1333 1334 int j; 1335 1336 /* shift CRC and control bit (CRC[32]) */ 1337 for (j = 32; j > 0; j--) 1338 CRC[j] = CRC[j-1]; 1339 CRC[0] = 0; 1340 1341 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */ 1342 if (bit ^ CRC[32]) 1343 for (j = 0; j < 32; j++) 1344 CRC[j] ^= poly[j]; 1345} /* updateCRC */ 1346 1347/* ---------------------------------------------------------------------------- 1348BuildLAF 1349 Build logical address filter. 1350 Modified from Am79C90 data sheet. 1351 1352Input 1353 ladrf: logical address filter (contents initialized to 0) 1354 adr: ethernet address 1355---------------------------------------------------------------------------- */ 1356static void BuildLAF(int *ladrf, int *adr) 1357{ 1358 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */ 1359 1360 int i, byte; /* temporary array indices */ 1361 int hashcode; /* the output object */ 1362 1363 CRC[32]=0; 1364 1365 for (byte = 0; byte < 6; byte++) 1366 for (i = 0; i < 8; i++) 1367 updateCRC(CRC, (adr[byte] >> i) & 1); 1368 1369 hashcode = 0; 1370 for (i = 0; i < 6; i++) 1371 hashcode = (hashcode << 1) + CRC[i]; 1372 1373 byte = hashcode >> 3; 1374 ladrf[byte] |= (1 << (hashcode & 7)); 1375 1376#ifdef PCMCIA_DEBUG 1377 if (0) 1378 printk(KERN_DEBUG " adr =%pM\n", adr); 1379 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode); 1380 for (i = 0; i < 8; i++) 1381 printk(KERN_CONT " %02X", ladrf[i]); 1382 printk(KERN_CONT "\n"); 1383#endif 1384} /* BuildLAF */ 1385 1386/* ---------------------------------------------------------------------------- 1387restore_multicast_list 1388 Restores the multicast filter for MACE chip to the last 1389 set_multicast_list() call. 1390 1391Input 1392 multicast_num_addrs 1393 multicast_ladrf[] 1394---------------------------------------------------------------------------- */ 1395static void restore_multicast_list(struct net_device *dev) 1396{ 1397 mace_private *lp = netdev_priv(dev); 1398 int num_addrs = lp->multicast_num_addrs; 1399 int *ladrf = lp->multicast_ladrf; 1400 unsigned int ioaddr = dev->base_addr; 1401 int i; 1402 1403 pr_debug("%s: restoring Rx mode to %d addresses.\n", 1404 dev->name, num_addrs); 1405 1406 if (num_addrs > 0) { 1407 1408 pr_debug("Attempt to restore multicast list detected.\n"); 1409 1410 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR); 1411 /* Poll ADDRCHG bit */ 1412 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) 1413 ; 1414 /* Set LADRF register */ 1415 for (i = 0; i < MACE_LADRF_LEN; i++) 1416 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]); 1417 1418 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL); 1419 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1420 1421 } else if (num_addrs < 0) { 1422 1423 /* Promiscuous mode: receive all packets */ 1424 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1425 mace_write(lp, ioaddr, MACE_MACCC, 1426 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV 1427 ); 1428 1429 } else { 1430 1431 /* Normal mode */ 1432 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1433 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1434 1435 } 1436} /* restore_multicast_list */ 1437 1438/* ---------------------------------------------------------------------------- 1439set_multicast_list 1440 Set or clear the multicast filter for this adaptor. 1441 1442Input 1443 num_addrs == -1 Promiscuous mode, receive all packets 1444 num_addrs == 0 Normal mode, clear multicast list 1445 num_addrs > 0 Multicast mode, receive normal and MC packets, and do 1446 best-effort filtering. 1447Output 1448 multicast_num_addrs 1449 multicast_ladrf[] 1450---------------------------------------------------------------------------- */ 1451 1452static void set_multicast_list(struct net_device *dev) 1453{ 1454 mace_private *lp = netdev_priv(dev); 1455 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */ 1456 struct netdev_hw_addr *ha; 1457 1458#ifdef PCMCIA_DEBUG 1459 { 1460 static int old; 1461 if (netdev_mc_count(dev) != old) { 1462 old = netdev_mc_count(dev); 1463 pr_debug("%s: setting Rx mode to %d addresses.\n", 1464 dev->name, old); 1465 } 1466 } 1467#endif 1468 1469 /* Set multicast_num_addrs. */ 1470 lp->multicast_num_addrs = netdev_mc_count(dev); 1471 1472 /* Set multicast_ladrf. */ 1473 if (num_addrs > 0) { 1474 /* Calculate multicast logical address filter */ 1475 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN); 1476 netdev_for_each_mc_addr(ha, dev) { 1477 memcpy(adr, ha->addr, ETHER_ADDR_LEN); 1478 BuildLAF(lp->multicast_ladrf, adr); 1479 } 1480 } 1481 1482 restore_multicast_list(dev); 1483 1484} /* set_multicast_list */ 1485 1486#endif /* BROKEN_MULTICAST */ 1487 1488static void restore_multicast_list(struct net_device *dev) 1489{ 1490 unsigned int ioaddr = dev->base_addr; 1491 mace_private *lp = netdev_priv(dev); 1492 1493 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name, 1494 lp->multicast_num_addrs); 1495 1496 if (dev->flags & IFF_PROMISC) { 1497 /* Promiscuous mode: receive all packets */ 1498 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1499 mace_write(lp, ioaddr, MACE_MACCC, 1500 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV 1501 ); 1502 } else { 1503 /* Normal mode */ 1504 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1505 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1506 } 1507} /* restore_multicast_list */ 1508 1509static void set_multicast_list(struct net_device *dev) 1510{ 1511 mace_private *lp = netdev_priv(dev); 1512 1513#ifdef PCMCIA_DEBUG 1514 { 1515 static int old; 1516 if (netdev_mc_count(dev) != old) { 1517 old = netdev_mc_count(dev); 1518 pr_debug("%s: setting Rx mode to %d addresses.\n", 1519 dev->name, old); 1520 } 1521 } 1522#endif 1523 1524 lp->multicast_num_addrs = netdev_mc_count(dev); 1525 restore_multicast_list(dev); 1526 1527} /* set_multicast_list */ 1528 1529static struct pcmcia_device_id nmclan_ids[] = { 1530 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941), 1531 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf), 1532 PCMCIA_DEVICE_NULL, 1533}; 1534MODULE_DEVICE_TABLE(pcmcia, nmclan_ids); 1535 1536static struct pcmcia_driver nmclan_cs_driver = { 1537 .owner = THIS_MODULE, 1538 .drv = { 1539 .name = "nmclan_cs", 1540 }, 1541 .probe = nmclan_probe, 1542 .remove = nmclan_detach, 1543 .id_table = nmclan_ids, 1544 .suspend = nmclan_suspend, 1545 .resume = nmclan_resume, 1546}; 1547 1548static int __init init_nmclan_cs(void) 1549{ 1550 return pcmcia_register_driver(&nmclan_cs_driver); 1551} 1552 1553static void __exit exit_nmclan_cs(void) 1554{ 1555 pcmcia_unregister_driver(&nmclan_cs_driver); 1556} 1557 1558module_init(init_nmclan_cs); 1559module_exit(exit_nmclan_cs); 1560