1/********************************************************************* 2 * 3 * Description: Driver for the SMC Infrared Communications Controller 4 * Status: Experimental. 5 * Author: Daniele Peri (peri@csai.unipa.it) 6 * Created at: 7 * Modified at: 8 * Modified by: 9 * 10 * Copyright (c) 2002 Daniele Peri 11 * All Rights Reserved. 12 * Copyright (c) 2002 Jean Tourrilhes 13 * Copyright (c) 2006 Linus Walleij 14 * 15 * 16 * Based on smc-ircc.c: 17 * 18 * Copyright (c) 2001 Stefani Seibold 19 * Copyright (c) 1999-2001 Dag Brattli 20 * Copyright (c) 1998-1999 Thomas Davis, 21 * 22 * and irport.c: 23 * 24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved. 25 * 26 * 27 * This program is free software; you can redistribute it and/or 28 * modify it under the terms of the GNU General Public License as 29 * published by the Free Software Foundation; either version 2 of 30 * the License, or (at your option) any later version. 31 * 32 * This program is distributed in the hope that it will be useful, 33 * but WITHOUT ANY WARRANTY; without even the implied warranty of 34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 35 * GNU General Public License for more details. 36 * 37 * You should have received a copy of the GNU General Public License 38 * along with this program; if not, write to the Free Software 39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 40 * MA 02111-1307 USA 41 * 42 ********************************************************************/ 43 44#include <linux/module.h> 45#include <linux/kernel.h> 46#include <linux/types.h> 47#include <linux/skbuff.h> 48#include <linux/netdevice.h> 49#include <linux/ioport.h> 50#include <linux/delay.h> 51#include <linux/init.h> 52#include <linux/rtnetlink.h> 53#include <linux/serial_reg.h> 54#include <linux/dma-mapping.h> 55#include <linux/pnp.h> 56#include <linux/platform_device.h> 57#include <linux/gfp.h> 58 59#include <asm/io.h> 60#include <asm/dma.h> 61#include <asm/byteorder.h> 62 63#include <linux/spinlock.h> 64#include <linux/pm.h> 65#ifdef CONFIG_PCI 66#include <linux/pci.h> 67#endif 68 69#include <net/irda/wrapper.h> 70#include <net/irda/irda.h> 71#include <net/irda/irda_device.h> 72 73#include "smsc-ircc2.h" 74#include "smsc-sio.h" 75 76 77MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>"); 78MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver"); 79MODULE_LICENSE("GPL"); 80 81static int smsc_nopnp = 1; 82module_param_named(nopnp, smsc_nopnp, bool, 0); 83MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true"); 84 85#define DMA_INVAL 255 86static int ircc_dma = DMA_INVAL; 87module_param(ircc_dma, int, 0); 88MODULE_PARM_DESC(ircc_dma, "DMA channel"); 89 90#define IRQ_INVAL 255 91static int ircc_irq = IRQ_INVAL; 92module_param(ircc_irq, int, 0); 93MODULE_PARM_DESC(ircc_irq, "IRQ line"); 94 95static int ircc_fir; 96module_param(ircc_fir, int, 0); 97MODULE_PARM_DESC(ircc_fir, "FIR Base Address"); 98 99static int ircc_sir; 100module_param(ircc_sir, int, 0); 101MODULE_PARM_DESC(ircc_sir, "SIR Base Address"); 102 103static int ircc_cfg; 104module_param(ircc_cfg, int, 0); 105MODULE_PARM_DESC(ircc_cfg, "Configuration register base address"); 106 107static int ircc_transceiver; 108module_param(ircc_transceiver, int, 0); 109MODULE_PARM_DESC(ircc_transceiver, "Transceiver type"); 110 111/* Types */ 112 113#ifdef CONFIG_PCI 114struct smsc_ircc_subsystem_configuration { 115 unsigned short vendor; /* PCI vendor ID */ 116 unsigned short device; /* PCI vendor ID */ 117 unsigned short subvendor; /* PCI subsystem vendor ID */ 118 unsigned short subdevice; /* PCI subsystem device ID */ 119 unsigned short sir_io; /* I/O port for SIR */ 120 unsigned short fir_io; /* I/O port for FIR */ 121 unsigned char fir_irq; /* FIR IRQ */ 122 unsigned char fir_dma; /* FIR DMA */ 123 unsigned short cfg_base; /* I/O port for chip configuration */ 124 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */ 125 const char *name; /* name shown as info */ 126}; 127#endif 128 129struct smsc_transceiver { 130 char *name; 131 void (*set_for_speed)(int fir_base, u32 speed); 132 int (*probe)(int fir_base); 133}; 134 135struct smsc_chip { 136 char *name; 137 u16 flags; 138 u8 devid; 139 u8 rev; 140}; 141 142struct smsc_chip_address { 143 unsigned int cfg_base; 144 unsigned int type; 145}; 146 147/* Private data for each instance */ 148struct smsc_ircc_cb { 149 struct net_device *netdev; /* Yes! we are some kind of netdevice */ 150 struct irlap_cb *irlap; /* The link layer we are binded to */ 151 152 chipio_t io; /* IrDA controller information */ 153 iobuff_t tx_buff; /* Transmit buffer */ 154 iobuff_t rx_buff; /* Receive buffer */ 155 dma_addr_t tx_buff_dma; 156 dma_addr_t rx_buff_dma; 157 158 struct qos_info qos; /* QoS capabilities for this device */ 159 160 spinlock_t lock; /* For serializing operations */ 161 162 __u32 new_speed; 163 __u32 flags; /* Interface flags */ 164 165 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */ 166 int tx_len; /* Number of frames in tx_buff */ 167 168 int transceiver; 169 struct platform_device *pldev; 170}; 171 172/* Constants */ 173 174#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2" 175 176#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600 177#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1 178#define SMSC_IRCC2_C_NET_TIMEOUT 0 179#define SMSC_IRCC2_C_SIR_STOP 0 180 181static const char *driver_name = SMSC_IRCC2_DRIVER_NAME; 182 183/* Prototypes */ 184 185static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq); 186static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base); 187static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq); 188static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self); 189static void smsc_ircc_init_chip(struct smsc_ircc_cb *self); 190static int __exit smsc_ircc_close(struct smsc_ircc_cb *self); 191static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self); 192static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self); 193static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self); 194static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb, 195 struct net_device *dev); 196static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb, 197 struct net_device *dev); 198static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs); 199static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self); 200static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed); 201static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed); 202static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id); 203static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev); 204static void smsc_ircc_sir_start(struct smsc_ircc_cb *self); 205#if SMSC_IRCC2_C_SIR_STOP 206static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self); 207#endif 208static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self); 209static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len); 210static int smsc_ircc_net_open(struct net_device *dev); 211static int smsc_ircc_net_close(struct net_device *dev); 212static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 213#if SMSC_IRCC2_C_NET_TIMEOUT 214static void smsc_ircc_timeout(struct net_device *dev); 215#endif 216static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self); 217static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self); 218static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed); 219static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self); 220 221/* Probing */ 222static int __init smsc_ircc_look_for_chips(void); 223static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type); 224static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type); 225static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type); 226static int __init smsc_superio_fdc(unsigned short cfg_base); 227static int __init smsc_superio_lpc(unsigned short cfg_base); 228#ifdef CONFIG_PCI 229static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf); 230static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); 231static void __init preconfigure_ali_port(struct pci_dev *dev, 232 unsigned short port); 233static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); 234static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, 235 unsigned short ircc_fir, 236 unsigned short ircc_sir, 237 unsigned char ircc_dma, 238 unsigned char ircc_irq); 239#endif 240 241/* Transceivers specific functions */ 242 243static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed); 244static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base); 245static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed); 246static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base); 247static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed); 248static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base); 249 250/* Power Management */ 251 252static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state); 253static int smsc_ircc_resume(struct platform_device *dev); 254 255static struct platform_driver smsc_ircc_driver = { 256 .suspend = smsc_ircc_suspend, 257 .resume = smsc_ircc_resume, 258 .driver = { 259 .name = SMSC_IRCC2_DRIVER_NAME, 260 }, 261}; 262 263/* Transceivers for SMSC-ircc */ 264 265static struct smsc_transceiver smsc_transceivers[] = 266{ 267 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 }, 268 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select }, 269 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc }, 270 { NULL, NULL } 271}; 272#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1) 273 274/* SMC SuperIO chipsets definitions */ 275 276#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */ 277#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */ 278#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */ 279#define SIR 0 /* SuperIO Chip has only slow IRDA */ 280#define FIR 4 /* SuperIO Chip has fast IRDA */ 281#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */ 282 283static struct smsc_chip __initdata fdc_chips_flat[] = 284{ 285 /* Base address 0x3f0 or 0x370 */ 286 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */ 287 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 }, 288 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 }, 289 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 }, 290 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */ 291 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 }, 292 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 }, 293 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 }, 294 { NULL } 295}; 296 297static struct smsc_chip __initdata fdc_chips_paged[] = 298{ 299 /* Base address 0x3f0 or 0x370 */ 300 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 }, 301 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 }, 302 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 }, 303 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 }, 304 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 }, 305 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 }, 306 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 }, 307 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 }, 308 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 }, 309 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 }, 310 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 }, 311 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 }, 312 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 }, 313 { NULL } 314}; 315 316static struct smsc_chip __initdata lpc_chips_flat[] = 317{ 318 /* Base address 0x2E or 0x4E */ 319 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 }, 320 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 }, 321 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 }, 322 { NULL } 323}; 324 325static struct smsc_chip __initdata lpc_chips_paged[] = 326{ 327 /* Base address 0x2E or 0x4E */ 328 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 }, 329 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 }, 330 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, 331 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 }, 332 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, 333 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 }, 334 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 }, 335 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 }, 336 { NULL } 337}; 338 339#define SMSCSIO_TYPE_FDC 1 340#define SMSCSIO_TYPE_LPC 2 341#define SMSCSIO_TYPE_FLAT 4 342#define SMSCSIO_TYPE_PAGED 8 343 344static struct smsc_chip_address __initdata possible_addresses[] = 345{ 346 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 347 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 348 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 349 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 350 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 351 { 0, 0 } 352}; 353 354/* Globals */ 355 356static struct smsc_ircc_cb *dev_self[] = { NULL, NULL }; 357static unsigned short dev_count; 358 359static inline void register_bank(int iobase, int bank) 360{ 361 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), 362 iobase + IRCC_MASTER); 363} 364 365/* PNP hotplug support */ 366static const struct pnp_device_id smsc_ircc_pnp_table[] = { 367 { .id = "SMCf010", .driver_data = 0 }, 368 /* and presumably others */ 369 { } 370}; 371MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table); 372 373static int pnp_driver_registered; 374 375#ifdef CONFIG_PNP 376static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev, 377 const struct pnp_device_id *dev_id) 378{ 379 unsigned int firbase, sirbase; 380 u8 dma, irq; 381 382 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) && 383 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0))) 384 return -EINVAL; 385 386 sirbase = pnp_port_start(dev, 0); 387 firbase = pnp_port_start(dev, 1); 388 dma = pnp_dma(dev, 0); 389 irq = pnp_irq(dev, 0); 390 391 if (smsc_ircc_open(firbase, sirbase, dma, irq)) 392 return -ENODEV; 393 394 return 0; 395} 396 397static struct pnp_driver smsc_ircc_pnp_driver = { 398 .name = "smsc-ircc2", 399 .id_table = smsc_ircc_pnp_table, 400 .probe = smsc_ircc_pnp_probe, 401}; 402#else /* CONFIG_PNP */ 403static struct pnp_driver smsc_ircc_pnp_driver; 404#endif 405 406/******************************************************************************* 407 * 408 * 409 * SMSC-ircc stuff 410 * 411 * 412 *******************************************************************************/ 413 414static int __init smsc_ircc_legacy_probe(void) 415{ 416 int ret = 0; 417 418#ifdef CONFIG_PCI 419 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) { 420 /* Ignore errors from preconfiguration */ 421 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name); 422 } 423#endif 424 425 if (ircc_fir > 0 && ircc_sir > 0) { 426 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir); 427 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir); 428 429 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq)) 430 ret = -ENODEV; 431 } else { 432 ret = -ENODEV; 433 434 /* try user provided configuration register base address */ 435 if (ircc_cfg > 0) { 436 IRDA_MESSAGE(" Overriding configuration address " 437 "0x%04x\n", ircc_cfg); 438 if (!smsc_superio_fdc(ircc_cfg)) 439 ret = 0; 440 if (!smsc_superio_lpc(ircc_cfg)) 441 ret = 0; 442 } 443 444 if (smsc_ircc_look_for_chips() > 0) 445 ret = 0; 446 } 447 return ret; 448} 449 450/* 451 * Function smsc_ircc_init () 452 * 453 * Initialize chip. Just try to find out how many chips we are dealing with 454 * and where they are 455 */ 456static int __init smsc_ircc_init(void) 457{ 458 int ret; 459 460 IRDA_DEBUG(1, "%s\n", __func__); 461 462 ret = platform_driver_register(&smsc_ircc_driver); 463 if (ret) { 464 IRDA_ERROR("%s, Can't register driver!\n", driver_name); 465 return ret; 466 } 467 468 dev_count = 0; 469 470 if (smsc_nopnp || !pnp_platform_devices || 471 ircc_cfg || ircc_fir || ircc_sir || 472 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) { 473 ret = smsc_ircc_legacy_probe(); 474 } else { 475 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0) 476 pnp_driver_registered = 1; 477 } 478 479 if (ret) { 480 if (pnp_driver_registered) 481 pnp_unregister_driver(&smsc_ircc_pnp_driver); 482 platform_driver_unregister(&smsc_ircc_driver); 483 } 484 485 return ret; 486} 487 488static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb, 489 struct net_device *dev) 490{ 491 struct smsc_ircc_cb *self = netdev_priv(dev); 492 493 if (self->io.speed > 115200) 494 return smsc_ircc_hard_xmit_fir(skb, dev); 495 else 496 return smsc_ircc_hard_xmit_sir(skb, dev); 497} 498 499static const struct net_device_ops smsc_ircc_netdev_ops = { 500 .ndo_open = smsc_ircc_net_open, 501 .ndo_stop = smsc_ircc_net_close, 502 .ndo_do_ioctl = smsc_ircc_net_ioctl, 503 .ndo_start_xmit = smsc_ircc_net_xmit, 504#if SMSC_IRCC2_C_NET_TIMEOUT 505 .ndo_tx_timeout = smsc_ircc_timeout, 506#endif 507}; 508 509/* 510 * Function smsc_ircc_open (firbase, sirbase, dma, irq) 511 * 512 * Try to open driver instance 513 * 514 */ 515static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq) 516{ 517 struct smsc_ircc_cb *self; 518 struct net_device *dev; 519 int err; 520 521 IRDA_DEBUG(1, "%s\n", __func__); 522 523 err = smsc_ircc_present(fir_base, sir_base); 524 if (err) 525 goto err_out; 526 527 err = -ENOMEM; 528 if (dev_count >= ARRAY_SIZE(dev_self)) { 529 IRDA_WARNING("%s(), too many devices!\n", __func__); 530 goto err_out1; 531 } 532 533 /* 534 * Allocate new instance of the driver 535 */ 536 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb)); 537 if (!dev) { 538 IRDA_WARNING("%s() can't allocate net device\n", __func__); 539 goto err_out1; 540 } 541 542#if SMSC_IRCC2_C_NET_TIMEOUT 543 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */ 544#endif 545 dev->netdev_ops = &smsc_ircc_netdev_ops; 546 547 self = netdev_priv(dev); 548 self->netdev = dev; 549 550 /* Make ifconfig display some details */ 551 dev->base_addr = self->io.fir_base = fir_base; 552 dev->irq = self->io.irq = irq; 553 554 /* Need to store self somewhere */ 555 dev_self[dev_count] = self; 556 spin_lock_init(&self->lock); 557 558 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE; 559 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE; 560 561 self->rx_buff.head = 562 dma_alloc_coherent(NULL, self->rx_buff.truesize, 563 &self->rx_buff_dma, GFP_KERNEL); 564 if (self->rx_buff.head == NULL) { 565 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n", 566 driver_name); 567 goto err_out2; 568 } 569 570 self->tx_buff.head = 571 dma_alloc_coherent(NULL, self->tx_buff.truesize, 572 &self->tx_buff_dma, GFP_KERNEL); 573 if (self->tx_buff.head == NULL) { 574 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n", 575 driver_name); 576 goto err_out3; 577 } 578 579 memset(self->rx_buff.head, 0, self->rx_buff.truesize); 580 memset(self->tx_buff.head, 0, self->tx_buff.truesize); 581 582 self->rx_buff.in_frame = FALSE; 583 self->rx_buff.state = OUTSIDE_FRAME; 584 self->tx_buff.data = self->tx_buff.head; 585 self->rx_buff.data = self->rx_buff.head; 586 587 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq); 588 smsc_ircc_setup_qos(self); 589 smsc_ircc_init_chip(self); 590 591 if (ircc_transceiver > 0 && 592 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS) 593 self->transceiver = ircc_transceiver; 594 else 595 smsc_ircc_probe_transceiver(self); 596 597 err = register_netdev(self->netdev); 598 if (err) { 599 IRDA_ERROR("%s, Network device registration failed!\n", 600 driver_name); 601 goto err_out4; 602 } 603 604 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME, 605 dev_count, NULL, 0); 606 if (IS_ERR(self->pldev)) { 607 err = PTR_ERR(self->pldev); 608 goto err_out5; 609 } 610 platform_set_drvdata(self->pldev, self); 611 612 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); 613 dev_count++; 614 615 return 0; 616 617 err_out5: 618 unregister_netdev(self->netdev); 619 620 err_out4: 621 dma_free_coherent(NULL, self->tx_buff.truesize, 622 self->tx_buff.head, self->tx_buff_dma); 623 err_out3: 624 dma_free_coherent(NULL, self->rx_buff.truesize, 625 self->rx_buff.head, self->rx_buff_dma); 626 err_out2: 627 free_netdev(self->netdev); 628 dev_self[dev_count] = NULL; 629 err_out1: 630 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); 631 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); 632 err_out: 633 return err; 634} 635 636/* 637 * Function smsc_ircc_present(fir_base, sir_base) 638 * 639 * Check the smsc-ircc chip presence 640 * 641 */ 642static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base) 643{ 644 unsigned char low, high, chip, config, dma, irq, version; 645 646 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT, 647 driver_name)) { 648 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n", 649 __func__, fir_base); 650 goto out1; 651 } 652 653 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT, 654 driver_name)) { 655 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n", 656 __func__, sir_base); 657 goto out2; 658 } 659 660 register_bank(fir_base, 3); 661 662 high = inb(fir_base + IRCC_ID_HIGH); 663 low = inb(fir_base + IRCC_ID_LOW); 664 chip = inb(fir_base + IRCC_CHIP_ID); 665 version = inb(fir_base + IRCC_VERSION); 666 config = inb(fir_base + IRCC_INTERFACE); 667 dma = config & IRCC_INTERFACE_DMA_MASK; 668 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; 669 670 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) { 671 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n", 672 __func__, fir_base); 673 goto out3; 674 } 675 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, " 676 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n", 677 chip & 0x0f, version, fir_base, sir_base, dma, irq); 678 679 return 0; 680 681 out3: 682 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); 683 out2: 684 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); 685 out1: 686 return -ENODEV; 687} 688 689/* 690 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq) 691 * 692 * Setup I/O 693 * 694 */ 695static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, 696 unsigned int fir_base, unsigned int sir_base, 697 u8 dma, u8 irq) 698{ 699 unsigned char config, chip_dma, chip_irq; 700 701 register_bank(fir_base, 3); 702 config = inb(fir_base + IRCC_INTERFACE); 703 chip_dma = config & IRCC_INTERFACE_DMA_MASK; 704 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; 705 706 self->io.fir_base = fir_base; 707 self->io.sir_base = sir_base; 708 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT; 709 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT; 710 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE; 711 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED; 712 713 if (irq != IRQ_INVAL) { 714 if (irq != chip_irq) 715 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n", 716 driver_name, chip_irq, irq); 717 self->io.irq = irq; 718 } else 719 self->io.irq = chip_irq; 720 721 if (dma != DMA_INVAL) { 722 if (dma != chip_dma) 723 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n", 724 driver_name, chip_dma, dma); 725 self->io.dma = dma; 726 } else 727 self->io.dma = chip_dma; 728 729} 730 731/* 732 * Function smsc_ircc_setup_qos(self) 733 * 734 * Setup qos 735 * 736 */ 737static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self) 738{ 739 /* Initialize QoS for this device */ 740 irda_init_max_qos_capabilies(&self->qos); 741 742 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| 743 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); 744 745 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME; 746 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE; 747 irda_qos_bits_to_value(&self->qos); 748} 749 750/* 751 * Function smsc_ircc_init_chip(self) 752 * 753 * Init chip 754 * 755 */ 756static void smsc_ircc_init_chip(struct smsc_ircc_cb *self) 757{ 758 int iobase = self->io.fir_base; 759 760 register_bank(iobase, 0); 761 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); 762 outb(0x00, iobase + IRCC_MASTER); 763 764 register_bank(iobase, 1); 765 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), 766 iobase + IRCC_SCE_CFGA); 767 768#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */ 769 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), 770 iobase + IRCC_SCE_CFGB); 771#else 772 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), 773 iobase + IRCC_SCE_CFGB); 774#endif 775 (void) inb(iobase + IRCC_FIFO_THRESHOLD); 776 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); 777 778 register_bank(iobase, 4); 779 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); 780 781 register_bank(iobase, 0); 782 outb(0, iobase + IRCC_LCR_A); 783 784 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); 785 786 /* Power on device */ 787 outb(0x00, iobase + IRCC_MASTER); 788} 789 790/* 791 * Function smsc_ircc_net_ioctl (dev, rq, cmd) 792 * 793 * Process IOCTL commands for this device 794 * 795 */ 796static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 797{ 798 struct if_irda_req *irq = (struct if_irda_req *) rq; 799 struct smsc_ircc_cb *self; 800 unsigned long flags; 801 int ret = 0; 802 803 IRDA_ASSERT(dev != NULL, return -1;); 804 805 self = netdev_priv(dev); 806 807 IRDA_ASSERT(self != NULL, return -1;); 808 809 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd); 810 811 switch (cmd) { 812 case SIOCSBANDWIDTH: /* Set bandwidth */ 813 if (!capable(CAP_NET_ADMIN)) 814 ret = -EPERM; 815 else { 816 /* Make sure we are the only one touching 817 * self->io.speed and the hardware - Jean II */ 818 spin_lock_irqsave(&self->lock, flags); 819 smsc_ircc_change_speed(self, irq->ifr_baudrate); 820 spin_unlock_irqrestore(&self->lock, flags); 821 } 822 break; 823 case SIOCSMEDIABUSY: /* Set media busy */ 824 if (!capable(CAP_NET_ADMIN)) { 825 ret = -EPERM; 826 break; 827 } 828 829 irda_device_set_media_busy(self->netdev, TRUE); 830 break; 831 case SIOCGRECEIVING: /* Check if we are receiving right now */ 832 irq->ifr_receiving = smsc_ircc_is_receiving(self); 833 break; 834 default: 835 ret = -EOPNOTSUPP; 836 } 837 838 return ret; 839} 840 841#if SMSC_IRCC2_C_NET_TIMEOUT 842/* 843 * Function smsc_ircc_timeout (struct net_device *dev) 844 * 845 * The networking timeout management. 846 * 847 */ 848 849static void smsc_ircc_timeout(struct net_device *dev) 850{ 851 struct smsc_ircc_cb *self = netdev_priv(dev); 852 unsigned long flags; 853 854 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n", 855 dev->name, self->io.speed); 856 spin_lock_irqsave(&self->lock, flags); 857 smsc_ircc_sir_start(self); 858 smsc_ircc_change_speed(self, self->io.speed); 859 dev->trans_start = jiffies; /* prevent tx timeout */ 860 netif_wake_queue(dev); 861 spin_unlock_irqrestore(&self->lock, flags); 862} 863#endif 864 865/* 866 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev) 867 * 868 * Transmits the current frame until FIFO is full, then 869 * waits until the next transmit interrupt, and continues until the 870 * frame is transmitted. 871 */ 872static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb, 873 struct net_device *dev) 874{ 875 struct smsc_ircc_cb *self; 876 unsigned long flags; 877 s32 speed; 878 879 IRDA_DEBUG(1, "%s\n", __func__); 880 881 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;); 882 883 self = netdev_priv(dev); 884 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;); 885 886 netif_stop_queue(dev); 887 888 /* Make sure test of self->io.speed & speed change are atomic */ 889 spin_lock_irqsave(&self->lock, flags); 890 891 /* Check if we need to change the speed */ 892 speed = irda_get_next_speed(skb); 893 if (speed != self->io.speed && speed != -1) { 894 /* Check for empty frame */ 895 if (!skb->len) { 896 /* 897 * We send frames one by one in SIR mode (no 898 * pipelining), so at this point, if we were sending 899 * a previous frame, we just received the interrupt 900 * telling us it is finished (UART_IIR_THRI). 901 * Therefore, waiting for the transmitter to really 902 * finish draining the fifo won't take too long. 903 * And the interrupt handler is not expected to run. 904 * - Jean II */ 905 smsc_ircc_sir_wait_hw_transmitter_finish(self); 906 smsc_ircc_change_speed(self, speed); 907 spin_unlock_irqrestore(&self->lock, flags); 908 dev_kfree_skb(skb); 909 return NETDEV_TX_OK; 910 } 911 self->new_speed = speed; 912 } 913 914 /* Init tx buffer */ 915 self->tx_buff.data = self->tx_buff.head; 916 917 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */ 918 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, 919 self->tx_buff.truesize); 920 921 dev->stats.tx_bytes += self->tx_buff.len; 922 923 /* Turn on transmit finished interrupt. Will fire immediately! */ 924 outb(UART_IER_THRI, self->io.sir_base + UART_IER); 925 926 spin_unlock_irqrestore(&self->lock, flags); 927 928 dev_kfree_skb(skb); 929 930 return NETDEV_TX_OK; 931} 932 933/* 934 * Function smsc_ircc_set_fir_speed (self, baud) 935 * 936 * Change the speed of the device 937 * 938 */ 939static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed) 940{ 941 int fir_base, ir_mode, ctrl, fast; 942 943 IRDA_ASSERT(self != NULL, return;); 944 fir_base = self->io.fir_base; 945 946 self->io.speed = speed; 947 948 switch (speed) { 949 default: 950 case 576000: 951 ir_mode = IRCC_CFGA_IRDA_HDLC; 952 ctrl = IRCC_CRC; 953 fast = 0; 954 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__); 955 break; 956 case 1152000: 957 ir_mode = IRCC_CFGA_IRDA_HDLC; 958 ctrl = IRCC_1152 | IRCC_CRC; 959 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA; 960 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", 961 __func__); 962 break; 963 case 4000000: 964 ir_mode = IRCC_CFGA_IRDA_4PPM; 965 ctrl = IRCC_CRC; 966 fast = IRCC_LCR_A_FAST; 967 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", 968 __func__); 969 break; 970 } 971 972 register_bank(fir_base, 1); 973 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA); 974 975 register_bank(fir_base, 4); 976 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); 977} 978 979/* 980 * Function smsc_ircc_fir_start(self) 981 * 982 * Change the speed of the device 983 * 984 */ 985static void smsc_ircc_fir_start(struct smsc_ircc_cb *self) 986{ 987 struct net_device *dev; 988 int fir_base; 989 990 IRDA_DEBUG(1, "%s\n", __func__); 991 992 IRDA_ASSERT(self != NULL, return;); 993 dev = self->netdev; 994 IRDA_ASSERT(dev != NULL, return;); 995 996 fir_base = self->io.fir_base; 997 998 /* Reset everything */ 999 1000 /* Clear FIFO */ 1001 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); 1002 1003 /* Enable interrupt */ 1004 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/ 1005 1006 register_bank(fir_base, 1); 1007 1008 /* Select the TX/RX interface */ 1009#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */ 1010 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), 1011 fir_base + IRCC_SCE_CFGB); 1012#else 1013 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), 1014 fir_base + IRCC_SCE_CFGB); 1015#endif 1016 (void) inb(fir_base + IRCC_FIFO_THRESHOLD); 1017 1018 /* Enable SCE interrupts */ 1019 outb(0, fir_base + IRCC_MASTER); 1020 register_bank(fir_base, 0); 1021 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER); 1022 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER); 1023} 1024 1025/* 1026 * Function smsc_ircc_fir_stop(self, baud) 1027 * 1028 * Change the speed of the device 1029 * 1030 */ 1031static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self) 1032{ 1033 int fir_base; 1034 1035 IRDA_DEBUG(1, "%s\n", __func__); 1036 1037 IRDA_ASSERT(self != NULL, return;); 1038 1039 fir_base = self->io.fir_base; 1040 register_bank(fir_base, 0); 1041 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/ 1042 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); 1043} 1044 1045 1046/* 1047 * Function smsc_ircc_change_speed(self, baud) 1048 * 1049 * Change the speed of the device 1050 * 1051 * This function *must* be called with spinlock held, because it may 1052 * be called from the irq handler. - Jean II 1053 */ 1054static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed) 1055{ 1056 struct net_device *dev; 1057 int last_speed_was_sir; 1058 1059 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed); 1060 1061 IRDA_ASSERT(self != NULL, return;); 1062 dev = self->netdev; 1063 1064 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED; 1065 1066 1067 if (self->io.speed == 0) 1068 smsc_ircc_sir_start(self); 1069 1070 1071 if (self->io.speed != speed) 1072 smsc_ircc_set_transceiver_for_speed(self, speed); 1073 1074 self->io.speed = speed; 1075 1076 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) { 1077 if (!last_speed_was_sir) { 1078 smsc_ircc_fir_stop(self); 1079 smsc_ircc_sir_start(self); 1080 } 1081 smsc_ircc_set_sir_speed(self, speed); 1082 } else { 1083 if (last_speed_was_sir) { 1084 #if SMSC_IRCC2_C_SIR_STOP 1085 smsc_ircc_sir_stop(self); 1086 #endif 1087 smsc_ircc_fir_start(self); 1088 } 1089 smsc_ircc_set_fir_speed(self, speed); 1090 1091 /* Be ready for incoming frames */ 1092 smsc_ircc_dma_receive(self); 1093 } 1094 1095 netif_wake_queue(dev); 1096} 1097 1098/* 1099 * Function smsc_ircc_set_sir_speed (self, speed) 1100 * 1101 * Set speed of IrDA port to specified baudrate 1102 * 1103 */ 1104static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed) 1105{ 1106 int iobase; 1107 int fcr; /* FIFO control reg */ 1108 int lcr; /* Line control reg */ 1109 int divisor; 1110 1111 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed); 1112 1113 IRDA_ASSERT(self != NULL, return;); 1114 iobase = self->io.sir_base; 1115 1116 /* Update accounting for new speed */ 1117 self->io.speed = speed; 1118 1119 /* Turn off interrupts */ 1120 outb(0, iobase + UART_IER); 1121 1122 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed; 1123 1124 fcr = UART_FCR_ENABLE_FIFO; 1125 1126 /* 1127 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and 1128 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget 1129 * about this timeout since it will always be fast enough. 1130 */ 1131 fcr |= self->io.speed < 38400 ? 1132 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; 1133 1134 /* IrDA ports use 8N1 */ 1135 lcr = UART_LCR_WLEN8; 1136 1137 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ 1138 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ 1139 outb(divisor >> 8, iobase + UART_DLM); 1140 outb(lcr, iobase + UART_LCR); /* Set 8N1 */ 1141 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ 1142 1143 /* Turn on interrups */ 1144 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); 1145 1146 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed); 1147} 1148 1149 1150/* 1151 * Function smsc_ircc_hard_xmit_fir (skb, dev) 1152 * 1153 * Transmit the frame! 1154 * 1155 */ 1156static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb, 1157 struct net_device *dev) 1158{ 1159 struct smsc_ircc_cb *self; 1160 unsigned long flags; 1161 s32 speed; 1162 int mtt; 1163 1164 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;); 1165 self = netdev_priv(dev); 1166 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;); 1167 1168 netif_stop_queue(dev); 1169 1170 /* Make sure test of self->io.speed & speed change are atomic */ 1171 spin_lock_irqsave(&self->lock, flags); 1172 1173 /* Check if we need to change the speed after this frame */ 1174 speed = irda_get_next_speed(skb); 1175 if (speed != self->io.speed && speed != -1) { 1176 /* Check for empty frame */ 1177 if (!skb->len) { 1178 /* Note : you should make sure that speed changes 1179 * are not going to corrupt any outgoing frame. 1180 * Look at nsc-ircc for the gory details - Jean II */ 1181 smsc_ircc_change_speed(self, speed); 1182 spin_unlock_irqrestore(&self->lock, flags); 1183 dev_kfree_skb(skb); 1184 return NETDEV_TX_OK; 1185 } 1186 1187 self->new_speed = speed; 1188 } 1189 1190 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len); 1191 1192 self->tx_buff.len = skb->len; 1193 self->tx_buff.data = self->tx_buff.head; 1194 1195 mtt = irda_get_mtt(skb); 1196 if (mtt) { 1197 int bofs; 1198 1199 /* 1200 * Compute how many BOFs (STA or PA's) we need to waste the 1201 * min turn time given the speed of the link. 1202 */ 1203 bofs = mtt * (self->io.speed / 1000) / 8000; 1204 if (bofs > 4095) 1205 bofs = 4095; 1206 1207 smsc_ircc_dma_xmit(self, bofs); 1208 } else { 1209 /* Transmit frame */ 1210 smsc_ircc_dma_xmit(self, 0); 1211 } 1212 1213 spin_unlock_irqrestore(&self->lock, flags); 1214 dev_kfree_skb(skb); 1215 1216 return NETDEV_TX_OK; 1217} 1218 1219/* 1220 * Function smsc_ircc_dma_xmit (self, bofs) 1221 * 1222 * Transmit data using DMA 1223 * 1224 */ 1225static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs) 1226{ 1227 int iobase = self->io.fir_base; 1228 u8 ctrl; 1229 1230 IRDA_DEBUG(3, "%s\n", __func__); 1231 /* Disable Rx */ 1232 register_bank(iobase, 0); 1233 outb(0x00, iobase + IRCC_LCR_B); 1234 register_bank(iobase, 1); 1235 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1236 iobase + IRCC_SCE_CFGB); 1237 1238 self->io.direction = IO_XMIT; 1239 1240 /* Set BOF additional count for generating the min turn time */ 1241 register_bank(iobase, 4); 1242 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); 1243 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; 1244 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); 1245 1246 /* Set max Tx frame size */ 1247 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); 1248 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); 1249 1250 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/ 1251 1252 /* Enable burst mode chip Tx DMA */ 1253 register_bank(iobase, 1); 1254 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | 1255 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); 1256 1257 /* Setup DMA controller (must be done after enabling chip DMA) */ 1258 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, 1259 DMA_TX_MODE); 1260 1261 /* Enable interrupt */ 1262 1263 register_bank(iobase, 0); 1264 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1265 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); 1266 1267 /* Enable transmit */ 1268 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); 1269} 1270 1271/* 1272 * Function smsc_ircc_dma_xmit_complete (self) 1273 * 1274 * The transfer of a frame in finished. This function will only be called 1275 * by the interrupt handler 1276 * 1277 */ 1278static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self) 1279{ 1280 int iobase = self->io.fir_base; 1281 1282 IRDA_DEBUG(3, "%s\n", __func__); 1283 register_bank(iobase, 1); 1284 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1285 iobase + IRCC_SCE_CFGB); 1286 1287 /* Check for underrun! */ 1288 register_bank(iobase, 0); 1289 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { 1290 self->netdev->stats.tx_errors++; 1291 self->netdev->stats.tx_fifo_errors++; 1292 1293 /* Reset error condition */ 1294 register_bank(iobase, 0); 1295 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); 1296 outb(0x00, iobase + IRCC_MASTER); 1297 } else { 1298 self->netdev->stats.tx_packets++; 1299 self->netdev->stats.tx_bytes += self->tx_buff.len; 1300 } 1301 1302 /* Check if it's time to change the speed */ 1303 if (self->new_speed) { 1304 smsc_ircc_change_speed(self, self->new_speed); 1305 self->new_speed = 0; 1306 } 1307 1308 netif_wake_queue(self->netdev); 1309} 1310 1311/* 1312 * Function smsc_ircc_dma_receive(self) 1313 * 1314 * Get ready for receiving a frame. The device will initiate a DMA 1315 * if it starts to receive a frame. 1316 * 1317 */ 1318static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self) 1319{ 1320 int iobase = self->io.fir_base; 1321 1322 /* Disable Tx */ 1323 register_bank(iobase, 0); 1324 outb(0x00, iobase + IRCC_LCR_B); 1325 1326 /* Turn off chip DMA */ 1327 register_bank(iobase, 1); 1328 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1329 iobase + IRCC_SCE_CFGB); 1330 1331 self->io.direction = IO_RECV; 1332 self->rx_buff.data = self->rx_buff.head; 1333 1334 /* Set max Rx frame size */ 1335 register_bank(iobase, 4); 1336 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); 1337 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); 1338 1339 /* Setup DMA controller */ 1340 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, 1341 DMA_RX_MODE); 1342 1343 /* Enable burst mode chip Rx DMA */ 1344 register_bank(iobase, 1); 1345 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | 1346 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); 1347 1348 /* Enable interrupt */ 1349 register_bank(iobase, 0); 1350 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1351 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); 1352 1353 /* Enable receiver */ 1354 register_bank(iobase, 0); 1355 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE, 1356 iobase + IRCC_LCR_B); 1357 1358 return 0; 1359} 1360 1361/* 1362 * Function smsc_ircc_dma_receive_complete(self) 1363 * 1364 * Finished with receiving frames 1365 * 1366 */ 1367static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self) 1368{ 1369 struct sk_buff *skb; 1370 int len, msgcnt, lsr; 1371 int iobase = self->io.fir_base; 1372 1373 register_bank(iobase, 0); 1374 1375 IRDA_DEBUG(3, "%s\n", __func__); 1376 register_bank(iobase, 0); 1377 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); 1378 lsr= inb(iobase + IRCC_LSR); 1379 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; 1380 1381 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__, 1382 get_dma_residue(self->io.dma)); 1383 1384 len = self->rx_buff.truesize - get_dma_residue(self->io.dma); 1385 1386 /* Look for errors */ 1387 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) { 1388 self->netdev->stats.rx_errors++; 1389 if (lsr & IRCC_LSR_FRAME_ERROR) 1390 self->netdev->stats.rx_frame_errors++; 1391 if (lsr & IRCC_LSR_CRC_ERROR) 1392 self->netdev->stats.rx_crc_errors++; 1393 if (lsr & IRCC_LSR_SIZE_ERROR) 1394 self->netdev->stats.rx_length_errors++; 1395 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) 1396 self->netdev->stats.rx_length_errors++; 1397 return; 1398 } 1399 1400 /* Remove CRC */ 1401 len -= self->io.speed < 4000000 ? 2 : 4; 1402 1403 if (len < 2 || len > 2050) { 1404 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len); 1405 return; 1406 } 1407 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len); 1408 1409 skb = dev_alloc_skb(len + 1); 1410 if (!skb) { 1411 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n", 1412 __func__); 1413 return; 1414 } 1415 /* Make sure IP header gets aligned */ 1416 skb_reserve(skb, 1); 1417 1418 memcpy(skb_put(skb, len), self->rx_buff.data, len); 1419 self->netdev->stats.rx_packets++; 1420 self->netdev->stats.rx_bytes += len; 1421 1422 skb->dev = self->netdev; 1423 skb_reset_mac_header(skb); 1424 skb->protocol = htons(ETH_P_IRDA); 1425 netif_rx(skb); 1426} 1427 1428/* 1429 * Function smsc_ircc_sir_receive (self) 1430 * 1431 * Receive one frame from the infrared port 1432 * 1433 */ 1434static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self) 1435{ 1436 int boguscount = 0; 1437 int iobase; 1438 1439 IRDA_ASSERT(self != NULL, return;); 1440 1441 iobase = self->io.sir_base; 1442 1443 /* 1444 * Receive all characters in Rx FIFO, unwrap and unstuff them. 1445 * async_unwrap_char will deliver all found frames 1446 */ 1447 do { 1448 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff, 1449 inb(iobase + UART_RX)); 1450 1451 /* Make sure we don't stay here to long */ 1452 if (boguscount++ > 32) { 1453 IRDA_DEBUG(2, "%s(), breaking!\n", __func__); 1454 break; 1455 } 1456 } while (inb(iobase + UART_LSR) & UART_LSR_DR); 1457} 1458 1459 1460/* 1461 * Function smsc_ircc_interrupt (irq, dev_id, regs) 1462 * 1463 * An interrupt from the chip has arrived. Time to do some work 1464 * 1465 */ 1466static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id) 1467{ 1468 struct net_device *dev = dev_id; 1469 struct smsc_ircc_cb *self = netdev_priv(dev); 1470 int iobase, iir, lcra, lsr; 1471 irqreturn_t ret = IRQ_NONE; 1472 1473 /* Serialise the interrupt handler in various CPUs, stop Tx path */ 1474 spin_lock(&self->lock); 1475 1476 /* Check if we should use the SIR interrupt handler */ 1477 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) { 1478 ret = smsc_ircc_interrupt_sir(dev); 1479 goto irq_ret_unlock; 1480 } 1481 1482 iobase = self->io.fir_base; 1483 1484 register_bank(iobase, 0); 1485 iir = inb(iobase + IRCC_IIR); 1486 if (iir == 0) 1487 goto irq_ret_unlock; 1488 ret = IRQ_HANDLED; 1489 1490 /* Disable interrupts */ 1491 outb(0, iobase + IRCC_IER); 1492 lcra = inb(iobase + IRCC_LCR_A); 1493 lsr = inb(iobase + IRCC_LSR); 1494 1495 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir); 1496 1497 if (iir & IRCC_IIR_EOM) { 1498 if (self->io.direction == IO_RECV) 1499 smsc_ircc_dma_receive_complete(self); 1500 else 1501 smsc_ircc_dma_xmit_complete(self); 1502 1503 smsc_ircc_dma_receive(self); 1504 } 1505 1506 if (iir & IRCC_IIR_ACTIVE_FRAME) { 1507 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/ 1508 } 1509 1510 /* Enable interrupts again */ 1511 1512 register_bank(iobase, 0); 1513 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1514 1515 irq_ret_unlock: 1516 spin_unlock(&self->lock); 1517 1518 return ret; 1519} 1520 1521/* 1522 * Function irport_interrupt_sir (irq, dev_id) 1523 * 1524 * Interrupt handler for SIR modes 1525 */ 1526static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev) 1527{ 1528 struct smsc_ircc_cb *self = netdev_priv(dev); 1529 int boguscount = 0; 1530 int iobase; 1531 int iir, lsr; 1532 1533 /* Already locked comming here in smsc_ircc_interrupt() */ 1534 /*spin_lock(&self->lock);*/ 1535 1536 iobase = self->io.sir_base; 1537 1538 iir = inb(iobase + UART_IIR) & UART_IIR_ID; 1539 if (iir == 0) 1540 return IRQ_NONE; 1541 while (iir) { 1542 /* Clear interrupt */ 1543 lsr = inb(iobase + UART_LSR); 1544 1545 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", 1546 __func__, iir, lsr, iobase); 1547 1548 switch (iir) { 1549 case UART_IIR_RLSI: 1550 IRDA_DEBUG(2, "%s(), RLSI\n", __func__); 1551 break; 1552 case UART_IIR_RDI: 1553 /* Receive interrupt */ 1554 smsc_ircc_sir_receive(self); 1555 break; 1556 case UART_IIR_THRI: 1557 if (lsr & UART_LSR_THRE) 1558 /* Transmitter ready for data */ 1559 smsc_ircc_sir_write_wakeup(self); 1560 break; 1561 default: 1562 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n", 1563 __func__, iir); 1564 break; 1565 } 1566 1567 /* Make sure we don't stay here to long */ 1568 if (boguscount++ > 100) 1569 break; 1570 1571 iir = inb(iobase + UART_IIR) & UART_IIR_ID; 1572 } 1573 /*spin_unlock(&self->lock);*/ 1574 return IRQ_HANDLED; 1575} 1576 1577 1578 1579static int smsc_ircc_request_irq(struct smsc_ircc_cb *self) 1580{ 1581 int error; 1582 1583 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0, 1584 self->netdev->name, self->netdev); 1585 if (error) 1586 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n", 1587 __func__, self->io.irq, error); 1588 1589 return error; 1590} 1591 1592static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self) 1593{ 1594 unsigned long flags; 1595 1596 spin_lock_irqsave(&self->lock, flags); 1597 1598 self->io.speed = 0; 1599 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); 1600 1601 spin_unlock_irqrestore(&self->lock, flags); 1602} 1603 1604static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self) 1605{ 1606 int iobase = self->io.fir_base; 1607 unsigned long flags; 1608 1609 spin_lock_irqsave(&self->lock, flags); 1610 1611 register_bank(iobase, 0); 1612 outb(0, iobase + IRCC_IER); 1613 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); 1614 outb(0x00, iobase + IRCC_MASTER); 1615 1616 spin_unlock_irqrestore(&self->lock, flags); 1617} 1618 1619 1620/* 1621 * Function smsc_ircc_net_open (dev) 1622 * 1623 * Start the device 1624 * 1625 */ 1626static int smsc_ircc_net_open(struct net_device *dev) 1627{ 1628 struct smsc_ircc_cb *self; 1629 char hwname[16]; 1630 1631 IRDA_DEBUG(1, "%s\n", __func__); 1632 1633 IRDA_ASSERT(dev != NULL, return -1;); 1634 self = netdev_priv(dev); 1635 IRDA_ASSERT(self != NULL, return 0;); 1636 1637 if (self->io.suspended) { 1638 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__); 1639 return -EAGAIN; 1640 } 1641 1642 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name, 1643 (void *) dev)) { 1644 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n", 1645 __func__, self->io.irq); 1646 return -EAGAIN; 1647 } 1648 1649 smsc_ircc_start_interrupts(self); 1650 1651 /* Give self a hardware name */ 1652 /* It would be cool to offer the chip revision here - Jean II */ 1653 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base); 1654 1655 /* 1656 * Open new IrLAP layer instance, now that everything should be 1657 * initialized properly 1658 */ 1659 self->irlap = irlap_open(dev, &self->qos, hwname); 1660 1661 /* 1662 * Always allocate the DMA channel after the IRQ, 1663 * and clean up on failure. 1664 */ 1665 if (request_dma(self->io.dma, dev->name)) { 1666 smsc_ircc_net_close(dev); 1667 1668 IRDA_WARNING("%s(), unable to allocate DMA=%d\n", 1669 __func__, self->io.dma); 1670 return -EAGAIN; 1671 } 1672 1673 netif_start_queue(dev); 1674 1675 return 0; 1676} 1677 1678/* 1679 * Function smsc_ircc_net_close (dev) 1680 * 1681 * Stop the device 1682 * 1683 */ 1684static int smsc_ircc_net_close(struct net_device *dev) 1685{ 1686 struct smsc_ircc_cb *self; 1687 1688 IRDA_DEBUG(1, "%s\n", __func__); 1689 1690 IRDA_ASSERT(dev != NULL, return -1;); 1691 self = netdev_priv(dev); 1692 IRDA_ASSERT(self != NULL, return 0;); 1693 1694 /* Stop device */ 1695 netif_stop_queue(dev); 1696 1697 /* Stop and remove instance of IrLAP */ 1698 if (self->irlap) 1699 irlap_close(self->irlap); 1700 self->irlap = NULL; 1701 1702 smsc_ircc_stop_interrupts(self); 1703 1704 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */ 1705 if (!self->io.suspended) 1706 free_irq(self->io.irq, dev); 1707 1708 disable_dma(self->io.dma); 1709 free_dma(self->io.dma); 1710 1711 return 0; 1712} 1713 1714static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state) 1715{ 1716 struct smsc_ircc_cb *self = platform_get_drvdata(dev); 1717 1718 if (!self->io.suspended) { 1719 IRDA_DEBUG(1, "%s, Suspending\n", driver_name); 1720 1721 rtnl_lock(); 1722 if (netif_running(self->netdev)) { 1723 netif_device_detach(self->netdev); 1724 smsc_ircc_stop_interrupts(self); 1725 free_irq(self->io.irq, self->netdev); 1726 disable_dma(self->io.dma); 1727 } 1728 self->io.suspended = 1; 1729 rtnl_unlock(); 1730 } 1731 1732 return 0; 1733} 1734 1735static int smsc_ircc_resume(struct platform_device *dev) 1736{ 1737 struct smsc_ircc_cb *self = platform_get_drvdata(dev); 1738 1739 if (self->io.suspended) { 1740 IRDA_DEBUG(1, "%s, Waking up\n", driver_name); 1741 1742 rtnl_lock(); 1743 smsc_ircc_init_chip(self); 1744 if (netif_running(self->netdev)) { 1745 if (smsc_ircc_request_irq(self)) { 1746 /* 1747 * Don't fail resume process, just kill this 1748 * network interface 1749 */ 1750 unregister_netdevice(self->netdev); 1751 } else { 1752 enable_dma(self->io.dma); 1753 smsc_ircc_start_interrupts(self); 1754 netif_device_attach(self->netdev); 1755 } 1756 } 1757 self->io.suspended = 0; 1758 rtnl_unlock(); 1759 } 1760 return 0; 1761} 1762 1763/* 1764 * Function smsc_ircc_close (self) 1765 * 1766 * Close driver instance 1767 * 1768 */ 1769static int __exit smsc_ircc_close(struct smsc_ircc_cb *self) 1770{ 1771 IRDA_DEBUG(1, "%s\n", __func__); 1772 1773 IRDA_ASSERT(self != NULL, return -1;); 1774 1775 platform_device_unregister(self->pldev); 1776 1777 /* Remove netdevice */ 1778 unregister_netdev(self->netdev); 1779 1780 smsc_ircc_stop_interrupts(self); 1781 1782 /* Release the PORTS that this driver is using */ 1783 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__, 1784 self->io.fir_base); 1785 1786 release_region(self->io.fir_base, self->io.fir_ext); 1787 1788 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__, 1789 self->io.sir_base); 1790 1791 release_region(self->io.sir_base, self->io.sir_ext); 1792 1793 if (self->tx_buff.head) 1794 dma_free_coherent(NULL, self->tx_buff.truesize, 1795 self->tx_buff.head, self->tx_buff_dma); 1796 1797 if (self->rx_buff.head) 1798 dma_free_coherent(NULL, self->rx_buff.truesize, 1799 self->rx_buff.head, self->rx_buff_dma); 1800 1801 free_netdev(self->netdev); 1802 1803 return 0; 1804} 1805 1806static void __exit smsc_ircc_cleanup(void) 1807{ 1808 int i; 1809 1810 IRDA_DEBUG(1, "%s\n", __func__); 1811 1812 for (i = 0; i < 2; i++) { 1813 if (dev_self[i]) 1814 smsc_ircc_close(dev_self[i]); 1815 } 1816 1817 if (pnp_driver_registered) 1818 pnp_unregister_driver(&smsc_ircc_pnp_driver); 1819 1820 platform_driver_unregister(&smsc_ircc_driver); 1821} 1822 1823/* 1824 * Start SIR operations 1825 * 1826 * This function *must* be called with spinlock held, because it may 1827 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II 1828 */ 1829static void smsc_ircc_sir_start(struct smsc_ircc_cb *self) 1830{ 1831 struct net_device *dev; 1832 int fir_base, sir_base; 1833 1834 IRDA_DEBUG(3, "%s\n", __func__); 1835 1836 IRDA_ASSERT(self != NULL, return;); 1837 dev = self->netdev; 1838 IRDA_ASSERT(dev != NULL, return;); 1839 1840 fir_base = self->io.fir_base; 1841 sir_base = self->io.sir_base; 1842 1843 /* Reset everything */ 1844 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER); 1845 1846 #if SMSC_IRCC2_C_SIR_STOP 1847 /*smsc_ircc_sir_stop(self);*/ 1848 #endif 1849 1850 register_bank(fir_base, 1); 1851 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA); 1852 1853 /* Initialize UART */ 1854 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */ 1855 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR); 1856 1857 /* Turn on interrups */ 1858 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER); 1859 1860 IRDA_DEBUG(3, "%s() - exit\n", __func__); 1861 1862 outb(0x00, fir_base + IRCC_MASTER); 1863} 1864 1865#if SMSC_IRCC2_C_SIR_STOP 1866void smsc_ircc_sir_stop(struct smsc_ircc_cb *self) 1867{ 1868 int iobase; 1869 1870 IRDA_DEBUG(3, "%s\n", __func__); 1871 iobase = self->io.sir_base; 1872 1873 /* Reset UART */ 1874 outb(0, iobase + UART_MCR); 1875 1876 /* Turn off interrupts */ 1877 outb(0, iobase + UART_IER); 1878} 1879#endif 1880 1881/* 1882 * Function smsc_sir_write_wakeup (self) 1883 * 1884 * Called by the SIR interrupt handler when there's room for more data. 1885 * If we have more packets to send, we send them here. 1886 * 1887 */ 1888static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self) 1889{ 1890 int actual = 0; 1891 int iobase; 1892 int fcr; 1893 1894 IRDA_ASSERT(self != NULL, return;); 1895 1896 IRDA_DEBUG(4, "%s\n", __func__); 1897 1898 iobase = self->io.sir_base; 1899 1900 /* Finished with frame? */ 1901 if (self->tx_buff.len > 0) { 1902 /* Write data left in transmit buffer */ 1903 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size, 1904 self->tx_buff.data, self->tx_buff.len); 1905 self->tx_buff.data += actual; 1906 self->tx_buff.len -= actual; 1907 } else { 1908 1909 /*if (self->tx_buff.len ==0) {*/ 1910 1911 /* 1912 * Now serial buffer is almost free & we can start 1913 * transmission of another packet. But first we must check 1914 * if we need to change the speed of the hardware 1915 */ 1916 if (self->new_speed) { 1917 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n", 1918 __func__, self->new_speed); 1919 smsc_ircc_sir_wait_hw_transmitter_finish(self); 1920 smsc_ircc_change_speed(self, self->new_speed); 1921 self->new_speed = 0; 1922 } else { 1923 /* Tell network layer that we want more frames */ 1924 netif_wake_queue(self->netdev); 1925 } 1926 self->netdev->stats.tx_packets++; 1927 1928 if (self->io.speed <= 115200) { 1929 /* 1930 * Reset Rx FIFO to make sure that all reflected transmit data 1931 * is discarded. This is needed for half duplex operation 1932 */ 1933 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; 1934 fcr |= self->io.speed < 38400 ? 1935 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; 1936 1937 outb(fcr, iobase + UART_FCR); 1938 1939 /* Turn on receive interrupts */ 1940 outb(UART_IER_RDI, iobase + UART_IER); 1941 } 1942 } 1943} 1944 1945/* 1946 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len) 1947 * 1948 * Fill Tx FIFO with transmit data 1949 * 1950 */ 1951static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) 1952{ 1953 int actual = 0; 1954 1955 /* Tx FIFO should be empty! */ 1956 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { 1957 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__); 1958 return 0; 1959 } 1960 1961 /* Fill FIFO with current frame */ 1962 while (fifo_size-- > 0 && actual < len) { 1963 /* Transmit next byte */ 1964 outb(buf[actual], iobase + UART_TX); 1965 actual++; 1966 } 1967 return actual; 1968} 1969 1970/* 1971 * Function smsc_ircc_is_receiving (self) 1972 * 1973 * Returns true is we are currently receiving data 1974 * 1975 */ 1976static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self) 1977{ 1978 return (self->rx_buff.state != OUTSIDE_FRAME); 1979} 1980 1981 1982/* 1983 * Function smsc_ircc_probe_transceiver(self) 1984 * 1985 * Tries to find the used Transceiver 1986 * 1987 */ 1988static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self) 1989{ 1990 unsigned int i; 1991 1992 IRDA_ASSERT(self != NULL, return;); 1993 1994 for (i = 0; smsc_transceivers[i].name != NULL; i++) 1995 if (smsc_transceivers[i].probe(self->io.fir_base)) { 1996 IRDA_MESSAGE(" %s transceiver found\n", 1997 smsc_transceivers[i].name); 1998 self->transceiver= i + 1; 1999 return; 2000 } 2001 2002 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n", 2003 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name); 2004 2005 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER; 2006} 2007 2008 2009/* 2010 * Function smsc_ircc_set_transceiver_for_speed(self, speed) 2011 * 2012 * Set the transceiver according to the speed 2013 * 2014 */ 2015static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed) 2016{ 2017 unsigned int trx; 2018 2019 trx = self->transceiver; 2020 if (trx > 0) 2021 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed); 2022} 2023 2024/* 2025 * Function smsc_ircc_wait_hw_transmitter_finish () 2026 * 2027 * Wait for the real end of HW transmission 2028 * 2029 * The UART is a strict FIFO, and we get called only when we have finished 2030 * pushing data to the FIFO, so the maximum amount of time we must wait 2031 * is only for the FIFO to drain out. 2032 * 2033 * We use a simple calibrated loop. We may need to adjust the loop 2034 * delay (udelay) to balance I/O traffic and latency. And we also need to 2035 * adjust the maximum timeout. 2036 * It would probably be better to wait for the proper interrupt, 2037 * but it doesn't seem to be available. 2038 * 2039 * We can't use jiffies or kernel timers because : 2040 * 1) We are called from the interrupt handler, which disable softirqs, 2041 * so jiffies won't be increased 2042 * 2) Jiffies granularity is usually very coarse (10ms), and we don't 2043 * want to wait that long to detect stuck hardware. 2044 * Jean II 2045 */ 2046 2047static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) 2048{ 2049 int iobase = self->io.sir_base; 2050 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US; 2051 2052 /* Calibrated busy loop */ 2053 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) 2054 udelay(1); 2055 2056 if (count < 0) 2057 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__); 2058} 2059 2060 2061/* PROBING 2062 * 2063 * REVISIT we can be told about the device by PNP, and should use that info 2064 * instead of probing hardware and creating a platform_device ... 2065 */ 2066 2067static int __init smsc_ircc_look_for_chips(void) 2068{ 2069 struct smsc_chip_address *address; 2070 char *type; 2071 unsigned int cfg_base, found; 2072 2073 found = 0; 2074 address = possible_addresses; 2075 2076 while (address->cfg_base) { 2077 cfg_base = address->cfg_base; 2078 2079 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/ 2080 2081 if (address->type & SMSCSIO_TYPE_FDC) { 2082 type = "FDC"; 2083 if (address->type & SMSCSIO_TYPE_FLAT) 2084 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type)) 2085 found++; 2086 2087 if (address->type & SMSCSIO_TYPE_PAGED) 2088 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type)) 2089 found++; 2090 } 2091 if (address->type & SMSCSIO_TYPE_LPC) { 2092 type = "LPC"; 2093 if (address->type & SMSCSIO_TYPE_FLAT) 2094 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type)) 2095 found++; 2096 2097 if (address->type & SMSCSIO_TYPE_PAGED) 2098 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type)) 2099 found++; 2100 } 2101 address++; 2102 } 2103 return found; 2104} 2105 2106/* 2107 * Function smsc_superio_flat (chip, base, type) 2108 * 2109 * Try to get configuration of a smc SuperIO chip with flat register model 2110 * 2111 */ 2112static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type) 2113{ 2114 unsigned short firbase, sirbase; 2115 u8 mode, dma, irq; 2116 int ret = -ENODEV; 2117 2118 IRDA_DEBUG(1, "%s\n", __func__); 2119 2120 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL) 2121 return ret; 2122 2123 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase); 2124 mode = inb(cfgbase + 1); 2125 2126 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/ 2127 2128 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA)) 2129 IRDA_WARNING("%s(): IrDA not enabled\n", __func__); 2130 2131 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); 2132 sirbase = inb(cfgbase + 1) << 2; 2133 2134 /* FIR iobase */ 2135 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); 2136 firbase = inb(cfgbase + 1) << 3; 2137 2138 /* DMA */ 2139 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase); 2140 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; 2141 2142 /* IRQ */ 2143 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase); 2144 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; 2145 2146 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode); 2147 2148 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0) 2149 ret = 0; 2150 2151 /* Exit configuration */ 2152 outb(SMSCSIO_CFGEXITKEY, cfgbase); 2153 2154 return ret; 2155} 2156 2157/* 2158 * Function smsc_superio_paged (chip, base, type) 2159 * 2160 * Try to get configuration of a smc SuperIO chip with paged register model 2161 * 2162 */ 2163static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type) 2164{ 2165 unsigned short fir_io, sir_io; 2166 int ret = -ENODEV; 2167 2168 IRDA_DEBUG(1, "%s\n", __func__); 2169 2170 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL) 2171 return ret; 2172 2173 /* Select logical device (UART2) */ 2174 outb(0x07, cfg_base); 2175 outb(0x05, cfg_base + 1); 2176 2177 /* SIR iobase */ 2178 outb(0x60, cfg_base); 2179 sir_io = inb(cfg_base + 1) << 8; 2180 outb(0x61, cfg_base); 2181 sir_io |= inb(cfg_base + 1); 2182 2183 /* Read FIR base */ 2184 outb(0x62, cfg_base); 2185 fir_io = inb(cfg_base + 1) << 8; 2186 outb(0x63, cfg_base); 2187 fir_io |= inb(cfg_base + 1); 2188 outb(0x2b, cfg_base); /* ??? */ 2189 2190 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0) 2191 ret = 0; 2192 2193 /* Exit configuration */ 2194 outb(SMSCSIO_CFGEXITKEY, cfg_base); 2195 2196 return ret; 2197} 2198 2199 2200static int __init smsc_access(unsigned short cfg_base, unsigned char reg) 2201{ 2202 IRDA_DEBUG(1, "%s\n", __func__); 2203 2204 outb(reg, cfg_base); 2205 return inb(cfg_base) != reg ? -1 : 0; 2206} 2207 2208static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type) 2209{ 2210 u8 devid, xdevid, rev; 2211 2212 IRDA_DEBUG(1, "%s\n", __func__); 2213 2214 /* Leave configuration */ 2215 2216 outb(SMSCSIO_CFGEXITKEY, cfg_base); 2217 2218 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */ 2219 return NULL; 2220 2221 outb(reg, cfg_base); 2222 2223 xdevid = inb(cfg_base + 1); 2224 2225 /* Enter configuration */ 2226 2227 outb(SMSCSIO_CFGACCESSKEY, cfg_base); 2228 2229 2230 /* probe device ID */ 2231 2232 if (smsc_access(cfg_base, reg)) 2233 return NULL; 2234 2235 devid = inb(cfg_base + 1); 2236 2237 if (devid == 0 || devid == 0xff) /* typical values for unused port */ 2238 return NULL; 2239 2240 /* probe revision ID */ 2241 2242 if (smsc_access(cfg_base, reg + 1)) 2243 return NULL; 2244 2245 rev = inb(cfg_base + 1); 2246 2247 if (rev >= 128) /* i think this will make no sense */ 2248 return NULL; 2249 2250 if (devid == xdevid) /* protection against false positives */ 2251 return NULL; 2252 2253 /* Check for expected device ID; are there others? */ 2254 2255 while (chip->devid != devid) { 2256 2257 chip++; 2258 2259 if (chip->name == NULL) 2260 return NULL; 2261 } 2262 2263 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n", 2264 devid, rev, cfg_base, type, chip->name); 2265 2266 if (chip->rev > rev) { 2267 IRDA_MESSAGE("Revision higher than expected\n"); 2268 return NULL; 2269 } 2270 2271 if (chip->flags & NoIRDA) 2272 IRDA_MESSAGE("chipset does not support IRDA\n"); 2273 2274 return chip; 2275} 2276 2277static int __init smsc_superio_fdc(unsigned short cfg_base) 2278{ 2279 int ret = -1; 2280 2281 if (!request_region(cfg_base, 2, driver_name)) { 2282 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", 2283 __func__, cfg_base); 2284 } else { 2285 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") || 2286 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC")) 2287 ret = 0; 2288 2289 release_region(cfg_base, 2); 2290 } 2291 2292 return ret; 2293} 2294 2295static int __init smsc_superio_lpc(unsigned short cfg_base) 2296{ 2297 int ret = -1; 2298 2299 if (!request_region(cfg_base, 2, driver_name)) { 2300 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", 2301 __func__, cfg_base); 2302 } else { 2303 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") || 2304 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC")) 2305 ret = 0; 2306 2307 release_region(cfg_base, 2); 2308 } 2309 return ret; 2310} 2311 2312/* 2313 * Look for some specific subsystem setups that need 2314 * pre-configuration not properly done by the BIOS (especially laptops) 2315 * This code is based in part on smcinit.c, tosh1800-smcinit.c 2316 * and tosh2450-smcinit.c. The table lists the device entries 2317 * for ISA bridges with an LPC (Low Pin Count) controller which 2318 * handles the communication with the SMSC device. After the LPC 2319 * controller is initialized through PCI, the SMSC device is initialized 2320 * through a dedicated port in the ISA port-mapped I/O area, this latter 2321 * area is used to configure the SMSC device with default 2322 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have 2323 * used different sets of parameters and different control port 2324 * addresses making a subsystem device table necessary. 2325 */ 2326#ifdef CONFIG_PCI 2327#define PCIID_VENDOR_INTEL 0x8086 2328#define PCIID_VENDOR_ALI 0x10b9 2329static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = { 2330 /* 2331 * Subsystems needing entries: 2332 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family 2333 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family 2334 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family 2335 */ 2336 { 2337 /* Guessed entry */ 2338 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2339 .device = 0x24cc, 2340 .subvendor = 0x103c, 2341 .subdevice = 0x08bc, 2342 .sir_io = 0x02f8, 2343 .fir_io = 0x0130, 2344 .fir_irq = 0x05, 2345 .fir_dma = 0x03, 2346 .cfg_base = 0x004e, 2347 .preconfigure = preconfigure_through_82801, 2348 .name = "HP nx5000 family", 2349 }, 2350 { 2351 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2352 .device = 0x24cc, 2353 .subvendor = 0x103c, 2354 .subdevice = 0x088c, 2355 /* Quite certain these are the same for nc8000 as for nc6000 */ 2356 .sir_io = 0x02f8, 2357 .fir_io = 0x0130, 2358 .fir_irq = 0x05, 2359 .fir_dma = 0x03, 2360 .cfg_base = 0x004e, 2361 .preconfigure = preconfigure_through_82801, 2362 .name = "HP nc8000 family", 2363 }, 2364 { 2365 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2366 .device = 0x24cc, 2367 .subvendor = 0x103c, 2368 .subdevice = 0x0890, 2369 .sir_io = 0x02f8, 2370 .fir_io = 0x0130, 2371 .fir_irq = 0x05, 2372 .fir_dma = 0x03, 2373 .cfg_base = 0x004e, 2374 .preconfigure = preconfigure_through_82801, 2375 .name = "HP nc6000 family", 2376 }, 2377 { 2378 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2379 .device = 0x24cc, 2380 .subvendor = 0x0e11, 2381 .subdevice = 0x0860, 2382 /* I assume these are the same for x1000 as for the others */ 2383 .sir_io = 0x02e8, 2384 .fir_io = 0x02f8, 2385 .fir_irq = 0x07, 2386 .fir_dma = 0x03, 2387 .cfg_base = 0x002e, 2388 .preconfigure = preconfigure_through_82801, 2389 .name = "Compaq x1000 family", 2390 }, 2391 { 2392 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */ 2393 .vendor = PCIID_VENDOR_INTEL, 2394 .device = 0x24c0, 2395 .subvendor = 0x1179, 2396 .subdevice = 0xffff, /* 0xffff is "any" */ 2397 .sir_io = 0x03f8, 2398 .fir_io = 0x0130, 2399 .fir_irq = 0x07, 2400 .fir_dma = 0x01, 2401 .cfg_base = 0x002e, 2402 .preconfigure = preconfigure_through_82801, 2403 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge", 2404 }, 2405 { 2406 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */ 2407 .device = 0x248c, 2408 .subvendor = 0x1179, 2409 .subdevice = 0xffff, /* 0xffff is "any" */ 2410 .sir_io = 0x03f8, 2411 .fir_io = 0x0130, 2412 .fir_irq = 0x03, 2413 .fir_dma = 0x03, 2414 .cfg_base = 0x002e, 2415 .preconfigure = preconfigure_through_82801, 2416 .name = "Toshiba laptop with Intel 82801CAM ISA bridge", 2417 }, 2418 { 2419 /* 82801DBM (ICH4-M) LPC Interface Bridge */ 2420 .vendor = PCIID_VENDOR_INTEL, 2421 .device = 0x24cc, 2422 .subvendor = 0x1179, 2423 .subdevice = 0xffff, /* 0xffff is "any" */ 2424 .sir_io = 0x03f8, 2425 .fir_io = 0x0130, 2426 .fir_irq = 0x03, 2427 .fir_dma = 0x03, 2428 .cfg_base = 0x002e, 2429 .preconfigure = preconfigure_through_82801, 2430 .name = "Toshiba laptop with Intel 8281DBM LPC bridge", 2431 }, 2432 { 2433 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */ 2434 .vendor = PCIID_VENDOR_ALI, 2435 .device = 0x1533, 2436 .subvendor = 0x1179, 2437 .subdevice = 0xffff, /* 0xffff is "any" */ 2438 .sir_io = 0x02e8, 2439 .fir_io = 0x02f8, 2440 .fir_irq = 0x07, 2441 .fir_dma = 0x03, 2442 .cfg_base = 0x002e, 2443 .preconfigure = preconfigure_through_ali, 2444 .name = "Toshiba laptop with ALi ISA bridge", 2445 }, 2446 { } // Terminator 2447}; 2448 2449 2450/* 2451 * This sets up the basic SMSC parameters 2452 * (FIR port, SIR port, FIR DMA, FIR IRQ) 2453 * through the chip configuration port. 2454 */ 2455static int __init preconfigure_smsc_chip(struct 2456 smsc_ircc_subsystem_configuration 2457 *conf) 2458{ 2459 unsigned short iobase = conf->cfg_base; 2460 unsigned char tmpbyte; 2461 2462 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state 2463 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID 2464 tmpbyte = inb(iobase +1); // Read device ID 2465 IRDA_DEBUG(0, 2466 "Detected Chip id: 0x%02x, setting up registers...\n", 2467 tmpbyte); 2468 2469 /* Disable UART1 and set up SIR I/O port */ 2470 outb(0x24, iobase); // select CR24 - UART1 base addr 2471 outb(0x00, iobase + 1); // disable UART1 2472 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr 2473 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8 2474 tmpbyte = inb(iobase + 1); 2475 if (tmpbyte != (conf->sir_io >> 2) ) { 2476 IRDA_WARNING("ERROR: could not configure SIR ioport.\n"); 2477 IRDA_WARNING("Try to supply ircc_cfg argument.\n"); 2478 return -ENXIO; 2479 } 2480 2481 /* Set up FIR IRQ channel for UART2 */ 2482 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select 2483 tmpbyte = inb(iobase + 1); 2484 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion 2485 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK); 2486 outb(tmpbyte, iobase + 1); 2487 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; 2488 if (tmpbyte != conf->fir_irq) { 2489 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n"); 2490 return -ENXIO; 2491 } 2492 2493 /* Set up FIR I/O port */ 2494 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr 2495 outb((conf->fir_io >> 3), iobase + 1); 2496 tmpbyte = inb(iobase + 1); 2497 if (tmpbyte != (conf->fir_io >> 3) ) { 2498 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n"); 2499 return -ENXIO; 2500 } 2501 2502 /* Set up FIR DMA channel */ 2503 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select 2504 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA 2505 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; 2506 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) { 2507 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n"); 2508 return -ENXIO; 2509 } 2510 2511 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode 2512 tmpbyte = inb(iobase + 1); 2513 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK | 2514 SMSCSIOFLAT_UART2MODE_VAL_IRDA; 2515 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed 2516 2517 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel 2518 tmpbyte = inb(iobase + 1); 2519 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down 2520 2521 /* This one was not part of tosh1800 */ 2522 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux 2523 tmpbyte = inb(iobase + 1); 2524 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port 2525 2526 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power 2527 tmpbyte = inb(iobase + 1); 2528 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down 2529 2530 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle 2531 tmpbyte = inb(iobase + 1); 2532 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done 2533 2534 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration 2535 2536 return 0; 2537} 2538 2539/* 82801CAM generic registers */ 2540#define VID 0x00 2541#define DID 0x02 2542#define PIRQ_A_D_ROUT 0x60 2543#define SIRQ_CNTL 0x64 2544#define PIRQ_E_H_ROUT 0x68 2545#define PCI_DMA_C 0x90 2546/* LPC-specific registers */ 2547#define COM_DEC 0xe0 2548#define GEN1_DEC 0xe4 2549#define LPC_EN 0xe6 2550#define GEN2_DEC 0xec 2551/* 2552 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge 2553 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge. 2554 * They all work the same way! 2555 */ 2556static int __init preconfigure_through_82801(struct pci_dev *dev, 2557 struct 2558 smsc_ircc_subsystem_configuration 2559 *conf) 2560{ 2561 unsigned short tmpword; 2562 unsigned char tmpbyte; 2563 2564 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n"); 2565 /* 2566 * Select the range for the COMA COM port (SIR) 2567 * Register COM_DEC: 2568 * Bit 7: reserved 2569 * Bit 6-4, COMB decode range 2570 * Bit 3: reserved 2571 * Bit 2-0, COMA decode range 2572 * 2573 * Decode ranges: 2574 * 000 = 0x3f8-0x3ff (COM1) 2575 * 001 = 0x2f8-0x2ff (COM2) 2576 * 010 = 0x220-0x227 2577 * 011 = 0x228-0x22f 2578 * 100 = 0x238-0x23f 2579 * 101 = 0x2e8-0x2ef (COM4) 2580 * 110 = 0x338-0x33f 2581 * 111 = 0x3e8-0x3ef (COM3) 2582 */ 2583 pci_read_config_byte(dev, COM_DEC, &tmpbyte); 2584 tmpbyte &= 0xf8; /* mask COMA bits */ 2585 switch(conf->sir_io) { 2586 case 0x3f8: 2587 tmpbyte |= 0x00; 2588 break; 2589 case 0x2f8: 2590 tmpbyte |= 0x01; 2591 break; 2592 case 0x220: 2593 tmpbyte |= 0x02; 2594 break; 2595 case 0x228: 2596 tmpbyte |= 0x03; 2597 break; 2598 case 0x238: 2599 tmpbyte |= 0x04; 2600 break; 2601 case 0x2e8: 2602 tmpbyte |= 0x05; 2603 break; 2604 case 0x338: 2605 tmpbyte |= 0x06; 2606 break; 2607 case 0x3e8: 2608 tmpbyte |= 0x07; 2609 break; 2610 default: 2611 tmpbyte |= 0x01; /* COM2 default */ 2612 } 2613 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte); 2614 pci_write_config_byte(dev, COM_DEC, tmpbyte); 2615 2616 /* Enable Low Pin Count interface */ 2617 pci_read_config_word(dev, LPC_EN, &tmpword); 2618 /* These seem to be set up at all times, 2619 * just make sure it is properly set. 2620 */ 2621 switch(conf->cfg_base) { 2622 case 0x04e: 2623 tmpword |= 0x2000; 2624 break; 2625 case 0x02e: 2626 tmpword |= 0x1000; 2627 break; 2628 case 0x062: 2629 tmpword |= 0x0800; 2630 break; 2631 case 0x060: 2632 tmpword |= 0x0400; 2633 break; 2634 default: 2635 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n", 2636 conf->cfg_base); 2637 break; 2638 } 2639 tmpword &= 0xfffd; /* disable LPC COMB */ 2640 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */ 2641 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword); 2642 pci_write_config_word(dev, LPC_EN, tmpword); 2643 2644 /* 2645 * Configure LPC DMA channel 2646 * PCI_DMA_C bits: 2647 * Bit 15-14: DMA channel 7 select 2648 * Bit 13-12: DMA channel 6 select 2649 * Bit 11-10: DMA channel 5 select 2650 * Bit 9-8: Reserved 2651 * Bit 7-6: DMA channel 3 select 2652 * Bit 5-4: DMA channel 2 select 2653 * Bit 3-2: DMA channel 1 select 2654 * Bit 1-0: DMA channel 0 select 2655 * 00 = Reserved value 2656 * 01 = PC/PCI DMA 2657 * 10 = Reserved value 2658 * 11 = LPC I/F DMA 2659 */ 2660 pci_read_config_word(dev, PCI_DMA_C, &tmpword); 2661 switch(conf->fir_dma) { 2662 case 0x07: 2663 tmpword |= 0xc000; 2664 break; 2665 case 0x06: 2666 tmpword |= 0x3000; 2667 break; 2668 case 0x05: 2669 tmpword |= 0x0c00; 2670 break; 2671 case 0x03: 2672 tmpword |= 0x00c0; 2673 break; 2674 case 0x02: 2675 tmpword |= 0x0030; 2676 break; 2677 case 0x01: 2678 tmpword |= 0x000c; 2679 break; 2680 case 0x00: 2681 tmpword |= 0x0003; 2682 break; 2683 default: 2684 break; /* do not change settings */ 2685 } 2686 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword); 2687 pci_write_config_word(dev, PCI_DMA_C, tmpword); 2688 2689 /* 2690 * GEN2_DEC bits: 2691 * Bit 15-4: Generic I/O range 2692 * Bit 3-1: reserved (read as 0) 2693 * Bit 0: enable GEN2 range on LPC I/F 2694 */ 2695 tmpword = conf->fir_io & 0xfff8; 2696 tmpword |= 0x0001; 2697 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword); 2698 pci_write_config_word(dev, GEN2_DEC, tmpword); 2699 2700 /* Pre-configure chip */ 2701 return preconfigure_smsc_chip(conf); 2702} 2703 2704/* 2705 * Pre-configure a certain port on the ALi 1533 bridge. 2706 * This is based on reverse-engineering since ALi does not 2707 * provide any data sheet for the 1533 chip. 2708 */ 2709static void __init preconfigure_ali_port(struct pci_dev *dev, 2710 unsigned short port) 2711{ 2712 unsigned char reg; 2713 /* These bits obviously control the different ports */ 2714 unsigned char mask; 2715 unsigned char tmpbyte; 2716 2717 switch(port) { 2718 case 0x0130: 2719 case 0x0178: 2720 reg = 0xb0; 2721 mask = 0x80; 2722 break; 2723 case 0x03f8: 2724 reg = 0xb4; 2725 mask = 0x80; 2726 break; 2727 case 0x02f8: 2728 reg = 0xb4; 2729 mask = 0x30; 2730 break; 2731 case 0x02e8: 2732 reg = 0xb4; 2733 mask = 0x08; 2734 break; 2735 default: 2736 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port); 2737 return; 2738 } 2739 2740 pci_read_config_byte(dev, reg, &tmpbyte); 2741 /* Turn on the right bits */ 2742 tmpbyte |= mask; 2743 pci_write_config_byte(dev, reg, tmpbyte); 2744 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port); 2745} 2746 2747static int __init preconfigure_through_ali(struct pci_dev *dev, 2748 struct 2749 smsc_ircc_subsystem_configuration 2750 *conf) 2751{ 2752 /* Configure the two ports on the ALi 1533 */ 2753 preconfigure_ali_port(dev, conf->sir_io); 2754 preconfigure_ali_port(dev, conf->fir_io); 2755 2756 /* Pre-configure chip */ 2757 return preconfigure_smsc_chip(conf); 2758} 2759 2760static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, 2761 unsigned short ircc_fir, 2762 unsigned short ircc_sir, 2763 unsigned char ircc_dma, 2764 unsigned char ircc_irq) 2765{ 2766 struct pci_dev *dev = NULL; 2767 unsigned short ss_vendor = 0x0000; 2768 unsigned short ss_device = 0x0000; 2769 int ret = 0; 2770 2771 for_each_pci_dev(dev) { 2772 struct smsc_ircc_subsystem_configuration *conf; 2773 2774 /* 2775 * Cache the subsystem vendor/device: 2776 * some manufacturers fail to set this for all components, 2777 * so we save it in case there is just 0x0000 0x0000 on the 2778 * device we want to check. 2779 */ 2780 if (dev->subsystem_vendor != 0x0000U) { 2781 ss_vendor = dev->subsystem_vendor; 2782 ss_device = dev->subsystem_device; 2783 } 2784 conf = subsystem_configurations; 2785 for( ; conf->subvendor; conf++) { 2786 if(conf->vendor == dev->vendor && 2787 conf->device == dev->device && 2788 conf->subvendor == ss_vendor && 2789 /* Sometimes these are cached values */ 2790 (conf->subdevice == ss_device || 2791 conf->subdevice == 0xffff)) { 2792 struct smsc_ircc_subsystem_configuration 2793 tmpconf; 2794 2795 memcpy(&tmpconf, conf, 2796 sizeof(struct smsc_ircc_subsystem_configuration)); 2797 2798 /* 2799 * Override the default values with anything 2800 * passed in as parameter 2801 */ 2802 if (ircc_cfg != 0) 2803 tmpconf.cfg_base = ircc_cfg; 2804 if (ircc_fir != 0) 2805 tmpconf.fir_io = ircc_fir; 2806 if (ircc_sir != 0) 2807 tmpconf.sir_io = ircc_sir; 2808 if (ircc_dma != DMA_INVAL) 2809 tmpconf.fir_dma = ircc_dma; 2810 if (ircc_irq != IRQ_INVAL) 2811 tmpconf.fir_irq = ircc_irq; 2812 2813 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name); 2814 if (conf->preconfigure) 2815 ret = conf->preconfigure(dev, &tmpconf); 2816 else 2817 ret = -ENODEV; 2818 } 2819 } 2820 } 2821 2822 return ret; 2823} 2824#endif // CONFIG_PCI 2825 2826/************************************************ 2827 * 2828 * Transceivers specific functions 2829 * 2830 ************************************************/ 2831 2832 2833/* 2834 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed) 2835 * 2836 * Program transceiver through smsc-ircc ATC circuitry 2837 * 2838 */ 2839 2840static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed) 2841{ 2842 unsigned long jiffies_now, jiffies_timeout; 2843 u8 val; 2844 2845 jiffies_now = jiffies; 2846 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES; 2847 2848 /* ATC */ 2849 register_bank(fir_base, 4); 2850 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, 2851 fir_base + IRCC_ATC); 2852 2853 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && 2854 !time_after(jiffies, jiffies_timeout)) 2855 /* empty */; 2856 2857 if (val) 2858 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__, 2859 inb(fir_base + IRCC_ATC)); 2860} 2861 2862/* 2863 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base) 2864 * 2865 * Probe transceiver smsc-ircc ATC circuitry 2866 * 2867 */ 2868 2869static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base) 2870{ 2871 return 0; 2872} 2873 2874/* 2875 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed) 2876 * 2877 * Set transceiver 2878 * 2879 */ 2880 2881static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed) 2882{ 2883 u8 fast_mode; 2884 2885 switch (speed) { 2886 default: 2887 case 576000 : 2888 fast_mode = 0; 2889 break; 2890 case 1152000 : 2891 case 4000000 : 2892 fast_mode = IRCC_LCR_A_FAST; 2893 break; 2894 } 2895 register_bank(fir_base, 0); 2896 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); 2897} 2898 2899/* 2900 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base) 2901 * 2902 * Probe transceiver 2903 * 2904 */ 2905 2906static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base) 2907{ 2908 return 0; 2909} 2910 2911/* 2912 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed) 2913 * 2914 * Set transceiver 2915 * 2916 */ 2917 2918static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed) 2919{ 2920 u8 fast_mode; 2921 2922 switch (speed) { 2923 default: 2924 case 576000 : 2925 fast_mode = 0; 2926 break; 2927 case 1152000 : 2928 case 4000000 : 2929 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA; 2930 break; 2931 2932 } 2933 /* This causes an interrupt */ 2934 register_bank(fir_base, 0); 2935 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); 2936} 2937 2938/* 2939 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base) 2940 * 2941 * Probe transceiver 2942 * 2943 */ 2944 2945static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base) 2946{ 2947 return 0; 2948} 2949 2950 2951module_init(smsc_ircc_init); 2952module_exit(smsc_ircc_cleanup); 2953