1/* 2 * Alchemy Semi Au1000 IrDA driver 3 * 4 * Copyright 2001 MontaVista Software Inc. 5 * Author: MontaVista Software, Inc. 6 * ppopov@mvista.com or source@mvista.com 7 * 8 * This program is free software; you can distribute it and/or modify it 9 * under the terms of the GNU General Public License (Version 2) as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 20 */ 21#include <linux/module.h> 22#include <linux/types.h> 23#include <linux/init.h> 24#include <linux/errno.h> 25#include <linux/netdevice.h> 26#include <linux/slab.h> 27#include <linux/rtnetlink.h> 28#include <linux/interrupt.h> 29#include <linux/pm.h> 30#include <linux/bitops.h> 31 32#include <asm/irq.h> 33#include <asm/io.h> 34#include <asm/au1000.h> 35#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) 36#include <asm/pb1000.h> 37#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 38#include <asm/db1x00.h> 39#include <asm/mach-db1x00/bcsr.h> 40#else 41#error au1k_ir: unsupported board 42#endif 43 44#include <net/irda/irda.h> 45#include <net/irda/irmod.h> 46#include <net/irda/wrapper.h> 47#include <net/irda/irda_device.h> 48#include "au1000_ircc.h" 49 50static int au1k_irda_net_init(struct net_device *); 51static int au1k_irda_start(struct net_device *); 52static int au1k_irda_stop(struct net_device *dev); 53static int au1k_irda_hard_xmit(struct sk_buff *, struct net_device *); 54static int au1k_irda_rx(struct net_device *); 55static void au1k_irda_interrupt(int, void *); 56static void au1k_tx_timeout(struct net_device *); 57static int au1k_irda_ioctl(struct net_device *, struct ifreq *, int); 58static int au1k_irda_set_speed(struct net_device *dev, int speed); 59 60static void *dma_alloc(size_t, dma_addr_t *); 61static void dma_free(void *, size_t); 62 63static int qos_mtt_bits = 0x07; /* 1 ms or more */ 64static struct net_device *ir_devs[NUM_IR_IFF]; 65static char version[] __devinitdata = 66 "au1k_ircc:1.2 ppopov@mvista.com\n"; 67 68#define RUN_AT(x) (jiffies + (x)) 69 70static DEFINE_SPINLOCK(ir_lock); 71 72/* 73 * IrDA peripheral bug. You have to read the register 74 * twice to get the right value. 75 */ 76u32 read_ir_reg(u32 addr) 77{ 78 readl(addr); 79 return readl(addr); 80} 81 82 83/* 84 * Buffer allocation/deallocation routines. The buffer descriptor returned 85 * has the virtual and dma address of a buffer suitable for 86 * both, receive and transmit operations. 87 */ 88static db_dest_t *GetFreeDB(struct au1k_private *aup) 89{ 90 db_dest_t *pDB; 91 pDB = aup->pDBfree; 92 93 if (pDB) { 94 aup->pDBfree = pDB->pnext; 95 } 96 return pDB; 97} 98 99static void ReleaseDB(struct au1k_private *aup, db_dest_t *pDB) 100{ 101 db_dest_t *pDBfree = aup->pDBfree; 102 if (pDBfree) 103 pDBfree->pnext = pDB; 104 aup->pDBfree = pDB; 105} 106 107 108/* 109 DMA memory allocation, derived from pci_alloc_consistent. 110 However, the Au1000 data cache is coherent (when programmed 111 so), therefore we return KSEG0 address, not KSEG1. 112*/ 113static void *dma_alloc(size_t size, dma_addr_t * dma_handle) 114{ 115 void *ret; 116 int gfp = GFP_ATOMIC | GFP_DMA; 117 118 ret = (void *) __get_free_pages(gfp, get_order(size)); 119 120 if (ret != NULL) { 121 memset(ret, 0, size); 122 *dma_handle = virt_to_bus(ret); 123 ret = (void *)KSEG0ADDR(ret); 124 } 125 return ret; 126} 127 128 129static void dma_free(void *vaddr, size_t size) 130{ 131 vaddr = (void *)KSEG0ADDR(vaddr); 132 free_pages((unsigned long) vaddr, get_order(size)); 133} 134 135 136static void 137setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base) 138{ 139 int i; 140 for (i=0; i<NUM_IR_DESC; i++) { 141 aup->rx_ring[i] = (volatile ring_dest_t *) 142 (rx_base + sizeof(ring_dest_t)*i); 143 } 144 for (i=0; i<NUM_IR_DESC; i++) { 145 aup->tx_ring[i] = (volatile ring_dest_t *) 146 (tx_base + sizeof(ring_dest_t)*i); 147 } 148} 149 150static int au1k_irda_init(void) 151{ 152 static unsigned version_printed = 0; 153 struct au1k_private *aup; 154 struct net_device *dev; 155 int err; 156 157 if (version_printed++ == 0) printk(version); 158 159 dev = alloc_irdadev(sizeof(struct au1k_private)); 160 if (!dev) 161 return -ENOMEM; 162 163 dev->irq = AU1000_IRDA_RX_INT; /* TX has its own interrupt */ 164 err = au1k_irda_net_init(dev); 165 if (err) 166 goto out; 167 err = register_netdev(dev); 168 if (err) 169 goto out1; 170 ir_devs[0] = dev; 171 printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); 172 return 0; 173 174out1: 175 aup = netdev_priv(dev); 176 dma_free((void *)aup->db[0].vaddr, 177 MAX_BUF_SIZE * 2*NUM_IR_DESC); 178 dma_free((void *)aup->rx_ring[0], 179 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); 180 kfree(aup->rx_buff.head); 181out: 182 free_netdev(dev); 183 return err; 184} 185 186static int au1k_irda_init_iobuf(iobuff_t *io, int size) 187{ 188 io->head = kmalloc(size, GFP_KERNEL); 189 if (io->head != NULL) { 190 io->truesize = size; 191 io->in_frame = FALSE; 192 io->state = OUTSIDE_FRAME; 193 io->data = io->head; 194 } 195 return io->head ? 0 : -ENOMEM; 196} 197 198static const struct net_device_ops au1k_irda_netdev_ops = { 199 .ndo_open = au1k_irda_start, 200 .ndo_stop = au1k_irda_stop, 201 .ndo_start_xmit = au1k_irda_hard_xmit, 202 .ndo_tx_timeout = au1k_tx_timeout, 203 .ndo_do_ioctl = au1k_irda_ioctl, 204}; 205 206static int au1k_irda_net_init(struct net_device *dev) 207{ 208 struct au1k_private *aup = netdev_priv(dev); 209 int i, retval = 0, err; 210 db_dest_t *pDB, *pDBfree; 211 dma_addr_t temp; 212 213 err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); 214 if (err) 215 goto out1; 216 217 dev->netdev_ops = &au1k_irda_netdev_ops; 218 219 irda_init_max_qos_capabilies(&aup->qos); 220 221 /* The only value we must override it the baudrate */ 222 aup->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| 223 IR_115200|IR_576000 |(IR_4000000 << 8); 224 225 aup->qos.min_turn_time.bits = qos_mtt_bits; 226 irda_qos_bits_to_value(&aup->qos); 227 228 retval = -ENOMEM; 229 230 /* Tx ring follows rx ring + 512 bytes */ 231 /* we need a 1k aligned buffer */ 232 aup->rx_ring[0] = (ring_dest_t *) 233 dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t)), &temp); 234 if (!aup->rx_ring[0]) 235 goto out2; 236 237 /* allocate the data buffers */ 238 aup->db[0].vaddr = 239 (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); 240 if (!aup->db[0].vaddr) 241 goto out3; 242 243 setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); 244 245 pDBfree = NULL; 246 pDB = aup->db; 247 for (i=0; i<(2*NUM_IR_DESC); i++) { 248 pDB->pnext = pDBfree; 249 pDBfree = pDB; 250 pDB->vaddr = 251 (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); 252 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); 253 pDB++; 254 } 255 aup->pDBfree = pDBfree; 256 257 /* attach a data buffer to each descriptor */ 258 for (i=0; i<NUM_IR_DESC; i++) { 259 pDB = GetFreeDB(aup); 260 if (!pDB) goto out; 261 aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); 262 aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); 263 aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); 264 aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); 265 aup->rx_db_inuse[i] = pDB; 266 } 267 for (i=0; i<NUM_IR_DESC; i++) { 268 pDB = GetFreeDB(aup); 269 if (!pDB) goto out; 270 aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); 271 aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); 272 aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); 273 aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); 274 aup->tx_ring[i]->count_0 = 0; 275 aup->tx_ring[i]->count_1 = 0; 276 aup->tx_ring[i]->flags = 0; 277 aup->tx_db_inuse[i] = pDB; 278 } 279 280#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 281 /* power on */ 282 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, 283 BCSR_RESETS_IRDA_MODE_FULL); 284#endif 285 286 return 0; 287 288out3: 289 dma_free((void *)aup->rx_ring[0], 290 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); 291out2: 292 kfree(aup->rx_buff.head); 293out1: 294 printk(KERN_ERR "au1k_init_module failed. Returns %d\n", retval); 295 return retval; 296} 297 298 299static int au1k_init(struct net_device *dev) 300{ 301 struct au1k_private *aup = netdev_priv(dev); 302 int i; 303 u32 control; 304 u32 ring_address; 305 306 /* bring the device out of reset */ 307 control = 0xe; /* coherent, clock enable, one half system clock */ 308 309#ifndef CONFIG_CPU_LITTLE_ENDIAN 310 control |= 1; 311#endif 312 aup->tx_head = 0; 313 aup->tx_tail = 0; 314 aup->rx_head = 0; 315 316 for (i=0; i<NUM_IR_DESC; i++) { 317 aup->rx_ring[i]->flags = AU_OWN; 318 } 319 320 writel(control, IR_INTERFACE_CONFIG); 321 au_sync_delay(10); 322 323 writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); /* disable PHY */ 324 au_sync_delay(1); 325 326 writel(MAX_BUF_SIZE, IR_MAX_PKT_LEN); 327 328 ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]); 329 writel(ring_address >> 26, IR_RING_BASE_ADDR_H); 330 writel((ring_address >> 10) & 0xffff, IR_RING_BASE_ADDR_L); 331 332 writel(RING_SIZE_64<<8 | RING_SIZE_64<<12, IR_RING_SIZE); 333 334 writel(1<<2 | IR_ONE_PIN, IR_CONFIG_2); /* 48MHz */ 335 writel(0, IR_RING_ADDR_CMPR); 336 337 au1k_irda_set_speed(dev, 9600); 338 return 0; 339} 340 341static int au1k_irda_start(struct net_device *dev) 342{ 343 int retval; 344 char hwname[32]; 345 struct au1k_private *aup = netdev_priv(dev); 346 347 if ((retval = au1k_init(dev))) { 348 printk(KERN_ERR "%s: error in au1k_init\n", dev->name); 349 return retval; 350 } 351 352 if ((retval = request_irq(AU1000_IRDA_TX_INT, au1k_irda_interrupt, 353 0, dev->name, dev))) { 354 printk(KERN_ERR "%s: unable to get IRQ %d\n", 355 dev->name, dev->irq); 356 return retval; 357 } 358 if ((retval = request_irq(AU1000_IRDA_RX_INT, au1k_irda_interrupt, 359 0, dev->name, dev))) { 360 free_irq(AU1000_IRDA_TX_INT, dev); 361 printk(KERN_ERR "%s: unable to get IRQ %d\n", 362 dev->name, dev->irq); 363 return retval; 364 } 365 366 /* Give self a hardware name */ 367 sprintf(hwname, "Au1000 SIR/FIR"); 368 aup->irlap = irlap_open(dev, &aup->qos, hwname); 369 netif_start_queue(dev); 370 371 writel(read_ir_reg(IR_CONFIG_2) | 1<<8, IR_CONFIG_2); /* int enable */ 372 373 aup->timer.expires = RUN_AT((3*HZ)); 374 aup->timer.data = (unsigned long)dev; 375 return 0; 376} 377 378static int au1k_irda_stop(struct net_device *dev) 379{ 380 struct au1k_private *aup = netdev_priv(dev); 381 382 /* disable interrupts */ 383 writel(read_ir_reg(IR_CONFIG_2) & ~(1<<8), IR_CONFIG_2); 384 writel(0, IR_CONFIG_1); 385 writel(0, IR_INTERFACE_CONFIG); /* disable clock */ 386 au_sync(); 387 388 if (aup->irlap) { 389 irlap_close(aup->irlap); 390 aup->irlap = NULL; 391 } 392 393 netif_stop_queue(dev); 394 del_timer(&aup->timer); 395 396 /* disable the interrupt */ 397 free_irq(AU1000_IRDA_TX_INT, dev); 398 free_irq(AU1000_IRDA_RX_INT, dev); 399 return 0; 400} 401 402static void __exit au1k_irda_exit(void) 403{ 404 struct net_device *dev = ir_devs[0]; 405 struct au1k_private *aup = netdev_priv(dev); 406 407 unregister_netdev(dev); 408 409 dma_free((void *)aup->db[0].vaddr, 410 MAX_BUF_SIZE * 2*NUM_IR_DESC); 411 dma_free((void *)aup->rx_ring[0], 412 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); 413 kfree(aup->rx_buff.head); 414 free_netdev(dev); 415} 416 417 418static inline void 419update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) 420{ 421 struct au1k_private *aup = netdev_priv(dev); 422 struct net_device_stats *ps = &aup->stats; 423 424 ps->tx_packets++; 425 ps->tx_bytes += pkt_len; 426 427 if (status & IR_TX_ERROR) { 428 ps->tx_errors++; 429 ps->tx_aborted_errors++; 430 } 431} 432 433 434static void au1k_tx_ack(struct net_device *dev) 435{ 436 struct au1k_private *aup = netdev_priv(dev); 437 volatile ring_dest_t *ptxd; 438 439 ptxd = aup->tx_ring[aup->tx_tail]; 440 while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) { 441 update_tx_stats(dev, ptxd->flags, 442 ptxd->count_1<<8 | ptxd->count_0); 443 ptxd->count_0 = 0; 444 ptxd->count_1 = 0; 445 au_sync(); 446 447 aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1); 448 ptxd = aup->tx_ring[aup->tx_tail]; 449 450 if (aup->tx_full) { 451 aup->tx_full = 0; 452 netif_wake_queue(dev); 453 } 454 } 455 456 if (aup->tx_tail == aup->tx_head) { 457 if (aup->newspeed) { 458 au1k_irda_set_speed(dev, aup->newspeed); 459 aup->newspeed = 0; 460 } 461 else { 462 writel(read_ir_reg(IR_CONFIG_1) & ~IR_TX_ENABLE, 463 IR_CONFIG_1); 464 au_sync(); 465 writel(read_ir_reg(IR_CONFIG_1) | IR_RX_ENABLE, 466 IR_CONFIG_1); 467 writel(0, IR_RING_PROMPT); 468 au_sync(); 469 } 470 } 471} 472 473 474/* 475 * Au1000 transmit routine. 476 */ 477static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) 478{ 479 struct au1k_private *aup = netdev_priv(dev); 480 int speed = irda_get_next_speed(skb); 481 volatile ring_dest_t *ptxd; 482 u32 len; 483 484 u32 flags; 485 db_dest_t *pDB; 486 487 if (speed != aup->speed && speed != -1) { 488 aup->newspeed = speed; 489 } 490 491 if ((skb->len == 0) && (aup->newspeed)) { 492 if (aup->tx_tail == aup->tx_head) { 493 au1k_irda_set_speed(dev, speed); 494 aup->newspeed = 0; 495 } 496 dev_kfree_skb(skb); 497 return NETDEV_TX_OK; 498 } 499 500 ptxd = aup->tx_ring[aup->tx_head]; 501 flags = ptxd->flags; 502 503 if (flags & AU_OWN) { 504 printk(KERN_DEBUG "%s: tx_full\n", dev->name); 505 netif_stop_queue(dev); 506 aup->tx_full = 1; 507 return NETDEV_TX_BUSY; 508 } 509 else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { 510 printk(KERN_DEBUG "%s: tx_full\n", dev->name); 511 netif_stop_queue(dev); 512 aup->tx_full = 1; 513 return NETDEV_TX_BUSY; 514 } 515 516 pDB = aup->tx_db_inuse[aup->tx_head]; 517 518 519 if (aup->speed == 4000000) { 520 /* FIR */ 521 skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); 522 ptxd->count_0 = skb->len & 0xff; 523 ptxd->count_1 = (skb->len >> 8) & 0xff; 524 525 } 526 else { 527 /* SIR */ 528 len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); 529 ptxd->count_0 = len & 0xff; 530 ptxd->count_1 = (len >> 8) & 0xff; 531 ptxd->flags |= IR_DIS_CRC; 532 au_writel(au_readl(0xae00000c) & ~(1<<13), 0xae00000c); 533 } 534 ptxd->flags |= AU_OWN; 535 au_sync(); 536 537 writel(read_ir_reg(IR_CONFIG_1) | IR_TX_ENABLE, IR_CONFIG_1); 538 writel(0, IR_RING_PROMPT); 539 au_sync(); 540 541 dev_kfree_skb(skb); 542 aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); 543 return NETDEV_TX_OK; 544} 545 546 547static inline void 548update_rx_stats(struct net_device *dev, u32 status, u32 count) 549{ 550 struct au1k_private *aup = netdev_priv(dev); 551 struct net_device_stats *ps = &aup->stats; 552 553 ps->rx_packets++; 554 555 if (status & IR_RX_ERROR) { 556 ps->rx_errors++; 557 if (status & (IR_PHY_ERROR|IR_FIFO_OVER)) 558 ps->rx_missed_errors++; 559 if (status & IR_MAX_LEN) 560 ps->rx_length_errors++; 561 if (status & IR_CRC_ERROR) 562 ps->rx_crc_errors++; 563 } 564 else 565 ps->rx_bytes += count; 566} 567 568/* 569 * Au1000 receive routine. 570 */ 571static int au1k_irda_rx(struct net_device *dev) 572{ 573 struct au1k_private *aup = netdev_priv(dev); 574 struct sk_buff *skb; 575 volatile ring_dest_t *prxd; 576 u32 flags, count; 577 db_dest_t *pDB; 578 579 prxd = aup->rx_ring[aup->rx_head]; 580 flags = prxd->flags; 581 582 while (!(flags & AU_OWN)) { 583 pDB = aup->rx_db_inuse[aup->rx_head]; 584 count = prxd->count_1<<8 | prxd->count_0; 585 if (!(flags & IR_RX_ERROR)) { 586 /* good frame */ 587 update_rx_stats(dev, flags, count); 588 skb=alloc_skb(count+1,GFP_ATOMIC); 589 if (skb == NULL) { 590 aup->netdev->stats.rx_dropped++; 591 continue; 592 } 593 skb_reserve(skb, 1); 594 if (aup->speed == 4000000) 595 skb_put(skb, count); 596 else 597 skb_put(skb, count-2); 598 skb_copy_to_linear_data(skb, pDB->vaddr, count - 2); 599 skb->dev = dev; 600 skb_reset_mac_header(skb); 601 skb->protocol = htons(ETH_P_IRDA); 602 netif_rx(skb); 603 prxd->count_0 = 0; 604 prxd->count_1 = 0; 605 } 606 prxd->flags |= AU_OWN; 607 aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1); 608 writel(0, IR_RING_PROMPT); 609 au_sync(); 610 611 /* next descriptor */ 612 prxd = aup->rx_ring[aup->rx_head]; 613 flags = prxd->flags; 614 615 } 616 return 0; 617} 618 619 620static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) 621{ 622 struct net_device *dev = dev_id; 623 624 writel(0, IR_INT_CLEAR); /* ack irda interrupts */ 625 626 au1k_irda_rx(dev); 627 au1k_tx_ack(dev); 628 629 return IRQ_HANDLED; 630} 631 632 633/* 634 * The Tx ring has been full longer than the watchdog timeout 635 * value. The transmitter must be hung? 636 */ 637static void au1k_tx_timeout(struct net_device *dev) 638{ 639 u32 speed; 640 struct au1k_private *aup = netdev_priv(dev); 641 642 printk(KERN_ERR "%s: tx timeout\n", dev->name); 643 speed = aup->speed; 644 aup->speed = 0; 645 au1k_irda_set_speed(dev, speed); 646 aup->tx_full = 0; 647 netif_wake_queue(dev); 648} 649 650 651/* 652 * Set the IrDA communications speed. 653 */ 654static int 655au1k_irda_set_speed(struct net_device *dev, int speed) 656{ 657 unsigned long flags; 658 struct au1k_private *aup = netdev_priv(dev); 659 u32 control; 660 int ret = 0, timeout = 10, i; 661 volatile ring_dest_t *ptxd; 662#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 663 unsigned long irda_resets; 664#endif 665 666 if (speed == aup->speed) 667 return ret; 668 669 spin_lock_irqsave(&ir_lock, flags); 670 671 /* disable PHY first */ 672 writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); 673 674 /* disable RX/TX */ 675 writel(read_ir_reg(IR_CONFIG_1) & ~(IR_RX_ENABLE|IR_TX_ENABLE), 676 IR_CONFIG_1); 677 au_sync_delay(1); 678 while (read_ir_reg(IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) { 679 mdelay(1); 680 if (!timeout--) { 681 printk(KERN_ERR "%s: rx/tx disable timeout\n", 682 dev->name); 683 break; 684 } 685 } 686 687 /* disable DMA */ 688 writel(read_ir_reg(IR_CONFIG_1) & ~IR_DMA_ENABLE, IR_CONFIG_1); 689 au_sync_delay(1); 690 691 /* 692 * After we disable tx/rx. the index pointers 693 * go back to zero. 694 */ 695 aup->tx_head = aup->tx_tail = aup->rx_head = 0; 696 for (i=0; i<NUM_IR_DESC; i++) { 697 ptxd = aup->tx_ring[i]; 698 ptxd->flags = 0; 699 ptxd->count_0 = 0; 700 ptxd->count_1 = 0; 701 } 702 703 for (i=0; i<NUM_IR_DESC; i++) { 704 ptxd = aup->rx_ring[i]; 705 ptxd->count_0 = 0; 706 ptxd->count_1 = 0; 707 ptxd->flags = AU_OWN; 708 } 709 710 if (speed == 4000000) { 711#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 712 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_FIR_SEL); 713#else /* Pb1000 and Pb1100 */ 714 writel(1<<13, CPLD_AUX1); 715#endif 716 } 717 else { 718#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) 719 bcsr_mod(BCSR_RESETS, BCSR_RESETS_FIR_SEL, 0); 720#else /* Pb1000 and Pb1100 */ 721 writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); 722#endif 723 } 724 725 switch (speed) { 726 case 9600: 727 writel(11<<10 | 12<<5, IR_WRITE_PHY_CONFIG); 728 writel(IR_SIR_MODE, IR_CONFIG_1); 729 break; 730 case 19200: 731 writel(5<<10 | 12<<5, IR_WRITE_PHY_CONFIG); 732 writel(IR_SIR_MODE, IR_CONFIG_1); 733 break; 734 case 38400: 735 writel(2<<10 | 12<<5, IR_WRITE_PHY_CONFIG); 736 writel(IR_SIR_MODE, IR_CONFIG_1); 737 break; 738 case 57600: 739 writel(1<<10 | 12<<5, IR_WRITE_PHY_CONFIG); 740 writel(IR_SIR_MODE, IR_CONFIG_1); 741 break; 742 case 115200: 743 writel(12<<5, IR_WRITE_PHY_CONFIG); 744 writel(IR_SIR_MODE, IR_CONFIG_1); 745 break; 746 case 4000000: 747 writel(0xF, IR_WRITE_PHY_CONFIG); 748 writel(IR_FIR|IR_DMA_ENABLE|IR_RX_ENABLE, IR_CONFIG_1); 749 break; 750 default: 751 printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); 752 ret = -EINVAL; 753 break; 754 } 755 756 aup->speed = speed; 757 writel(read_ir_reg(IR_ENABLE) | 0x8000, IR_ENABLE); 758 au_sync(); 759 760 control = read_ir_reg(IR_ENABLE); 761 writel(0, IR_RING_PROMPT); 762 au_sync(); 763 764 if (control & (1<<14)) { 765 printk(KERN_ERR "%s: configuration error\n", dev->name); 766 } 767 else { 768 if (control & (1<<11)) 769 printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); 770 if (control & (1<<12)) 771 printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); 772 if (control & (1<<13)) 773 printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); 774 if (control & (1<<10)) 775 printk(KERN_DEBUG "%s TX enabled\n", dev->name); 776 if (control & (1<<9)) 777 printk(KERN_DEBUG "%s RX enabled\n", dev->name); 778 } 779 780 spin_unlock_irqrestore(&ir_lock, flags); 781 return ret; 782} 783 784static int 785au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) 786{ 787 struct if_irda_req *rq = (struct if_irda_req *)ifreq; 788 struct au1k_private *aup = netdev_priv(dev); 789 int ret = -EOPNOTSUPP; 790 791 switch (cmd) { 792 case SIOCSBANDWIDTH: 793 if (capable(CAP_NET_ADMIN)) { 794 /* 795 * We are unable to set the speed if the 796 * device is not running. 797 */ 798 if (aup->open) 799 ret = au1k_irda_set_speed(dev, 800 rq->ifr_baudrate); 801 else { 802 printk(KERN_ERR "%s ioctl: !netif_running\n", 803 dev->name); 804 ret = 0; 805 } 806 } 807 break; 808 809 case SIOCSMEDIABUSY: 810 ret = -EPERM; 811 if (capable(CAP_NET_ADMIN)) { 812 irda_device_set_media_busy(dev, TRUE); 813 ret = 0; 814 } 815 break; 816 817 case SIOCGRECEIVING: 818 rq->ifr_receiving = 0; 819 break; 820 default: 821 break; 822 } 823 return ret; 824} 825 826MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>"); 827MODULE_DESCRIPTION("Au1000 IrDA Device Driver"); 828 829module_init(au1k_irda_init); 830module_exit(au1k_irda_exit); 831