1/* 2 * drivers/net/gianfar.h 3 * 4 * Gianfar Ethernet Driver 5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009 Freescale Semiconductor, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of the GNU General Public License as published by the 16 * Free Software Foundation; either version 2 of the License, or (at your 17 * option) any later version. 18 * 19 * Still left to do: 20 * -Add support for module parameters 21 * -Add patch for ethtool phys id 22 */ 23#ifndef __GIANFAR_H 24#define __GIANFAR_H 25 26#include <linux/kernel.h> 27#include <linux/sched.h> 28#include <linux/string.h> 29#include <linux/errno.h> 30#include <linux/slab.h> 31#include <linux/interrupt.h> 32#include <linux/init.h> 33#include <linux/delay.h> 34#include <linux/netdevice.h> 35#include <linux/etherdevice.h> 36#include <linux/skbuff.h> 37#include <linux/spinlock.h> 38#include <linux/mm.h> 39#include <linux/mii.h> 40#include <linux/phy.h> 41 42#include <asm/io.h> 43#include <asm/irq.h> 44#include <asm/uaccess.h> 45#include <linux/module.h> 46#include <linux/crc32.h> 47#include <linux/workqueue.h> 48#include <linux/ethtool.h> 49 50/* The maximum number of packets to be handled in one call of gfar_poll */ 51#define GFAR_DEV_WEIGHT 64 52 53/* Length for FCB */ 54#define GMAC_FCB_LEN 8 55 56/* Default padding amount */ 57#define DEFAULT_PADDING 2 58 59/* Number of bytes to align the rx bufs to */ 60#define RXBUF_ALIGNMENT 64 61 62/* The number of bytes which composes a unit for the purpose of 63 * allocating data buffers. ie-for any given MTU, the data buffer 64 * will be the next highest multiple of 512 bytes. */ 65#define INCREMENTAL_BUFFER_SIZE 512 66 67 68#define MAC_ADDR_LEN 6 69 70#define PHY_INIT_TIMEOUT 100000 71#define GFAR_PHY_CHANGE_TIME 2 72 73#define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, " 74#define DRV_NAME "gfar-enet" 75extern const char gfar_driver_name[]; 76extern const char gfar_driver_version[]; 77 78/* MAXIMUM NUMBER OF QUEUES SUPPORTED */ 79#define MAX_TX_QS 0x8 80#define MAX_RX_QS 0x8 81 82/* MAXIMUM NUMBER OF GROUPS SUPPORTED */ 83#define MAXGROUPS 0x2 84 85/* These need to be powers of 2 for this driver */ 86#define DEFAULT_TX_RING_SIZE 256 87#define DEFAULT_RX_RING_SIZE 256 88 89#define GFAR_RX_MAX_RING_SIZE 256 90#define GFAR_TX_MAX_RING_SIZE 256 91 92#define GFAR_MAX_FIFO_THRESHOLD 511 93#define GFAR_MAX_FIFO_STARVE 511 94#define GFAR_MAX_FIFO_STARVE_OFF 511 95 96#define DEFAULT_RX_BUFFER_SIZE 1536 97#define TX_RING_MOD_MASK(size) (size-1) 98#define RX_RING_MOD_MASK(size) (size-1) 99#define JUMBO_BUFFER_SIZE 9728 100#define JUMBO_FRAME_SIZE 9600 101 102#define DEFAULT_FIFO_TX_THR 0x100 103#define DEFAULT_FIFO_TX_STARVE 0x40 104#define DEFAULT_FIFO_TX_STARVE_OFF 0x80 105#define DEFAULT_BD_STASH 1 106#define DEFAULT_STASH_LENGTH 96 107#define DEFAULT_STASH_INDEX 0 108 109/* The number of Exact Match registers */ 110#define GFAR_EM_NUM 15 111 112/* Latency of interface clock in nanoseconds */ 113/* Interface clock latency , in this case, means the 114 * time described by a value of 1 in the interrupt 115 * coalescing registers' time fields. Since those fields 116 * refer to the time it takes for 64 clocks to pass, the 117 * latencies are as such: 118 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick 119 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick 120 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick 121 */ 122#define GFAR_GBIT_TIME 512 123#define GFAR_100_TIME 2560 124#define GFAR_10_TIME 25600 125 126#define DEFAULT_TX_COALESCE 1 127#define DEFAULT_TXCOUNT 16 128#define DEFAULT_TXTIME 21 129 130#define DEFAULT_RXTIME 21 131 132#define DEFAULT_RX_COALESCE 0 133#define DEFAULT_RXCOUNT 0 134 135#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \ 136 | SUPPORTED_10baseT_Full \ 137 | SUPPORTED_100baseT_Half \ 138 | SUPPORTED_100baseT_Full \ 139 | SUPPORTED_Autoneg \ 140 | SUPPORTED_MII) 141 142/* TBI register addresses */ 143#define MII_TBICON 0x11 144 145/* TBICON register bit fields */ 146#define TBICON_CLK_SELECT 0x0020 147 148/* MAC register bits */ 149#define MACCFG1_SOFT_RESET 0x80000000 150#define MACCFG1_RESET_RX_MC 0x00080000 151#define MACCFG1_RESET_TX_MC 0x00040000 152#define MACCFG1_RESET_RX_FUN 0x00020000 153#define MACCFG1_RESET_TX_FUN 0x00010000 154#define MACCFG1_LOOPBACK 0x00000100 155#define MACCFG1_RX_FLOW 0x00000020 156#define MACCFG1_TX_FLOW 0x00000010 157#define MACCFG1_SYNCD_RX_EN 0x00000008 158#define MACCFG1_RX_EN 0x00000004 159#define MACCFG1_SYNCD_TX_EN 0x00000002 160#define MACCFG1_TX_EN 0x00000001 161 162#define MACCFG2_INIT_SETTINGS 0x00007205 163#define MACCFG2_FULL_DUPLEX 0x00000001 164#define MACCFG2_IF 0x00000300 165#define MACCFG2_MII 0x00000100 166#define MACCFG2_GMII 0x00000200 167#define MACCFG2_HUGEFRAME 0x00000020 168#define MACCFG2_LENGTHCHECK 0x00000010 169#define MACCFG2_MPEN 0x00000008 170 171#define ECNTRL_INIT_SETTINGS 0x00001000 172#define ECNTRL_TBI_MODE 0x00000020 173#define ECNTRL_REDUCED_MODE 0x00000010 174#define ECNTRL_R100 0x00000008 175#define ECNTRL_REDUCED_MII_MODE 0x00000004 176#define ECNTRL_SGMII_MODE 0x00000002 177 178#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE 179 180#define MINFLR_INIT_SETTINGS 0x00000040 181 182/* Tqueue control */ 183#define TQUEUE_EN0 0x00008000 184#define TQUEUE_EN1 0x00004000 185#define TQUEUE_EN2 0x00002000 186#define TQUEUE_EN3 0x00001000 187#define TQUEUE_EN4 0x00000800 188#define TQUEUE_EN5 0x00000400 189#define TQUEUE_EN6 0x00000200 190#define TQUEUE_EN7 0x00000100 191#define TQUEUE_EN_ALL 0x0000FF00 192 193#define TR03WT_WT0_MASK 0xFF000000 194#define TR03WT_WT1_MASK 0x00FF0000 195#define TR03WT_WT2_MASK 0x0000FF00 196#define TR03WT_WT3_MASK 0x000000FF 197 198#define TR47WT_WT4_MASK 0xFF000000 199#define TR47WT_WT5_MASK 0x00FF0000 200#define TR47WT_WT6_MASK 0x0000FF00 201#define TR47WT_WT7_MASK 0x000000FF 202 203/* Rqueue control */ 204#define RQUEUE_EX0 0x00800000 205#define RQUEUE_EX1 0x00400000 206#define RQUEUE_EX2 0x00200000 207#define RQUEUE_EX3 0x00100000 208#define RQUEUE_EX4 0x00080000 209#define RQUEUE_EX5 0x00040000 210#define RQUEUE_EX6 0x00020000 211#define RQUEUE_EX7 0x00010000 212#define RQUEUE_EX_ALL 0x00FF0000 213 214#define RQUEUE_EN0 0x00000080 215#define RQUEUE_EN1 0x00000040 216#define RQUEUE_EN2 0x00000020 217#define RQUEUE_EN3 0x00000010 218#define RQUEUE_EN4 0x00000008 219#define RQUEUE_EN5 0x00000004 220#define RQUEUE_EN6 0x00000002 221#define RQUEUE_EN7 0x00000001 222#define RQUEUE_EN_ALL 0x000000FF 223 224/* Init to do tx snooping for buffers and descriptors */ 225#define DMACTRL_INIT_SETTINGS 0x000000c3 226#define DMACTRL_GRS 0x00000010 227#define DMACTRL_GTS 0x00000008 228 229#define TSTAT_CLEAR_THALT_ALL 0xFF000000 230#define TSTAT_CLEAR_THALT 0x80000000 231#define TSTAT_CLEAR_THALT0 0x80000000 232#define TSTAT_CLEAR_THALT1 0x40000000 233#define TSTAT_CLEAR_THALT2 0x20000000 234#define TSTAT_CLEAR_THALT3 0x10000000 235#define TSTAT_CLEAR_THALT4 0x08000000 236#define TSTAT_CLEAR_THALT5 0x04000000 237#define TSTAT_CLEAR_THALT6 0x02000000 238#define TSTAT_CLEAR_THALT7 0x01000000 239 240/* Interrupt coalescing macros */ 241#define IC_ICEN 0x80000000 242#define IC_ICFT_MASK 0x1fe00000 243#define IC_ICFT_SHIFT 21 244#define mk_ic_icft(x) \ 245 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) 246#define IC_ICTT_MASK 0x0000ffff 247#define mk_ic_ictt(x) (x&IC_ICTT_MASK) 248 249#define mk_ic_value(count, time) (IC_ICEN | \ 250 mk_ic_icft(count) | \ 251 mk_ic_ictt(time)) 252#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ 253 IC_ICFT_SHIFT) 254#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) 255 256#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME) 257#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME) 258 259#define skip_bd(bdp, stride, base, ring_size) ({ \ 260 typeof(bdp) new_bd = (bdp) + (stride); \ 261 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; }) 262 263#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size) 264 265#define RCTRL_TS_ENABLE 0x01000000 266#define RCTRL_PAL_MASK 0x001f0000 267#define RCTRL_VLEX 0x00002000 268#define RCTRL_FILREN 0x00001000 269#define RCTRL_GHTX 0x00000400 270#define RCTRL_IPCSEN 0x00000200 271#define RCTRL_TUCSEN 0x00000100 272#define RCTRL_PRSDEP_MASK 0x000000c0 273#define RCTRL_PRSDEP_INIT 0x000000c0 274#define RCTRL_PROM 0x00000008 275#define RCTRL_EMEN 0x00000002 276#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \ 277 RCTRL_TUCSEN) 278#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \ 279 RCTRL_PRSDEP_INIT) 280#define RCTRL_EXTHASH (RCTRL_GHTX) 281#define RCTRL_VLAN (RCTRL_PRSDEP_INIT) 282#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) 283 284 285#define RSTAT_CLEAR_RHALT 0x00800000 286 287#define TCTRL_IPCSEN 0x00004000 288#define TCTRL_TUCSEN 0x00002000 289#define TCTRL_VLINS 0x00001000 290#define TCTRL_THDF 0x00000800 291#define TCTRL_RFCPAUSE 0x00000010 292#define TCTRL_TFCPAUSE 0x00000008 293#define TCTRL_TXSCHED_MASK 0x00000006 294#define TCTRL_TXSCHED_INIT 0x00000000 295#define TCTRL_TXSCHED_PRIO 0x00000002 296#define TCTRL_TXSCHED_WRRS 0x00000004 297#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) 298 299#define IEVENT_INIT_CLEAR 0xffffffff 300#define IEVENT_BABR 0x80000000 301#define IEVENT_RXC 0x40000000 302#define IEVENT_BSY 0x20000000 303#define IEVENT_EBERR 0x10000000 304#define IEVENT_MSRO 0x04000000 305#define IEVENT_GTSC 0x02000000 306#define IEVENT_BABT 0x01000000 307#define IEVENT_TXC 0x00800000 308#define IEVENT_TXE 0x00400000 309#define IEVENT_TXB 0x00200000 310#define IEVENT_TXF 0x00100000 311#define IEVENT_LC 0x00040000 312#define IEVENT_CRL 0x00020000 313#define IEVENT_XFUN 0x00010000 314#define IEVENT_RXB0 0x00008000 315#define IEVENT_MAG 0x00000800 316#define IEVENT_GRSC 0x00000100 317#define IEVENT_RXF0 0x00000080 318#define IEVENT_FIR 0x00000008 319#define IEVENT_FIQ 0x00000004 320#define IEVENT_DPE 0x00000002 321#define IEVENT_PERR 0x00000001 322#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY) 323#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 324#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK) 325#define IEVENT_ERR_MASK \ 326(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 327 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 328 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \ 329 | IEVENT_MAG | IEVENT_BABR) 330 331#define IMASK_INIT_CLEAR 0x00000000 332#define IMASK_BABR 0x80000000 333#define IMASK_RXC 0x40000000 334#define IMASK_BSY 0x20000000 335#define IMASK_EBERR 0x10000000 336#define IMASK_MSRO 0x04000000 337#define IMASK_GTSC 0x02000000 338#define IMASK_BABT 0x01000000 339#define IMASK_TXC 0x00800000 340#define IMASK_TXEEN 0x00400000 341#define IMASK_TXBEN 0x00200000 342#define IMASK_TXFEN 0x00100000 343#define IMASK_LC 0x00040000 344#define IMASK_CRL 0x00020000 345#define IMASK_XFUN 0x00010000 346#define IMASK_RXB0 0x00008000 347#define IMASK_MAG 0x00000800 348#define IMASK_GRSC 0x00000100 349#define IMASK_RXFEN0 0x00000080 350#define IMASK_FIR 0x00000008 351#define IMASK_FIQ 0x00000004 352#define IMASK_DPE 0x00000002 353#define IMASK_PERR 0x00000001 354#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 355 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 356 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ 357 | IMASK_PERR) 358#define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \ 359 & IMASK_DEFAULT) 360 361/* Fifo management */ 362#define FIFO_TX_THR_MASK 0x01ff 363#define FIFO_TX_STARVE_MASK 0x01ff 364#define FIFO_TX_STARVE_OFF_MASK 0x01ff 365 366/* Attribute fields */ 367 368/* This enables rx snooping for buffers and descriptors */ 369#define ATTR_BDSTASH 0x00000800 370 371#define ATTR_BUFSTASH 0x00004000 372 373#define ATTR_SNOOPING 0x000000c0 374#define ATTR_INIT_SETTINGS ATTR_SNOOPING 375 376#define ATTRELI_INIT_SETTINGS 0x0 377#define ATTRELI_EL_MASK 0x3fff0000 378#define ATTRELI_EL(x) (x << 16) 379#define ATTRELI_EI_MASK 0x00003fff 380#define ATTRELI_EI(x) (x) 381 382#define BD_LFLAG(flags) ((flags) << 16) 383#define BD_LENGTH_MASK 0x0000ffff 384 385#define CLASS_CODE_UNRECOG 0x00 386#define CLASS_CODE_DUMMY1 0x01 387#define CLASS_CODE_ETHERTYPE1 0x02 388#define CLASS_CODE_ETHERTYPE2 0x03 389#define CLASS_CODE_USER_PROG1 0x04 390#define CLASS_CODE_USER_PROG2 0x05 391#define CLASS_CODE_USER_PROG3 0x06 392#define CLASS_CODE_USER_PROG4 0x07 393#define CLASS_CODE_TCP_IPV4 0x08 394#define CLASS_CODE_UDP_IPV4 0x09 395#define CLASS_CODE_AH_ESP_IPV4 0x0a 396#define CLASS_CODE_SCTP_IPV4 0x0b 397#define CLASS_CODE_TCP_IPV6 0x0c 398#define CLASS_CODE_UDP_IPV6 0x0d 399#define CLASS_CODE_AH_ESP_IPV6 0x0e 400#define CLASS_CODE_SCTP_IPV6 0x0f 401 402#define FPR_FILER_MASK 0xFFFFFFFF 403#define MAX_FILER_IDX 0xFF 404 405/* This default RIR value directly corresponds 406 * to the 3-bit hash value generated */ 407#define DEFAULT_RIR0 0x05397700 408 409/* RQFCR register bits */ 410#define RQFCR_GPI 0x80000000 411#define RQFCR_HASHTBL_Q 0x00000000 412#define RQFCR_HASHTBL_0 0x00020000 413#define RQFCR_HASHTBL_1 0x00040000 414#define RQFCR_HASHTBL_2 0x00060000 415#define RQFCR_HASHTBL_3 0x00080000 416#define RQFCR_HASH 0x00010000 417#define RQFCR_CLE 0x00000200 418#define RQFCR_RJE 0x00000100 419#define RQFCR_AND 0x00000080 420#define RQFCR_CMP_EXACT 0x00000000 421#define RQFCR_CMP_MATCH 0x00000020 422#define RQFCR_CMP_NOEXACT 0x00000040 423#define RQFCR_CMP_NOMATCH 0x00000060 424 425/* RQFCR PID values */ 426#define RQFCR_PID_MASK 0x00000000 427#define RQFCR_PID_PARSE 0x00000001 428#define RQFCR_PID_ARB 0x00000002 429#define RQFCR_PID_DAH 0x00000003 430#define RQFCR_PID_DAL 0x00000004 431#define RQFCR_PID_SAH 0x00000005 432#define RQFCR_PID_SAL 0x00000006 433#define RQFCR_PID_ETY 0x00000007 434#define RQFCR_PID_VID 0x00000008 435#define RQFCR_PID_PRI 0x00000009 436#define RQFCR_PID_TOS 0x0000000A 437#define RQFCR_PID_L4P 0x0000000B 438#define RQFCR_PID_DIA 0x0000000C 439#define RQFCR_PID_SIA 0x0000000D 440#define RQFCR_PID_DPT 0x0000000E 441#define RQFCR_PID_SPT 0x0000000F 442 443/* RQFPR when PID is 0x0001 */ 444#define RQFPR_HDR_GE_512 0x00200000 445#define RQFPR_LERR 0x00100000 446#define RQFPR_RAR 0x00080000 447#define RQFPR_RARQ 0x00040000 448#define RQFPR_AR 0x00020000 449#define RQFPR_ARQ 0x00010000 450#define RQFPR_EBC 0x00008000 451#define RQFPR_VLN 0x00004000 452#define RQFPR_CFI 0x00002000 453#define RQFPR_JUM 0x00001000 454#define RQFPR_IPF 0x00000800 455#define RQFPR_FIF 0x00000400 456#define RQFPR_IPV4 0x00000200 457#define RQFPR_IPV6 0x00000100 458#define RQFPR_ICC 0x00000080 459#define RQFPR_ICV 0x00000040 460#define RQFPR_TCP 0x00000020 461#define RQFPR_UDP 0x00000010 462#define RQFPR_TUC 0x00000008 463#define RQFPR_TUV 0x00000004 464#define RQFPR_PER 0x00000002 465#define RQFPR_EER 0x00000001 466 467/* TxBD status field bits */ 468#define TXBD_READY 0x8000 469#define TXBD_PADCRC 0x4000 470#define TXBD_WRAP 0x2000 471#define TXBD_INTERRUPT 0x1000 472#define TXBD_LAST 0x0800 473#define TXBD_CRC 0x0400 474#define TXBD_DEF 0x0200 475#define TXBD_HUGEFRAME 0x0080 476#define TXBD_LATECOLLISION 0x0080 477#define TXBD_RETRYLIMIT 0x0040 478#define TXBD_RETRYCOUNTMASK 0x003c 479#define TXBD_UNDERRUN 0x0002 480#define TXBD_TOE 0x0002 481 482/* Tx FCB param bits */ 483#define TXFCB_VLN 0x80 484#define TXFCB_IP 0x40 485#define TXFCB_IP6 0x20 486#define TXFCB_TUP 0x10 487#define TXFCB_UDP 0x08 488#define TXFCB_CIP 0x04 489#define TXFCB_CTU 0x02 490#define TXFCB_NPH 0x01 491#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) 492 493/* RxBD status field bits */ 494#define RXBD_EMPTY 0x8000 495#define RXBD_RO1 0x4000 496#define RXBD_WRAP 0x2000 497#define RXBD_INTERRUPT 0x1000 498#define RXBD_LAST 0x0800 499#define RXBD_FIRST 0x0400 500#define RXBD_MISS 0x0100 501#define RXBD_BROADCAST 0x0080 502#define RXBD_MULTICAST 0x0040 503#define RXBD_LARGE 0x0020 504#define RXBD_NONOCTET 0x0010 505#define RXBD_SHORT 0x0008 506#define RXBD_CRCERR 0x0004 507#define RXBD_OVERRUN 0x0002 508#define RXBD_TRUNCATED 0x0001 509#define RXBD_STATS 0x01ff 510#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \ 511 | RXBD_CRCERR | RXBD_OVERRUN \ 512 | RXBD_TRUNCATED) 513 514/* Rx FCB status field bits */ 515#define RXFCB_VLN 0x8000 516#define RXFCB_IP 0x4000 517#define RXFCB_IP6 0x2000 518#define RXFCB_TUP 0x1000 519#define RXFCB_CIP 0x0800 520#define RXFCB_CTU 0x0400 521#define RXFCB_EIP 0x0200 522#define RXFCB_ETU 0x0100 523#define RXFCB_CSUM_MASK 0x0f00 524#define RXFCB_PERR_MASK 0x000c 525#define RXFCB_PERR_BADL3 0x0008 526 527#define GFAR_INT_NAME_MAX IFNAMSIZ + 4 528 529struct txbd8 530{ 531 union { 532 struct { 533 u16 status; /* Status Fields */ 534 u16 length; /* Buffer length */ 535 }; 536 u32 lstatus; 537 }; 538 u32 bufPtr; /* Buffer Pointer */ 539}; 540 541struct txfcb { 542 u8 flags; 543 u8 ptp; /* Flag to enable tx timestamping */ 544 u8 l4os; /* Level 4 Header Offset */ 545 u8 l3os; /* Level 3 Header Offset */ 546 u16 phcs; /* Pseudo-header Checksum */ 547 u16 vlctl; /* VLAN control word */ 548}; 549 550struct rxbd8 551{ 552 union { 553 struct { 554 u16 status; /* Status Fields */ 555 u16 length; /* Buffer Length */ 556 }; 557 u32 lstatus; 558 }; 559 u32 bufPtr; /* Buffer Pointer */ 560}; 561 562struct rxfcb { 563 u16 flags; 564 u8 rq; /* Receive Queue index */ 565 u8 pro; /* Layer 4 Protocol */ 566 u16 reserved; 567 u16 vlctl; /* VLAN control word */ 568}; 569 570struct gianfar_skb_cb { 571 int alignamount; 572}; 573 574#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb)) 575 576struct rmon_mib 577{ 578 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 579 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ 580 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ 581 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ 582 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ 583 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ 584 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ 585 u32 rbyt; /* 0x.69c - Receive Byte Counter */ 586 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ 587 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ 588 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ 589 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ 590 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ 591 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ 592 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ 593 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ 594 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ 595 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ 596 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ 597 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ 598 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ 599 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ 600 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ 601 u32 rdrp; /* 0x.6dc - Receive Drop Counter */ 602 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ 603 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ 604 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ 605 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ 606 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ 607 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ 608 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ 609 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ 610 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ 611 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ 612 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ 613 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ 614 u8 res1[4]; 615 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ 616 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ 617 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ 618 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ 619 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ 620 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ 621 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ 622 u32 car1; /* 0x.730 - Carry Register One */ 623 u32 car2; /* 0x.734 - Carry Register Two */ 624 u32 cam1; /* 0x.738 - Carry Mask Register One */ 625 u32 cam2; /* 0x.73c - Carry Mask Register Two */ 626}; 627 628struct gfar_extra_stats { 629 u64 kernel_dropped; 630 u64 rx_large; 631 u64 rx_short; 632 u64 rx_nonoctet; 633 u64 rx_crcerr; 634 u64 rx_overrun; 635 u64 rx_bsy; 636 u64 rx_babr; 637 u64 rx_trunc; 638 u64 eberr; 639 u64 tx_babt; 640 u64 tx_underrun; 641 u64 rx_skbmissing; 642 u64 tx_timeout; 643}; 644 645#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) 646#define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64)) 647 648/* Number of stats in the stats structure (ignore car and cam regs)*/ 649#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) 650 651#define GFAR_INFOSTR_LEN 32 652 653struct gfar_stats { 654 u64 extra[GFAR_EXTRA_STATS_LEN]; 655 u64 rmon[GFAR_RMON_LEN]; 656}; 657 658 659struct gfar { 660 u32 tsec_id; /* 0x.000 - Controller ID register */ 661 u32 tsec_id2; /* 0x.004 - Controller ID2 register */ 662 u8 res1[8]; 663 u32 ievent; /* 0x.010 - Interrupt Event Register */ 664 u32 imask; /* 0x.014 - Interrupt Mask Register */ 665 u32 edis; /* 0x.018 - Error Disabled Register */ 666 u32 emapg; /* 0x.01c - Group Error mapping register */ 667 u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 668 u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 669 u32 ptv; /* 0x.028 - Pause Time Value Register */ 670 u32 dmactrl; /* 0x.02c - DMA Control Register */ 671 u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 672 u8 res2[28]; 673 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold 674 register */ 675 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff 676 register */ 677 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold 678 register */ 679 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve 680 shutoff register */ 681 u8 res3[44]; 682 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 683 u8 res4[8]; 684 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 685 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 686 u8 res5[96]; 687 u32 tctrl; /* 0x.100 - Transmit Control Register */ 688 u32 tstat; /* 0x.104 - Transmit Status Register */ 689 u32 dfvlan; /* 0x.108 - Default VLAN Control word */ 690 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 691 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 692 u32 tqueue; /* 0x.114 - Transmit queue control register */ 693 u8 res7[40]; 694 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ 695 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ 696 u8 res8[52]; 697 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ 698 u8 res9a[4]; 699 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ 700 u8 res9b[4]; 701 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ 702 u8 res9c[4]; 703 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ 704 u8 res9d[4]; 705 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ 706 u8 res9e[4]; 707 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ 708 u8 res9f[4]; 709 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ 710 u8 res9g[4]; 711 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ 712 u8 res9h[4]; 713 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ 714 u8 res9[64]; 715 u32 tbaseh; /* 0x.200 - TxBD base address high */ 716 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ 717 u8 res10a[4]; 718 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ 719 u8 res10b[4]; 720 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ 721 u8 res10c[4]; 722 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ 723 u8 res10d[4]; 724 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ 725 u8 res10e[4]; 726 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ 727 u8 res10f[4]; 728 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ 729 u8 res10g[4]; 730 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ 731 u8 res10[192]; 732 u32 rctrl; /* 0x.300 - Receive Control Register */ 733 u32 rstat; /* 0x.304 - Receive Status Register */ 734 u8 res12[8]; 735 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 736 u32 rqueue; /* 0x.314 - Receive queue control register */ 737 u32 rir0; /* 0x.318 - Ring mapping register 0 */ 738 u32 rir1; /* 0x.31c - Ring mapping register 1 */ 739 u32 rir2; /* 0x.320 - Ring mapping register 2 */ 740 u32 rir3; /* 0x.324 - Ring mapping register 3 */ 741 u8 res13[8]; 742 u32 rbifx; /* 0x.330 - Receive bit field extract control register */ 743 u32 rqfar; /* 0x.334 - Receive queue filing table address register */ 744 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ 745 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ 746 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 747 u8 res14[56]; 748 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ 749 u8 res15a[4]; 750 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ 751 u8 res15b[4]; 752 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ 753 u8 res15c[4]; 754 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ 755 u8 res15d[4]; 756 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ 757 u8 res15e[4]; 758 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ 759 u8 res15f[4]; 760 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ 761 u8 res15g[4]; 762 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ 763 u8 res15h[4]; 764 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ 765 u8 res16[64]; 766 u32 rbaseh; /* 0x.400 - RxBD base address high */ 767 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ 768 u8 res17a[4]; 769 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ 770 u8 res17b[4]; 771 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ 772 u8 res17c[4]; 773 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ 774 u8 res17d[4]; 775 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ 776 u8 res17e[4]; 777 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ 778 u8 res17f[4]; 779 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ 780 u8 res17g[4]; 781 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ 782 u8 res17[192]; 783 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 784 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 785 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 786 u32 hafdup; /* 0x.50c - Half Duplex Register */ 787 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 788 u8 res18[12]; 789 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ 790 u32 ifctrl; /* 0x.538 - Interface control register */ 791 u32 ifstat; /* 0x.53c - Interface Status Register */ 792 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 793 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 794 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ 795 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ 796 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ 797 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ 798 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ 799 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ 800 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ 801 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ 802 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ 803 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ 804 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ 805 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ 806 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ 807 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ 808 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ 809 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ 810 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ 811 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ 812 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ 813 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ 814 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ 815 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ 816 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ 817 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ 818 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ 819 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ 820 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ 821 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ 822 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ 823 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ 824 u8 res20[192]; 825 struct rmon_mib rmon; /* 0x.680-0x.73c */ 826 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ 827 u8 res21[188]; 828 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ 829 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ 830 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ 831 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ 832 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ 833 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ 834 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ 835 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ 836 u8 res22[96]; 837 u32 gaddr0; /* 0x.880 - Group address register 0 */ 838 u32 gaddr1; /* 0x.884 - Group address register 1 */ 839 u32 gaddr2; /* 0x.888 - Group address register 2 */ 840 u32 gaddr3; /* 0x.88c - Group address register 3 */ 841 u32 gaddr4; /* 0x.890 - Group address register 4 */ 842 u32 gaddr5; /* 0x.894 - Group address register 5 */ 843 u32 gaddr6; /* 0x.898 - Group address register 6 */ 844 u32 gaddr7; /* 0x.89c - Group address register 7 */ 845 u8 res23a[352]; 846 u32 fifocfg; /* 0x.a00 - FIFO interface config register */ 847 u8 res23b[252]; 848 u8 res23c[248]; 849 u32 attr; /* 0x.bf8 - Attributes Register */ 850 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 851 u8 res24[688]; 852 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */ 853 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */ 854 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */ 855 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */ 856 u8 res25[16]; 857 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */ 858 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */ 859 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */ 860 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */ 861 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */ 862 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */ 863 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */ 864 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */ 865 u8 res26[32]; 866 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */ 867 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */ 868 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */ 869 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */ 870 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */ 871 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */ 872 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */ 873 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */ 874 u8 res27[208]; 875}; 876 877/* Flags related to gianfar device features */ 878#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 879#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 880#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 881#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 882#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 883#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 884#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 885#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080 886#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 887#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 888#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 889#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800 890 891#if (MAXGROUPS == 2) 892#define DEFAULT_MAPPING 0xAA 893#else 894#define DEFAULT_MAPPING 0xFF 895#endif 896 897#define ISRG_SHIFT_TX 0x10 898#define ISRG_SHIFT_RX 0x18 899 900/* The same driver can operate in two modes */ 901/* SQ_SG_MODE: Single Queue Single Group Mode 902 * (Backward compatible mode) 903 * MQ_MG_MODE: Multi Queue Multi Group mode 904 */ 905enum { 906 SQ_SG_MODE = 0, 907 MQ_MG_MODE 908}; 909 910/** 911 * struct gfar_priv_tx_q - per tx queue structure 912 * @txlock: per queue tx spin lock 913 * @tx_skbuff:skb pointers 914 * @skb_curtx: to be used skb pointer 915 * @skb_dirtytx:the last used skb pointer 916 * @qindex: index of this queue 917 * @dev: back pointer to the dev structure 918 * @grp: back pointer to the group to which this queue belongs 919 * @tx_bd_base: First tx buffer descriptor 920 * @cur_tx: Next free ring entry 921 * @dirty_tx: First buffer in line to be transmitted 922 * @tx_ring_size: Tx ring size 923 * @num_txbdfree: number of free TxBds 924 * @txcoalescing: enable/disable tx coalescing 925 * @txic: transmit interrupt coalescing value 926 * @txcount: coalescing value if based on tx frame count 927 * @txtime: coalescing value if based on time 928 */ 929struct gfar_priv_tx_q { 930 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 931 struct sk_buff ** tx_skbuff; 932 /* Buffer descriptor pointers */ 933 dma_addr_t tx_bd_dma_base; 934 struct txbd8 *tx_bd_base; 935 struct txbd8 *cur_tx; 936 struct txbd8 *dirty_tx; 937 struct net_device *dev; 938 struct gfar_priv_grp *grp; 939 u16 skb_curtx; 940 u16 skb_dirtytx; 941 u16 qindex; 942 unsigned int tx_ring_size; 943 unsigned int num_txbdfree; 944 /* Configuration info for the coalescing features */ 945 unsigned char txcoalescing; 946 unsigned long txic; 947 unsigned short txcount; 948 unsigned short txtime; 949}; 950 951/* 952 * Per RX queue stats 953 */ 954struct rx_q_stats { 955 unsigned long rx_packets; 956 unsigned long rx_bytes; 957 unsigned long rx_dropped; 958}; 959 960/** 961 * struct gfar_priv_rx_q - per rx queue structure 962 * @rxlock: per queue rx spin lock 963 * @rx_skbuff: skb pointers 964 * @skb_currx: currently use skb pointer 965 * @rx_bd_base: First rx buffer descriptor 966 * @cur_rx: Next free rx ring entry 967 * @qindex: index of this queue 968 * @dev: back pointer to the dev structure 969 * @rx_ring_size: Rx ring size 970 * @rxcoalescing: enable/disable rx-coalescing 971 * @rxic: receive interrupt coalescing vlaue 972 */ 973 974struct gfar_priv_rx_q { 975 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 976 struct sk_buff ** rx_skbuff; 977 dma_addr_t rx_bd_dma_base; 978 struct rxbd8 *rx_bd_base; 979 struct rxbd8 *cur_rx; 980 struct net_device *dev; 981 struct gfar_priv_grp *grp; 982 struct rx_q_stats stats; 983 u16 skb_currx; 984 u16 qindex; 985 unsigned int rx_ring_size; 986 /* RX Coalescing values */ 987 unsigned char rxcoalescing; 988 unsigned long rxic; 989}; 990 991/** 992 * struct gfar_priv_grp - per group structure 993 * @napi: the napi poll function 994 * @priv: back pointer to the priv structure 995 * @regs: the ioremapped register space for this group 996 * @grp_id: group id for this group 997 * @interruptTransmit: The TX interrupt number for this group 998 * @interruptReceive: The RX interrupt number for this group 999 * @interruptError: The ERROR interrupt number for this group 1000 * @int_name_tx: tx interrupt name for this group 1001 * @int_name_rx: rx interrupt name for this group 1002 * @int_name_er: er interrupt name for this group 1003 */ 1004 1005struct gfar_priv_grp { 1006 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES))); 1007 struct napi_struct napi; 1008 struct gfar_private *priv; 1009 struct gfar __iomem *regs; 1010 unsigned int grp_id; 1011 unsigned long rx_bit_map; 1012 unsigned long tx_bit_map; 1013 unsigned long num_tx_queues; 1014 unsigned long num_rx_queues; 1015 unsigned int rstat; 1016 unsigned int tstat; 1017 unsigned int imask; 1018 unsigned int ievent; 1019 unsigned int interruptTransmit; 1020 unsigned int interruptReceive; 1021 unsigned int interruptError; 1022 1023 char int_name_tx[GFAR_INT_NAME_MAX]; 1024 char int_name_rx[GFAR_INT_NAME_MAX]; 1025 char int_name_er[GFAR_INT_NAME_MAX]; 1026}; 1027 1028enum gfar_errata { 1029 GFAR_ERRATA_74 = 0x01, 1030 GFAR_ERRATA_76 = 0x02, 1031 GFAR_ERRATA_A002 = 0x04, 1032}; 1033 1034/* Struct stolen almost completely (and shamelessly) from the FCC enet source 1035 * (Ok, that's not so true anymore, but there is a family resemblence) 1036 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base 1037 * and tx_bd_base always point to the currently available buffer. 1038 * The dirty_tx tracks the current buffer that is being sent by the 1039 * controller. The cur_tx and dirty_tx are equal under both completely 1040 * empty and completely full conditions. The empty/ready indicator in 1041 * the buffer descriptor determines the actual condition. 1042 */ 1043struct gfar_private { 1044 1045 /* Indicates how many tx, rx queues are enabled */ 1046 unsigned int num_tx_queues; 1047 unsigned int num_rx_queues; 1048 unsigned int num_grps; 1049 unsigned int mode; 1050 1051 /* The total tx and rx ring size for the enabled queues */ 1052 unsigned int total_tx_ring_size; 1053 unsigned int total_rx_ring_size; 1054 1055 struct device_node *node; 1056 struct net_device *ndev; 1057 struct platform_device *ofdev; 1058 enum gfar_errata errata; 1059 1060 struct gfar_priv_grp gfargrp[MAXGROUPS]; 1061 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS]; 1062 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS]; 1063 1064 /* RX per device parameters */ 1065 unsigned int rx_buffer_size; 1066 unsigned int rx_stash_size; 1067 unsigned int rx_stash_index; 1068 1069 u32 cur_filer_idx; 1070 1071 struct sk_buff_head rx_recycle; 1072 1073 struct vlan_group *vlgrp; 1074 1075 1076 /* Hash registers and their width */ 1077 u32 __iomem *hash_regs[16]; 1078 int hash_width; 1079 1080 /* global parameters */ 1081 unsigned int fifo_threshold; 1082 unsigned int fifo_starve; 1083 unsigned int fifo_starve_off; 1084 1085 /* Bitfield update lock */ 1086 spinlock_t bflock; 1087 1088 phy_interface_t interface; 1089 struct device_node *phy_node; 1090 struct device_node *tbi_node; 1091 u32 device_flags; 1092 unsigned char rx_csum_enable:1, 1093 extended_hash:1, 1094 bd_stash_en:1, 1095 rx_filer_enable:1, 1096 wol_en:1; /* Wake-on-LAN enabled */ 1097 unsigned short padding; 1098 1099 /* PHY stuff */ 1100 struct phy_device *phydev; 1101 struct mii_bus *mii_bus; 1102 int oldspeed; 1103 int oldduplex; 1104 int oldlink; 1105 1106 uint32_t msg_enable; 1107 1108 struct work_struct reset_task; 1109 1110 /* Network Statistics */ 1111 struct gfar_extra_stats extra_stats; 1112 1113 /* HW time stamping enabled flag */ 1114 int hwts_rx_en; 1115 int hwts_tx_en; 1116}; 1117 1118extern unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; 1119extern unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; 1120 1121static inline int gfar_has_errata(struct gfar_private *priv, 1122 enum gfar_errata err) 1123{ 1124 return priv->errata & err; 1125} 1126 1127static inline u32 gfar_read(volatile unsigned __iomem *addr) 1128{ 1129 u32 val; 1130 val = in_be32(addr); 1131 return val; 1132} 1133 1134static inline void gfar_write(volatile unsigned __iomem *addr, u32 val) 1135{ 1136 out_be32(addr, val); 1137} 1138 1139static inline void gfar_write_filer(struct gfar_private *priv, 1140 unsigned int far, unsigned int fcr, unsigned int fpr) 1141{ 1142 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1143 1144 gfar_write(®s->rqfar, far); 1145 gfar_write(®s->rqfcr, fcr); 1146 gfar_write(®s->rqfpr, fpr); 1147} 1148 1149extern void lock_rx_qs(struct gfar_private *priv); 1150extern void lock_tx_qs(struct gfar_private *priv); 1151extern void unlock_rx_qs(struct gfar_private *priv); 1152extern void unlock_tx_qs(struct gfar_private *priv); 1153extern irqreturn_t gfar_receive(int irq, void *dev_id); 1154extern int startup_gfar(struct net_device *dev); 1155extern void stop_gfar(struct net_device *dev); 1156extern void gfar_halt(struct net_device *dev); 1157extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, 1158 int enable, u32 regnum, u32 read); 1159extern void gfar_configure_coalescing(struct gfar_private *priv, 1160 unsigned long tx_mask, unsigned long rx_mask); 1161void gfar_init_sysfs(struct net_device *dev); 1162 1163extern const struct ethtool_ops gfar_ethtool_ops; 1164 1165#endif /* __GIANFAR_H */ 1166