1/* 2 * Microchip ENC28J60 ethernet driver (MAC + PHY) 3 * 4 * Copyright (C) 2007 Eurek srl 5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com> 6 * based on enc28j60.c written by David Anders for 2.4 kernel version 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 Exp $ 14 */ 15 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/types.h> 19#include <linux/fcntl.h> 20#include <linux/interrupt.h> 21#include <linux/string.h> 22#include <linux/errno.h> 23#include <linux/init.h> 24#include <linux/netdevice.h> 25#include <linux/etherdevice.h> 26#include <linux/ethtool.h> 27#include <linux/tcp.h> 28#include <linux/skbuff.h> 29#include <linux/delay.h> 30#include <linux/spi/spi.h> 31 32#include "enc28j60_hw.h" 33 34#define DRV_NAME "enc28j60" 35#define DRV_VERSION "1.01" 36 37#define SPI_OPLEN 1 38 39#define ENC28J60_MSG_DEFAULT \ 40 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK) 41 42/* Buffer size required for the largest SPI transfer (i.e., reading a 43 * frame). */ 44#define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN) 45 46#define TX_TIMEOUT (4 * HZ) 47 48/* Max TX retries in case of collision as suggested by errata datasheet */ 49#define MAX_TX_RETRYCOUNT 16 50 51enum { 52 RXFILTER_NORMAL, 53 RXFILTER_MULTI, 54 RXFILTER_PROMISC 55}; 56 57/* Driver local data */ 58struct enc28j60_net { 59 struct net_device *netdev; 60 struct spi_device *spi; 61 struct mutex lock; 62 struct sk_buff *tx_skb; 63 struct work_struct tx_work; 64 struct work_struct irq_work; 65 struct work_struct setrx_work; 66 struct work_struct restart_work; 67 u8 bank; /* current register bank selected */ 68 u16 next_pk_ptr; /* next packet pointer within FIFO */ 69 u16 max_pk_counter; /* statistics: max packet counter */ 70 u16 tx_retry_count; 71 bool hw_enable; 72 bool full_duplex; 73 int rxfilter; 74 u32 msg_enable; 75 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN]; 76}; 77 78/* use ethtool to change the level for any given device */ 79static struct { 80 u32 msg_enable; 81} debug = { -1 }; 82 83/* 84 * SPI read buffer 85 * wait for the SPI transfer and copy received data to destination 86 */ 87static int 88spi_read_buf(struct enc28j60_net *priv, int len, u8 *data) 89{ 90 u8 *rx_buf = priv->spi_transfer_buf + 4; 91 u8 *tx_buf = priv->spi_transfer_buf; 92 struct spi_transfer t = { 93 .tx_buf = tx_buf, 94 .rx_buf = rx_buf, 95 .len = SPI_OPLEN + len, 96 }; 97 struct spi_message msg; 98 int ret; 99 100 tx_buf[0] = ENC28J60_READ_BUF_MEM; 101 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */ 102 103 spi_message_init(&msg); 104 spi_message_add_tail(&t, &msg); 105 ret = spi_sync(priv->spi, &msg); 106 if (ret == 0) { 107 memcpy(data, &rx_buf[SPI_OPLEN], len); 108 ret = msg.status; 109 } 110 if (ret && netif_msg_drv(priv)) 111 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", 112 __func__, ret); 113 114 return ret; 115} 116 117/* 118 * SPI write buffer 119 */ 120static int spi_write_buf(struct enc28j60_net *priv, int len, 121 const u8 *data) 122{ 123 int ret; 124 125 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0) 126 ret = -EINVAL; 127 else { 128 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM; 129 memcpy(&priv->spi_transfer_buf[1], data, len); 130 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1); 131 if (ret && netif_msg_drv(priv)) 132 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", 133 __func__, ret); 134 } 135 return ret; 136} 137 138/* 139 * basic SPI read operation 140 */ 141static u8 spi_read_op(struct enc28j60_net *priv, u8 op, 142 u8 addr) 143{ 144 u8 tx_buf[2]; 145 u8 rx_buf[4]; 146 u8 val = 0; 147 int ret; 148 int slen = SPI_OPLEN; 149 150 /* do dummy read if needed */ 151 if (addr & SPRD_MASK) 152 slen++; 153 154 tx_buf[0] = op | (addr & ADDR_MASK); 155 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen); 156 if (ret) 157 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", 158 __func__, ret); 159 else 160 val = rx_buf[slen - 1]; 161 162 return val; 163} 164 165/* 166 * basic SPI write operation 167 */ 168static int spi_write_op(struct enc28j60_net *priv, u8 op, 169 u8 addr, u8 val) 170{ 171 int ret; 172 173 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK); 174 priv->spi_transfer_buf[1] = val; 175 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2); 176 if (ret && netif_msg_drv(priv)) 177 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", 178 __func__, ret); 179 return ret; 180} 181 182static void enc28j60_soft_reset(struct enc28j60_net *priv) 183{ 184 if (netif_msg_hw(priv)) 185 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); 186 187 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); 188 udelay(2000); 189} 190 191/* 192 * select the current register bank if necessary 193 */ 194static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr) 195{ 196 u8 b = (addr & BANK_MASK) >> 5; 197 198 /* These registers (EIE, EIR, ESTAT, ECON2, ECON1) 199 * are present in all banks, no need to switch bank 200 */ 201 if (addr >= EIE && addr <= ECON1) 202 return; 203 204 /* Clear or set each bank selection bit as needed */ 205 if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) { 206 if (b & ECON1_BSEL0) 207 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, 208 ECON1_BSEL0); 209 else 210 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, 211 ECON1_BSEL0); 212 } 213 if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) { 214 if (b & ECON1_BSEL1) 215 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, 216 ECON1_BSEL1); 217 else 218 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, 219 ECON1_BSEL1); 220 } 221 priv->bank = b; 222} 223 224/* 225 * Register access routines through the SPI bus. 226 * Every register access comes in two flavours: 227 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access 228 * atomically more than one register 229 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access 230 * 231 * Some registers can be accessed through the bit field clear and 232 * bit field set to avoid a read modify write cycle. 233 */ 234 235/* 236 * Register bit field Set 237 */ 238static void nolock_reg_bfset(struct enc28j60_net *priv, 239 u8 addr, u8 mask) 240{ 241 enc28j60_set_bank(priv, addr); 242 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask); 243} 244 245static void locked_reg_bfset(struct enc28j60_net *priv, 246 u8 addr, u8 mask) 247{ 248 mutex_lock(&priv->lock); 249 nolock_reg_bfset(priv, addr, mask); 250 mutex_unlock(&priv->lock); 251} 252 253/* 254 * Register bit field Clear 255 */ 256static void nolock_reg_bfclr(struct enc28j60_net *priv, 257 u8 addr, u8 mask) 258{ 259 enc28j60_set_bank(priv, addr); 260 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask); 261} 262 263static void locked_reg_bfclr(struct enc28j60_net *priv, 264 u8 addr, u8 mask) 265{ 266 mutex_lock(&priv->lock); 267 nolock_reg_bfclr(priv, addr, mask); 268 mutex_unlock(&priv->lock); 269} 270 271/* 272 * Register byte read 273 */ 274static int nolock_regb_read(struct enc28j60_net *priv, 275 u8 address) 276{ 277 enc28j60_set_bank(priv, address); 278 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address); 279} 280 281static int locked_regb_read(struct enc28j60_net *priv, 282 u8 address) 283{ 284 int ret; 285 286 mutex_lock(&priv->lock); 287 ret = nolock_regb_read(priv, address); 288 mutex_unlock(&priv->lock); 289 290 return ret; 291} 292 293/* 294 * Register word read 295 */ 296static int nolock_regw_read(struct enc28j60_net *priv, 297 u8 address) 298{ 299 int rl, rh; 300 301 enc28j60_set_bank(priv, address); 302 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address); 303 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1); 304 305 return (rh << 8) | rl; 306} 307 308static int locked_regw_read(struct enc28j60_net *priv, 309 u8 address) 310{ 311 int ret; 312 313 mutex_lock(&priv->lock); 314 ret = nolock_regw_read(priv, address); 315 mutex_unlock(&priv->lock); 316 317 return ret; 318} 319 320/* 321 * Register byte write 322 */ 323static void nolock_regb_write(struct enc28j60_net *priv, 324 u8 address, u8 data) 325{ 326 enc28j60_set_bank(priv, address); 327 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data); 328} 329 330static void locked_regb_write(struct enc28j60_net *priv, 331 u8 address, u8 data) 332{ 333 mutex_lock(&priv->lock); 334 nolock_regb_write(priv, address, data); 335 mutex_unlock(&priv->lock); 336} 337 338/* 339 * Register word write 340 */ 341static void nolock_regw_write(struct enc28j60_net *priv, 342 u8 address, u16 data) 343{ 344 enc28j60_set_bank(priv, address); 345 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data); 346 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1, 347 (u8) (data >> 8)); 348} 349 350static void locked_regw_write(struct enc28j60_net *priv, 351 u8 address, u16 data) 352{ 353 mutex_lock(&priv->lock); 354 nolock_regw_write(priv, address, data); 355 mutex_unlock(&priv->lock); 356} 357 358/* 359 * Buffer memory read 360 * Select the starting address and execute a SPI buffer read 361 */ 362static void enc28j60_mem_read(struct enc28j60_net *priv, 363 u16 addr, int len, u8 *data) 364{ 365 mutex_lock(&priv->lock); 366 nolock_regw_write(priv, ERDPTL, addr); 367#ifdef CONFIG_ENC28J60_WRITEVERIFY 368 if (netif_msg_drv(priv)) { 369 u16 reg; 370 reg = nolock_regw_read(priv, ERDPTL); 371 if (reg != addr) 372 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT " 373 "(0x%04x - 0x%04x)\n", __func__, reg, addr); 374 } 375#endif 376 spi_read_buf(priv, len, data); 377 mutex_unlock(&priv->lock); 378} 379 380/* 381 * Write packet to enc28j60 TX buffer memory 382 */ 383static void 384enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data) 385{ 386 mutex_lock(&priv->lock); 387 /* Set the write pointer to start of transmit buffer area */ 388 nolock_regw_write(priv, EWRPTL, TXSTART_INIT); 389#ifdef CONFIG_ENC28J60_WRITEVERIFY 390 if (netif_msg_drv(priv)) { 391 u16 reg; 392 reg = nolock_regw_read(priv, EWRPTL); 393 if (reg != TXSTART_INIT) 394 printk(KERN_DEBUG DRV_NAME 395 ": %s() ERWPT:0x%04x != 0x%04x\n", 396 __func__, reg, TXSTART_INIT); 397 } 398#endif 399 /* Set the TXND pointer to correspond to the packet size given */ 400 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len); 401 /* write per-packet control byte */ 402 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00); 403 if (netif_msg_hw(priv)) 404 printk(KERN_DEBUG DRV_NAME 405 ": %s() after control byte ERWPT:0x%04x\n", 406 __func__, nolock_regw_read(priv, EWRPTL)); 407 /* copy the packet into the transmit buffer */ 408 spi_write_buf(priv, len, data); 409 if (netif_msg_hw(priv)) 410 printk(KERN_DEBUG DRV_NAME 411 ": %s() after write packet ERWPT:0x%04x, len=%d\n", 412 __func__, nolock_regw_read(priv, EWRPTL), len); 413 mutex_unlock(&priv->lock); 414} 415 416static unsigned long msec20_to_jiffies; 417 418static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val) 419{ 420 unsigned long timeout = jiffies + msec20_to_jiffies; 421 422 /* 20 msec timeout read */ 423 while ((nolock_regb_read(priv, reg) & mask) != val) { 424 if (time_after(jiffies, timeout)) { 425 if (netif_msg_drv(priv)) 426 dev_dbg(&priv->spi->dev, 427 "reg %02x ready timeout!\n", reg); 428 return -ETIMEDOUT; 429 } 430 cpu_relax(); 431 } 432 return 0; 433} 434 435/* 436 * Wait until the PHY operation is complete. 437 */ 438static int wait_phy_ready(struct enc28j60_net *priv) 439{ 440 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1; 441} 442 443/* 444 * PHY register read 445 * PHY registers are not accessed directly, but through the MII 446 */ 447static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address) 448{ 449 u16 ret; 450 451 mutex_lock(&priv->lock); 452 /* set the PHY register address */ 453 nolock_regb_write(priv, MIREGADR, address); 454 /* start the register read operation */ 455 nolock_regb_write(priv, MICMD, MICMD_MIIRD); 456 /* wait until the PHY read completes */ 457 wait_phy_ready(priv); 458 /* quit reading */ 459 nolock_regb_write(priv, MICMD, 0x00); 460 /* return the data */ 461 ret = nolock_regw_read(priv, MIRDL); 462 mutex_unlock(&priv->lock); 463 464 return ret; 465} 466 467static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data) 468{ 469 int ret; 470 471 mutex_lock(&priv->lock); 472 /* set the PHY register address */ 473 nolock_regb_write(priv, MIREGADR, address); 474 /* write the PHY data */ 475 nolock_regw_write(priv, MIWRL, data); 476 /* wait until the PHY write completes and return */ 477 ret = wait_phy_ready(priv); 478 mutex_unlock(&priv->lock); 479 480 return ret; 481} 482 483/* 484 * Program the hardware MAC address from dev->dev_addr. 485 */ 486static int enc28j60_set_hw_macaddr(struct net_device *ndev) 487{ 488 int ret; 489 struct enc28j60_net *priv = netdev_priv(ndev); 490 491 mutex_lock(&priv->lock); 492 if (!priv->hw_enable) { 493 if (netif_msg_drv(priv)) 494 printk(KERN_INFO DRV_NAME 495 ": %s: Setting MAC address to %pM\n", 496 ndev->name, ndev->dev_addr); 497 /* NOTE: MAC address in ENC28J60 is byte-backward */ 498 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]); 499 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]); 500 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]); 501 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]); 502 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]); 503 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]); 504 ret = 0; 505 } else { 506 if (netif_msg_drv(priv)) 507 printk(KERN_DEBUG DRV_NAME 508 ": %s() Hardware must be disabled to set " 509 "Mac address\n", __func__); 510 ret = -EBUSY; 511 } 512 mutex_unlock(&priv->lock); 513 return ret; 514} 515 516/* 517 * Store the new hardware address in dev->dev_addr, and update the MAC. 518 */ 519static int enc28j60_set_mac_address(struct net_device *dev, void *addr) 520{ 521 struct sockaddr *address = addr; 522 523 if (netif_running(dev)) 524 return -EBUSY; 525 if (!is_valid_ether_addr(address->sa_data)) 526 return -EADDRNOTAVAIL; 527 528 memcpy(dev->dev_addr, address->sa_data, dev->addr_len); 529 return enc28j60_set_hw_macaddr(dev); 530} 531 532/* 533 * Debug routine to dump useful register contents 534 */ 535static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg) 536{ 537 mutex_lock(&priv->lock); 538 printk(KERN_DEBUG DRV_NAME " %s\n" 539 "HwRevID: 0x%02x\n" 540 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n" 541 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" 542 "MAC : MACON1 MACON3 MACON4\n" 543 " 0x%02x 0x%02x 0x%02x\n" 544 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n" 545 " 0x%04x 0x%04x 0x%04x 0x%04x " 546 "0x%02x 0x%02x 0x%04x\n" 547 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n" 548 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n", 549 msg, nolock_regb_read(priv, EREVID), 550 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2), 551 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR), 552 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1), 553 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4), 554 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL), 555 nolock_regw_read(priv, ERXWRPTL), 556 nolock_regw_read(priv, ERXRDPTL), 557 nolock_regb_read(priv, ERXFCON), 558 nolock_regb_read(priv, EPKTCNT), 559 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL), 560 nolock_regw_read(priv, ETXNDL), 561 nolock_regb_read(priv, MACLCON1), 562 nolock_regb_read(priv, MACLCON2), 563 nolock_regb_read(priv, MAPHSUP)); 564 mutex_unlock(&priv->lock); 565} 566 567/* 568 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet 569 */ 570static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end) 571{ 572 u16 erxrdpt; 573 574 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end)) 575 erxrdpt = end; 576 else 577 erxrdpt = next_packet_ptr - 1; 578 579 return erxrdpt; 580} 581 582/* 583 * Calculate wrap around when reading beyond the end of the RX buffer 584 */ 585static u16 rx_packet_start(u16 ptr) 586{ 587 if (ptr + RSV_SIZE > RXEND_INIT) 588 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1); 589 else 590 return ptr + RSV_SIZE; 591} 592 593static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end) 594{ 595 u16 erxrdpt; 596 597 if (start > 0x1FFF || end > 0x1FFF || start > end) { 598 if (netif_msg_drv(priv)) 599 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO " 600 "bad parameters!\n", __func__, start, end); 601 return; 602 } 603 /* set receive buffer start + end */ 604 priv->next_pk_ptr = start; 605 nolock_regw_write(priv, ERXSTL, start); 606 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end); 607 nolock_regw_write(priv, ERXRDPTL, erxrdpt); 608 nolock_regw_write(priv, ERXNDL, end); 609} 610 611static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end) 612{ 613 if (start > 0x1FFF || end > 0x1FFF || start > end) { 614 if (netif_msg_drv(priv)) 615 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO " 616 "bad parameters!\n", __func__, start, end); 617 return; 618 } 619 /* set transmit buffer start + end */ 620 nolock_regw_write(priv, ETXSTL, start); 621 nolock_regw_write(priv, ETXNDL, end); 622} 623 624/* 625 * Low power mode shrinks power consumption about 100x, so we'd like 626 * the chip to be in that mode whenever it's inactive. (However, we 627 * can't stay in lowpower mode during suspend with WOL active.) 628 */ 629static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low) 630{ 631 if (netif_msg_drv(priv)) 632 dev_dbg(&priv->spi->dev, "%s power...\n", 633 is_low ? "low" : "high"); 634 635 mutex_lock(&priv->lock); 636 if (is_low) { 637 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); 638 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0); 639 poll_ready(priv, ECON1, ECON1_TXRTS, 0); 640 /* ECON2_VRPS was set during initialization */ 641 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV); 642 } else { 643 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV); 644 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY); 645 /* caller sets ECON1_RXEN */ 646 } 647 mutex_unlock(&priv->lock); 648} 649 650static int enc28j60_hw_init(struct enc28j60_net *priv) 651{ 652 u8 reg; 653 654 if (netif_msg_drv(priv)) 655 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__, 656 priv->full_duplex ? "FullDuplex" : "HalfDuplex"); 657 658 mutex_lock(&priv->lock); 659 /* first reset the chip */ 660 enc28j60_soft_reset(priv); 661 /* Clear ECON1 */ 662 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00); 663 priv->bank = 0; 664 priv->hw_enable = false; 665 priv->tx_retry_count = 0; 666 priv->max_pk_counter = 0; 667 priv->rxfilter = RXFILTER_NORMAL; 668 /* enable address auto increment and voltage regulator powersave */ 669 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS); 670 671 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); 672 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); 673 mutex_unlock(&priv->lock); 674 675 /* 676 * Check the RevID. 677 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or 678 * damaged 679 */ 680 reg = locked_regb_read(priv, EREVID); 681 if (netif_msg_drv(priv)) 682 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg); 683 if (reg == 0x00 || reg == 0xff) { 684 if (netif_msg_drv(priv)) 685 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n", 686 __func__, reg); 687 return 0; 688 } 689 690 /* default filter mode: (unicast OR broadcast) AND crc valid */ 691 locked_regb_write(priv, ERXFCON, 692 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); 693 694 /* enable MAC receive */ 695 locked_regb_write(priv, MACON1, 696 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); 697 /* enable automatic padding and CRC operations */ 698 if (priv->full_duplex) { 699 locked_regb_write(priv, MACON3, 700 MACON3_PADCFG0 | MACON3_TXCRCEN | 701 MACON3_FRMLNEN | MACON3_FULDPX); 702 /* set inter-frame gap (non-back-to-back) */ 703 locked_regb_write(priv, MAIPGL, 0x12); 704 /* set inter-frame gap (back-to-back) */ 705 locked_regb_write(priv, MABBIPG, 0x15); 706 } else { 707 locked_regb_write(priv, MACON3, 708 MACON3_PADCFG0 | MACON3_TXCRCEN | 709 MACON3_FRMLNEN); 710 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */ 711 /* set inter-frame gap (non-back-to-back) */ 712 locked_regw_write(priv, MAIPGL, 0x0C12); 713 /* set inter-frame gap (back-to-back) */ 714 locked_regb_write(priv, MABBIPG, 0x12); 715 } 716 /* 717 * MACLCON1 (default) 718 * MACLCON2 (default) 719 * Set the maximum packet size which the controller will accept 720 */ 721 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN); 722 723 /* Configure LEDs */ 724 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE)) 725 return 0; 726 727 if (priv->full_duplex) { 728 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD)) 729 return 0; 730 if (!enc28j60_phy_write(priv, PHCON2, 0x00)) 731 return 0; 732 } else { 733 if (!enc28j60_phy_write(priv, PHCON1, 0x00)) 734 return 0; 735 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS)) 736 return 0; 737 } 738 if (netif_msg_hw(priv)) 739 enc28j60_dump_regs(priv, "Hw initialized."); 740 741 return 1; 742} 743 744static void enc28j60_hw_enable(struct enc28j60_net *priv) 745{ 746 /* enable interrupts */ 747 if (netif_msg_hw(priv)) 748 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n", 749 __func__); 750 751 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE); 752 753 mutex_lock(&priv->lock); 754 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF | 755 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF); 756 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE | 757 EIE_TXIE | EIE_TXERIE | EIE_RXERIE); 758 759 /* enable receive logic */ 760 nolock_reg_bfset(priv, ECON1, ECON1_RXEN); 761 priv->hw_enable = true; 762 mutex_unlock(&priv->lock); 763} 764 765static void enc28j60_hw_disable(struct enc28j60_net *priv) 766{ 767 mutex_lock(&priv->lock); 768 /* disable interrutps and packet reception */ 769 nolock_regb_write(priv, EIE, 0x00); 770 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); 771 priv->hw_enable = false; 772 mutex_unlock(&priv->lock); 773} 774 775static int 776enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex) 777{ 778 struct enc28j60_net *priv = netdev_priv(ndev); 779 int ret = 0; 780 781 if (!priv->hw_enable) { 782 /* link is in low power mode now; duplex setting 783 * will take effect on next enc28j60_hw_init(). 784 */ 785 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10) 786 priv->full_duplex = (duplex == DUPLEX_FULL); 787 else { 788 if (netif_msg_link(priv)) 789 dev_warn(&ndev->dev, 790 "unsupported link setting\n"); 791 ret = -EOPNOTSUPP; 792 } 793 } else { 794 if (netif_msg_link(priv)) 795 dev_warn(&ndev->dev, "Warning: hw must be disabled " 796 "to set link mode\n"); 797 ret = -EBUSY; 798 } 799 return ret; 800} 801 802/* 803 * Read the Transmit Status Vector 804 */ 805static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE]) 806{ 807 int endptr; 808 809 endptr = locked_regw_read(priv, ETXNDL); 810 if (netif_msg_hw(priv)) 811 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n", 812 endptr + 1); 813 enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv); 814} 815 816static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg, 817 u8 tsv[TSV_SIZE]) 818{ 819 u16 tmp1, tmp2; 820 821 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg); 822 tmp1 = tsv[1]; 823 tmp1 <<= 8; 824 tmp1 |= tsv[0]; 825 826 tmp2 = tsv[5]; 827 tmp2 <<= 8; 828 tmp2 |= tsv[4]; 829 830 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d," 831 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2); 832 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d," 833 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE), 834 TSV_GETBIT(tsv, TSV_TXCRCERROR), 835 TSV_GETBIT(tsv, TSV_TXLENCHKERROR), 836 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE)); 837 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, " 838 "PacketDefer: %d, ExDefer: %d\n", 839 TSV_GETBIT(tsv, TSV_TXMULTICAST), 840 TSV_GETBIT(tsv, TSV_TXBROADCAST), 841 TSV_GETBIT(tsv, TSV_TXPACKETDEFER), 842 TSV_GETBIT(tsv, TSV_TXEXDEFER)); 843 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, " 844 "Giant: %d, Underrun: %d\n", 845 TSV_GETBIT(tsv, TSV_TXEXCOLLISION), 846 TSV_GETBIT(tsv, TSV_TXLATECOLLISION), 847 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN)); 848 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, " 849 "BackPressApp: %d, VLanTagFrame: %d\n", 850 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME), 851 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME), 852 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP), 853 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME)); 854} 855 856/* 857 * Receive Status vector 858 */ 859static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg, 860 u16 pk_ptr, int len, u16 sts) 861{ 862 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n", 863 msg, pk_ptr); 864 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len, 865 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE)); 866 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d," 867 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK), 868 RSV_GETBIT(sts, RSV_CRCERROR), 869 RSV_GETBIT(sts, RSV_LENCHECKERR), 870 RSV_GETBIT(sts, RSV_LENOUTOFRANGE)); 871 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, " 872 "LongDropEvent: %d, CarrierEvent: %d\n", 873 RSV_GETBIT(sts, RSV_RXMULTICAST), 874 RSV_GETBIT(sts, RSV_RXBROADCAST), 875 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV), 876 RSV_GETBIT(sts, RSV_CARRIEREV)); 877 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d," 878 " UnknownOp: %d, VLanTagFrame: %d\n", 879 RSV_GETBIT(sts, RSV_RXCONTROLFRAME), 880 RSV_GETBIT(sts, RSV_RXPAUSEFRAME), 881 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE), 882 RSV_GETBIT(sts, RSV_RXTYPEVLAN)); 883} 884 885static void dump_packet(const char *msg, int len, const char *data) 886{ 887 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len); 888 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1, 889 data, len, true); 890} 891 892/* 893 * Hardware receive function. 894 * Read the buffer memory, update the FIFO pointer to free the buffer, 895 * check the status vector and decrement the packet counter. 896 */ 897static void enc28j60_hw_rx(struct net_device *ndev) 898{ 899 struct enc28j60_net *priv = netdev_priv(ndev); 900 struct sk_buff *skb = NULL; 901 u16 erxrdpt, next_packet, rxstat; 902 u8 rsv[RSV_SIZE]; 903 int len; 904 905 if (netif_msg_rx_status(priv)) 906 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n", 907 priv->next_pk_ptr); 908 909 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) { 910 if (netif_msg_rx_err(priv)) 911 dev_err(&ndev->dev, 912 "%s() Invalid packet address!! 0x%04x\n", 913 __func__, priv->next_pk_ptr); 914 /* packet address corrupted: reset RX logic */ 915 mutex_lock(&priv->lock); 916 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); 917 nolock_reg_bfset(priv, ECON1, ECON1_RXRST); 918 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST); 919 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); 920 nolock_reg_bfclr(priv, EIR, EIR_RXERIF); 921 nolock_reg_bfset(priv, ECON1, ECON1_RXEN); 922 mutex_unlock(&priv->lock); 923 ndev->stats.rx_errors++; 924 return; 925 } 926 /* Read next packet pointer and rx status vector */ 927 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv); 928 929 next_packet = rsv[1]; 930 next_packet <<= 8; 931 next_packet |= rsv[0]; 932 933 len = rsv[3]; 934 len <<= 8; 935 len |= rsv[2]; 936 937 rxstat = rsv[5]; 938 rxstat <<= 8; 939 rxstat |= rsv[4]; 940 941 if (netif_msg_rx_status(priv)) 942 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat); 943 944 if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) { 945 if (netif_msg_rx_err(priv)) 946 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat); 947 ndev->stats.rx_errors++; 948 if (RSV_GETBIT(rxstat, RSV_CRCERROR)) 949 ndev->stats.rx_crc_errors++; 950 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR)) 951 ndev->stats.rx_frame_errors++; 952 if (len > MAX_FRAMELEN) 953 ndev->stats.rx_over_errors++; 954 } else { 955 skb = dev_alloc_skb(len + NET_IP_ALIGN); 956 if (!skb) { 957 if (netif_msg_rx_err(priv)) 958 dev_err(&ndev->dev, 959 "out of memory for Rx'd frame\n"); 960 ndev->stats.rx_dropped++; 961 } else { 962 skb->dev = ndev; 963 skb_reserve(skb, NET_IP_ALIGN); 964 /* copy the packet from the receive buffer */ 965 enc28j60_mem_read(priv, 966 rx_packet_start(priv->next_pk_ptr), 967 len, skb_put(skb, len)); 968 if (netif_msg_pktdata(priv)) 969 dump_packet(__func__, skb->len, skb->data); 970 skb->protocol = eth_type_trans(skb, ndev); 971 /* update statistics */ 972 ndev->stats.rx_packets++; 973 ndev->stats.rx_bytes += len; 974 netif_rx_ni(skb); 975 } 976 } 977 /* 978 * Move the RX read pointer to the start of the next 979 * received packet. 980 * This frees the memory we just read out 981 */ 982 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT); 983 if (netif_msg_hw(priv)) 984 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n", 985 __func__, erxrdpt); 986 987 mutex_lock(&priv->lock); 988 nolock_regw_write(priv, ERXRDPTL, erxrdpt); 989#ifdef CONFIG_ENC28J60_WRITEVERIFY 990 if (netif_msg_drv(priv)) { 991 u16 reg; 992 reg = nolock_regw_read(priv, ERXRDPTL); 993 if (reg != erxrdpt) 994 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify " 995 "error (0x%04x - 0x%04x)\n", __func__, 996 reg, erxrdpt); 997 } 998#endif 999 priv->next_pk_ptr = next_packet; 1000 /* we are done with this packet, decrement the packet counter */ 1001 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC); 1002 mutex_unlock(&priv->lock); 1003} 1004 1005/* 1006 * Calculate free space in RxFIFO 1007 */ 1008static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv) 1009{ 1010 int epkcnt, erxst, erxnd, erxwr, erxrd; 1011 int free_space; 1012 1013 mutex_lock(&priv->lock); 1014 epkcnt = nolock_regb_read(priv, EPKTCNT); 1015 if (epkcnt >= 255) 1016 free_space = -1; 1017 else { 1018 erxst = nolock_regw_read(priv, ERXSTL); 1019 erxnd = nolock_regw_read(priv, ERXNDL); 1020 erxwr = nolock_regw_read(priv, ERXWRPTL); 1021 erxrd = nolock_regw_read(priv, ERXRDPTL); 1022 1023 if (erxwr > erxrd) 1024 free_space = (erxnd - erxst) - (erxwr - erxrd); 1025 else if (erxwr == erxrd) 1026 free_space = (erxnd - erxst); 1027 else 1028 free_space = erxrd - erxwr - 1; 1029 } 1030 mutex_unlock(&priv->lock); 1031 if (netif_msg_rx_status(priv)) 1032 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n", 1033 __func__, free_space); 1034 return free_space; 1035} 1036 1037/* 1038 * Access the PHY to determine link status 1039 */ 1040static void enc28j60_check_link_status(struct net_device *ndev) 1041{ 1042 struct enc28j60_net *priv = netdev_priv(ndev); 1043 u16 reg; 1044 int duplex; 1045 1046 reg = enc28j60_phy_read(priv, PHSTAT2); 1047 if (netif_msg_hw(priv)) 1048 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, " 1049 "PHSTAT2: %04x\n", __func__, 1050 enc28j60_phy_read(priv, PHSTAT1), reg); 1051 duplex = reg & PHSTAT2_DPXSTAT; 1052 1053 if (reg & PHSTAT2_LSTAT) { 1054 netif_carrier_on(ndev); 1055 if (netif_msg_ifup(priv)) 1056 dev_info(&ndev->dev, "link up - %s\n", 1057 duplex ? "Full duplex" : "Half duplex"); 1058 } else { 1059 if (netif_msg_ifdown(priv)) 1060 dev_info(&ndev->dev, "link down\n"); 1061 netif_carrier_off(ndev); 1062 } 1063} 1064 1065static void enc28j60_tx_clear(struct net_device *ndev, bool err) 1066{ 1067 struct enc28j60_net *priv = netdev_priv(ndev); 1068 1069 if (err) 1070 ndev->stats.tx_errors++; 1071 else 1072 ndev->stats.tx_packets++; 1073 1074 if (priv->tx_skb) { 1075 if (!err) 1076 ndev->stats.tx_bytes += priv->tx_skb->len; 1077 dev_kfree_skb(priv->tx_skb); 1078 priv->tx_skb = NULL; 1079 } 1080 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); 1081 netif_wake_queue(ndev); 1082} 1083 1084static int enc28j60_rx_interrupt(struct net_device *ndev) 1085{ 1086 struct enc28j60_net *priv = netdev_priv(ndev); 1087 int pk_counter, ret; 1088 1089 pk_counter = locked_regb_read(priv, EPKTCNT); 1090 if (pk_counter && netif_msg_intr(priv)) 1091 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter); 1092 if (pk_counter > priv->max_pk_counter) { 1093 /* update statistics */ 1094 priv->max_pk_counter = pk_counter; 1095 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1) 1096 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n", 1097 priv->max_pk_counter); 1098 } 1099 ret = pk_counter; 1100 while (pk_counter-- > 0) 1101 enc28j60_hw_rx(ndev); 1102 1103 return ret; 1104} 1105 1106static void enc28j60_irq_work_handler(struct work_struct *work) 1107{ 1108 struct enc28j60_net *priv = 1109 container_of(work, struct enc28j60_net, irq_work); 1110 struct net_device *ndev = priv->netdev; 1111 int intflags, loop; 1112 1113 if (netif_msg_intr(priv)) 1114 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); 1115 /* disable further interrupts */ 1116 locked_reg_bfclr(priv, EIE, EIE_INTIE); 1117 1118 do { 1119 loop = 0; 1120 intflags = locked_regb_read(priv, EIR); 1121 /* DMA interrupt handler (not currently used) */ 1122 if ((intflags & EIR_DMAIF) != 0) { 1123 loop++; 1124 if (netif_msg_intr(priv)) 1125 printk(KERN_DEBUG DRV_NAME 1126 ": intDMA(%d)\n", loop); 1127 locked_reg_bfclr(priv, EIR, EIR_DMAIF); 1128 } 1129 /* LINK changed handler */ 1130 if ((intflags & EIR_LINKIF) != 0) { 1131 loop++; 1132 if (netif_msg_intr(priv)) 1133 printk(KERN_DEBUG DRV_NAME 1134 ": intLINK(%d)\n", loop); 1135 enc28j60_check_link_status(ndev); 1136 /* read PHIR to clear the flag */ 1137 enc28j60_phy_read(priv, PHIR); 1138 } 1139 /* TX complete handler */ 1140 if ((intflags & EIR_TXIF) != 0) { 1141 bool err = false; 1142 loop++; 1143 if (netif_msg_intr(priv)) 1144 printk(KERN_DEBUG DRV_NAME 1145 ": intTX(%d)\n", loop); 1146 priv->tx_retry_count = 0; 1147 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) { 1148 if (netif_msg_tx_err(priv)) 1149 dev_err(&ndev->dev, 1150 "Tx Error (aborted)\n"); 1151 err = true; 1152 } 1153 if (netif_msg_tx_done(priv)) { 1154 u8 tsv[TSV_SIZE]; 1155 enc28j60_read_tsv(priv, tsv); 1156 enc28j60_dump_tsv(priv, "Tx Done", tsv); 1157 } 1158 enc28j60_tx_clear(ndev, err); 1159 locked_reg_bfclr(priv, EIR, EIR_TXIF); 1160 } 1161 /* TX Error handler */ 1162 if ((intflags & EIR_TXERIF) != 0) { 1163 u8 tsv[TSV_SIZE]; 1164 1165 loop++; 1166 if (netif_msg_intr(priv)) 1167 printk(KERN_DEBUG DRV_NAME 1168 ": intTXErr(%d)\n", loop); 1169 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); 1170 enc28j60_read_tsv(priv, tsv); 1171 if (netif_msg_tx_err(priv)) 1172 enc28j60_dump_tsv(priv, "Tx Error", tsv); 1173 /* Reset TX logic */ 1174 mutex_lock(&priv->lock); 1175 nolock_reg_bfset(priv, ECON1, ECON1_TXRST); 1176 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST); 1177 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); 1178 mutex_unlock(&priv->lock); 1179 /* Transmit Late collision check for retransmit */ 1180 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) { 1181 if (netif_msg_tx_err(priv)) 1182 printk(KERN_DEBUG DRV_NAME 1183 ": LateCollision TXErr (%d)\n", 1184 priv->tx_retry_count); 1185 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT) 1186 locked_reg_bfset(priv, ECON1, 1187 ECON1_TXRTS); 1188 else 1189 enc28j60_tx_clear(ndev, true); 1190 } else 1191 enc28j60_tx_clear(ndev, true); 1192 locked_reg_bfclr(priv, EIR, EIR_TXERIF); 1193 } 1194 /* RX Error handler */ 1195 if ((intflags & EIR_RXERIF) != 0) { 1196 loop++; 1197 if (netif_msg_intr(priv)) 1198 printk(KERN_DEBUG DRV_NAME 1199 ": intRXErr(%d)\n", loop); 1200 /* Check free FIFO space to flag RX overrun */ 1201 if (enc28j60_get_free_rxfifo(priv) <= 0) { 1202 if (netif_msg_rx_err(priv)) 1203 printk(KERN_DEBUG DRV_NAME 1204 ": RX Overrun\n"); 1205 ndev->stats.rx_dropped++; 1206 } 1207 locked_reg_bfclr(priv, EIR, EIR_RXERIF); 1208 } 1209 /* RX handler */ 1210 if (enc28j60_rx_interrupt(ndev)) 1211 loop++; 1212 } while (loop); 1213 1214 /* re-enable interrupts */ 1215 locked_reg_bfset(priv, EIE, EIE_INTIE); 1216 if (netif_msg_intr(priv)) 1217 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__); 1218} 1219 1220/* 1221 * Hardware transmit function. 1222 * Fill the buffer memory and send the contents of the transmit buffer 1223 * onto the network 1224 */ 1225static void enc28j60_hw_tx(struct enc28j60_net *priv) 1226{ 1227 if (netif_msg_tx_queued(priv)) 1228 printk(KERN_DEBUG DRV_NAME 1229 ": Tx Packet Len:%d\n", priv->tx_skb->len); 1230 1231 if (netif_msg_pktdata(priv)) 1232 dump_packet(__func__, 1233 priv->tx_skb->len, priv->tx_skb->data); 1234 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data); 1235 1236#ifdef CONFIG_ENC28J60_WRITEVERIFY 1237 /* readback and verify written data */ 1238 if (netif_msg_drv(priv)) { 1239 int test_len, k; 1240 u8 test_buf[64]; /* limit the test to the first 64 bytes */ 1241 int okflag; 1242 1243 test_len = priv->tx_skb->len; 1244 if (test_len > sizeof(test_buf)) 1245 test_len = sizeof(test_buf); 1246 1247 /* + 1 to skip control byte */ 1248 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf); 1249 okflag = 1; 1250 for (k = 0; k < test_len; k++) { 1251 if (priv->tx_skb->data[k] != test_buf[k]) { 1252 printk(KERN_DEBUG DRV_NAME 1253 ": Error, %d location differ: " 1254 "0x%02x-0x%02x\n", k, 1255 priv->tx_skb->data[k], test_buf[k]); 1256 okflag = 0; 1257 } 1258 } 1259 if (!okflag) 1260 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, " 1261 "verify ERROR!\n"); 1262 } 1263#endif 1264 /* set TX request flag */ 1265 locked_reg_bfset(priv, ECON1, ECON1_TXRTS); 1266} 1267 1268static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb, 1269 struct net_device *dev) 1270{ 1271 struct enc28j60_net *priv = netdev_priv(dev); 1272 1273 if (netif_msg_tx_queued(priv)) 1274 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); 1275 1276 /* If some error occurs while trying to transmit this 1277 * packet, you should return '1' from this function. 1278 * In such a case you _may not_ do anything to the 1279 * SKB, it is still owned by the network queueing 1280 * layer when an error is returned. This means you 1281 * may not modify any SKB fields, you may not free 1282 * the SKB, etc. 1283 */ 1284 netif_stop_queue(dev); 1285 1286 /* Remember the skb for deferred processing */ 1287 priv->tx_skb = skb; 1288 schedule_work(&priv->tx_work); 1289 1290 return NETDEV_TX_OK; 1291} 1292 1293static void enc28j60_tx_work_handler(struct work_struct *work) 1294{ 1295 struct enc28j60_net *priv = 1296 container_of(work, struct enc28j60_net, tx_work); 1297 1298 /* actual delivery of data */ 1299 enc28j60_hw_tx(priv); 1300} 1301 1302static irqreturn_t enc28j60_irq(int irq, void *dev_id) 1303{ 1304 struct enc28j60_net *priv = dev_id; 1305 1306 /* 1307 * Can't do anything in interrupt context because we need to 1308 * block (spi_sync() is blocking) so fire of the interrupt 1309 * handling workqueue. 1310 * Remember that we access enc28j60 registers through SPI bus 1311 * via spi_sync() call. 1312 */ 1313 schedule_work(&priv->irq_work); 1314 1315 return IRQ_HANDLED; 1316} 1317 1318static void enc28j60_tx_timeout(struct net_device *ndev) 1319{ 1320 struct enc28j60_net *priv = netdev_priv(ndev); 1321 1322 if (netif_msg_timer(priv)) 1323 dev_err(&ndev->dev, DRV_NAME " tx timeout\n"); 1324 1325 ndev->stats.tx_errors++; 1326 /* can't restart safely under softirq */ 1327 schedule_work(&priv->restart_work); 1328} 1329 1330/* 1331 * Open/initialize the board. This is called (in the current kernel) 1332 * sometime after booting when the 'ifconfig' program is run. 1333 * 1334 * This routine should set everything up anew at each open, even 1335 * registers that "should" only need to be set once at boot, so that 1336 * there is non-reboot way to recover if something goes wrong. 1337 */ 1338static int enc28j60_net_open(struct net_device *dev) 1339{ 1340 struct enc28j60_net *priv = netdev_priv(dev); 1341 1342 if (netif_msg_drv(priv)) 1343 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); 1344 1345 if (!is_valid_ether_addr(dev->dev_addr)) { 1346 if (netif_msg_ifup(priv)) 1347 dev_err(&dev->dev, "invalid MAC address %pM\n", 1348 dev->dev_addr); 1349 return -EADDRNOTAVAIL; 1350 } 1351 /* Reset the hardware here (and take it out of low power mode) */ 1352 enc28j60_lowpower(priv, false); 1353 enc28j60_hw_disable(priv); 1354 if (!enc28j60_hw_init(priv)) { 1355 if (netif_msg_ifup(priv)) 1356 dev_err(&dev->dev, "hw_reset() failed\n"); 1357 return -EINVAL; 1358 } 1359 /* Update the MAC address (in case user has changed it) */ 1360 enc28j60_set_hw_macaddr(dev); 1361 /* Enable interrupts */ 1362 enc28j60_hw_enable(priv); 1363 /* check link status */ 1364 enc28j60_check_link_status(dev); 1365 /* We are now ready to accept transmit requests from 1366 * the queueing layer of the networking. 1367 */ 1368 netif_start_queue(dev); 1369 1370 return 0; 1371} 1372 1373/* The inverse routine to net_open(). */ 1374static int enc28j60_net_close(struct net_device *dev) 1375{ 1376 struct enc28j60_net *priv = netdev_priv(dev); 1377 1378 if (netif_msg_drv(priv)) 1379 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); 1380 1381 enc28j60_hw_disable(priv); 1382 enc28j60_lowpower(priv, true); 1383 netif_stop_queue(dev); 1384 1385 return 0; 1386} 1387 1388/* 1389 * Set or clear the multicast filter for this adapter 1390 * num_addrs == -1 Promiscuous mode, receive all packets 1391 * num_addrs == 0 Normal mode, filter out multicast packets 1392 * num_addrs > 0 Multicast mode, receive normal and MC packets 1393 */ 1394static void enc28j60_set_multicast_list(struct net_device *dev) 1395{ 1396 struct enc28j60_net *priv = netdev_priv(dev); 1397 int oldfilter = priv->rxfilter; 1398 1399 if (dev->flags & IFF_PROMISC) { 1400 if (netif_msg_link(priv)) 1401 dev_info(&dev->dev, "promiscuous mode\n"); 1402 priv->rxfilter = RXFILTER_PROMISC; 1403 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) { 1404 if (netif_msg_link(priv)) 1405 dev_info(&dev->dev, "%smulticast mode\n", 1406 (dev->flags & IFF_ALLMULTI) ? "all-" : ""); 1407 priv->rxfilter = RXFILTER_MULTI; 1408 } else { 1409 if (netif_msg_link(priv)) 1410 dev_info(&dev->dev, "normal mode\n"); 1411 priv->rxfilter = RXFILTER_NORMAL; 1412 } 1413 1414 if (oldfilter != priv->rxfilter) 1415 schedule_work(&priv->setrx_work); 1416} 1417 1418static void enc28j60_setrx_work_handler(struct work_struct *work) 1419{ 1420 struct enc28j60_net *priv = 1421 container_of(work, struct enc28j60_net, setrx_work); 1422 1423 if (priv->rxfilter == RXFILTER_PROMISC) { 1424 if (netif_msg_drv(priv)) 1425 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n"); 1426 locked_regb_write(priv, ERXFCON, 0x00); 1427 } else if (priv->rxfilter == RXFILTER_MULTI) { 1428 if (netif_msg_drv(priv)) 1429 printk(KERN_DEBUG DRV_NAME ": multicast mode\n"); 1430 locked_regb_write(priv, ERXFCON, 1431 ERXFCON_UCEN | ERXFCON_CRCEN | 1432 ERXFCON_BCEN | ERXFCON_MCEN); 1433 } else { 1434 if (netif_msg_drv(priv)) 1435 printk(KERN_DEBUG DRV_NAME ": normal mode\n"); 1436 locked_regb_write(priv, ERXFCON, 1437 ERXFCON_UCEN | ERXFCON_CRCEN | 1438 ERXFCON_BCEN); 1439 } 1440} 1441 1442static void enc28j60_restart_work_handler(struct work_struct *work) 1443{ 1444 struct enc28j60_net *priv = 1445 container_of(work, struct enc28j60_net, restart_work); 1446 struct net_device *ndev = priv->netdev; 1447 int ret; 1448 1449 rtnl_lock(); 1450 if (netif_running(ndev)) { 1451 enc28j60_net_close(ndev); 1452 ret = enc28j60_net_open(ndev); 1453 if (unlikely(ret)) { 1454 dev_info(&ndev->dev, " could not restart %d\n", ret); 1455 dev_close(ndev); 1456 } 1457 } 1458 rtnl_unlock(); 1459} 1460 1461/* ......................... ETHTOOL SUPPORT ........................... */ 1462 1463static void 1464enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1465{ 1466 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1467 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1468 strlcpy(info->bus_info, 1469 dev_name(dev->dev.parent), sizeof(info->bus_info)); 1470} 1471 1472static int 1473enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1474{ 1475 struct enc28j60_net *priv = netdev_priv(dev); 1476 1477 cmd->transceiver = XCVR_INTERNAL; 1478 cmd->supported = SUPPORTED_10baseT_Half 1479 | SUPPORTED_10baseT_Full 1480 | SUPPORTED_TP; 1481 cmd->speed = SPEED_10; 1482 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 1483 cmd->port = PORT_TP; 1484 cmd->autoneg = AUTONEG_DISABLE; 1485 1486 return 0; 1487} 1488 1489static int 1490enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1491{ 1492 return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex); 1493} 1494 1495static u32 enc28j60_get_msglevel(struct net_device *dev) 1496{ 1497 struct enc28j60_net *priv = netdev_priv(dev); 1498 return priv->msg_enable; 1499} 1500 1501static void enc28j60_set_msglevel(struct net_device *dev, u32 val) 1502{ 1503 struct enc28j60_net *priv = netdev_priv(dev); 1504 priv->msg_enable = val; 1505} 1506 1507static const struct ethtool_ops enc28j60_ethtool_ops = { 1508 .get_settings = enc28j60_get_settings, 1509 .set_settings = enc28j60_set_settings, 1510 .get_drvinfo = enc28j60_get_drvinfo, 1511 .get_msglevel = enc28j60_get_msglevel, 1512 .set_msglevel = enc28j60_set_msglevel, 1513}; 1514 1515static int enc28j60_chipset_init(struct net_device *dev) 1516{ 1517 struct enc28j60_net *priv = netdev_priv(dev); 1518 1519 return enc28j60_hw_init(priv); 1520} 1521 1522static const struct net_device_ops enc28j60_netdev_ops = { 1523 .ndo_open = enc28j60_net_open, 1524 .ndo_stop = enc28j60_net_close, 1525 .ndo_start_xmit = enc28j60_send_packet, 1526 .ndo_set_multicast_list = enc28j60_set_multicast_list, 1527 .ndo_set_mac_address = enc28j60_set_mac_address, 1528 .ndo_tx_timeout = enc28j60_tx_timeout, 1529 .ndo_change_mtu = eth_change_mtu, 1530 .ndo_validate_addr = eth_validate_addr, 1531}; 1532 1533static int __devinit enc28j60_probe(struct spi_device *spi) 1534{ 1535 struct net_device *dev; 1536 struct enc28j60_net *priv; 1537 int ret = 0; 1538 1539 if (netif_msg_drv(&debug)) 1540 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n", 1541 DRV_VERSION); 1542 1543 dev = alloc_etherdev(sizeof(struct enc28j60_net)); 1544 if (!dev) { 1545 if (netif_msg_drv(&debug)) 1546 dev_err(&spi->dev, DRV_NAME 1547 ": unable to alloc new ethernet\n"); 1548 ret = -ENOMEM; 1549 goto error_alloc; 1550 } 1551 priv = netdev_priv(dev); 1552 1553 priv->netdev = dev; /* priv to netdev reference */ 1554 priv->spi = spi; /* priv to spi reference */ 1555 priv->msg_enable = netif_msg_init(debug.msg_enable, 1556 ENC28J60_MSG_DEFAULT); 1557 mutex_init(&priv->lock); 1558 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler); 1559 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler); 1560 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler); 1561 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler); 1562 dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */ 1563 SET_NETDEV_DEV(dev, &spi->dev); 1564 1565 if (!enc28j60_chipset_init(dev)) { 1566 if (netif_msg_probe(priv)) 1567 dev_info(&spi->dev, DRV_NAME " chip not found\n"); 1568 ret = -EIO; 1569 goto error_irq; 1570 } 1571 random_ether_addr(dev->dev_addr); 1572 enc28j60_set_hw_macaddr(dev); 1573 1574 /* Board setup must set the relevant edge trigger type; 1575 * level triggers won't currently work. 1576 */ 1577 ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv); 1578 if (ret < 0) { 1579 if (netif_msg_probe(priv)) 1580 dev_err(&spi->dev, DRV_NAME ": request irq %d failed " 1581 "(ret = %d)\n", spi->irq, ret); 1582 goto error_irq; 1583 } 1584 1585 dev->if_port = IF_PORT_10BASET; 1586 dev->irq = spi->irq; 1587 dev->netdev_ops = &enc28j60_netdev_ops; 1588 dev->watchdog_timeo = TX_TIMEOUT; 1589 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops); 1590 1591 enc28j60_lowpower(priv, true); 1592 1593 ret = register_netdev(dev); 1594 if (ret) { 1595 if (netif_msg_probe(priv)) 1596 dev_err(&spi->dev, "register netdev " DRV_NAME 1597 " failed (ret = %d)\n", ret); 1598 goto error_register; 1599 } 1600 dev_info(&dev->dev, DRV_NAME " driver registered\n"); 1601 1602 return 0; 1603 1604error_register: 1605 free_irq(spi->irq, priv); 1606error_irq: 1607 free_netdev(dev); 1608error_alloc: 1609 return ret; 1610} 1611 1612static int __devexit enc28j60_remove(struct spi_device *spi) 1613{ 1614 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev); 1615 1616 if (netif_msg_drv(priv)) 1617 printk(KERN_DEBUG DRV_NAME ": remove\n"); 1618 1619 unregister_netdev(priv->netdev); 1620 free_irq(spi->irq, priv); 1621 free_netdev(priv->netdev); 1622 1623 return 0; 1624} 1625 1626static struct spi_driver enc28j60_driver = { 1627 .driver = { 1628 .name = DRV_NAME, 1629 .owner = THIS_MODULE, 1630 }, 1631 .probe = enc28j60_probe, 1632 .remove = __devexit_p(enc28j60_remove), 1633}; 1634 1635static int __init enc28j60_init(void) 1636{ 1637 msec20_to_jiffies = msecs_to_jiffies(20); 1638 1639 return spi_register_driver(&enc28j60_driver); 1640} 1641 1642module_init(enc28j60_init); 1643 1644static void __exit enc28j60_exit(void) 1645{ 1646 spi_unregister_driver(&enc28j60_driver); 1647} 1648 1649module_exit(enc28j60_exit); 1650 1651MODULE_DESCRIPTION(DRV_NAME " ethernet driver"); 1652MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>"); 1653MODULE_LICENSE("GPL"); 1654module_param_named(debug, debug.msg_enable, int, 0); 1655MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)"); 1656MODULE_ALIAS("spi:" DRV_NAME); 1657