1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2010 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29/* 30 * 82562G 10/100 Network Connection 31 * 82562G-2 10/100 Network Connection 32 * 82562GT 10/100 Network Connection 33 * 82562GT-2 10/100 Network Connection 34 * 82562V 10/100 Network Connection 35 * 82562V-2 10/100 Network Connection 36 * 82566DC-2 Gigabit Network Connection 37 * 82566DC Gigabit Network Connection 38 * 82566DM-2 Gigabit Network Connection 39 * 82566DM Gigabit Network Connection 40 * 82566MC Gigabit Network Connection 41 * 82566MM Gigabit Network Connection 42 * 82567LM Gigabit Network Connection 43 * 82567LF Gigabit Network Connection 44 * 82567V Gigabit Network Connection 45 * 82567LM-2 Gigabit Network Connection 46 * 82567LF-2 Gigabit Network Connection 47 * 82567V-2 Gigabit Network Connection 48 * 82567LF-3 Gigabit Network Connection 49 * 82567LM-3 Gigabit Network Connection 50 * 82567LM-4 Gigabit Network Connection 51 * 82577LM Gigabit Network Connection 52 * 82577LC Gigabit Network Connection 53 * 82578DM Gigabit Network Connection 54 * 82578DC Gigabit Network Connection 55 * 82579LM Gigabit Network Connection 56 * 82579V Gigabit Network Connection 57 */ 58 59#include "e1000.h" 60 61#define ICH_FLASH_GFPREG 0x0000 62#define ICH_FLASH_HSFSTS 0x0004 63#define ICH_FLASH_HSFCTL 0x0006 64#define ICH_FLASH_FADDR 0x0008 65#define ICH_FLASH_FDATA0 0x0010 66#define ICH_FLASH_PR0 0x0074 67 68#define ICH_FLASH_READ_COMMAND_TIMEOUT 500 69#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 70#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 71#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 72#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 73 74#define ICH_CYCLE_READ 0 75#define ICH_CYCLE_WRITE 2 76#define ICH_CYCLE_ERASE 3 77 78#define FLASH_GFPREG_BASE_MASK 0x1FFF 79#define FLASH_SECTOR_ADDR_SHIFT 12 80 81#define ICH_FLASH_SEG_SIZE_256 256 82#define ICH_FLASH_SEG_SIZE_4K 4096 83#define ICH_FLASH_SEG_SIZE_8K 8192 84#define ICH_FLASH_SEG_SIZE_64K 65536 85 86 87#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 88/* FW established a valid mode */ 89#define E1000_ICH_FWSM_FW_VALID 0x00008000 90 91#define E1000_ICH_MNG_IAMT_MODE 0x2 92 93#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 94 (ID_LED_DEF1_OFF2 << 8) | \ 95 (ID_LED_DEF1_ON2 << 4) | \ 96 (ID_LED_DEF1_DEF2)) 97 98#define E1000_ICH_NVM_SIG_WORD 0x13 99#define E1000_ICH_NVM_SIG_MASK 0xC000 100#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 101#define E1000_ICH_NVM_SIG_VALUE 0x80 102 103#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 104 105#define E1000_FEXTNVM_SW_CONFIG 1 106#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ 107 108#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 109#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 110#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 111 112#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 113 114#define E1000_ICH_RAR_ENTRIES 7 115 116#define PHY_PAGE_SHIFT 5 117#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 118 ((reg) & MAX_PHY_REG_ADDRESS)) 119#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 120#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 121 122#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 123#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 124#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 125 126#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 127 128#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ 129 130/* SMBus Address Phy Register */ 131#define HV_SMB_ADDR PHY_REG(768, 26) 132#define HV_SMB_ADDR_MASK 0x007F 133#define HV_SMB_ADDR_PEC_EN 0x0200 134#define HV_SMB_ADDR_VALID 0x0080 135 136/* PHY Power Management Control */ 137#define HV_PM_CTRL PHY_REG(770, 17) 138 139/* PHY Low Power Idle Control */ 140#define I82579_LPI_CTRL PHY_REG(772, 20) 141#define I82579_LPI_CTRL_ENABLE_MASK 0x6000 142 143/* Strapping Option Register - RO */ 144#define E1000_STRAP 0x0000C 145#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 146#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 147 148/* OEM Bits Phy Register */ 149#define HV_OEM_BITS PHY_REG(768, 25) 150#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 151#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 152#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 153 154#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 155#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 156 157/* KMRN Mode Control */ 158#define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 159#define HV_KMRN_MDIO_SLOW 0x0400 160 161/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 162/* Offset 04h HSFSTS */ 163union ich8_hws_flash_status { 164 struct ich8_hsfsts { 165 u16 flcdone :1; /* bit 0 Flash Cycle Done */ 166 u16 flcerr :1; /* bit 1 Flash Cycle Error */ 167 u16 dael :1; /* bit 2 Direct Access error Log */ 168 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 169 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 170 u16 reserved1 :2; /* bit 13:6 Reserved */ 171 u16 reserved2 :6; /* bit 13:6 Reserved */ 172 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 173 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 174 } hsf_status; 175 u16 regval; 176}; 177 178/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 179/* Offset 06h FLCTL */ 180union ich8_hws_flash_ctrl { 181 struct ich8_hsflctl { 182 u16 flcgo :1; /* 0 Flash Cycle Go */ 183 u16 flcycle :2; /* 2:1 Flash Cycle */ 184 u16 reserved :5; /* 7:3 Reserved */ 185 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 186 u16 flockdn :6; /* 15:10 Reserved */ 187 } hsf_ctrl; 188 u16 regval; 189}; 190 191/* ICH Flash Region Access Permissions */ 192union ich8_hws_flash_regacc { 193 struct ich8_flracc { 194 u32 grra :8; /* 0:7 GbE region Read Access */ 195 u32 grwa :8; /* 8:15 GbE region Write Access */ 196 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 197 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 198 } hsf_flregacc; 199 u16 regval; 200}; 201 202/* ICH Flash Protected Region */ 203union ich8_flash_protected_range { 204 struct ich8_pr { 205 u32 base:13; /* 0:12 Protected Range Base */ 206 u32 reserved1:2; /* 13:14 Reserved */ 207 u32 rpe:1; /* 15 Read Protection Enable */ 208 u32 limit:13; /* 16:28 Protected Range Limit */ 209 u32 reserved2:2; /* 29:30 Reserved */ 210 u32 wpe:1; /* 31 Write Protection Enable */ 211 } range; 212 u32 regval; 213}; 214 215static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 216static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 217static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 218static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 219static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 220 u32 offset, u8 byte); 221static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 222 u8 *data); 223static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 224 u16 *data); 225static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 226 u8 size, u16 *data); 227static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 228static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 229static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 230static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 231static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 232static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 233static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 234static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 235static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 236static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 237static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 238static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 239static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 240static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 241static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 242static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 243static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 244static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 245static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 246static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 247 248static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 249{ 250 return readw(hw->flash_address + reg); 251} 252 253static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 254{ 255 return readl(hw->flash_address + reg); 256} 257 258static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 259{ 260 writew(val, hw->flash_address + reg); 261} 262 263static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 264{ 265 writel(val, hw->flash_address + reg); 266} 267 268#define er16flash(reg) __er16flash(hw, (reg)) 269#define er32flash(reg) __er32flash(hw, (reg)) 270#define ew16flash(reg,val) __ew16flash(hw, (reg), (val)) 271#define ew32flash(reg,val) __ew32flash(hw, (reg), (val)) 272 273/** 274 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 275 * @hw: pointer to the HW structure 276 * 277 * Initialize family-specific PHY parameters and function pointers. 278 **/ 279static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 280{ 281 struct e1000_phy_info *phy = &hw->phy; 282 u32 ctrl, fwsm; 283 s32 ret_val = 0; 284 285 phy->addr = 1; 286 phy->reset_delay_us = 100; 287 288 phy->ops.read_reg = e1000_read_phy_reg_hv; 289 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 290 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 291 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 292 phy->ops.write_reg = e1000_write_phy_reg_hv; 293 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 294 phy->ops.power_up = e1000_power_up_phy_copper; 295 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 296 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 297 298 /* 299 * The MAC-PHY interconnect may still be in SMBus mode 300 * after Sx->S0. If the manageability engine (ME) is 301 * disabled, then toggle the LANPHYPC Value bit to force 302 * the interconnect to PCIe mode. 303 */ 304 fwsm = er32(FWSM); 305 if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) { 306 ctrl = er32(CTRL); 307 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 308 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 309 ew32(CTRL, ctrl); 310 udelay(10); 311 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 312 ew32(CTRL, ctrl); 313 msleep(50); 314 315 /* 316 * Gate automatic PHY configuration by hardware on 317 * non-managed 82579 318 */ 319 if (hw->mac.type == e1000_pch2lan) 320 e1000_gate_hw_phy_config_ich8lan(hw, true); 321 } 322 323 /* 324 * Reset the PHY before any acccess to it. Doing so, ensures that 325 * the PHY is in a known good state before we read/write PHY registers. 326 * The generic reset is sufficient here, because we haven't determined 327 * the PHY type yet. 328 */ 329 ret_val = e1000e_phy_hw_reset_generic(hw); 330 if (ret_val) 331 goto out; 332 333 /* Ungate automatic PHY configuration on non-managed 82579 */ 334 if ((hw->mac.type == e1000_pch2lan) && 335 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 336 msleep(10); 337 e1000_gate_hw_phy_config_ich8lan(hw, false); 338 } 339 340 phy->id = e1000_phy_unknown; 341 ret_val = e1000e_get_phy_id(hw); 342 if (ret_val) 343 goto out; 344 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) { 345 /* 346 * In case the PHY needs to be in mdio slow mode (eg. 82577), 347 * set slow mode and try to get the PHY id again. 348 */ 349 ret_val = e1000_set_mdio_slow_mode_hv(hw); 350 if (ret_val) 351 goto out; 352 ret_val = e1000e_get_phy_id(hw); 353 if (ret_val) 354 goto out; 355 } 356 phy->type = e1000e_get_phy_type_from_id(phy->id); 357 358 switch (phy->type) { 359 case e1000_phy_82577: 360 case e1000_phy_82579: 361 phy->ops.check_polarity = e1000_check_polarity_82577; 362 phy->ops.force_speed_duplex = 363 e1000_phy_force_speed_duplex_82577; 364 phy->ops.get_cable_length = e1000_get_cable_length_82577; 365 phy->ops.get_info = e1000_get_phy_info_82577; 366 phy->ops.commit = e1000e_phy_sw_reset; 367 break; 368 case e1000_phy_82578: 369 phy->ops.check_polarity = e1000_check_polarity_m88; 370 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 371 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 372 phy->ops.get_info = e1000e_get_phy_info_m88; 373 break; 374 default: 375 ret_val = -E1000_ERR_PHY; 376 break; 377 } 378 379out: 380 return ret_val; 381} 382 383/** 384 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 385 * @hw: pointer to the HW structure 386 * 387 * Initialize family-specific PHY parameters and function pointers. 388 **/ 389static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 390{ 391 struct e1000_phy_info *phy = &hw->phy; 392 s32 ret_val; 393 u16 i = 0; 394 395 phy->addr = 1; 396 phy->reset_delay_us = 100; 397 398 phy->ops.power_up = e1000_power_up_phy_copper; 399 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 400 401 /* 402 * We may need to do this twice - once for IGP and if that fails, 403 * we'll set BM func pointers and try again 404 */ 405 ret_val = e1000e_determine_phy_address(hw); 406 if (ret_val) { 407 phy->ops.write_reg = e1000e_write_phy_reg_bm; 408 phy->ops.read_reg = e1000e_read_phy_reg_bm; 409 ret_val = e1000e_determine_phy_address(hw); 410 if (ret_val) { 411 e_dbg("Cannot determine PHY addr. Erroring out\n"); 412 return ret_val; 413 } 414 } 415 416 phy->id = 0; 417 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 418 (i++ < 100)) { 419 msleep(1); 420 ret_val = e1000e_get_phy_id(hw); 421 if (ret_val) 422 return ret_val; 423 } 424 425 /* Verify phy id */ 426 switch (phy->id) { 427 case IGP03E1000_E_PHY_ID: 428 phy->type = e1000_phy_igp_3; 429 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 430 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 431 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 432 phy->ops.get_info = e1000e_get_phy_info_igp; 433 phy->ops.check_polarity = e1000_check_polarity_igp; 434 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 435 break; 436 case IFE_E_PHY_ID: 437 case IFE_PLUS_E_PHY_ID: 438 case IFE_C_E_PHY_ID: 439 phy->type = e1000_phy_ife; 440 phy->autoneg_mask = E1000_ALL_NOT_GIG; 441 phy->ops.get_info = e1000_get_phy_info_ife; 442 phy->ops.check_polarity = e1000_check_polarity_ife; 443 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 444 break; 445 case BME1000_E_PHY_ID: 446 phy->type = e1000_phy_bm; 447 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 448 phy->ops.read_reg = e1000e_read_phy_reg_bm; 449 phy->ops.write_reg = e1000e_write_phy_reg_bm; 450 phy->ops.commit = e1000e_phy_sw_reset; 451 phy->ops.get_info = e1000e_get_phy_info_m88; 452 phy->ops.check_polarity = e1000_check_polarity_m88; 453 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 454 break; 455 default: 456 return -E1000_ERR_PHY; 457 break; 458 } 459 460 return 0; 461} 462 463/** 464 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 465 * @hw: pointer to the HW structure 466 * 467 * Initialize family-specific NVM parameters and function 468 * pointers. 469 **/ 470static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 471{ 472 struct e1000_nvm_info *nvm = &hw->nvm; 473 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 474 u32 gfpreg, sector_base_addr, sector_end_addr; 475 u16 i; 476 477 /* Can't read flash registers if the register set isn't mapped. */ 478 if (!hw->flash_address) { 479 e_dbg("ERROR: Flash registers not mapped\n"); 480 return -E1000_ERR_CONFIG; 481 } 482 483 nvm->type = e1000_nvm_flash_sw; 484 485 gfpreg = er32flash(ICH_FLASH_GFPREG); 486 487 /* 488 * sector_X_addr is a "sector"-aligned address (4096 bytes) 489 * Add 1 to sector_end_addr since this sector is included in 490 * the overall size. 491 */ 492 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 493 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 494 495 /* flash_base_addr is byte-aligned */ 496 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 497 498 /* 499 * find total size of the NVM, then cut in half since the total 500 * size represents two separate NVM banks. 501 */ 502 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 503 << FLASH_SECTOR_ADDR_SHIFT; 504 nvm->flash_bank_size /= 2; 505 /* Adjust to word count */ 506 nvm->flash_bank_size /= sizeof(u16); 507 508 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 509 510 /* Clear shadow ram */ 511 for (i = 0; i < nvm->word_size; i++) { 512 dev_spec->shadow_ram[i].modified = false; 513 dev_spec->shadow_ram[i].value = 0xFFFF; 514 } 515 516 return 0; 517} 518 519/** 520 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 521 * @hw: pointer to the HW structure 522 * 523 * Initialize family-specific MAC parameters and function 524 * pointers. 525 **/ 526static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) 527{ 528 struct e1000_hw *hw = &adapter->hw; 529 struct e1000_mac_info *mac = &hw->mac; 530 531 /* Set media type function pointer */ 532 hw->phy.media_type = e1000_media_type_copper; 533 534 /* Set mta register count */ 535 mac->mta_reg_count = 32; 536 /* Set rar entry count */ 537 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 538 if (mac->type == e1000_ich8lan) 539 mac->rar_entry_count--; 540 /* FWSM register */ 541 mac->has_fwsm = true; 542 /* ARC subsystem not supported */ 543 mac->arc_subsystem_valid = false; 544 /* Adaptive IFS supported */ 545 mac->adaptive_ifs = true; 546 547 /* LED operations */ 548 switch (mac->type) { 549 case e1000_ich8lan: 550 case e1000_ich9lan: 551 case e1000_ich10lan: 552 /* check management mode */ 553 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 554 /* ID LED init */ 555 mac->ops.id_led_init = e1000e_id_led_init; 556 /* setup LED */ 557 mac->ops.setup_led = e1000e_setup_led_generic; 558 /* cleanup LED */ 559 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 560 /* turn on/off LED */ 561 mac->ops.led_on = e1000_led_on_ich8lan; 562 mac->ops.led_off = e1000_led_off_ich8lan; 563 break; 564 case e1000_pchlan: 565 case e1000_pch2lan: 566 /* check management mode */ 567 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 568 /* ID LED init */ 569 mac->ops.id_led_init = e1000_id_led_init_pchlan; 570 /* setup LED */ 571 mac->ops.setup_led = e1000_setup_led_pchlan; 572 /* cleanup LED */ 573 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 574 /* turn on/off LED */ 575 mac->ops.led_on = e1000_led_on_pchlan; 576 mac->ops.led_off = e1000_led_off_pchlan; 577 break; 578 default: 579 break; 580 } 581 582 if (mac->type == e1000_ich8lan) 583 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 584 585 /* Gate automatic PHY configuration by hardware on managed 82579 */ 586 if ((mac->type == e1000_pch2lan) && 587 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 588 e1000_gate_hw_phy_config_ich8lan(hw, true); 589 590 return 0; 591} 592 593/** 594 * e1000_set_eee_pchlan - Enable/disable EEE support 595 * @hw: pointer to the HW structure 596 * 597 * Enable/disable EEE based on setting in dev_spec structure. The bits in 598 * the LPI Control register will remain set only if/when link is up. 599 **/ 600static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 601{ 602 s32 ret_val = 0; 603 u16 phy_reg; 604 605 if (hw->phy.type != e1000_phy_82579) 606 goto out; 607 608 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); 609 if (ret_val) 610 goto out; 611 612 if (hw->dev_spec.ich8lan.eee_disable) 613 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 614 else 615 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 616 617 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); 618out: 619 return ret_val; 620} 621 622/** 623 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 624 * @hw: pointer to the HW structure 625 * 626 * Checks to see of the link status of the hardware has changed. If a 627 * change in link status has been detected, then we read the PHY registers 628 * to get the current speed/duplex if link exists. 629 **/ 630static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 631{ 632 struct e1000_mac_info *mac = &hw->mac; 633 s32 ret_val; 634 bool link; 635 636 /* 637 * We only want to go out to the PHY registers to see if Auto-Neg 638 * has completed and/or if our link status has changed. The 639 * get_link_status flag is set upon receiving a Link Status 640 * Change or Rx Sequence Error interrupt. 641 */ 642 if (!mac->get_link_status) { 643 ret_val = 0; 644 goto out; 645 } 646 647 /* 648 * First we want to see if the MII Status Register reports 649 * link. If so, then we want to get the current speed/duplex 650 * of the PHY. 651 */ 652 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 653 if (ret_val) 654 goto out; 655 656 if (hw->mac.type == e1000_pchlan) { 657 ret_val = e1000_k1_gig_workaround_hv(hw, link); 658 if (ret_val) 659 goto out; 660 } 661 662 if (!link) 663 goto out; /* No link detected */ 664 665 mac->get_link_status = false; 666 667 if (hw->phy.type == e1000_phy_82578) { 668 ret_val = e1000_link_stall_workaround_hv(hw); 669 if (ret_val) 670 goto out; 671 } 672 673 if (hw->mac.type == e1000_pch2lan) { 674 ret_val = e1000_k1_workaround_lv(hw); 675 if (ret_val) 676 goto out; 677 } 678 679 /* 680 * Check if there was DownShift, must be checked 681 * immediately after link-up 682 */ 683 e1000e_check_downshift(hw); 684 685 /* Enable/Disable EEE after link up */ 686 ret_val = e1000_set_eee_pchlan(hw); 687 if (ret_val) 688 goto out; 689 690 /* 691 * If we are forcing speed/duplex, then we simply return since 692 * we have already determined whether we have link or not. 693 */ 694 if (!mac->autoneg) { 695 ret_val = -E1000_ERR_CONFIG; 696 goto out; 697 } 698 699 /* 700 * Auto-Neg is enabled. Auto Speed Detection takes care 701 * of MAC speed/duplex configuration. So we only need to 702 * configure Collision Distance in the MAC. 703 */ 704 e1000e_config_collision_dist(hw); 705 706 /* 707 * Configure Flow Control now that Auto-Neg has completed. 708 * First, we need to restore the desired flow control 709 * settings because we may have had to re-autoneg with a 710 * different link partner. 711 */ 712 ret_val = e1000e_config_fc_after_link_up(hw); 713 if (ret_val) 714 e_dbg("Error configuring flow control\n"); 715 716out: 717 return ret_val; 718} 719 720static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 721{ 722 struct e1000_hw *hw = &adapter->hw; 723 s32 rc; 724 725 rc = e1000_init_mac_params_ich8lan(adapter); 726 if (rc) 727 return rc; 728 729 rc = e1000_init_nvm_params_ich8lan(hw); 730 if (rc) 731 return rc; 732 733 switch (hw->mac.type) { 734 case e1000_ich8lan: 735 case e1000_ich9lan: 736 case e1000_ich10lan: 737 rc = e1000_init_phy_params_ich8lan(hw); 738 break; 739 case e1000_pchlan: 740 case e1000_pch2lan: 741 rc = e1000_init_phy_params_pchlan(hw); 742 break; 743 default: 744 break; 745 } 746 if (rc) 747 return rc; 748 749 if (adapter->hw.phy.type == e1000_phy_ife) { 750 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 751 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; 752 } 753 754 if ((adapter->hw.mac.type == e1000_ich8lan) && 755 (adapter->hw.phy.type == e1000_phy_igp_3)) 756 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 757 758 /* Disable EEE by default until IEEE802.3az spec is finalized */ 759 if (adapter->flags2 & FLAG2_HAS_EEE) 760 adapter->hw.dev_spec.ich8lan.eee_disable = true; 761 762 return 0; 763} 764 765static DEFINE_MUTEX(nvm_mutex); 766 767/** 768 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 769 * @hw: pointer to the HW structure 770 * 771 * Acquires the mutex for performing NVM operations. 772 **/ 773static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 774{ 775 mutex_lock(&nvm_mutex); 776 777 return 0; 778} 779 780/** 781 * e1000_release_nvm_ich8lan - Release NVM mutex 782 * @hw: pointer to the HW structure 783 * 784 * Releases the mutex used while performing NVM operations. 785 **/ 786static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 787{ 788 mutex_unlock(&nvm_mutex); 789} 790 791static DEFINE_MUTEX(swflag_mutex); 792 793/** 794 * e1000_acquire_swflag_ich8lan - Acquire software control flag 795 * @hw: pointer to the HW structure 796 * 797 * Acquires the software control flag for performing PHY and select 798 * MAC CSR accesses. 799 **/ 800static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 801{ 802 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 803 s32 ret_val = 0; 804 805 mutex_lock(&swflag_mutex); 806 807 while (timeout) { 808 extcnf_ctrl = er32(EXTCNF_CTRL); 809 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 810 break; 811 812 mdelay(1); 813 timeout--; 814 } 815 816 if (!timeout) { 817 e_dbg("SW/FW/HW has locked the resource for too long.\n"); 818 ret_val = -E1000_ERR_CONFIG; 819 goto out; 820 } 821 822 timeout = SW_FLAG_TIMEOUT; 823 824 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 825 ew32(EXTCNF_CTRL, extcnf_ctrl); 826 827 while (timeout) { 828 extcnf_ctrl = er32(EXTCNF_CTRL); 829 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 830 break; 831 832 mdelay(1); 833 timeout--; 834 } 835 836 if (!timeout) { 837 e_dbg("Failed to acquire the semaphore.\n"); 838 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 839 ew32(EXTCNF_CTRL, extcnf_ctrl); 840 ret_val = -E1000_ERR_CONFIG; 841 goto out; 842 } 843 844out: 845 if (ret_val) 846 mutex_unlock(&swflag_mutex); 847 848 return ret_val; 849} 850 851/** 852 * e1000_release_swflag_ich8lan - Release software control flag 853 * @hw: pointer to the HW structure 854 * 855 * Releases the software control flag for performing PHY and select 856 * MAC CSR accesses. 857 **/ 858static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 859{ 860 u32 extcnf_ctrl; 861 862 extcnf_ctrl = er32(EXTCNF_CTRL); 863 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 864 ew32(EXTCNF_CTRL, extcnf_ctrl); 865 866 mutex_unlock(&swflag_mutex); 867} 868 869/** 870 * e1000_check_mng_mode_ich8lan - Checks management mode 871 * @hw: pointer to the HW structure 872 * 873 * This checks if the adapter has any manageability enabled. 874 * This is a function pointer entry point only called by read/write 875 * routines for the PHY and NVM parts. 876 **/ 877static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 878{ 879 u32 fwsm; 880 881 fwsm = er32(FWSM); 882 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 883 ((fwsm & E1000_FWSM_MODE_MASK) == 884 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 885} 886 887/** 888 * e1000_check_mng_mode_pchlan - Checks management mode 889 * @hw: pointer to the HW structure 890 * 891 * This checks if the adapter has iAMT enabled. 892 * This is a function pointer entry point only called by read/write 893 * routines for the PHY and NVM parts. 894 **/ 895static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 896{ 897 u32 fwsm; 898 899 fwsm = er32(FWSM); 900 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 901 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 902} 903 904/** 905 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 906 * @hw: pointer to the HW structure 907 * 908 * Checks if firmware is blocking the reset of the PHY. 909 * This is a function pointer entry point only called by 910 * reset routines. 911 **/ 912static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 913{ 914 u32 fwsm; 915 916 fwsm = er32(FWSM); 917 918 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; 919} 920 921/** 922 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 923 * @hw: pointer to the HW structure 924 * 925 * Assumes semaphore already acquired. 926 * 927 **/ 928static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 929{ 930 u16 phy_data; 931 u32 strap = er32(STRAP); 932 s32 ret_val = 0; 933 934 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 935 936 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 937 if (ret_val) 938 goto out; 939 940 phy_data &= ~HV_SMB_ADDR_MASK; 941 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 942 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 943 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 944 945out: 946 return ret_val; 947} 948 949static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 950{ 951 struct e1000_phy_info *phy = &hw->phy; 952 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 953 s32 ret_val = 0; 954 u16 word_addr, reg_data, reg_addr, phy_page = 0; 955 956 /* 957 * Initialize the PHY from the NVM on ICH platforms. This 958 * is needed due to an issue where the NVM configuration is 959 * not properly autoloaded after power transitions. 960 * Therefore, after each PHY reset, we will load the 961 * configuration data out of the NVM manually. 962 */ 963 switch (hw->mac.type) { 964 case e1000_ich8lan: 965 if (phy->type != e1000_phy_igp_3) 966 return ret_val; 967 968 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 969 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 970 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 971 break; 972 } 973 /* Fall-thru */ 974 case e1000_pchlan: 975 case e1000_pch2lan: 976 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 977 break; 978 default: 979 return ret_val; 980 } 981 982 ret_val = hw->phy.ops.acquire(hw); 983 if (ret_val) 984 return ret_val; 985 986 data = er32(FEXTNVM); 987 if (!(data & sw_cfg_mask)) 988 goto out; 989 990 /* 991 * Make sure HW does not configure LCD from PHY 992 * extended configuration before SW configuration 993 */ 994 data = er32(EXTCNF_CTRL); 995 if (!(hw->mac.type == e1000_pch2lan)) { 996 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 997 goto out; 998 } 999 1000 cnf_size = er32(EXTCNF_SIZE); 1001 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 1002 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 1003 if (!cnf_size) 1004 goto out; 1005 1006 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 1007 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 1008 1009 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && 1010 (hw->mac.type == e1000_pchlan)) || 1011 (hw->mac.type == e1000_pch2lan)) { 1012 /* 1013 * HW configures the SMBus address and LEDs when the 1014 * OEM and LCD Write Enable bits are set in the NVM. 1015 * When both NVM bits are cleared, SW will configure 1016 * them instead. 1017 */ 1018 ret_val = e1000_write_smbus_addr(hw); 1019 if (ret_val) 1020 goto out; 1021 1022 data = er32(LEDCTL); 1023 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 1024 (u16)data); 1025 if (ret_val) 1026 goto out; 1027 } 1028 1029 /* Configure LCD from extended configuration region. */ 1030 1031 /* cnf_base_addr is in DWORD */ 1032 word_addr = (u16)(cnf_base_addr << 1); 1033 1034 for (i = 0; i < cnf_size; i++) { 1035 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, 1036 ®_data); 1037 if (ret_val) 1038 goto out; 1039 1040 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 1041 1, ®_addr); 1042 if (ret_val) 1043 goto out; 1044 1045 /* Save off the PHY page for future writes. */ 1046 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 1047 phy_page = reg_data; 1048 continue; 1049 } 1050 1051 reg_addr &= PHY_REG_MASK; 1052 reg_addr |= phy_page; 1053 1054 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 1055 reg_data); 1056 if (ret_val) 1057 goto out; 1058 } 1059 1060out: 1061 hw->phy.ops.release(hw); 1062 return ret_val; 1063} 1064 1065static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 1066{ 1067 s32 ret_val = 0; 1068 u16 status_reg = 0; 1069 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 1070 1071 if (hw->mac.type != e1000_pchlan) 1072 goto out; 1073 1074 /* Wrap the whole flow with the sw flag */ 1075 ret_val = hw->phy.ops.acquire(hw); 1076 if (ret_val) 1077 goto out; 1078 1079 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 1080 if (link) { 1081 if (hw->phy.type == e1000_phy_82578) { 1082 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 1083 &status_reg); 1084 if (ret_val) 1085 goto release; 1086 1087 status_reg &= BM_CS_STATUS_LINK_UP | 1088 BM_CS_STATUS_RESOLVED | 1089 BM_CS_STATUS_SPEED_MASK; 1090 1091 if (status_reg == (BM_CS_STATUS_LINK_UP | 1092 BM_CS_STATUS_RESOLVED | 1093 BM_CS_STATUS_SPEED_1000)) 1094 k1_enable = false; 1095 } 1096 1097 if (hw->phy.type == e1000_phy_82577) { 1098 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 1099 &status_reg); 1100 if (ret_val) 1101 goto release; 1102 1103 status_reg &= HV_M_STATUS_LINK_UP | 1104 HV_M_STATUS_AUTONEG_COMPLETE | 1105 HV_M_STATUS_SPEED_MASK; 1106 1107 if (status_reg == (HV_M_STATUS_LINK_UP | 1108 HV_M_STATUS_AUTONEG_COMPLETE | 1109 HV_M_STATUS_SPEED_1000)) 1110 k1_enable = false; 1111 } 1112 1113 /* Link stall fix for link up */ 1114 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1115 0x0100); 1116 if (ret_val) 1117 goto release; 1118 1119 } else { 1120 /* Link stall fix for link down */ 1121 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1122 0x4100); 1123 if (ret_val) 1124 goto release; 1125 } 1126 1127 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 1128 1129release: 1130 hw->phy.ops.release(hw); 1131out: 1132 return ret_val; 1133} 1134 1135/** 1136 * e1000_configure_k1_ich8lan - Configure K1 power state 1137 * @hw: pointer to the HW structure 1138 * @enable: K1 state to configure 1139 * 1140 * Configure the K1 power state based on the provided parameter. 1141 * Assumes semaphore already acquired. 1142 * 1143 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1144 **/ 1145s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 1146{ 1147 s32 ret_val = 0; 1148 u32 ctrl_reg = 0; 1149 u32 ctrl_ext = 0; 1150 u32 reg = 0; 1151 u16 kmrn_reg = 0; 1152 1153 ret_val = e1000e_read_kmrn_reg_locked(hw, 1154 E1000_KMRNCTRLSTA_K1_CONFIG, 1155 &kmrn_reg); 1156 if (ret_val) 1157 goto out; 1158 1159 if (k1_enable) 1160 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 1161 else 1162 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 1163 1164 ret_val = e1000e_write_kmrn_reg_locked(hw, 1165 E1000_KMRNCTRLSTA_K1_CONFIG, 1166 kmrn_reg); 1167 if (ret_val) 1168 goto out; 1169 1170 udelay(20); 1171 ctrl_ext = er32(CTRL_EXT); 1172 ctrl_reg = er32(CTRL); 1173 1174 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1175 reg |= E1000_CTRL_FRCSPD; 1176 ew32(CTRL, reg); 1177 1178 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 1179 udelay(20); 1180 ew32(CTRL, ctrl_reg); 1181 ew32(CTRL_EXT, ctrl_ext); 1182 udelay(20); 1183 1184out: 1185 return ret_val; 1186} 1187 1188/** 1189 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 1190 * @hw: pointer to the HW structure 1191 * @d0_state: boolean if entering d0 or d3 device state 1192 * 1193 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 1194 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 1195 * in NVM determines whether HW should configure LPLU and Gbe Disable. 1196 **/ 1197static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 1198{ 1199 s32 ret_val = 0; 1200 u32 mac_reg; 1201 u16 oem_reg; 1202 1203 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan)) 1204 return ret_val; 1205 1206 ret_val = hw->phy.ops.acquire(hw); 1207 if (ret_val) 1208 return ret_val; 1209 1210 if (!(hw->mac.type == e1000_pch2lan)) { 1211 mac_reg = er32(EXTCNF_CTRL); 1212 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 1213 goto out; 1214 } 1215 1216 mac_reg = er32(FEXTNVM); 1217 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 1218 goto out; 1219 1220 mac_reg = er32(PHY_CTRL); 1221 1222 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 1223 if (ret_val) 1224 goto out; 1225 1226 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 1227 1228 if (d0_state) { 1229 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 1230 oem_reg |= HV_OEM_BITS_GBE_DIS; 1231 1232 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 1233 oem_reg |= HV_OEM_BITS_LPLU; 1234 } else { 1235 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE) 1236 oem_reg |= HV_OEM_BITS_GBE_DIS; 1237 1238 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU) 1239 oem_reg |= HV_OEM_BITS_LPLU; 1240 } 1241 /* Restart auto-neg to activate the bits */ 1242 if (!e1000_check_reset_block(hw)) 1243 oem_reg |= HV_OEM_BITS_RESTART_AN; 1244 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 1245 1246out: 1247 hw->phy.ops.release(hw); 1248 1249 return ret_val; 1250} 1251 1252 1253/** 1254 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 1255 * @hw: pointer to the HW structure 1256 **/ 1257static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 1258{ 1259 s32 ret_val; 1260 u16 data; 1261 1262 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 1263 if (ret_val) 1264 return ret_val; 1265 1266 data |= HV_KMRN_MDIO_SLOW; 1267 1268 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 1269 1270 return ret_val; 1271} 1272 1273/** 1274 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1275 * done after every PHY reset. 1276 **/ 1277static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1278{ 1279 s32 ret_val = 0; 1280 u16 phy_data; 1281 1282 if (hw->mac.type != e1000_pchlan) 1283 return ret_val; 1284 1285 /* Set MDIO slow mode before any other MDIO access */ 1286 if (hw->phy.type == e1000_phy_82577) { 1287 ret_val = e1000_set_mdio_slow_mode_hv(hw); 1288 if (ret_val) 1289 goto out; 1290 } 1291 1292 if (((hw->phy.type == e1000_phy_82577) && 1293 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 1294 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 1295 /* Disable generation of early preamble */ 1296 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 1297 if (ret_val) 1298 return ret_val; 1299 1300 /* Preamble tuning for SSC */ 1301 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204); 1302 if (ret_val) 1303 return ret_val; 1304 } 1305 1306 if (hw->phy.type == e1000_phy_82578) { 1307 /* 1308 * Return registers to default by doing a soft reset then 1309 * writing 0x3140 to the control register. 1310 */ 1311 if (hw->phy.revision < 2) { 1312 e1000e_phy_sw_reset(hw); 1313 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140); 1314 } 1315 } 1316 1317 /* Select page 0 */ 1318 ret_val = hw->phy.ops.acquire(hw); 1319 if (ret_val) 1320 return ret_val; 1321 1322 hw->phy.addr = 1; 1323 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 1324 hw->phy.ops.release(hw); 1325 if (ret_val) 1326 goto out; 1327 1328 ret_val = e1000_k1_gig_workaround_hv(hw, true); 1329 if (ret_val) 1330 goto out; 1331 1332 ret_val = hw->phy.ops.acquire(hw); 1333 if (ret_val) 1334 goto out; 1335 ret_val = hw->phy.ops.read_reg_locked(hw, 1336 PHY_REG(BM_PORT_CTRL_PAGE, 17), 1337 &phy_data); 1338 if (ret_val) 1339 goto release; 1340 ret_val = hw->phy.ops.write_reg_locked(hw, 1341 PHY_REG(BM_PORT_CTRL_PAGE, 17), 1342 phy_data & 0x00FF); 1343release: 1344 hw->phy.ops.release(hw); 1345out: 1346 return ret_val; 1347} 1348 1349/** 1350 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 1351 * @hw: pointer to the HW structure 1352 **/ 1353void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 1354{ 1355 u32 mac_reg; 1356 u16 i; 1357 1358 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ 1359 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1360 mac_reg = er32(RAL(i)); 1361 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF)); 1362 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF)); 1363 mac_reg = er32(RAH(i)); 1364 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF)); 1365 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000)); 1366 } 1367} 1368 1369static u32 e1000_calc_rx_da_crc(u8 mac[]) 1370{ 1371 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ 1372 u32 i, j, mask, crc; 1373 1374 crc = 0xffffffff; 1375 for (i = 0; i < 6; i++) { 1376 crc = crc ^ mac[i]; 1377 for (j = 8; j > 0; j--) { 1378 mask = (crc & 1) * (-1); 1379 crc = (crc >> 1) ^ (poly & mask); 1380 } 1381 } 1382 return ~crc; 1383} 1384 1385s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 1386{ 1387 s32 ret_val = 0; 1388 u16 phy_reg, data; 1389 u32 mac_reg; 1390 u16 i; 1391 1392 if (hw->mac.type != e1000_pch2lan) 1393 goto out; 1394 1395 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 1396 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); 1397 if (ret_val) 1398 goto out; 1399 1400 if (enable) { 1401 /* 1402 * Write Rx addresses (rar_entry_count for RAL/H, +4 for 1403 * SHRAL/H) and initial CRC values to the MAC 1404 */ 1405 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1406 u8 mac_addr[ETH_ALEN] = {0}; 1407 u32 addr_high, addr_low; 1408 1409 addr_high = er32(RAH(i)); 1410 if (!(addr_high & E1000_RAH_AV)) 1411 continue; 1412 addr_low = er32(RAL(i)); 1413 mac_addr[0] = (addr_low & 0xFF); 1414 mac_addr[1] = ((addr_low >> 8) & 0xFF); 1415 mac_addr[2] = ((addr_low >> 16) & 0xFF); 1416 mac_addr[3] = ((addr_low >> 24) & 0xFF); 1417 mac_addr[4] = (addr_high & 0xFF); 1418 mac_addr[5] = ((addr_high >> 8) & 0xFF); 1419 1420 ew32(PCH_RAICC(i), 1421 e1000_calc_rx_da_crc(mac_addr)); 1422 } 1423 1424 /* Write Rx addresses to the PHY */ 1425 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 1426 1427 mac_reg = er32(FFLT_DBG); 1428 mac_reg &= ~(1 << 14); 1429 mac_reg |= (7 << 15); 1430 ew32(FFLT_DBG, mac_reg); 1431 1432 mac_reg = er32(RCTL); 1433 mac_reg |= E1000_RCTL_SECRC; 1434 ew32(RCTL, mac_reg); 1435 1436 ret_val = e1000e_read_kmrn_reg(hw, 1437 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1438 &data); 1439 if (ret_val) 1440 goto out; 1441 ret_val = e1000e_write_kmrn_reg(hw, 1442 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1443 data | (1 << 0)); 1444 if (ret_val) 1445 goto out; 1446 ret_val = e1000e_read_kmrn_reg(hw, 1447 E1000_KMRNCTRLSTA_HD_CTRL, 1448 &data); 1449 if (ret_val) 1450 goto out; 1451 data &= ~(0xF << 8); 1452 data |= (0xB << 8); 1453 ret_val = e1000e_write_kmrn_reg(hw, 1454 E1000_KMRNCTRLSTA_HD_CTRL, 1455 data); 1456 if (ret_val) 1457 goto out; 1458 1459 e1e_rphy(hw, PHY_REG(769, 23), &data); 1460 data &= ~(0x7F << 5); 1461 data |= (0x37 << 5); 1462 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 1463 if (ret_val) 1464 goto out; 1465 e1e_rphy(hw, PHY_REG(769, 16), &data); 1466 data &= ~(1 << 13); 1467 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 1468 if (ret_val) 1469 goto out; 1470 e1e_rphy(hw, PHY_REG(776, 20), &data); 1471 data &= ~(0x3FF << 2); 1472 data |= (0x1A << 2); 1473 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 1474 if (ret_val) 1475 goto out; 1476 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00); 1477 if (ret_val) 1478 goto out; 1479 e1e_rphy(hw, HV_PM_CTRL, &data); 1480 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); 1481 if (ret_val) 1482 goto out; 1483 } else { 1484 /* Write MAC register values back to h/w defaults */ 1485 mac_reg = er32(FFLT_DBG); 1486 mac_reg &= ~(0xF << 14); 1487 ew32(FFLT_DBG, mac_reg); 1488 1489 mac_reg = er32(RCTL); 1490 mac_reg &= ~E1000_RCTL_SECRC; 1491 ew32(RCTL, mac_reg); 1492 1493 ret_val = e1000e_read_kmrn_reg(hw, 1494 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1495 &data); 1496 if (ret_val) 1497 goto out; 1498 ret_val = e1000e_write_kmrn_reg(hw, 1499 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1500 data & ~(1 << 0)); 1501 if (ret_val) 1502 goto out; 1503 ret_val = e1000e_read_kmrn_reg(hw, 1504 E1000_KMRNCTRLSTA_HD_CTRL, 1505 &data); 1506 if (ret_val) 1507 goto out; 1508 data &= ~(0xF << 8); 1509 data |= (0xB << 8); 1510 ret_val = e1000e_write_kmrn_reg(hw, 1511 E1000_KMRNCTRLSTA_HD_CTRL, 1512 data); 1513 if (ret_val) 1514 goto out; 1515 1516 /* Write PHY register values back to h/w defaults */ 1517 e1e_rphy(hw, PHY_REG(769, 23), &data); 1518 data &= ~(0x7F << 5); 1519 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 1520 if (ret_val) 1521 goto out; 1522 e1e_rphy(hw, PHY_REG(769, 16), &data); 1523 data |= (1 << 13); 1524 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 1525 if (ret_val) 1526 goto out; 1527 e1e_rphy(hw, PHY_REG(776, 20), &data); 1528 data &= ~(0x3FF << 2); 1529 data |= (0x8 << 2); 1530 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 1531 if (ret_val) 1532 goto out; 1533 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 1534 if (ret_val) 1535 goto out; 1536 e1e_rphy(hw, HV_PM_CTRL, &data); 1537 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); 1538 if (ret_val) 1539 goto out; 1540 } 1541 1542 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); 1543 1544out: 1545 return ret_val; 1546} 1547 1548/** 1549 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1550 * done after every PHY reset. 1551 **/ 1552static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1553{ 1554 s32 ret_val = 0; 1555 1556 if (hw->mac.type != e1000_pch2lan) 1557 goto out; 1558 1559 /* Set MDIO slow mode before any other MDIO access */ 1560 ret_val = e1000_set_mdio_slow_mode_hv(hw); 1561 1562out: 1563 return ret_val; 1564} 1565 1566static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 1567{ 1568 s32 ret_val = 0; 1569 u16 status_reg = 0; 1570 u32 mac_reg; 1571 1572 if (hw->mac.type != e1000_pch2lan) 1573 goto out; 1574 1575 /* Set K1 beacon duration based on 1Gbps speed or otherwise */ 1576 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 1577 if (ret_val) 1578 goto out; 1579 1580 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 1581 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 1582 mac_reg = er32(FEXTNVM4); 1583 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1584 1585 if (status_reg & HV_M_STATUS_SPEED_1000) 1586 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1587 else 1588 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 1589 1590 ew32(FEXTNVM4, mac_reg); 1591 } 1592 1593out: 1594 return ret_val; 1595} 1596 1597/** 1598 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 1599 * @hw: pointer to the HW structure 1600 * @gate: boolean set to true to gate, false to ungate 1601 * 1602 * Gate/ungate the automatic PHY configuration via hardware; perform 1603 * the configuration via software instead. 1604 **/ 1605static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 1606{ 1607 u32 extcnf_ctrl; 1608 1609 if (hw->mac.type != e1000_pch2lan) 1610 return; 1611 1612 extcnf_ctrl = er32(EXTCNF_CTRL); 1613 1614 if (gate) 1615 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 1616 else 1617 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 1618 1619 ew32(EXTCNF_CTRL, extcnf_ctrl); 1620 return; 1621} 1622 1623/** 1624 * e1000_lan_init_done_ich8lan - Check for PHY config completion 1625 * @hw: pointer to the HW structure 1626 * 1627 * Check the appropriate indication the MAC has finished configuring the 1628 * PHY after a software reset. 1629 **/ 1630static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 1631{ 1632 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 1633 1634 /* Wait for basic configuration completes before proceeding */ 1635 do { 1636 data = er32(STATUS); 1637 data &= E1000_STATUS_LAN_INIT_DONE; 1638 udelay(100); 1639 } while ((!data) && --loop); 1640 1641 /* 1642 * If basic configuration is incomplete before the above loop 1643 * count reaches 0, loading the configuration from NVM will 1644 * leave the PHY in a bad state possibly resulting in no link. 1645 */ 1646 if (loop == 0) 1647 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 1648 1649 /* Clear the Init Done bit for the next init event */ 1650 data = er32(STATUS); 1651 data &= ~E1000_STATUS_LAN_INIT_DONE; 1652 ew32(STATUS, data); 1653} 1654 1655/** 1656 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 1657 * @hw: pointer to the HW structure 1658 **/ 1659static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 1660{ 1661 s32 ret_val = 0; 1662 u16 reg; 1663 1664 if (e1000_check_reset_block(hw)) 1665 goto out; 1666 1667 /* Allow time for h/w to get to quiescent state after reset */ 1668 msleep(10); 1669 1670 /* Perform any necessary post-reset workarounds */ 1671 switch (hw->mac.type) { 1672 case e1000_pchlan: 1673 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 1674 if (ret_val) 1675 goto out; 1676 break; 1677 case e1000_pch2lan: 1678 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 1679 if (ret_val) 1680 goto out; 1681 break; 1682 default: 1683 break; 1684 } 1685 1686 /* Dummy read to clear the phy wakeup bit after lcd reset */ 1687 if (hw->mac.type >= e1000_pchlan) 1688 e1e_rphy(hw, BM_WUC, ®); 1689 1690 /* Configure the LCD with the extended configuration region in NVM */ 1691 ret_val = e1000_sw_lcd_config_ich8lan(hw); 1692 if (ret_val) 1693 goto out; 1694 1695 /* Configure the LCD with the OEM bits in NVM */ 1696 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 1697 1698 /* Ungate automatic PHY configuration on non-managed 82579 */ 1699 if ((hw->mac.type == e1000_pch2lan) && 1700 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 1701 msleep(10); 1702 e1000_gate_hw_phy_config_ich8lan(hw, false); 1703 } 1704 1705out: 1706 return ret_val; 1707} 1708 1709/** 1710 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 1711 * @hw: pointer to the HW structure 1712 * 1713 * Resets the PHY 1714 * This is a function pointer entry point called by drivers 1715 * or other shared routines. 1716 **/ 1717static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 1718{ 1719 s32 ret_val = 0; 1720 1721 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 1722 if ((hw->mac.type == e1000_pch2lan) && 1723 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1724 e1000_gate_hw_phy_config_ich8lan(hw, true); 1725 1726 ret_val = e1000e_phy_hw_reset_generic(hw); 1727 if (ret_val) 1728 goto out; 1729 1730 ret_val = e1000_post_phy_reset_ich8lan(hw); 1731 1732out: 1733 return ret_val; 1734} 1735 1736/** 1737 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 1738 * @hw: pointer to the HW structure 1739 * @active: true to enable LPLU, false to disable 1740 * 1741 * Sets the LPLU state according to the active flag. For PCH, if OEM write 1742 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 1743 * the phy speed. This function will manually set the LPLU bit and restart 1744 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 1745 * since it configures the same bit. 1746 **/ 1747static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 1748{ 1749 s32 ret_val = 0; 1750 u16 oem_reg; 1751 1752 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 1753 if (ret_val) 1754 goto out; 1755 1756 if (active) 1757 oem_reg |= HV_OEM_BITS_LPLU; 1758 else 1759 oem_reg &= ~HV_OEM_BITS_LPLU; 1760 1761 oem_reg |= HV_OEM_BITS_RESTART_AN; 1762 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg); 1763 1764out: 1765 return ret_val; 1766} 1767 1768/** 1769 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 1770 * @hw: pointer to the HW structure 1771 * @active: true to enable LPLU, false to disable 1772 * 1773 * Sets the LPLU D0 state according to the active flag. When 1774 * activating LPLU this function also disables smart speed 1775 * and vice versa. LPLU will not be activated unless the 1776 * device autonegotiation advertisement meets standards of 1777 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1778 * This is a function pointer entry point only called by 1779 * PHY setup routines. 1780 **/ 1781static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 1782{ 1783 struct e1000_phy_info *phy = &hw->phy; 1784 u32 phy_ctrl; 1785 s32 ret_val = 0; 1786 u16 data; 1787 1788 if (phy->type == e1000_phy_ife) 1789 return ret_val; 1790 1791 phy_ctrl = er32(PHY_CTRL); 1792 1793 if (active) { 1794 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 1795 ew32(PHY_CTRL, phy_ctrl); 1796 1797 if (phy->type != e1000_phy_igp_3) 1798 return 0; 1799 1800 if (hw->mac.type == e1000_ich8lan) 1801 e1000e_gig_downshift_workaround_ich8lan(hw); 1802 1803 /* When LPLU is enabled, we should disable SmartSpeed */ 1804 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 1805 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1806 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 1807 if (ret_val) 1808 return ret_val; 1809 } else { 1810 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 1811 ew32(PHY_CTRL, phy_ctrl); 1812 1813 if (phy->type != e1000_phy_igp_3) 1814 return 0; 1815 1816 /* 1817 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1818 * during Dx states where the power conservation is most 1819 * important. During driver activity we should enable 1820 * SmartSpeed, so performance is maintained. 1821 */ 1822 if (phy->smart_speed == e1000_smart_speed_on) { 1823 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1824 &data); 1825 if (ret_val) 1826 return ret_val; 1827 1828 data |= IGP01E1000_PSCFR_SMART_SPEED; 1829 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1830 data); 1831 if (ret_val) 1832 return ret_val; 1833 } else if (phy->smart_speed == e1000_smart_speed_off) { 1834 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1835 &data); 1836 if (ret_val) 1837 return ret_val; 1838 1839 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1840 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1841 data); 1842 if (ret_val) 1843 return ret_val; 1844 } 1845 } 1846 1847 return 0; 1848} 1849 1850/** 1851 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 1852 * @hw: pointer to the HW structure 1853 * @active: true to enable LPLU, false to disable 1854 * 1855 * Sets the LPLU D3 state according to the active flag. When 1856 * activating LPLU this function also disables smart speed 1857 * and vice versa. LPLU will not be activated unless the 1858 * device autonegotiation advertisement meets standards of 1859 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1860 * This is a function pointer entry point only called by 1861 * PHY setup routines. 1862 **/ 1863static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 1864{ 1865 struct e1000_phy_info *phy = &hw->phy; 1866 u32 phy_ctrl; 1867 s32 ret_val; 1868 u16 data; 1869 1870 phy_ctrl = er32(PHY_CTRL); 1871 1872 if (!active) { 1873 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 1874 ew32(PHY_CTRL, phy_ctrl); 1875 1876 if (phy->type != e1000_phy_igp_3) 1877 return 0; 1878 1879 /* 1880 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1881 * during Dx states where the power conservation is most 1882 * important. During driver activity we should enable 1883 * SmartSpeed, so performance is maintained. 1884 */ 1885 if (phy->smart_speed == e1000_smart_speed_on) { 1886 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1887 &data); 1888 if (ret_val) 1889 return ret_val; 1890 1891 data |= IGP01E1000_PSCFR_SMART_SPEED; 1892 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1893 data); 1894 if (ret_val) 1895 return ret_val; 1896 } else if (phy->smart_speed == e1000_smart_speed_off) { 1897 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1898 &data); 1899 if (ret_val) 1900 return ret_val; 1901 1902 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1903 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1904 data); 1905 if (ret_val) 1906 return ret_val; 1907 } 1908 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1909 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1910 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1911 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 1912 ew32(PHY_CTRL, phy_ctrl); 1913 1914 if (phy->type != e1000_phy_igp_3) 1915 return 0; 1916 1917 if (hw->mac.type == e1000_ich8lan) 1918 e1000e_gig_downshift_workaround_ich8lan(hw); 1919 1920 /* When LPLU is enabled, we should disable SmartSpeed */ 1921 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 1922 if (ret_val) 1923 return ret_val; 1924 1925 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1926 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 1927 } 1928 1929 return 0; 1930} 1931 1932/** 1933 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 1934 * @hw: pointer to the HW structure 1935 * @bank: pointer to the variable that returns the active bank 1936 * 1937 * Reads signature byte from the NVM using the flash access registers. 1938 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 1939 **/ 1940static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 1941{ 1942 u32 eecd; 1943 struct e1000_nvm_info *nvm = &hw->nvm; 1944 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1945 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1946 u8 sig_byte = 0; 1947 s32 ret_val = 0; 1948 1949 switch (hw->mac.type) { 1950 case e1000_ich8lan: 1951 case e1000_ich9lan: 1952 eecd = er32(EECD); 1953 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 1954 E1000_EECD_SEC1VAL_VALID_MASK) { 1955 if (eecd & E1000_EECD_SEC1VAL) 1956 *bank = 1; 1957 else 1958 *bank = 0; 1959 1960 return 0; 1961 } 1962 e_dbg("Unable to determine valid NVM bank via EEC - " 1963 "reading flash signature\n"); 1964 /* fall-thru */ 1965 default: 1966 /* set bank to 0 in case flash read fails */ 1967 *bank = 0; 1968 1969 /* Check bank 0 */ 1970 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 1971 &sig_byte); 1972 if (ret_val) 1973 return ret_val; 1974 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1975 E1000_ICH_NVM_SIG_VALUE) { 1976 *bank = 0; 1977 return 0; 1978 } 1979 1980 /* Check bank 1 */ 1981 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 1982 bank1_offset, 1983 &sig_byte); 1984 if (ret_val) 1985 return ret_val; 1986 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1987 E1000_ICH_NVM_SIG_VALUE) { 1988 *bank = 1; 1989 return 0; 1990 } 1991 1992 e_dbg("ERROR: No valid NVM bank present\n"); 1993 return -E1000_ERR_NVM; 1994 } 1995 1996 return 0; 1997} 1998 1999/** 2000 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 2001 * @hw: pointer to the HW structure 2002 * @offset: The offset (in bytes) of the word(s) to read. 2003 * @words: Size of data to read in words 2004 * @data: Pointer to the word(s) to read at offset. 2005 * 2006 * Reads a word(s) from the NVM using the flash access registers. 2007 **/ 2008static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2009 u16 *data) 2010{ 2011 struct e1000_nvm_info *nvm = &hw->nvm; 2012 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2013 u32 act_offset; 2014 s32 ret_val = 0; 2015 u32 bank = 0; 2016 u16 i, word; 2017 2018 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2019 (words == 0)) { 2020 e_dbg("nvm parameter(s) out of bounds\n"); 2021 ret_val = -E1000_ERR_NVM; 2022 goto out; 2023 } 2024 2025 nvm->ops.acquire(hw); 2026 2027 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2028 if (ret_val) { 2029 e_dbg("Could not detect valid bank, assuming bank 0\n"); 2030 bank = 0; 2031 } 2032 2033 act_offset = (bank) ? nvm->flash_bank_size : 0; 2034 act_offset += offset; 2035 2036 ret_val = 0; 2037 for (i = 0; i < words; i++) { 2038 if ((dev_spec->shadow_ram) && 2039 (dev_spec->shadow_ram[offset+i].modified)) { 2040 data[i] = dev_spec->shadow_ram[offset+i].value; 2041 } else { 2042 ret_val = e1000_read_flash_word_ich8lan(hw, 2043 act_offset + i, 2044 &word); 2045 if (ret_val) 2046 break; 2047 data[i] = word; 2048 } 2049 } 2050 2051 nvm->ops.release(hw); 2052 2053out: 2054 if (ret_val) 2055 e_dbg("NVM read error: %d\n", ret_val); 2056 2057 return ret_val; 2058} 2059 2060/** 2061 * e1000_flash_cycle_init_ich8lan - Initialize flash 2062 * @hw: pointer to the HW structure 2063 * 2064 * This function does initial flash setup so that a new read/write/erase cycle 2065 * can be started. 2066 **/ 2067static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 2068{ 2069 union ich8_hws_flash_status hsfsts; 2070 s32 ret_val = -E1000_ERR_NVM; 2071 s32 i = 0; 2072 2073 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2074 2075 /* Check if the flash descriptor is valid */ 2076 if (hsfsts.hsf_status.fldesvalid == 0) { 2077 e_dbg("Flash descriptor invalid. " 2078 "SW Sequencing must be used.\n"); 2079 return -E1000_ERR_NVM; 2080 } 2081 2082 /* Clear FCERR and DAEL in hw status by writing 1 */ 2083 hsfsts.hsf_status.flcerr = 1; 2084 hsfsts.hsf_status.dael = 1; 2085 2086 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2087 2088 /* 2089 * Either we should have a hardware SPI cycle in progress 2090 * bit to check against, in order to start a new cycle or 2091 * FDONE bit should be changed in the hardware so that it 2092 * is 1 after hardware reset, which can then be used as an 2093 * indication whether a cycle is in progress or has been 2094 * completed. 2095 */ 2096 2097 if (hsfsts.hsf_status.flcinprog == 0) { 2098 /* 2099 * There is no cycle running at present, 2100 * so we can start a cycle. 2101 * Begin by setting Flash Cycle Done. 2102 */ 2103 hsfsts.hsf_status.flcdone = 1; 2104 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2105 ret_val = 0; 2106 } else { 2107 /* 2108 * Otherwise poll for sometime so the current 2109 * cycle has a chance to end before giving up. 2110 */ 2111 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 2112 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS); 2113 if (hsfsts.hsf_status.flcinprog == 0) { 2114 ret_val = 0; 2115 break; 2116 } 2117 udelay(1); 2118 } 2119 if (ret_val == 0) { 2120 /* 2121 * Successful in waiting for previous cycle to timeout, 2122 * now set the Flash Cycle Done. 2123 */ 2124 hsfsts.hsf_status.flcdone = 1; 2125 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2126 } else { 2127 e_dbg("Flash controller busy, cannot get access\n"); 2128 } 2129 } 2130 2131 return ret_val; 2132} 2133 2134/** 2135 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 2136 * @hw: pointer to the HW structure 2137 * @timeout: maximum time to wait for completion 2138 * 2139 * This function starts a flash cycle and waits for its completion. 2140 **/ 2141static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 2142{ 2143 union ich8_hws_flash_ctrl hsflctl; 2144 union ich8_hws_flash_status hsfsts; 2145 s32 ret_val = -E1000_ERR_NVM; 2146 u32 i = 0; 2147 2148 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 2149 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 2150 hsflctl.hsf_ctrl.flcgo = 1; 2151 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 2152 2153 /* wait till FDONE bit is set to 1 */ 2154 do { 2155 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2156 if (hsfsts.hsf_status.flcdone == 1) 2157 break; 2158 udelay(1); 2159 } while (i++ < timeout); 2160 2161 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 2162 return 0; 2163 2164 return ret_val; 2165} 2166 2167/** 2168 * e1000_read_flash_word_ich8lan - Read word from flash 2169 * @hw: pointer to the HW structure 2170 * @offset: offset to data location 2171 * @data: pointer to the location for storing the data 2172 * 2173 * Reads the flash word at offset into data. Offset is converted 2174 * to bytes before read. 2175 **/ 2176static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 2177 u16 *data) 2178{ 2179 /* Must convert offset into bytes. */ 2180 offset <<= 1; 2181 2182 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 2183} 2184 2185/** 2186 * e1000_read_flash_byte_ich8lan - Read byte from flash 2187 * @hw: pointer to the HW structure 2188 * @offset: The offset of the byte to read. 2189 * @data: Pointer to a byte to store the value read. 2190 * 2191 * Reads a single byte from the NVM using the flash access registers. 2192 **/ 2193static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2194 u8 *data) 2195{ 2196 s32 ret_val; 2197 u16 word = 0; 2198 2199 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 2200 if (ret_val) 2201 return ret_val; 2202 2203 *data = (u8)word; 2204 2205 return 0; 2206} 2207 2208/** 2209 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 2210 * @hw: pointer to the HW structure 2211 * @offset: The offset (in bytes) of the byte or word to read. 2212 * @size: Size of data to read, 1=byte 2=word 2213 * @data: Pointer to the word to store the value read. 2214 * 2215 * Reads a byte or word from the NVM using the flash access registers. 2216 **/ 2217static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2218 u8 size, u16 *data) 2219{ 2220 union ich8_hws_flash_status hsfsts; 2221 union ich8_hws_flash_ctrl hsflctl; 2222 u32 flash_linear_addr; 2223 u32 flash_data = 0; 2224 s32 ret_val = -E1000_ERR_NVM; 2225 u8 count = 0; 2226 2227 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 2228 return -E1000_ERR_NVM; 2229 2230 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2231 hw->nvm.flash_base_addr; 2232 2233 do { 2234 udelay(1); 2235 /* Steps */ 2236 ret_val = e1000_flash_cycle_init_ich8lan(hw); 2237 if (ret_val != 0) 2238 break; 2239 2240 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 2241 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2242 hsflctl.hsf_ctrl.fldbcount = size - 1; 2243 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 2244 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 2245 2246 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 2247 2248 ret_val = e1000_flash_cycle_ich8lan(hw, 2249 ICH_FLASH_READ_COMMAND_TIMEOUT); 2250 2251 /* 2252 * Check if FCERR is set to 1, if set to 1, clear it 2253 * and try the whole sequence a few more times, else 2254 * read in (shift in) the Flash Data0, the order is 2255 * least significant byte first msb to lsb 2256 */ 2257 if (ret_val == 0) { 2258 flash_data = er32flash(ICH_FLASH_FDATA0); 2259 if (size == 1) { 2260 *data = (u8)(flash_data & 0x000000FF); 2261 } else if (size == 2) { 2262 *data = (u16)(flash_data & 0x0000FFFF); 2263 } 2264 break; 2265 } else { 2266 /* 2267 * If we've gotten here, then things are probably 2268 * completely hosed, but if the error condition is 2269 * detected, it won't hurt to give it another try... 2270 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 2271 */ 2272 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2273 if (hsfsts.hsf_status.flcerr == 1) { 2274 /* Repeat for some time before giving up. */ 2275 continue; 2276 } else if (hsfsts.hsf_status.flcdone == 0) { 2277 e_dbg("Timeout error - flash cycle " 2278 "did not complete.\n"); 2279 break; 2280 } 2281 } 2282 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2283 2284 return ret_val; 2285} 2286 2287/** 2288 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 2289 * @hw: pointer to the HW structure 2290 * @offset: The offset (in bytes) of the word(s) to write. 2291 * @words: Size of data to write in words 2292 * @data: Pointer to the word(s) to write at offset. 2293 * 2294 * Writes a byte or word to the NVM using the flash access registers. 2295 **/ 2296static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2297 u16 *data) 2298{ 2299 struct e1000_nvm_info *nvm = &hw->nvm; 2300 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2301 u16 i; 2302 2303 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2304 (words == 0)) { 2305 e_dbg("nvm parameter(s) out of bounds\n"); 2306 return -E1000_ERR_NVM; 2307 } 2308 2309 nvm->ops.acquire(hw); 2310 2311 for (i = 0; i < words; i++) { 2312 dev_spec->shadow_ram[offset+i].modified = true; 2313 dev_spec->shadow_ram[offset+i].value = data[i]; 2314 } 2315 2316 nvm->ops.release(hw); 2317 2318 return 0; 2319} 2320 2321/** 2322 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 2323 * @hw: pointer to the HW structure 2324 * 2325 * The NVM checksum is updated by calling the generic update_nvm_checksum, 2326 * which writes the checksum to the shadow ram. The changes in the shadow 2327 * ram are then committed to the EEPROM by processing each bank at a time 2328 * checking for the modified bit and writing only the pending changes. 2329 * After a successful commit, the shadow ram is cleared and is ready for 2330 * future writes. 2331 **/ 2332static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 2333{ 2334 struct e1000_nvm_info *nvm = &hw->nvm; 2335 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2336 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 2337 s32 ret_val; 2338 u16 data; 2339 2340 ret_val = e1000e_update_nvm_checksum_generic(hw); 2341 if (ret_val) 2342 goto out; 2343 2344 if (nvm->type != e1000_nvm_flash_sw) 2345 goto out; 2346 2347 nvm->ops.acquire(hw); 2348 2349 /* 2350 * We're writing to the opposite bank so if we're on bank 1, 2351 * write to bank 0 etc. We also need to erase the segment that 2352 * is going to be written 2353 */ 2354 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2355 if (ret_val) { 2356 e_dbg("Could not detect valid bank, assuming bank 0\n"); 2357 bank = 0; 2358 } 2359 2360 if (bank == 0) { 2361 new_bank_offset = nvm->flash_bank_size; 2362 old_bank_offset = 0; 2363 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 2364 if (ret_val) 2365 goto release; 2366 } else { 2367 old_bank_offset = nvm->flash_bank_size; 2368 new_bank_offset = 0; 2369 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 2370 if (ret_val) 2371 goto release; 2372 } 2373 2374 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 2375 /* 2376 * Determine whether to write the value stored 2377 * in the other NVM bank or a modified value stored 2378 * in the shadow RAM 2379 */ 2380 if (dev_spec->shadow_ram[i].modified) { 2381 data = dev_spec->shadow_ram[i].value; 2382 } else { 2383 ret_val = e1000_read_flash_word_ich8lan(hw, i + 2384 old_bank_offset, 2385 &data); 2386 if (ret_val) 2387 break; 2388 } 2389 2390 /* 2391 * If the word is 0x13, then make sure the signature bits 2392 * (15:14) are 11b until the commit has completed. 2393 * This will allow us to write 10b which indicates the 2394 * signature is valid. We want to do this after the write 2395 * has completed so that we don't mark the segment valid 2396 * while the write is still in progress 2397 */ 2398 if (i == E1000_ICH_NVM_SIG_WORD) 2399 data |= E1000_ICH_NVM_SIG_MASK; 2400 2401 /* Convert offset to bytes. */ 2402 act_offset = (i + new_bank_offset) << 1; 2403 2404 udelay(100); 2405 /* Write the bytes to the new bank. */ 2406 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2407 act_offset, 2408 (u8)data); 2409 if (ret_val) 2410 break; 2411 2412 udelay(100); 2413 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2414 act_offset + 1, 2415 (u8)(data >> 8)); 2416 if (ret_val) 2417 break; 2418 } 2419 2420 /* 2421 * Don't bother writing the segment valid bits if sector 2422 * programming failed. 2423 */ 2424 if (ret_val) { 2425 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 2426 e_dbg("Flash commit failed.\n"); 2427 goto release; 2428 } 2429 2430 /* 2431 * Finally validate the new segment by setting bit 15:14 2432 * to 10b in word 0x13 , this can be done without an 2433 * erase as well since these bits are 11 to start with 2434 * and we need to change bit 14 to 0b 2435 */ 2436 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 2437 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 2438 if (ret_val) 2439 goto release; 2440 2441 data &= 0xBFFF; 2442 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2443 act_offset * 2 + 1, 2444 (u8)(data >> 8)); 2445 if (ret_val) 2446 goto release; 2447 2448 /* 2449 * And invalidate the previously valid segment by setting 2450 * its signature word (0x13) high_byte to 0b. This can be 2451 * done without an erase because flash erase sets all bits 2452 * to 1's. We can write 1's to 0's without an erase 2453 */ 2454 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 2455 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 2456 if (ret_val) 2457 goto release; 2458 2459 /* Great! Everything worked, we can now clear the cached entries. */ 2460 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 2461 dev_spec->shadow_ram[i].modified = false; 2462 dev_spec->shadow_ram[i].value = 0xFFFF; 2463 } 2464 2465release: 2466 nvm->ops.release(hw); 2467 2468 /* 2469 * Reload the EEPROM, or else modifications will not appear 2470 * until after the next adapter reset. 2471 */ 2472 if (!ret_val) { 2473 e1000e_reload_nvm(hw); 2474 msleep(10); 2475 } 2476 2477out: 2478 if (ret_val) 2479 e_dbg("NVM update error: %d\n", ret_val); 2480 2481 return ret_val; 2482} 2483 2484/** 2485 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 2486 * @hw: pointer to the HW structure 2487 * 2488 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 2489 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 2490 * calculated, in which case we need to calculate the checksum and set bit 6. 2491 **/ 2492static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 2493{ 2494 s32 ret_val; 2495 u16 data; 2496 2497 /* 2498 * Read 0x19 and check bit 6. If this bit is 0, the checksum 2499 * needs to be fixed. This bit is an indication that the NVM 2500 * was prepared by OEM software and did not calculate the 2501 * checksum...a likely scenario. 2502 */ 2503 ret_val = e1000_read_nvm(hw, 0x19, 1, &data); 2504 if (ret_val) 2505 return ret_val; 2506 2507 if ((data & 0x40) == 0) { 2508 data |= 0x40; 2509 ret_val = e1000_write_nvm(hw, 0x19, 1, &data); 2510 if (ret_val) 2511 return ret_val; 2512 ret_val = e1000e_update_nvm_checksum(hw); 2513 if (ret_val) 2514 return ret_val; 2515 } 2516 2517 return e1000e_validate_nvm_checksum_generic(hw); 2518} 2519 2520/** 2521 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 2522 * @hw: pointer to the HW structure 2523 * 2524 * To prevent malicious write/erase of the NVM, set it to be read-only 2525 * so that the hardware ignores all write/erase cycles of the NVM via 2526 * the flash control registers. The shadow-ram copy of the NVM will 2527 * still be updated, however any updates to this copy will not stick 2528 * across driver reloads. 2529 **/ 2530void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 2531{ 2532 struct e1000_nvm_info *nvm = &hw->nvm; 2533 union ich8_flash_protected_range pr0; 2534 union ich8_hws_flash_status hsfsts; 2535 u32 gfpreg; 2536 2537 nvm->ops.acquire(hw); 2538 2539 gfpreg = er32flash(ICH_FLASH_GFPREG); 2540 2541 /* Write-protect GbE Sector of NVM */ 2542 pr0.regval = er32flash(ICH_FLASH_PR0); 2543 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 2544 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 2545 pr0.range.wpe = true; 2546 ew32flash(ICH_FLASH_PR0, pr0.regval); 2547 2548 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2549 hsfsts.hsf_status.flockdn = true; 2550 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2551 2552 nvm->ops.release(hw); 2553} 2554 2555/** 2556 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 2557 * @hw: pointer to the HW structure 2558 * @offset: The offset (in bytes) of the byte/word to read. 2559 * @size: Size of data to read, 1=byte 2=word 2560 * @data: The byte(s) to write to the NVM. 2561 * 2562 * Writes one/two bytes to the NVM using the flash access registers. 2563 **/ 2564static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2565 u8 size, u16 data) 2566{ 2567 union ich8_hws_flash_status hsfsts; 2568 union ich8_hws_flash_ctrl hsflctl; 2569 u32 flash_linear_addr; 2570 u32 flash_data = 0; 2571 s32 ret_val; 2572 u8 count = 0; 2573 2574 if (size < 1 || size > 2 || data > size * 0xff || 2575 offset > ICH_FLASH_LINEAR_ADDR_MASK) 2576 return -E1000_ERR_NVM; 2577 2578 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2579 hw->nvm.flash_base_addr; 2580 2581 do { 2582 udelay(1); 2583 /* Steps */ 2584 ret_val = e1000_flash_cycle_init_ich8lan(hw); 2585 if (ret_val) 2586 break; 2587 2588 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 2589 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2590 hsflctl.hsf_ctrl.fldbcount = size -1; 2591 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 2592 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 2593 2594 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 2595 2596 if (size == 1) 2597 flash_data = (u32)data & 0x00FF; 2598 else 2599 flash_data = (u32)data; 2600 2601 ew32flash(ICH_FLASH_FDATA0, flash_data); 2602 2603 /* 2604 * check if FCERR is set to 1 , if set to 1, clear it 2605 * and try the whole sequence a few more times else done 2606 */ 2607 ret_val = e1000_flash_cycle_ich8lan(hw, 2608 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 2609 if (!ret_val) 2610 break; 2611 2612 /* 2613 * If we're here, then things are most likely 2614 * completely hosed, but if the error condition 2615 * is detected, it won't hurt to give it another 2616 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 2617 */ 2618 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2619 if (hsfsts.hsf_status.flcerr == 1) 2620 /* Repeat for some time before giving up. */ 2621 continue; 2622 if (hsfsts.hsf_status.flcdone == 0) { 2623 e_dbg("Timeout error - flash cycle " 2624 "did not complete."); 2625 break; 2626 } 2627 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2628 2629 return ret_val; 2630} 2631 2632/** 2633 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 2634 * @hw: pointer to the HW structure 2635 * @offset: The index of the byte to read. 2636 * @data: The byte to write to the NVM. 2637 * 2638 * Writes a single byte to the NVM using the flash access registers. 2639 **/ 2640static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2641 u8 data) 2642{ 2643 u16 word = (u16)data; 2644 2645 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 2646} 2647 2648/** 2649 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 2650 * @hw: pointer to the HW structure 2651 * @offset: The offset of the byte to write. 2652 * @byte: The byte to write to the NVM. 2653 * 2654 * Writes a single byte to the NVM using the flash access registers. 2655 * Goes through a retry algorithm before giving up. 2656 **/ 2657static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 2658 u32 offset, u8 byte) 2659{ 2660 s32 ret_val; 2661 u16 program_retries; 2662 2663 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 2664 if (!ret_val) 2665 return ret_val; 2666 2667 for (program_retries = 0; program_retries < 100; program_retries++) { 2668 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 2669 udelay(100); 2670 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 2671 if (!ret_val) 2672 break; 2673 } 2674 if (program_retries == 100) 2675 return -E1000_ERR_NVM; 2676 2677 return 0; 2678} 2679 2680/** 2681 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 2682 * @hw: pointer to the HW structure 2683 * @bank: 0 for first bank, 1 for second bank, etc. 2684 * 2685 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 2686 * bank N is 4096 * N + flash_reg_addr. 2687 **/ 2688static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 2689{ 2690 struct e1000_nvm_info *nvm = &hw->nvm; 2691 union ich8_hws_flash_status hsfsts; 2692 union ich8_hws_flash_ctrl hsflctl; 2693 u32 flash_linear_addr; 2694 /* bank size is in 16bit words - adjust to bytes */ 2695 u32 flash_bank_size = nvm->flash_bank_size * 2; 2696 s32 ret_val; 2697 s32 count = 0; 2698 s32 j, iteration, sector_size; 2699 2700 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2701 2702 /* 2703 * Determine HW Sector size: Read BERASE bits of hw flash status 2704 * register 2705 * 00: The Hw sector is 256 bytes, hence we need to erase 16 2706 * consecutive sectors. The start index for the nth Hw sector 2707 * can be calculated as = bank * 4096 + n * 256 2708 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 2709 * The start index for the nth Hw sector can be calculated 2710 * as = bank * 4096 2711 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 2712 * (ich9 only, otherwise error condition) 2713 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 2714 */ 2715 switch (hsfsts.hsf_status.berasesz) { 2716 case 0: 2717 /* Hw sector size 256 */ 2718 sector_size = ICH_FLASH_SEG_SIZE_256; 2719 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 2720 break; 2721 case 1: 2722 sector_size = ICH_FLASH_SEG_SIZE_4K; 2723 iteration = 1; 2724 break; 2725 case 2: 2726 sector_size = ICH_FLASH_SEG_SIZE_8K; 2727 iteration = 1; 2728 break; 2729 case 3: 2730 sector_size = ICH_FLASH_SEG_SIZE_64K; 2731 iteration = 1; 2732 break; 2733 default: 2734 return -E1000_ERR_NVM; 2735 } 2736 2737 /* Start with the base address, then add the sector offset. */ 2738 flash_linear_addr = hw->nvm.flash_base_addr; 2739 flash_linear_addr += (bank) ? flash_bank_size : 0; 2740 2741 for (j = 0; j < iteration ; j++) { 2742 do { 2743 /* Steps */ 2744 ret_val = e1000_flash_cycle_init_ich8lan(hw); 2745 if (ret_val) 2746 return ret_val; 2747 2748 /* 2749 * Write a value 11 (block Erase) in Flash 2750 * Cycle field in hw flash control 2751 */ 2752 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 2753 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 2754 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 2755 2756 /* 2757 * Write the last 24 bits of an index within the 2758 * block into Flash Linear address field in Flash 2759 * Address. 2760 */ 2761 flash_linear_addr += (j * sector_size); 2762 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 2763 2764 ret_val = e1000_flash_cycle_ich8lan(hw, 2765 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 2766 if (ret_val == 0) 2767 break; 2768 2769 /* 2770 * Check if FCERR is set to 1. If 1, 2771 * clear it and try the whole sequence 2772 * a few more times else Done 2773 */ 2774 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2775 if (hsfsts.hsf_status.flcerr == 1) 2776 /* repeat for some time before giving up */ 2777 continue; 2778 else if (hsfsts.hsf_status.flcdone == 0) 2779 return ret_val; 2780 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 2781 } 2782 2783 return 0; 2784} 2785 2786/** 2787 * e1000_valid_led_default_ich8lan - Set the default LED settings 2788 * @hw: pointer to the HW structure 2789 * @data: Pointer to the LED settings 2790 * 2791 * Reads the LED default settings from the NVM to data. If the NVM LED 2792 * settings is all 0's or F's, set the LED default to a valid LED default 2793 * setting. 2794 **/ 2795static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 2796{ 2797 s32 ret_val; 2798 2799 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 2800 if (ret_val) { 2801 e_dbg("NVM Read Error\n"); 2802 return ret_val; 2803 } 2804 2805 if (*data == ID_LED_RESERVED_0000 || 2806 *data == ID_LED_RESERVED_FFFF) 2807 *data = ID_LED_DEFAULT_ICH8LAN; 2808 2809 return 0; 2810} 2811 2812/** 2813 * e1000_id_led_init_pchlan - store LED configurations 2814 * @hw: pointer to the HW structure 2815 * 2816 * PCH does not control LEDs via the LEDCTL register, rather it uses 2817 * the PHY LED configuration register. 2818 * 2819 * PCH also does not have an "always on" or "always off" mode which 2820 * complicates the ID feature. Instead of using the "on" mode to indicate 2821 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()), 2822 * use "link_up" mode. The LEDs will still ID on request if there is no 2823 * link based on logic in e1000_led_[on|off]_pchlan(). 2824 **/ 2825static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 2826{ 2827 struct e1000_mac_info *mac = &hw->mac; 2828 s32 ret_val; 2829 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 2830 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 2831 u16 data, i, temp, shift; 2832 2833 /* Get default ID LED modes */ 2834 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 2835 if (ret_val) 2836 goto out; 2837 2838 mac->ledctl_default = er32(LEDCTL); 2839 mac->ledctl_mode1 = mac->ledctl_default; 2840 mac->ledctl_mode2 = mac->ledctl_default; 2841 2842 for (i = 0; i < 4; i++) { 2843 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 2844 shift = (i * 5); 2845 switch (temp) { 2846 case ID_LED_ON1_DEF2: 2847 case ID_LED_ON1_ON2: 2848 case ID_LED_ON1_OFF2: 2849 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 2850 mac->ledctl_mode1 |= (ledctl_on << shift); 2851 break; 2852 case ID_LED_OFF1_DEF2: 2853 case ID_LED_OFF1_ON2: 2854 case ID_LED_OFF1_OFF2: 2855 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 2856 mac->ledctl_mode1 |= (ledctl_off << shift); 2857 break; 2858 default: 2859 /* Do nothing */ 2860 break; 2861 } 2862 switch (temp) { 2863 case ID_LED_DEF1_ON2: 2864 case ID_LED_ON1_ON2: 2865 case ID_LED_OFF1_ON2: 2866 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 2867 mac->ledctl_mode2 |= (ledctl_on << shift); 2868 break; 2869 case ID_LED_DEF1_OFF2: 2870 case ID_LED_ON1_OFF2: 2871 case ID_LED_OFF1_OFF2: 2872 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 2873 mac->ledctl_mode2 |= (ledctl_off << shift); 2874 break; 2875 default: 2876 /* Do nothing */ 2877 break; 2878 } 2879 } 2880 2881out: 2882 return ret_val; 2883} 2884 2885/** 2886 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 2887 * @hw: pointer to the HW structure 2888 * 2889 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 2890 * register, so the the bus width is hard coded. 2891 **/ 2892static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 2893{ 2894 struct e1000_bus_info *bus = &hw->bus; 2895 s32 ret_val; 2896 2897 ret_val = e1000e_get_bus_info_pcie(hw); 2898 2899 /* 2900 * ICH devices are "PCI Express"-ish. They have 2901 * a configuration space, but do not contain 2902 * PCI Express Capability registers, so bus width 2903 * must be hardcoded. 2904 */ 2905 if (bus->width == e1000_bus_width_unknown) 2906 bus->width = e1000_bus_width_pcie_x1; 2907 2908 return ret_val; 2909} 2910 2911/** 2912 * e1000_reset_hw_ich8lan - Reset the hardware 2913 * @hw: pointer to the HW structure 2914 * 2915 * Does a full reset of the hardware which includes a reset of the PHY and 2916 * MAC. 2917 **/ 2918static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 2919{ 2920 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2921 u16 reg; 2922 u32 ctrl, icr, kab; 2923 s32 ret_val; 2924 2925 /* 2926 * Prevent the PCI-E bus from sticking if there is no TLP connection 2927 * on the last TLP read/write transaction when MAC is reset. 2928 */ 2929 ret_val = e1000e_disable_pcie_master(hw); 2930 if (ret_val) 2931 e_dbg("PCI-E Master disable polling has failed.\n"); 2932 2933 e_dbg("Masking off all interrupts\n"); 2934 ew32(IMC, 0xffffffff); 2935 2936 /* 2937 * Disable the Transmit and Receive units. Then delay to allow 2938 * any pending transactions to complete before we hit the MAC 2939 * with the global reset. 2940 */ 2941 ew32(RCTL, 0); 2942 ew32(TCTL, E1000_TCTL_PSP); 2943 e1e_flush(); 2944 2945 msleep(10); 2946 2947 if (hw->mac.type == e1000_ich8lan) { 2948 /* Set Tx and Rx buffer allocation to 8k apiece. */ 2949 ew32(PBA, E1000_PBA_8K); 2950 /* Set Packet Buffer Size to 16k. */ 2951 ew32(PBS, E1000_PBS_16K); 2952 } 2953 2954 if (hw->mac.type == e1000_pchlan) { 2955 /* Save the NVM K1 bit setting*/ 2956 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); 2957 if (ret_val) 2958 return ret_val; 2959 2960 if (reg & E1000_NVM_K1_ENABLE) 2961 dev_spec->nvm_k1_enabled = true; 2962 else 2963 dev_spec->nvm_k1_enabled = false; 2964 } 2965 2966 ctrl = er32(CTRL); 2967 2968 if (!e1000_check_reset_block(hw)) { 2969 /* 2970 * Full-chip reset requires MAC and PHY reset at the same 2971 * time to make sure the interface between MAC and the 2972 * external PHY is reset. 2973 */ 2974 ctrl |= E1000_CTRL_PHY_RST; 2975 2976 /* 2977 * Gate automatic PHY configuration by hardware on 2978 * non-managed 82579 2979 */ 2980 if ((hw->mac.type == e1000_pch2lan) && 2981 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2982 e1000_gate_hw_phy_config_ich8lan(hw, true); 2983 } 2984 ret_val = e1000_acquire_swflag_ich8lan(hw); 2985 e_dbg("Issuing a global reset to ich8lan\n"); 2986 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 2987 msleep(20); 2988 2989 if (!ret_val) 2990 e1000_release_swflag_ich8lan(hw); 2991 2992 if (ctrl & E1000_CTRL_PHY_RST) { 2993 ret_val = hw->phy.ops.get_cfg_done(hw); 2994 if (ret_val) 2995 goto out; 2996 2997 ret_val = e1000_post_phy_reset_ich8lan(hw); 2998 if (ret_val) 2999 goto out; 3000 } 3001 3002 /* 3003 * For PCH, this write will make sure that any noise 3004 * will be detected as a CRC error and be dropped rather than show up 3005 * as a bad packet to the DMA engine. 3006 */ 3007 if (hw->mac.type == e1000_pchlan) 3008 ew32(CRC_OFFSET, 0x65656565); 3009 3010 ew32(IMC, 0xffffffff); 3011 icr = er32(ICR); 3012 3013 kab = er32(KABGTXD); 3014 kab |= E1000_KABGTXD_BGSQLBIAS; 3015 ew32(KABGTXD, kab); 3016 3017out: 3018 return ret_val; 3019} 3020 3021/** 3022 * e1000_init_hw_ich8lan - Initialize the hardware 3023 * @hw: pointer to the HW structure 3024 * 3025 * Prepares the hardware for transmit and receive by doing the following: 3026 * - initialize hardware bits 3027 * - initialize LED identification 3028 * - setup receive address registers 3029 * - setup flow control 3030 * - setup transmit descriptors 3031 * - clear statistics 3032 **/ 3033static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 3034{ 3035 struct e1000_mac_info *mac = &hw->mac; 3036 u32 ctrl_ext, txdctl, snoop; 3037 s32 ret_val; 3038 u16 i; 3039 3040 e1000_initialize_hw_bits_ich8lan(hw); 3041 3042 /* Initialize identification LED */ 3043 ret_val = mac->ops.id_led_init(hw); 3044 if (ret_val) 3045 e_dbg("Error initializing identification LED\n"); 3046 /* This is not fatal and we should not stop init due to this */ 3047 3048 /* Setup the receive address. */ 3049 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 3050 3051 /* Zero out the Multicast HASH table */ 3052 e_dbg("Zeroing the MTA\n"); 3053 for (i = 0; i < mac->mta_reg_count; i++) 3054 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 3055 3056 /* 3057 * The 82578 Rx buffer will stall if wakeup is enabled in host and 3058 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 3059 * Reset the phy after disabling host wakeup to reset the Rx buffer. 3060 */ 3061 if (hw->phy.type == e1000_phy_82578) { 3062 hw->phy.ops.read_reg(hw, BM_WUC, &i); 3063 ret_val = e1000_phy_hw_reset_ich8lan(hw); 3064 if (ret_val) 3065 return ret_val; 3066 } 3067 3068 /* Setup link and flow control */ 3069 ret_val = e1000_setup_link_ich8lan(hw); 3070 3071 /* Set the transmit descriptor write-back policy for both queues */ 3072 txdctl = er32(TXDCTL(0)); 3073 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3074 E1000_TXDCTL_FULL_TX_DESC_WB; 3075 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3076 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3077 ew32(TXDCTL(0), txdctl); 3078 txdctl = er32(TXDCTL(1)); 3079 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3080 E1000_TXDCTL_FULL_TX_DESC_WB; 3081 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3082 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3083 ew32(TXDCTL(1), txdctl); 3084 3085 /* 3086 * ICH8 has opposite polarity of no_snoop bits. 3087 * By default, we should use snoop behavior. 3088 */ 3089 if (mac->type == e1000_ich8lan) 3090 snoop = PCIE_ICH8_SNOOP_ALL; 3091 else 3092 snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 3093 e1000e_set_pcie_no_snoop(hw, snoop); 3094 3095 ctrl_ext = er32(CTRL_EXT); 3096 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 3097 ew32(CTRL_EXT, ctrl_ext); 3098 3099 /* 3100 * Clear all of the statistics registers (clear on read). It is 3101 * important that we do this after we have tried to establish link 3102 * because the symbol error count will increment wildly if there 3103 * is no link. 3104 */ 3105 e1000_clear_hw_cntrs_ich8lan(hw); 3106 3107 return 0; 3108} 3109/** 3110 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 3111 * @hw: pointer to the HW structure 3112 * 3113 * Sets/Clears required hardware bits necessary for correctly setting up the 3114 * hardware for transmit and receive. 3115 **/ 3116static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 3117{ 3118 u32 reg; 3119 3120 /* Extended Device Control */ 3121 reg = er32(CTRL_EXT); 3122 reg |= (1 << 22); 3123 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 3124 if (hw->mac.type >= e1000_pchlan) 3125 reg |= E1000_CTRL_EXT_PHYPDEN; 3126 ew32(CTRL_EXT, reg); 3127 3128 /* Transmit Descriptor Control 0 */ 3129 reg = er32(TXDCTL(0)); 3130 reg |= (1 << 22); 3131 ew32(TXDCTL(0), reg); 3132 3133 /* Transmit Descriptor Control 1 */ 3134 reg = er32(TXDCTL(1)); 3135 reg |= (1 << 22); 3136 ew32(TXDCTL(1), reg); 3137 3138 /* Transmit Arbitration Control 0 */ 3139 reg = er32(TARC(0)); 3140 if (hw->mac.type == e1000_ich8lan) 3141 reg |= (1 << 28) | (1 << 29); 3142 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 3143 ew32(TARC(0), reg); 3144 3145 /* Transmit Arbitration Control 1 */ 3146 reg = er32(TARC(1)); 3147 if (er32(TCTL) & E1000_TCTL_MULR) 3148 reg &= ~(1 << 28); 3149 else 3150 reg |= (1 << 28); 3151 reg |= (1 << 24) | (1 << 26) | (1 << 30); 3152 ew32(TARC(1), reg); 3153 3154 /* Device Status */ 3155 if (hw->mac.type == e1000_ich8lan) { 3156 reg = er32(STATUS); 3157 reg &= ~(1 << 31); 3158 ew32(STATUS, reg); 3159 } 3160 3161 reg = er32(RFCTL); 3162 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 3163 ew32(RFCTL, reg); 3164} 3165 3166/** 3167 * e1000_setup_link_ich8lan - Setup flow control and link settings 3168 * @hw: pointer to the HW structure 3169 * 3170 * Determines which flow control settings to use, then configures flow 3171 * control. Calls the appropriate media-specific link configuration 3172 * function. Assuming the adapter has a valid link partner, a valid link 3173 * should be established. Assumes the hardware has previously been reset 3174 * and the transmitter and receiver are not enabled. 3175 **/ 3176static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 3177{ 3178 s32 ret_val; 3179 3180 if (e1000_check_reset_block(hw)) 3181 return 0; 3182 3183 /* 3184 * ICH parts do not have a word in the NVM to determine 3185 * the default flow control setting, so we explicitly 3186 * set it to full. 3187 */ 3188 if (hw->fc.requested_mode == e1000_fc_default) { 3189 if (hw->mac.type == e1000_pchlan) 3190 hw->fc.requested_mode = e1000_fc_rx_pause; 3191 else 3192 hw->fc.requested_mode = e1000_fc_full; 3193 } 3194 3195 /* 3196 * Save off the requested flow control mode for use later. Depending 3197 * on the link partner's capabilities, we may or may not use this mode. 3198 */ 3199 hw->fc.current_mode = hw->fc.requested_mode; 3200 3201 e_dbg("After fix-ups FlowControl is now = %x\n", 3202 hw->fc.current_mode); 3203 3204 /* Continue to configure the copper link. */ 3205 ret_val = e1000_setup_copper_link_ich8lan(hw); 3206 if (ret_val) 3207 return ret_val; 3208 3209 ew32(FCTTV, hw->fc.pause_time); 3210 if ((hw->phy.type == e1000_phy_82578) || 3211 (hw->phy.type == e1000_phy_82579) || 3212 (hw->phy.type == e1000_phy_82577)) { 3213 ew32(FCRTV_PCH, hw->fc.refresh_time); 3214 3215 ret_val = hw->phy.ops.write_reg(hw, 3216 PHY_REG(BM_PORT_CTRL_PAGE, 27), 3217 hw->fc.pause_time); 3218 if (ret_val) 3219 return ret_val; 3220 } 3221 3222 return e1000e_set_fc_watermarks(hw); 3223} 3224 3225/** 3226 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 3227 * @hw: pointer to the HW structure 3228 * 3229 * Configures the kumeran interface to the PHY to wait the appropriate time 3230 * when polling the PHY, then call the generic setup_copper_link to finish 3231 * configuring the copper link. 3232 **/ 3233static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 3234{ 3235 u32 ctrl; 3236 s32 ret_val; 3237 u16 reg_data; 3238 3239 ctrl = er32(CTRL); 3240 ctrl |= E1000_CTRL_SLU; 3241 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3242 ew32(CTRL, ctrl); 3243 3244 /* 3245 * Set the mac to wait the maximum time between each iteration 3246 * and increase the max iterations when polling the phy; 3247 * this fixes erroneous timeouts at 10Mbps. 3248 */ 3249 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 3250 if (ret_val) 3251 return ret_val; 3252 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 3253 ®_data); 3254 if (ret_val) 3255 return ret_val; 3256 reg_data |= 0x3F; 3257 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 3258 reg_data); 3259 if (ret_val) 3260 return ret_val; 3261 3262 switch (hw->phy.type) { 3263 case e1000_phy_igp_3: 3264 ret_val = e1000e_copper_link_setup_igp(hw); 3265 if (ret_val) 3266 return ret_val; 3267 break; 3268 case e1000_phy_bm: 3269 case e1000_phy_82578: 3270 ret_val = e1000e_copper_link_setup_m88(hw); 3271 if (ret_val) 3272 return ret_val; 3273 break; 3274 case e1000_phy_82577: 3275 case e1000_phy_82579: 3276 ret_val = e1000_copper_link_setup_82577(hw); 3277 if (ret_val) 3278 return ret_val; 3279 break; 3280 case e1000_phy_ife: 3281 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 3282 ®_data); 3283 if (ret_val) 3284 return ret_val; 3285 3286 reg_data &= ~IFE_PMC_AUTO_MDIX; 3287 3288 switch (hw->phy.mdix) { 3289 case 1: 3290 reg_data &= ~IFE_PMC_FORCE_MDIX; 3291 break; 3292 case 2: 3293 reg_data |= IFE_PMC_FORCE_MDIX; 3294 break; 3295 case 0: 3296 default: 3297 reg_data |= IFE_PMC_AUTO_MDIX; 3298 break; 3299 } 3300 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 3301 reg_data); 3302 if (ret_val) 3303 return ret_val; 3304 break; 3305 default: 3306 break; 3307 } 3308 return e1000e_setup_copper_link(hw); 3309} 3310 3311static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 3312 u16 *duplex) 3313{ 3314 s32 ret_val; 3315 3316 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 3317 if (ret_val) 3318 return ret_val; 3319 3320 if ((hw->mac.type == e1000_ich8lan) && 3321 (hw->phy.type == e1000_phy_igp_3) && 3322 (*speed == SPEED_1000)) { 3323 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 3324 } 3325 3326 return ret_val; 3327} 3328 3329static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 3330{ 3331 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3332 u32 phy_ctrl; 3333 s32 ret_val; 3334 u16 i, data; 3335 bool link; 3336 3337 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 3338 return 0; 3339 3340 /* 3341 * Make sure link is up before proceeding. If not just return. 3342 * Attempting this while link is negotiating fouled up link 3343 * stability 3344 */ 3345 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 3346 if (!link) 3347 return 0; 3348 3349 for (i = 0; i < 10; i++) { 3350 /* read once to clear */ 3351 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 3352 if (ret_val) 3353 return ret_val; 3354 /* and again to get new status */ 3355 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 3356 if (ret_val) 3357 return ret_val; 3358 3359 /* check for PCS lock */ 3360 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 3361 return 0; 3362 3363 /* Issue PHY reset */ 3364 e1000_phy_hw_reset(hw); 3365 mdelay(5); 3366 } 3367 /* Disable GigE link negotiation */ 3368 phy_ctrl = er32(PHY_CTRL); 3369 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 3370 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3371 ew32(PHY_CTRL, phy_ctrl); 3372 3373 e1000e_gig_downshift_workaround_ich8lan(hw); 3374 3375 /* unable to acquire PCS lock */ 3376 return -E1000_ERR_PHY; 3377} 3378 3379void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 3380 bool state) 3381{ 3382 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3383 3384 if (hw->mac.type != e1000_ich8lan) { 3385 e_dbg("Workaround applies to ICH8 only.\n"); 3386 return; 3387 } 3388 3389 dev_spec->kmrn_lock_loss_workaround_enabled = state; 3390} 3391 3392void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 3393{ 3394 u32 reg; 3395 u16 data; 3396 u8 retry = 0; 3397 3398 if (hw->phy.type != e1000_phy_igp_3) 3399 return; 3400 3401 do { 3402 /* Disable link */ 3403 reg = er32(PHY_CTRL); 3404 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 3405 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3406 ew32(PHY_CTRL, reg); 3407 3408 if (hw->mac.type == e1000_ich8lan) 3409 e1000e_gig_downshift_workaround_ich8lan(hw); 3410 3411 /* Write VR power-down enable */ 3412 e1e_rphy(hw, IGP3_VR_CTRL, &data); 3413 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3414 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 3415 3416 /* Read it back and test */ 3417 e1e_rphy(hw, IGP3_VR_CTRL, &data); 3418 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3419 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 3420 break; 3421 3422 /* Issue PHY reset and repeat at most one more time */ 3423 reg = er32(CTRL); 3424 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 3425 retry++; 3426 } while (retry); 3427} 3428 3429/** 3430 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 3431 * @hw: pointer to the HW structure 3432 * 3433 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 3434 * LPLU, Gig disable, MDIC PHY reset): 3435 * 1) Set Kumeran Near-end loopback 3436 * 2) Clear Kumeran Near-end loopback 3437 * Should only be called for ICH8[m] devices with IGP_3 Phy. 3438 **/ 3439void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 3440{ 3441 s32 ret_val; 3442 u16 reg_data; 3443 3444 if ((hw->mac.type != e1000_ich8lan) || 3445 (hw->phy.type != e1000_phy_igp_3)) 3446 return; 3447 3448 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 3449 ®_data); 3450 if (ret_val) 3451 return; 3452 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 3453 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 3454 reg_data); 3455 if (ret_val) 3456 return; 3457 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 3458 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 3459 reg_data); 3460} 3461 3462/** 3463 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL 3464 * @hw: pointer to the HW structure 3465 * 3466 * During S0 to Sx transition, it is possible the link remains at gig 3467 * instead of negotiating to a lower speed. Before going to Sx, set 3468 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 3469 * to a lower speed. 3470 * 3471 * Should only be called for applicable parts. 3472 **/ 3473void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) 3474{ 3475 u32 phy_ctrl; 3476 s32 ret_val; 3477 3478 phy_ctrl = er32(PHY_CTRL); 3479 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE; 3480 ew32(PHY_CTRL, phy_ctrl); 3481 3482 if (hw->mac.type >= e1000_pchlan) { 3483 e1000_oem_bits_config_ich8lan(hw, true); 3484 ret_val = hw->phy.ops.acquire(hw); 3485 if (ret_val) 3486 return; 3487 e1000_write_smbus_addr(hw); 3488 hw->phy.ops.release(hw); 3489 } 3490} 3491 3492/** 3493 * e1000_cleanup_led_ich8lan - Restore the default LED operation 3494 * @hw: pointer to the HW structure 3495 * 3496 * Return the LED back to the default configuration. 3497 **/ 3498static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 3499{ 3500 if (hw->phy.type == e1000_phy_ife) 3501 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 3502 3503 ew32(LEDCTL, hw->mac.ledctl_default); 3504 return 0; 3505} 3506 3507/** 3508 * e1000_led_on_ich8lan - Turn LEDs on 3509 * @hw: pointer to the HW structure 3510 * 3511 * Turn on the LEDs. 3512 **/ 3513static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 3514{ 3515 if (hw->phy.type == e1000_phy_ife) 3516 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3517 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 3518 3519 ew32(LEDCTL, hw->mac.ledctl_mode2); 3520 return 0; 3521} 3522 3523/** 3524 * e1000_led_off_ich8lan - Turn LEDs off 3525 * @hw: pointer to the HW structure 3526 * 3527 * Turn off the LEDs. 3528 **/ 3529static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 3530{ 3531 if (hw->phy.type == e1000_phy_ife) 3532 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3533 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 3534 3535 ew32(LEDCTL, hw->mac.ledctl_mode1); 3536 return 0; 3537} 3538 3539/** 3540 * e1000_setup_led_pchlan - Configures SW controllable LED 3541 * @hw: pointer to the HW structure 3542 * 3543 * This prepares the SW controllable LED for use. 3544 **/ 3545static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 3546{ 3547 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3548 (u16)hw->mac.ledctl_mode1); 3549} 3550 3551/** 3552 * e1000_cleanup_led_pchlan - Restore the default LED operation 3553 * @hw: pointer to the HW structure 3554 * 3555 * Return the LED back to the default configuration. 3556 **/ 3557static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 3558{ 3559 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3560 (u16)hw->mac.ledctl_default); 3561} 3562 3563/** 3564 * e1000_led_on_pchlan - Turn LEDs on 3565 * @hw: pointer to the HW structure 3566 * 3567 * Turn on the LEDs. 3568 **/ 3569static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 3570{ 3571 u16 data = (u16)hw->mac.ledctl_mode2; 3572 u32 i, led; 3573 3574 /* 3575 * If no link, then turn LED on by setting the invert bit 3576 * for each LED that's mode is "link_up" in ledctl_mode2. 3577 */ 3578 if (!(er32(STATUS) & E1000_STATUS_LU)) { 3579 for (i = 0; i < 3; i++) { 3580 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 3581 if ((led & E1000_PHY_LED0_MODE_MASK) != 3582 E1000_LEDCTL_MODE_LINK_UP) 3583 continue; 3584 if (led & E1000_PHY_LED0_IVRT) 3585 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 3586 else 3587 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 3588 } 3589 } 3590 3591 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3592} 3593 3594/** 3595 * e1000_led_off_pchlan - Turn LEDs off 3596 * @hw: pointer to the HW structure 3597 * 3598 * Turn off the LEDs. 3599 **/ 3600static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 3601{ 3602 u16 data = (u16)hw->mac.ledctl_mode1; 3603 u32 i, led; 3604 3605 /* 3606 * If no link, then turn LED off by clearing the invert bit 3607 * for each LED that's mode is "link_up" in ledctl_mode1. 3608 */ 3609 if (!(er32(STATUS) & E1000_STATUS_LU)) { 3610 for (i = 0; i < 3; i++) { 3611 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 3612 if ((led & E1000_PHY_LED0_MODE_MASK) != 3613 E1000_LEDCTL_MODE_LINK_UP) 3614 continue; 3615 if (led & E1000_PHY_LED0_IVRT) 3616 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 3617 else 3618 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 3619 } 3620 } 3621 3622 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3623} 3624 3625/** 3626 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 3627 * @hw: pointer to the HW structure 3628 * 3629 * Read appropriate register for the config done bit for completion status 3630 * and configure the PHY through s/w for EEPROM-less parts. 3631 * 3632 * NOTE: some silicon which is EEPROM-less will fail trying to read the 3633 * config done bit, so only an error is logged and continues. If we were 3634 * to return with error, EEPROM-less silicon would not be able to be reset 3635 * or change link. 3636 **/ 3637static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 3638{ 3639 s32 ret_val = 0; 3640 u32 bank = 0; 3641 u32 status; 3642 3643 e1000e_get_cfg_done(hw); 3644 3645 /* Wait for indication from h/w that it has completed basic config */ 3646 if (hw->mac.type >= e1000_ich10lan) { 3647 e1000_lan_init_done_ich8lan(hw); 3648 } else { 3649 ret_val = e1000e_get_auto_rd_done(hw); 3650 if (ret_val) { 3651 /* 3652 * When auto config read does not complete, do not 3653 * return with an error. This can happen in situations 3654 * where there is no eeprom and prevents getting link. 3655 */ 3656 e_dbg("Auto Read Done did not complete\n"); 3657 ret_val = 0; 3658 } 3659 } 3660 3661 /* Clear PHY Reset Asserted bit */ 3662 status = er32(STATUS); 3663 if (status & E1000_STATUS_PHYRA) 3664 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 3665 else 3666 e_dbg("PHY Reset Asserted not set - needs delay\n"); 3667 3668 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 3669 if (hw->mac.type <= e1000_ich9lan) { 3670 if (((er32(EECD) & E1000_EECD_PRES) == 0) && 3671 (hw->phy.type == e1000_phy_igp_3)) { 3672 e1000e_phy_init_script_igp3(hw); 3673 } 3674 } else { 3675 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 3676 /* Maybe we should do a basic PHY config */ 3677 e_dbg("EEPROM not present\n"); 3678 ret_val = -E1000_ERR_CONFIG; 3679 } 3680 } 3681 3682 return ret_val; 3683} 3684 3685/** 3686 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 3687 * @hw: pointer to the HW structure 3688 * 3689 * In the case of a PHY power down to save power, or to turn off link during a 3690 * driver unload, or wake on lan is not enabled, remove the link. 3691 **/ 3692static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 3693{ 3694 /* If the management interface is not enabled, then power down */ 3695 if (!(hw->mac.ops.check_mng_mode(hw) || 3696 hw->phy.ops.check_reset_block(hw))) 3697 e1000_power_down_phy_copper(hw); 3698} 3699 3700/** 3701 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 3702 * @hw: pointer to the HW structure 3703 * 3704 * Clears hardware counters specific to the silicon family and calls 3705 * clear_hw_cntrs_generic to clear all general purpose counters. 3706 **/ 3707static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 3708{ 3709 u16 phy_data; 3710 3711 e1000e_clear_hw_cntrs_base(hw); 3712 3713 er32(ALGNERRC); 3714 er32(RXERRC); 3715 er32(TNCRS); 3716 er32(CEXTERR); 3717 er32(TSCTC); 3718 er32(TSCTFC); 3719 3720 er32(MGTPRC); 3721 er32(MGTPDC); 3722 er32(MGTPTC); 3723 3724 er32(IAC); 3725 er32(ICRXOC); 3726 3727 /* Clear PHY statistics registers */ 3728 if ((hw->phy.type == e1000_phy_82578) || 3729 (hw->phy.type == e1000_phy_82579) || 3730 (hw->phy.type == e1000_phy_82577)) { 3731 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); 3732 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); 3733 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); 3734 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); 3735 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); 3736 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); 3737 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); 3738 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); 3739 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); 3740 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data); 3741 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data); 3742 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data); 3743 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data); 3744 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data); 3745 } 3746} 3747 3748static struct e1000_mac_operations ich8_mac_ops = { 3749 .id_led_init = e1000e_id_led_init, 3750 /* check_mng_mode dependent on mac type */ 3751 .check_for_link = e1000_check_for_copper_link_ich8lan, 3752 /* cleanup_led dependent on mac type */ 3753 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 3754 .get_bus_info = e1000_get_bus_info_ich8lan, 3755 .set_lan_id = e1000_set_lan_id_single_port, 3756 .get_link_up_info = e1000_get_link_up_info_ich8lan, 3757 /* led_on dependent on mac type */ 3758 /* led_off dependent on mac type */ 3759 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 3760 .reset_hw = e1000_reset_hw_ich8lan, 3761 .init_hw = e1000_init_hw_ich8lan, 3762 .setup_link = e1000_setup_link_ich8lan, 3763 .setup_physical_interface= e1000_setup_copper_link_ich8lan, 3764 /* id_led_init dependent on mac type */ 3765}; 3766 3767static struct e1000_phy_operations ich8_phy_ops = { 3768 .acquire = e1000_acquire_swflag_ich8lan, 3769 .check_reset_block = e1000_check_reset_block_ich8lan, 3770 .commit = NULL, 3771 .get_cfg_done = e1000_get_cfg_done_ich8lan, 3772 .get_cable_length = e1000e_get_cable_length_igp_2, 3773 .read_reg = e1000e_read_phy_reg_igp, 3774 .release = e1000_release_swflag_ich8lan, 3775 .reset = e1000_phy_hw_reset_ich8lan, 3776 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 3777 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 3778 .write_reg = e1000e_write_phy_reg_igp, 3779}; 3780 3781static struct e1000_nvm_operations ich8_nvm_ops = { 3782 .acquire = e1000_acquire_nvm_ich8lan, 3783 .read = e1000_read_nvm_ich8lan, 3784 .release = e1000_release_nvm_ich8lan, 3785 .update = e1000_update_nvm_checksum_ich8lan, 3786 .valid_led_default = e1000_valid_led_default_ich8lan, 3787 .validate = e1000_validate_nvm_checksum_ich8lan, 3788 .write = e1000_write_nvm_ich8lan, 3789}; 3790 3791struct e1000_info e1000_ich8_info = { 3792 .mac = e1000_ich8lan, 3793 .flags = FLAG_HAS_WOL 3794 | FLAG_IS_ICH 3795 | FLAG_RX_CSUM_ENABLED 3796 | FLAG_HAS_CTRLEXT_ON_LOAD 3797 | FLAG_HAS_AMT 3798 | FLAG_HAS_FLASH 3799 | FLAG_APME_IN_WUC, 3800 .pba = 8, 3801 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, 3802 .get_variants = e1000_get_variants_ich8lan, 3803 .mac_ops = &ich8_mac_ops, 3804 .phy_ops = &ich8_phy_ops, 3805 .nvm_ops = &ich8_nvm_ops, 3806}; 3807 3808struct e1000_info e1000_ich9_info = { 3809 .mac = e1000_ich9lan, 3810 .flags = FLAG_HAS_JUMBO_FRAMES 3811 | FLAG_IS_ICH 3812 | FLAG_HAS_WOL 3813 | FLAG_RX_CSUM_ENABLED 3814 | FLAG_HAS_CTRLEXT_ON_LOAD 3815 | FLAG_HAS_AMT 3816 | FLAG_HAS_ERT 3817 | FLAG_HAS_FLASH 3818 | FLAG_APME_IN_WUC, 3819 .pba = 10, 3820 .max_hw_frame_size = DEFAULT_JUMBO, 3821 .get_variants = e1000_get_variants_ich8lan, 3822 .mac_ops = &ich8_mac_ops, 3823 .phy_ops = &ich8_phy_ops, 3824 .nvm_ops = &ich8_nvm_ops, 3825}; 3826 3827struct e1000_info e1000_ich10_info = { 3828 .mac = e1000_ich10lan, 3829 .flags = FLAG_HAS_JUMBO_FRAMES 3830 | FLAG_IS_ICH 3831 | FLAG_HAS_WOL 3832 | FLAG_RX_CSUM_ENABLED 3833 | FLAG_HAS_CTRLEXT_ON_LOAD 3834 | FLAG_HAS_AMT 3835 | FLAG_HAS_ERT 3836 | FLAG_HAS_FLASH 3837 | FLAG_APME_IN_WUC, 3838 .pba = 10, 3839 .max_hw_frame_size = DEFAULT_JUMBO, 3840 .get_variants = e1000_get_variants_ich8lan, 3841 .mac_ops = &ich8_mac_ops, 3842 .phy_ops = &ich8_phy_ops, 3843 .nvm_ops = &ich8_nvm_ops, 3844}; 3845 3846struct e1000_info e1000_pch_info = { 3847 .mac = e1000_pchlan, 3848 .flags = FLAG_IS_ICH 3849 | FLAG_HAS_WOL 3850 | FLAG_RX_CSUM_ENABLED 3851 | FLAG_HAS_CTRLEXT_ON_LOAD 3852 | FLAG_HAS_AMT 3853 | FLAG_HAS_FLASH 3854 | FLAG_HAS_JUMBO_FRAMES 3855 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 3856 | FLAG_APME_IN_WUC, 3857 .flags2 = FLAG2_HAS_PHY_STATS, 3858 .pba = 26, 3859 .max_hw_frame_size = 4096, 3860 .get_variants = e1000_get_variants_ich8lan, 3861 .mac_ops = &ich8_mac_ops, 3862 .phy_ops = &ich8_phy_ops, 3863 .nvm_ops = &ich8_nvm_ops, 3864}; 3865 3866struct e1000_info e1000_pch2_info = { 3867 .mac = e1000_pch2lan, 3868 .flags = FLAG_IS_ICH 3869 | FLAG_HAS_WOL 3870 | FLAG_RX_CSUM_ENABLED 3871 | FLAG_HAS_CTRLEXT_ON_LOAD 3872 | FLAG_HAS_AMT 3873 | FLAG_HAS_FLASH 3874 | FLAG_HAS_JUMBO_FRAMES 3875 | FLAG_APME_IN_WUC, 3876 .flags2 = FLAG2_HAS_PHY_STATS 3877 | FLAG2_HAS_EEE, 3878 .pba = 18, 3879 .max_hw_frame_size = DEFAULT_JUMBO, 3880 .get_variants = e1000_get_variants_ich8lan, 3881 .mac_ops = &ich8_mac_ops, 3882 .phy_ops = &ich8_phy_ops, 3883 .nvm_ops = &ich8_nvm_ops, 3884}; 3885