1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2010 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#ifndef _E1000_DEFINES_H_ 30#define _E1000_DEFINES_H_ 31 32#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 33#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 34#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 35#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 36#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 37#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 38#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 39#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 40#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 41#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 42#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 43#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 44#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 45#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 46#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 47#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 48#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 49#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 50 51/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 52#define REQ_TX_DESCRIPTOR_MULTIPLE 8 53#define REQ_RX_DESCRIPTOR_MULTIPLE 8 54 55/* Definitions for power management and wakeup registers */ 56/* Wake Up Control */ 57#define E1000_WUC_APME 0x00000001 /* APM Enable */ 58#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 59#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 60 61/* Wake Up Filter Control */ 62#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 63#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 64#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 65#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 66#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 67#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 68 69/* Wake Up Status */ 70#define E1000_WUS_LNKC E1000_WUFC_LNKC 71#define E1000_WUS_MAG E1000_WUFC_MAG 72#define E1000_WUS_EX E1000_WUFC_EX 73#define E1000_WUS_MC E1000_WUFC_MC 74#define E1000_WUS_BC E1000_WUFC_BC 75 76/* Extended Device Control */ 77#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 78#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 79#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 80#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 81#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 82#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 83#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 84#define E1000_CTRL_EXT_EIAME 0x01000000 85#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 86#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 87#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 88#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 89#define E1000_CTRL_EXT_PHYPDEN 0x00100000 90 91/* Receive Descriptor bit definitions */ 92#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 93#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 94#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 95#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 96#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 97#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 98#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 99#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 100#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 101#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 102#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 103#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 104#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 105 106#define E1000_RXDEXT_STATERR_CE 0x01000000 107#define E1000_RXDEXT_STATERR_SE 0x02000000 108#define E1000_RXDEXT_STATERR_SEQ 0x04000000 109#define E1000_RXDEXT_STATERR_CXE 0x10000000 110#define E1000_RXDEXT_STATERR_RXE 0x80000000 111 112/* mask to determine if packets should be dropped due to frame errors */ 113#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 114 E1000_RXD_ERR_CE | \ 115 E1000_RXD_ERR_SE | \ 116 E1000_RXD_ERR_SEQ | \ 117 E1000_RXD_ERR_CXE | \ 118 E1000_RXD_ERR_RXE) 119 120/* Same mask, but for extended and packet split descriptors */ 121#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 122 E1000_RXDEXT_STATERR_CE | \ 123 E1000_RXDEXT_STATERR_SE | \ 124 E1000_RXDEXT_STATERR_SEQ | \ 125 E1000_RXDEXT_STATERR_CXE | \ 126 E1000_RXDEXT_STATERR_RXE) 127 128#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 129 130/* Management Control */ 131#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 132#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 133#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 134#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 135#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 136/* Enable MAC address filtering */ 137#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 138/* Enable MNG packets to host memory */ 139#define E1000_MANC_EN_MNG2HOST 0x00200000 140 141#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 142#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 143#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 144#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 145 146/* Receive Control */ 147#define E1000_RCTL_EN 0x00000002 /* enable */ 148#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 149#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 150#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 151#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 152#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 153#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 154#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 155#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 156#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 157#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 158#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 159#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 160/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 161#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 162#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 163#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 164#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 165/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 166#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 167#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 168#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 169#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 170#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 171#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 172#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 173#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 174#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 175 176/* 177 * Use byte values for the following shift parameters 178 * Usage: 179 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 180 * E1000_PSRCTL_BSIZE0_MASK) | 181 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 182 * E1000_PSRCTL_BSIZE1_MASK) | 183 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 184 * E1000_PSRCTL_BSIZE2_MASK) | 185 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 186 * E1000_PSRCTL_BSIZE3_MASK)) 187 * where value0 = [128..16256], default=256 188 * value1 = [1024..64512], default=4096 189 * value2 = [0..64512], default=4096 190 * value3 = [0..64512], default=0 191 */ 192 193#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 194#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 195#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 196#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 197 198#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 199#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 200#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 201#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 202 203/* SWFW_SYNC Definitions */ 204#define E1000_SWFW_EEP_SM 0x1 205#define E1000_SWFW_PHY0_SM 0x2 206#define E1000_SWFW_PHY1_SM 0x4 207#define E1000_SWFW_CSR_SM 0x8 208 209/* Device Control */ 210#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 211#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 212#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 213#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 214#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 215#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 216#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 217#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 218#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 219#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 220#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 221#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 222#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 223#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 224#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 225#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 226#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 227#define E1000_CTRL_RST 0x04000000 /* Global reset */ 228#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 229#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 230#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 231#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 232 233/* 234 * Bit definitions for the Management Data IO (MDIO) and Management Data 235 * Clock (MDC) pins in the Device Control Register. 236 */ 237 238/* Device Status */ 239#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 240#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 241#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 242#define E1000_STATUS_FUNC_SHIFT 2 243#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 244#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 245#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 246#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 247#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 248#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 249#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 250#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 251 252/* Constants used to interpret the masked PCI-X bus speed. */ 253 254#define HALF_DUPLEX 1 255#define FULL_DUPLEX 2 256 257 258#define ADVERTISE_10_HALF 0x0001 259#define ADVERTISE_10_FULL 0x0002 260#define ADVERTISE_100_HALF 0x0004 261#define ADVERTISE_100_FULL 0x0008 262#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 263#define ADVERTISE_1000_FULL 0x0020 264 265/* 1000/H is not supported, nor spec-compliant. */ 266#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 267 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 268 ADVERTISE_1000_FULL) 269#define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 270 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 271#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 272#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 273#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 274 275#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 276 277/* LED Control */ 278#define E1000_PHY_LED0_MODE_MASK 0x00000007 279#define E1000_PHY_LED0_IVRT 0x00000008 280#define E1000_PHY_LED0_MASK 0x0000001F 281 282#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 283#define E1000_LEDCTL_LED0_MODE_SHIFT 0 284#define E1000_LEDCTL_LED0_IVRT 0x00000040 285#define E1000_LEDCTL_LED0_BLINK 0x00000080 286 287#define E1000_LEDCTL_MODE_LINK_UP 0x2 288#define E1000_LEDCTL_MODE_LED_ON 0xE 289#define E1000_LEDCTL_MODE_LED_OFF 0xF 290 291/* Transmit Descriptor bit definitions */ 292#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 293#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 294#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 295#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 296#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 297#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 298#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 299#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 300#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 301#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 302#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 303#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 304#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 305#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 306#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 307#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 308#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 309#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 310#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 311 312/* Transmit Control */ 313#define E1000_TCTL_EN 0x00000002 /* enable Tx */ 314#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 315#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 316#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 317#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 318#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 319 320/* Transmit Arbitration Count */ 321 322/* SerDes Control */ 323#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 324 325/* Receive Checksum Control */ 326#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 327#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 328 329/* Header split receive */ 330#define E1000_RFCTL_NFSW_DIS 0x00000040 331#define E1000_RFCTL_NFSR_DIS 0x00000080 332#define E1000_RFCTL_ACK_DIS 0x00001000 333#define E1000_RFCTL_EXTEN 0x00008000 334#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 335#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 336 337/* Collision related configuration parameters */ 338#define E1000_COLLISION_THRESHOLD 15 339#define E1000_CT_SHIFT 4 340#define E1000_COLLISION_DISTANCE 63 341#define E1000_COLD_SHIFT 12 342 343/* Default values for the transmit IPG register */ 344#define DEFAULT_82543_TIPG_IPGT_COPPER 8 345 346#define E1000_TIPG_IPGT_MASK 0x000003FF 347 348#define DEFAULT_82543_TIPG_IPGR1 8 349#define E1000_TIPG_IPGR1_SHIFT 10 350 351#define DEFAULT_82543_TIPG_IPGR2 6 352#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 353#define E1000_TIPG_IPGR2_SHIFT 20 354 355#define MAX_JUMBO_FRAME_SIZE 0x3F00 356 357/* Extended Configuration Control and Size */ 358#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 359#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 360#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 361#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 362#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 363#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 364#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 365#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 366#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 367 368#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 369#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 370#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 371#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 372 373#define E1000_KABGTXD_BGSQLBIAS 0x00050000 374 375/* PBA constants */ 376#define E1000_PBA_8K 0x0008 /* 8KB */ 377#define E1000_PBA_16K 0x0010 /* 16KB */ 378 379#define E1000_PBS_16K E1000_PBA_16K 380 381#define IFS_MAX 80 382#define IFS_MIN 40 383#define IFS_RATIO 4 384#define IFS_STEP 10 385#define MIN_NUM_XMITS 1000 386 387/* SW Semaphore Register */ 388#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 389#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 390#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 391 392#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 393 394/* Interrupt Cause Read */ 395#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 396#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 397#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 398#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 399#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 400#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 401#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 402#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 403#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 404#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 405#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 406 407/* PBA ECC Register */ 408#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 409#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 410#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 411#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 412#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 413 414/* 415 * This defines the bits that are set in the Interrupt Mask 416 * Set/Read Register. Each bit is documented below: 417 * o RXT0 = Receiver Timer Interrupt (ring 0) 418 * o TXDW = Transmit Descriptor Written Back 419 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 420 * o RXSEQ = Receive Sequence Error 421 * o LSC = Link Status Change 422 */ 423#define IMS_ENABLE_MASK ( \ 424 E1000_IMS_RXT0 | \ 425 E1000_IMS_TXDW | \ 426 E1000_IMS_RXDMT0 | \ 427 E1000_IMS_RXSEQ | \ 428 E1000_IMS_LSC) 429 430/* Interrupt Mask Set */ 431#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 432#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 433#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 434#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 435#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 436#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 437#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 438#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 439#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 440#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 441 442/* Interrupt Cause Set */ 443#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 444#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 445#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 446 447/* Transmit Descriptor Control */ 448#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 449#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 450#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 451#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 452/* Enable the counting of desc. still to be processed. */ 453#define E1000_TXDCTL_COUNT_DESC 0x00400000 454 455/* Flow Control Constants */ 456#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 457#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 458#define FLOW_CONTROL_TYPE 0x8808 459 460/* 802.1q VLAN Packet Size */ 461#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 462 463/* Receive Address */ 464/* 465 * Number of high/low register pairs in the RAR. The RAR (Receive Address 466 * Registers) holds the directed and multicast addresses that we monitor. 467 * Technically, we have 16 spots. However, we reserve one of these spots 468 * (RAR[15]) for our directed address used by controllers with 469 * manageability enabled, allowing us room for 15 multicast addresses. 470 */ 471#define E1000_RAR_ENTRIES 15 472#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 473#define E1000_RAL_MAC_ADDR_LEN 4 474#define E1000_RAH_MAC_ADDR_LEN 2 475 476/* Error Codes */ 477#define E1000_ERR_NVM 1 478#define E1000_ERR_PHY 2 479#define E1000_ERR_CONFIG 3 480#define E1000_ERR_PARAM 4 481#define E1000_ERR_MAC_INIT 5 482#define E1000_ERR_PHY_TYPE 6 483#define E1000_ERR_RESET 9 484#define E1000_ERR_MASTER_REQUESTS_PENDING 10 485#define E1000_ERR_HOST_INTERFACE_COMMAND 11 486#define E1000_BLK_PHY_RESET 12 487#define E1000_ERR_SWFW_SYNC 13 488#define E1000_NOT_IMPLEMENTED 14 489 490/* Loop limit on how long we wait for auto-negotiation to complete */ 491#define FIBER_LINK_UP_LIMIT 50 492#define COPPER_LINK_UP_LIMIT 10 493#define PHY_AUTO_NEG_LIMIT 45 494#define PHY_FORCE_LIMIT 20 495/* Number of 100 microseconds we wait for PCI Express master disable */ 496#define MASTER_DISABLE_TIMEOUT 800 497/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 498#define PHY_CFG_TIMEOUT 100 499/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 500#define MDIO_OWNERSHIP_TIMEOUT 10 501/* Number of milliseconds for NVM auto read done after MAC reset. */ 502#define AUTO_READ_DONE_TIMEOUT 10 503 504/* Flow Control */ 505#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 506#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 507#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 508 509/* Transmit Configuration Word */ 510#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 511#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 512#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 513#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 514#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 515 516/* Receive Configuration Word */ 517#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 518#define E1000_RXCW_C 0x20000000 /* Receive config */ 519#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 520 521/* PCI Express Control */ 522#define E1000_GCR_RXD_NO_SNOOP 0x00000001 523#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 524#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 525#define E1000_GCR_TXD_NO_SNOOP 0x00000008 526#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 527#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 528 529#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 530 E1000_GCR_RXDSCW_NO_SNOOP | \ 531 E1000_GCR_RXDSCR_NO_SNOOP | \ 532 E1000_GCR_TXD_NO_SNOOP | \ 533 E1000_GCR_TXDSCW_NO_SNOOP | \ 534 E1000_GCR_TXDSCR_NO_SNOOP) 535 536/* PHY Control Register */ 537#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 538#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 539#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 540#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 541#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 542#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 543#define MII_CR_SPEED_1000 0x0040 544#define MII_CR_SPEED_100 0x2000 545#define MII_CR_SPEED_10 0x0000 546 547/* PHY Status Register */ 548#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 549#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 550 551/* Autoneg Advertisement Register */ 552#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 553#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 554#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 555#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 556#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 557#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 558 559/* Link Partner Ability Register (Base Page) */ 560#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 561#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 562 563/* Autoneg Expansion Register */ 564#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 565 566/* 1000BASE-T Control Register */ 567#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 568#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 569 /* 0=DTE device */ 570#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 571 /* 0=Configure PHY as Slave */ 572#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 573 /* 0=Automatic Master/Slave config */ 574 575/* 1000BASE-T Status Register */ 576#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 577#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 578 579 580/* PHY 1000 MII Register/Bit Definitions */ 581/* PHY Registers defined by IEEE */ 582#define PHY_CONTROL 0x00 /* Control Register */ 583#define PHY_STATUS 0x01 /* Status Register */ 584#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 585#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 586#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 587#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 588#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 589#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 590#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 591#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 592 593#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 594 595/* NVM Control */ 596#define E1000_EECD_SK 0x00000001 /* NVM Clock */ 597#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 598#define E1000_EECD_DI 0x00000004 /* NVM Data In */ 599#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 600#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 601#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 602#define E1000_EECD_PRES 0x00000100 /* NVM Present */ 603#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 604/* NVM Addressing bits based on type (0-small, 1-large) */ 605#define E1000_EECD_ADDR_BITS 0x00000400 606#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 607#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 608#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 609#define E1000_EECD_SIZE_EX_SHIFT 11 610#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 611#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 612#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 613#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 614 615#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ 616#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 617#define E1000_NVM_RW_REG_START 1 /* Start operation */ 618#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 619#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 620#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 621#define E1000_FLASH_UPDATES 2000 622 623/* NVM Word Offsets */ 624#define NVM_COMPAT 0x0003 625#define NVM_ID_LED_SETTINGS 0x0004 626#define NVM_INIT_CONTROL2_REG 0x000F 627#define NVM_INIT_CONTROL3_PORT_B 0x0014 628#define NVM_INIT_3GIO_3 0x001A 629#define NVM_INIT_CONTROL3_PORT_A 0x0024 630#define NVM_CFG 0x0012 631#define NVM_ALT_MAC_ADDR_PTR 0x0037 632#define NVM_CHECKSUM_REG 0x003F 633 634#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ 635 636#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 637#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 638 639/* Mask bits for fields in Word 0x0f of the NVM */ 640#define NVM_WORD0F_PAUSE_MASK 0x3000 641#define NVM_WORD0F_PAUSE 0x1000 642#define NVM_WORD0F_ASM_DIR 0x2000 643 644/* Mask bits for fields in Word 0x1a of the NVM */ 645#define NVM_WORD1A_ASPM_MASK 0x000C 646 647/* Mask bits for fields in Word 0x03 of the EEPROM */ 648#define NVM_COMPAT_LOM 0x0800 649 650/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 651#define NVM_SUM 0xBABA 652 653/* PBA (printed board assembly) number words */ 654#define NVM_PBA_OFFSET_0 8 655#define NVM_PBA_OFFSET_1 9 656 657#define NVM_WORD_SIZE_BASE_SHIFT 6 658 659/* NVM Commands - SPI */ 660#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 661#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 662#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 663#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 664#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 665#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 666 667/* SPI NVM Status Register */ 668#define NVM_STATUS_RDY_SPI 0x01 669 670/* Word definitions for ID LED Settings */ 671#define ID_LED_RESERVED_0000 0x0000 672#define ID_LED_RESERVED_FFFF 0xFFFF 673#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 674 (ID_LED_OFF1_OFF2 << 8) | \ 675 (ID_LED_DEF1_DEF2 << 4) | \ 676 (ID_LED_DEF1_DEF2)) 677#define ID_LED_DEF1_DEF2 0x1 678#define ID_LED_DEF1_ON2 0x2 679#define ID_LED_DEF1_OFF2 0x3 680#define ID_LED_ON1_DEF2 0x4 681#define ID_LED_ON1_ON2 0x5 682#define ID_LED_ON1_OFF2 0x6 683#define ID_LED_OFF1_DEF2 0x7 684#define ID_LED_OFF1_ON2 0x8 685#define ID_LED_OFF1_OFF2 0x9 686 687#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 688#define IGP_ACTIVITY_LED_ENABLE 0x0300 689#define IGP_LED3_MODE 0x07000000 690 691/* PCI/PCI-X/PCI-EX Config space */ 692#define PCI_HEADER_TYPE_REGISTER 0x0E 693#define PCIE_LINK_STATUS 0x12 694 695#define PCI_HEADER_TYPE_MULTIFUNC 0x80 696#define PCIE_LINK_WIDTH_MASK 0x3F0 697#define PCIE_LINK_WIDTH_SHIFT 4 698 699#define PHY_REVISION_MASK 0xFFFFFFF0 700#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 701#define MAX_PHY_MULTI_PAGE_REG 0xF 702 703/* Bit definitions for valid PHY IDs. */ 704/* 705 * I = Integrated 706 * E = External 707 */ 708#define M88E1000_E_PHY_ID 0x01410C50 709#define M88E1000_I_PHY_ID 0x01410C30 710#define M88E1011_I_PHY_ID 0x01410C20 711#define IGP01E1000_I_PHY_ID 0x02A80380 712#define M88E1111_I_PHY_ID 0x01410CC0 713#define GG82563_E_PHY_ID 0x01410CA0 714#define IGP03E1000_E_PHY_ID 0x02A80390 715#define IFE_E_PHY_ID 0x02A80330 716#define IFE_PLUS_E_PHY_ID 0x02A80320 717#define IFE_C_E_PHY_ID 0x02A80310 718#define BME1000_E_PHY_ID 0x01410CB0 719#define BME1000_E_PHY_ID_R2 0x01410CB1 720#define I82577_E_PHY_ID 0x01540050 721#define I82578_E_PHY_ID 0x004DD040 722#define I82579_E_PHY_ID 0x01540090 723 724/* M88E1000 Specific Registers */ 725#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 726#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 727#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 728 729#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 730#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 731 732/* M88E1000 PHY Specific Control Register */ 733#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 734#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 735 /* Manual MDI configuration */ 736#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 737/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 738#define M88E1000_PSCR_AUTO_X_1000T 0x0040 739/* Auto crossover enabled all speeds */ 740#define M88E1000_PSCR_AUTO_X_MODE 0x0060 741/* 742 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) 743 * 0=Normal 10BASE-T Rx Threshold 744 */ 745#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 746 747/* M88E1000 PHY Specific Status Register */ 748#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 749#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 750#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 751/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 752#define M88E1000_PSSR_CABLE_LENGTH 0x0380 753#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 754#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 755 756#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 757 758/* 759 * Number of times we will attempt to autonegotiate before downshifting if we 760 * are the master 761 */ 762#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 763#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 764/* 765 * Number of times we will attempt to autonegotiate before downshifting if we 766 * are the slave 767 */ 768#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 769#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 770#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 771 772/* M88EC018 Rev 2 specific DownShift settings */ 773#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 774#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 775 776#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 777#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 778 779/* BME1000 PHY Specific Control Register */ 780#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 781 782 783#define PHY_PAGE_SHIFT 5 784#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 785 ((reg) & MAX_PHY_REG_ADDRESS)) 786 787/* 788 * Bits... 789 * 15-5: page 790 * 4-0: register offset 791 */ 792#define GG82563_PAGE_SHIFT 5 793#define GG82563_REG(page, reg) \ 794 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 795#define GG82563_MIN_ALT_REG 30 796 797/* GG82563 Specific Registers */ 798#define GG82563_PHY_SPEC_CTRL \ 799 GG82563_REG(0, 16) /* PHY Specific Control */ 800#define GG82563_PHY_PAGE_SELECT \ 801 GG82563_REG(0, 22) /* Page Select */ 802#define GG82563_PHY_SPEC_CTRL_2 \ 803 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 804#define GG82563_PHY_PAGE_SELECT_ALT \ 805 GG82563_REG(0, 29) /* Alternate Page Select */ 806 807#define GG82563_PHY_MAC_SPEC_CTRL \ 808 GG82563_REG(2, 21) /* MAC Specific Control Register */ 809 810#define GG82563_PHY_DSP_DISTANCE \ 811 GG82563_REG(5, 26) /* DSP Distance */ 812 813/* Page 193 - Port Control Registers */ 814#define GG82563_PHY_KMRN_MODE_CTRL \ 815 GG82563_REG(193, 16) /* Kumeran Mode Control */ 816#define GG82563_PHY_PWR_MGMT_CTRL \ 817 GG82563_REG(193, 20) /* Power Management Control */ 818 819/* Page 194 - KMRN Registers */ 820#define GG82563_PHY_INBAND_CTRL \ 821 GG82563_REG(194, 18) /* Inband Control */ 822 823/* MDI Control */ 824#define E1000_MDIC_REG_SHIFT 16 825#define E1000_MDIC_PHY_SHIFT 21 826#define E1000_MDIC_OP_WRITE 0x04000000 827#define E1000_MDIC_OP_READ 0x08000000 828#define E1000_MDIC_READY 0x10000000 829#define E1000_MDIC_ERROR 0x40000000 830 831/* SerDes Control */ 832#define E1000_GEN_POLL_TIMEOUT 640 833 834#endif /* _E1000_DEFINES_H_ */ 835