1/* atl2.h -- atl2 driver definitions 2 * 3 * Copyright(c) 2007 Atheros Corporation. All rights reserved. 4 * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com> 5 * Copyright(c) 2007 Chris Snook <csnook@redhat.com> 6 * 7 * Derived from Intel e1000 driver 8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the Free 12 * Software Foundation; either version 2 of the License, or (at your option) 13 * any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along with 21 * this program; if not, write to the Free Software Foundation, Inc., 59 22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 23 */ 24 25#ifndef _ATL2_H_ 26#define _ATL2_H_ 27 28#include <asm/atomic.h> 29#include <linux/netdevice.h> 30 31#ifndef _ATL2_HW_H_ 32#define _ATL2_HW_H_ 33 34#ifndef _ATL2_OSDEP_H_ 35#define _ATL2_OSDEP_H_ 36 37#include <linux/pci.h> 38#include <linux/delay.h> 39#include <linux/interrupt.h> 40#include <linux/if_ether.h> 41 42#include "atlx.h" 43 44#ifdef ETHTOOL_OPS_COMPAT 45extern int ethtool_ioctl(struct ifreq *ifr); 46#endif 47 48#define PCI_COMMAND_REGISTER PCI_COMMAND 49#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE 50#define ETH_ADDR_LEN ETH_ALEN 51 52#define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \ 53 ((a)->hw_addr + (reg)))) 54 55#define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr)) 56 57#define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg))) 58 59#define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \ 60 ((a)->hw_addr + (reg)))) 61 62#define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg))) 63 64#define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \ 65 ((a)->hw_addr + (reg)))) 66 67#define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg))) 68 69#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \ 70 (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2)))) 71 72#define ATL2_READ_REG_ARRAY(a, reg, offset) \ 73 (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2))) 74 75#endif /* _ATL2_OSDEP_H_ */ 76 77struct atl2_adapter; 78struct atl2_hw; 79 80/* function prototype */ 81static s32 atl2_reset_hw(struct atl2_hw *hw); 82static s32 atl2_read_mac_addr(struct atl2_hw *hw); 83static s32 atl2_init_hw(struct atl2_hw *hw); 84static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 85 u16 *duplex); 86static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr); 87static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value); 88static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data); 89static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data); 90static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); 91static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); 92static void atl2_set_mac_addr(struct atl2_hw *hw); 93static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue); 94static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value); 95static s32 atl2_phy_init(struct atl2_hw *hw); 96static int atl2_check_eeprom_exist(struct atl2_hw *hw); 97static void atl2_force_ps(struct atl2_hw *hw); 98 99/* register definition */ 100 101/* Block IDLE Status Register */ 102#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC is non-IDLE */ 103#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC is non-IDLE */ 104#define IDLE_STATUS_DMAR 8 /* 1: DMAR is non-IDLE */ 105#define IDLE_STATUS_DMAW 4 /* 1: DMAW is non-IDLE */ 106 107/* MDIO Control Register */ 108#define MDIO_WAIT_TIMES 10 109 110/* MAC Control Register */ 111#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: TX max backoff */ 112#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: 25MHz from phy */ 113#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28 114#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* MAC retry buf x32B */ 115 116/* Internal SRAM Partition Register */ 117#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM 118 * default: 2byte*1024 */ 119#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM 120 * default: 2byte*1024 */ 121 122/* Descriptor Control register */ 123#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit 124 * Data Mem low 32-bit(dword align) */ 125#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by 126 * double word , max 256KB) */ 127#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit 128 * Status Memory low 32-bit(dword word 129 * align) */ 130#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047 131 * bytes. */ 132#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit 133 * Status Memory low 32-bit(unit 8 134 * bytes) */ 135#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer 136 * number (unit 1536bytes, max 137 * 1536*2047) */ 138 139/* DMAR Control Register */ 140#define REG_DMAR 0x1580 141#define DMAR_EN 0x1 /* 1: Enable DMAR */ 142 143/* TX Cur-Through (early tx threshold) Control Register */ 144#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet 145 * threshold(unit word) */ 146 147/* DMAW Control Register */ 148#define REG_DMAW 0x15A0 149#define DMAW_EN 0x1 150 151/* Flow control register */ 152#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow 153 * threshold configuration register */ 154#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow 155 * threshold configuration register */ 156 157/* Mailbox Register */ 158#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */ 159#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */ 160 161/* Interrupt Status Register */ 162#define ISR_TIMER 1 /* Interrupt when Timer counts down to zero */ 163#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set 164 * when SW_MAN_INT_EN is set in Table 51 165 * Selene Master Control Register 166 * (Offset 0x1400). */ 167#define ISR_RXF_OV 4 /* RXF overflow interrupt */ 168#define ISR_TXF_UR 8 /* TXF underrun interrupt */ 169#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full 170 * interrupt */ 171#define ISR_RXS_OV 0x20 /* Internal receive status buffer full 172 * interrupt */ 173#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */ 174#define ISR_HOST_TXD_UR 0x80 175#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */ 176#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should 177 * do Reset */ 178#define ISR_DMAW_TO_RST 0x400 179#define ISR_PHY 0x800 /* phy interrupt */ 180#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written 181 * to host */ 182#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written 183 * to host. */ 184#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one 185 * packet */ 186 187#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\ 188 ISR_TS_UPDATE | ISR_TX_EARLY) 189#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\ 190 ISR_RS_UPDATE) 191 192#define IMR_NORMAL_MASK (\ 193 /*ISR_LINK_CHG |*/\ 194 ISR_MANUAL |\ 195 ISR_DMAR_TO_RST |\ 196 ISR_DMAW_TO_RST |\ 197 ISR_PHY |\ 198 ISR_PHY_LINKDOWN |\ 199 ISR_TS_UPDATE |\ 200 ISR_RS_UPDATE) 201 202/* Receive MAC Statistics Registers */ 203#define REG_STS_RX_PAUSE 0x1700 /* Num pause packets received */ 204#define REG_STS_RXD_OV 0x1704 /* Num frames dropped due to RX 205 * FIFO overflow */ 206#define REG_STS_RXS_OV 0x1708 /* Num frames dropped due to RX 207 * Status Buffer Overflow */ 208#define REG_STS_RX_FILTER 0x170C /* Num packets dropped due to 209 * address filtering */ 210 211/* MII definitions */ 212 213/* PHY Common Register */ 214#define MII_SMARTSPEED 0x14 215#define MII_DBG_ADDR 0x1D 216#define MII_DBG_DATA 0x1E 217 218/* PCI Command Register Bit Definitions */ 219#define PCI_REG_COMMAND 0x04 220#define CMD_IO_SPACE 0x0001 221#define CMD_MEMORY_SPACE 0x0002 222#define CMD_BUS_MASTER 0x0004 223 224#define MEDIA_TYPE_100M_FULL 1 225#define MEDIA_TYPE_100M_HALF 2 226#define MEDIA_TYPE_10M_FULL 3 227#define MEDIA_TYPE_10M_HALF 4 228 229#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */ 230 231/* The size (in bytes) of a ethernet packet */ 232#define ENET_HEADER_SIZE 14 233#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */ 234#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */ 235#define ETHERNET_FCS_SIZE 4 236#define MAX_JUMBO_FRAME_SIZE 0x2000 237#define VLAN_SIZE 4 238 239struct tx_pkt_header { 240 unsigned pkt_size:11; 241 unsigned:4; /* reserved */ 242 unsigned ins_vlan:1; /* txmac should insert vlan */ 243 unsigned short vlan; /* vlan tag */ 244}; 245#define TX_PKT_HEADER_SIZE_MASK 0x7FF 246#define TX_PKT_HEADER_SIZE_SHIFT 0 247#define TX_PKT_HEADER_INS_VLAN_MASK 0x1 248#define TX_PKT_HEADER_INS_VLAN_SHIFT 15 249#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF 250#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16 251 252struct tx_pkt_status { 253 unsigned pkt_size:11; 254 unsigned:5; /* reserved */ 255 unsigned ok:1; /* current packet transmitted without error */ 256 unsigned bcast:1; /* broadcast packet */ 257 unsigned mcast:1; /* multicast packet */ 258 unsigned pause:1; /* transmiited a pause frame */ 259 unsigned ctrl:1; 260 unsigned defer:1; /* current packet is xmitted with defer */ 261 unsigned exc_defer:1; 262 unsigned single_col:1; 263 unsigned multi_col:1; 264 unsigned late_col:1; 265 unsigned abort_col:1; 266 unsigned underun:1; /* current packet is aborted 267 * due to txram underrun */ 268 unsigned:3; /* reserved */ 269 unsigned update:1; /* always 1'b1 in tx_status_buf */ 270}; 271#define TX_PKT_STATUS_SIZE_MASK 0x7FF 272#define TX_PKT_STATUS_SIZE_SHIFT 0 273#define TX_PKT_STATUS_OK_MASK 0x1 274#define TX_PKT_STATUS_OK_SHIFT 16 275#define TX_PKT_STATUS_BCAST_MASK 0x1 276#define TX_PKT_STATUS_BCAST_SHIFT 17 277#define TX_PKT_STATUS_MCAST_MASK 0x1 278#define TX_PKT_STATUS_MCAST_SHIFT 18 279#define TX_PKT_STATUS_PAUSE_MASK 0x1 280#define TX_PKT_STATUS_PAUSE_SHIFT 19 281#define TX_PKT_STATUS_CTRL_MASK 0x1 282#define TX_PKT_STATUS_CTRL_SHIFT 20 283#define TX_PKT_STATUS_DEFER_MASK 0x1 284#define TX_PKT_STATUS_DEFER_SHIFT 21 285#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1 286#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22 287#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1 288#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23 289#define TX_PKT_STATUS_MULTI_COL_MASK 0x1 290#define TX_PKT_STATUS_MULTI_COL_SHIFT 24 291#define TX_PKT_STATUS_LATE_COL_MASK 0x1 292#define TX_PKT_STATUS_LATE_COL_SHIFT 25 293#define TX_PKT_STATUS_ABORT_COL_MASK 0x1 294#define TX_PKT_STATUS_ABORT_COL_SHIFT 26 295#define TX_PKT_STATUS_UNDERRUN_MASK 0x1 296#define TX_PKT_STATUS_UNDERRUN_SHIFT 27 297#define TX_PKT_STATUS_UPDATE_MASK 0x1 298#define TX_PKT_STATUS_UPDATE_SHIFT 31 299 300struct rx_pkt_status { 301 unsigned pkt_size:11; /* packet size, max 2047 bytes */ 302 unsigned:5; /* reserved */ 303 unsigned ok:1; /* current packet received ok without error */ 304 unsigned bcast:1; /* current packet is broadcast */ 305 unsigned mcast:1; /* current packet is multicast */ 306 unsigned pause:1; 307 unsigned ctrl:1; 308 unsigned crc:1; /* received a packet with crc error */ 309 unsigned code:1; /* received a packet with code error */ 310 unsigned runt:1; /* received a packet less than 64 bytes 311 * with good crc */ 312 unsigned frag:1; /* received a packet less than 64 bytes 313 * with bad crc */ 314 unsigned trunc:1; /* current frame truncated due to rxram full */ 315 unsigned align:1; /* this packet is alignment error */ 316 unsigned vlan:1; /* this packet has vlan */ 317 unsigned:3; /* reserved */ 318 unsigned update:1; 319 unsigned short vtag; /* vlan tag */ 320 unsigned:16; 321}; 322#define RX_PKT_STATUS_SIZE_MASK 0x7FF 323#define RX_PKT_STATUS_SIZE_SHIFT 0 324#define RX_PKT_STATUS_OK_MASK 0x1 325#define RX_PKT_STATUS_OK_SHIFT 16 326#define RX_PKT_STATUS_BCAST_MASK 0x1 327#define RX_PKT_STATUS_BCAST_SHIFT 17 328#define RX_PKT_STATUS_MCAST_MASK 0x1 329#define RX_PKT_STATUS_MCAST_SHIFT 18 330#define RX_PKT_STATUS_PAUSE_MASK 0x1 331#define RX_PKT_STATUS_PAUSE_SHIFT 19 332#define RX_PKT_STATUS_CTRL_MASK 0x1 333#define RX_PKT_STATUS_CTRL_SHIFT 20 334#define RX_PKT_STATUS_CRC_MASK 0x1 335#define RX_PKT_STATUS_CRC_SHIFT 21 336#define RX_PKT_STATUS_CODE_MASK 0x1 337#define RX_PKT_STATUS_CODE_SHIFT 22 338#define RX_PKT_STATUS_RUNT_MASK 0x1 339#define RX_PKT_STATUS_RUNT_SHIFT 23 340#define RX_PKT_STATUS_FRAG_MASK 0x1 341#define RX_PKT_STATUS_FRAG_SHIFT 24 342#define RX_PKT_STATUS_TRUNK_MASK 0x1 343#define RX_PKT_STATUS_TRUNK_SHIFT 25 344#define RX_PKT_STATUS_ALIGN_MASK 0x1 345#define RX_PKT_STATUS_ALIGN_SHIFT 26 346#define RX_PKT_STATUS_VLAN_MASK 0x1 347#define RX_PKT_STATUS_VLAN_SHIFT 27 348#define RX_PKT_STATUS_UPDATE_MASK 0x1 349#define RX_PKT_STATUS_UPDATE_SHIFT 31 350#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF 351#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32 352 353struct rx_desc { 354 struct rx_pkt_status status; 355 unsigned char packet[1536-sizeof(struct rx_pkt_status)]; 356}; 357 358enum atl2_speed_duplex { 359 atl2_10_half = 0, 360 atl2_10_full = 1, 361 atl2_100_half = 2, 362 atl2_100_full = 3 363}; 364 365struct atl2_spi_flash_dev { 366 const char *manu_name; /* manufacturer id */ 367 /* op-code */ 368 u8 cmdWRSR; 369 u8 cmdREAD; 370 u8 cmdPROGRAM; 371 u8 cmdWREN; 372 u8 cmdWRDI; 373 u8 cmdRDSR; 374 u8 cmdRDID; 375 u8 cmdSECTOR_ERASE; 376 u8 cmdCHIP_ERASE; 377}; 378 379/* Structure containing variables used by the shared code (atl2_hw.c) */ 380struct atl2_hw { 381 u8 __iomem *hw_addr; 382 void *back; 383 384 u8 preamble_len; 385 u8 max_retry; /* Retransmission maximum, afterwards the 386 * packet will be discarded. */ 387 u8 jam_ipg; /* IPG to start JAM for collision based flow 388 * control in half-duplex mode. In unit of 389 * 8-bit time. */ 390 u8 ipgt; /* Desired back to back inter-packet gap. The 391 * default is 96-bit time. */ 392 u8 min_ifg; /* Minimum number of IFG to enforce in between 393 * RX frames. Frame gap below such IFP is 394 * dropped. */ 395 u8 ipgr1; /* 64bit Carrier-Sense window */ 396 u8 ipgr2; /* 96-bit IPG window */ 397 u8 retry_buf; /* When half-duplex mode, should hold some 398 * bytes for mac retry . (8*4bytes unit) */ 399 400 u16 fc_rxd_hi; 401 u16 fc_rxd_lo; 402 u16 lcol; /* Collision Window */ 403 u16 max_frame_size; 404 405 u16 MediaType; 406 u16 autoneg_advertised; 407 u16 pci_cmd_word; 408 409 u16 mii_autoneg_adv_reg; 410 411 u32 mem_rang; 412 u32 txcw; 413 u32 mc_filter_type; 414 u32 num_mc_addrs; 415 u32 collision_delta; 416 u32 tx_packet_delta; 417 u16 phy_spd_default; 418 419 u16 device_id; 420 u16 vendor_id; 421 u16 subsystem_id; 422 u16 subsystem_vendor_id; 423 u8 revision_id; 424 425 /* spi flash */ 426 u8 flash_vendor; 427 428 u8 dma_fairness; 429 u8 mac_addr[NODE_ADDRESS_SIZE]; 430 u8 perm_mac_addr[NODE_ADDRESS_SIZE]; 431 432 /* bool phy_preamble_sup; */ 433 bool phy_configured; 434}; 435 436#endif /* _ATL2_HW_H_ */ 437 438struct atl2_ring_header { 439 /* pointer to the descriptor ring memory */ 440 void *desc; 441 /* physical address of the descriptor ring */ 442 dma_addr_t dma; 443 /* length of descriptor ring in bytes */ 444 unsigned int size; 445}; 446 447/* board specific private data structure */ 448struct atl2_adapter { 449 /* OS defined structs */ 450 struct net_device *netdev; 451 struct pci_dev *pdev; 452#ifdef NETIF_F_HW_VLAN_TX 453 struct vlan_group *vlgrp; 454#endif 455 u32 wol; 456 u16 link_speed; 457 u16 link_duplex; 458 459 spinlock_t stats_lock; 460 461 struct work_struct reset_task; 462 struct work_struct link_chg_task; 463 struct timer_list watchdog_timer; 464 struct timer_list phy_config_timer; 465 466 unsigned long cfg_phy; 467 bool mac_disabled; 468 469 /* All Descriptor memory */ 470 dma_addr_t ring_dma; 471 void *ring_vir_addr; 472 int ring_size; 473 474 struct tx_pkt_header *txd_ring; 475 dma_addr_t txd_dma; 476 477 struct tx_pkt_status *txs_ring; 478 dma_addr_t txs_dma; 479 480 struct rx_desc *rxd_ring; 481 dma_addr_t rxd_dma; 482 483 u32 txd_ring_size; /* bytes per unit */ 484 u32 txs_ring_size; /* dwords per unit */ 485 u32 rxd_ring_size; /* 1536 bytes per unit */ 486 487 /* read /write ptr: */ 488 /* host */ 489 u32 txd_write_ptr; 490 u32 txs_next_clear; 491 u32 rxd_read_ptr; 492 493 /* nic */ 494 atomic_t txd_read_ptr; 495 atomic_t txs_write_ptr; 496 u32 rxd_write_ptr; 497 498 /* Interrupt Moderator timer ( 2us resolution) */ 499 u16 imt; 500 /* Interrupt Clear timer (2us resolution) */ 501 u16 ict; 502 503 unsigned long flags; 504 /* structs defined in atl2_hw.h */ 505 u32 bd_number; /* board number */ 506 bool pci_using_64; 507 bool have_msi; 508 struct atl2_hw hw; 509 510 u32 usr_cmd; 511 /* u32 regs_buff[ATL2_REGS_LEN]; */ 512 u32 pci_state[16]; 513 514 u32 *config_space; 515}; 516 517enum atl2_state_t { 518 __ATL2_TESTING, 519 __ATL2_RESETTING, 520 __ATL2_DOWN 521}; 522 523#endif /* _ATL2_H_ */ 524