1/* 2 3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. 4 5 Maintained by Jeff Garzik <jgarzik@pobox.com> 6 Copyright 2000-2002 Jeff Garzik 7 8 Much code comes from Donald Becker's rtl8139.c driver, 9 versions 1.13 and older. This driver was originally based 10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: 11 12 -----<snip>----- 13 14 Written 1997-2001 by Donald Becker. 15 This software may be used and distributed according to the 16 terms of the GNU General Public License (GPL), incorporated 17 herein by reference. Drivers based on or derived from this 18 code fall under the GPL and must retain the authorship, 19 copyright and license notice. This file is not a complete 20 program and may only be used when the entire operating 21 system is licensed under the GPL. 22 23 This driver is for boards based on the RTL8129 and RTL8139 24 PCI ethernet chips. 25 26 The author may be reached as becker@scyld.com, or C/O Scyld 27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis 28 MD 21403 29 30 Support and updates available at 31 http://www.scyld.com/network/rtl8139.html 32 33 Twister-tuning table provided by Kinston 34 <shangh@realtek.com.tw>. 35 36 -----<snip>----- 37 38 This software may be used and distributed according to the terms 39 of the GNU General Public License, incorporated herein by reference. 40 41 Contributors: 42 43 Donald Becker - he wrote the original driver, kudos to him! 44 (but please don't e-mail him for support, this isn't his driver) 45 46 Tigran Aivazian - bug fixes, skbuff free cleanup 47 48 Martin Mares - suggestions for PCI cleanup 49 50 David S. Miller - PCI DMA and softnet updates 51 52 Ernst Gill - fixes ported from BSD driver 53 54 Daniel Kobras - identified specific locations of 55 posted MMIO write bugginess 56 57 Gerard Sharp - bug fix, testing and feedback 58 59 David Ford - Rx ring wrap fix 60 61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me 62 to find and fix a crucial bug on older chipsets. 63 64 Donald Becker/Chris Butterworth/Marcus Westergren - 65 Noticed various Rx packet size-related buglets. 66 67 Santiago Garcia Mantinan - testing and feedback 68 69 Jens David - 2.2.x kernel backports 70 71 Martin Dennett - incredibly helpful insight on undocumented 72 features of the 8139 chips 73 74 Jean-Jacques Michel - bug fix 75 76 Tobias Ringstr��m - Rx interrupt status checking suggestion 77 78 Andrew Morton - Clear blocked signals, avoid 79 buffer overrun setting current->comm. 80 81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls 82 83 Robert Kuebel - Save kernel thread from dying on any signal. 84 85 Submitting bug reports: 86 87 "rtl8139-diag -mmmaaavvveefN" output 88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log 89 90*/ 91 92#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 93 94#define DRV_NAME "8139too" 95#define DRV_VERSION "0.9.28" 96 97 98#include <linux/module.h> 99#include <linux/kernel.h> 100#include <linux/compiler.h> 101#include <linux/pci.h> 102#include <linux/init.h> 103#include <linux/netdevice.h> 104#include <linux/etherdevice.h> 105#include <linux/rtnetlink.h> 106#include <linux/delay.h> 107#include <linux/ethtool.h> 108#include <linux/mii.h> 109#include <linux/completion.h> 110#include <linux/crc32.h> 111#include <linux/io.h> 112#include <linux/uaccess.h> 113#include <linux/gfp.h> 114#include <asm/irq.h> 115 116#define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION 117 118/* Default Message level */ 119#define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 120 NETIF_MSG_PROBE | \ 121 NETIF_MSG_LINK) 122 123 124/* define to 1, 2 or 3 to enable copious debugging info */ 125#define RTL8139_DEBUG 0 126 127/* define to 1 to disable lightweight runtime debugging checks */ 128#undef RTL8139_NDEBUG 129 130 131#ifdef RTL8139_NDEBUG 132# define assert(expr) do {} while (0) 133#else 134# define assert(expr) \ 135 if (unlikely(!(expr))) { \ 136 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ 137 #expr, __FILE__, __func__, __LINE__); \ 138 } 139#endif 140 141 142/* A few user-configurable values. */ 143/* media options */ 144#define MAX_UNITS 8 145static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 146static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 147 148/* Whether to use MMIO or PIO. Default to MMIO. */ 149#ifdef CONFIG_8139TOO_PIO 150static int use_io = 1; 151#else 152static int use_io = 0; 153#endif 154 155/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 156 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 157static int multicast_filter_limit = 32; 158 159/* bitmapped message enable number */ 160static int debug = -1; 161 162/* 163 * Receive ring size 164 * Warning: 64K ring has hardware issues and may lock up. 165 */ 166#if defined(CONFIG_SH_DREAMCAST) 167#define RX_BUF_IDX 0 /* 8K ring */ 168#else 169#define RX_BUF_IDX 2 /* 32K ring */ 170#endif 171#define RX_BUF_LEN (8192 << RX_BUF_IDX) 172#define RX_BUF_PAD 16 173#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ 174 175#if RX_BUF_LEN == 65536 176#define RX_BUF_TOT_LEN RX_BUF_LEN 177#else 178#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) 179#endif 180 181/* Number of Tx descriptor registers. */ 182#define NUM_TX_DESC 4 183 184/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/ 185#define MAX_ETH_FRAME_SIZE 1536 186 187/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */ 188#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE 189#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) 190 191/* PCI Tuning Parameters 192 Threshold is bytes transferred to chip before transmission starts. */ 193#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 194 195/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 196#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ 197#define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ 198#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 199#define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ 200 201/* Operational parameters that usually are not changed. */ 202/* Time in jiffies before concluding the transmitter is hung. */ 203#define TX_TIMEOUT (6*HZ) 204 205 206enum { 207 HAS_MII_XCVR = 0x010000, 208 HAS_CHIP_XCVR = 0x020000, 209 HAS_LNK_CHNG = 0x040000, 210}; 211 212#define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ 213#define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ 214#define RTL_MIN_IO_SIZE 0x80 215#define RTL8139B_IO_SIZE 256 216 217#define RTL8129_CAPS HAS_MII_XCVR 218#define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG) 219 220typedef enum { 221 RTL8139 = 0, 222 RTL8129, 223} board_t; 224 225 226/* indexed by board_t, above */ 227static const struct { 228 const char *name; 229 u32 hw_flags; 230} board_info[] __devinitdata = { 231 { "RealTek RTL8139", RTL8139_CAPS }, 232 { "RealTek RTL8129", RTL8129_CAPS }, 233}; 234 235 236static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = { 237 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 238 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 239 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 240 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 241 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 242 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 243 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 244 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 245 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 246 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 247 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 248 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 249 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 250 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 251 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 252 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 253 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 254 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 255 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 256 257#ifdef CONFIG_SH_SECUREEDGE5410 258 /* Bogus 8139 silicon reports 8129 without external PROM :-( */ 259 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 260#endif 261#ifdef CONFIG_8139TOO_8129 262 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, 263#endif 264 265 /* some crazy cards report invalid vendor ids like 266 * 0x0001 here. The other ids are valid and constant, 267 * so we simply don't match on the main vendor id. 268 */ 269 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, 270 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 }, 271 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 }, 272 273 {0,} 274}; 275MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); 276 277static struct { 278 const char str[ETH_GSTRING_LEN]; 279} ethtool_stats_keys[] = { 280 { "early_rx" }, 281 { "tx_buf_mapped" }, 282 { "tx_timeouts" }, 283 { "rx_lost_in_ring" }, 284}; 285 286/* The rest of these values should never change. */ 287 288/* Symbolic offsets to registers. */ 289enum RTL8139_registers { 290 MAC0 = 0, /* Ethernet hardware address. */ 291 MAR0 = 8, /* Multicast filter. */ 292 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ 293 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 294 RxBuf = 0x30, 295 ChipCmd = 0x37, 296 RxBufPtr = 0x38, 297 RxBufAddr = 0x3A, 298 IntrMask = 0x3C, 299 IntrStatus = 0x3E, 300 TxConfig = 0x40, 301 RxConfig = 0x44, 302 Timer = 0x48, /* A general-purpose counter. */ 303 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 304 Cfg9346 = 0x50, 305 Config0 = 0x51, 306 Config1 = 0x52, 307 TimerInt = 0x54, 308 MediaStatus = 0x58, 309 Config3 = 0x59, 310 Config4 = 0x5A, /* absent on RTL-8139A */ 311 HltClk = 0x5B, 312 MultiIntr = 0x5C, 313 TxSummary = 0x60, 314 BasicModeCtrl = 0x62, 315 BasicModeStatus = 0x64, 316 NWayAdvert = 0x66, 317 NWayLPAR = 0x68, 318 NWayExpansion = 0x6A, 319 /* Undocumented registers, but required for proper operation. */ 320 FIFOTMS = 0x70, /* FIFO Control and test. */ 321 CSCR = 0x74, /* Chip Status and Configuration Register. */ 322 PARA78 = 0x78, 323 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */ 324 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 325 Config5 = 0xD8, /* absent on RTL-8139A */ 326}; 327 328enum ClearBitMasks { 329 MultiIntrClear = 0xF000, 330 ChipCmdClear = 0xE2, 331 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 332}; 333 334enum ChipCmdBits { 335 CmdReset = 0x10, 336 CmdRxEnb = 0x08, 337 CmdTxEnb = 0x04, 338 RxBufEmpty = 0x01, 339}; 340 341/* Interrupt register bits, using my own meaningful names. */ 342enum IntrStatusBits { 343 PCIErr = 0x8000, 344 PCSTimeout = 0x4000, 345 RxFIFOOver = 0x40, 346 RxUnderrun = 0x20, 347 RxOverflow = 0x10, 348 TxErr = 0x08, 349 TxOK = 0x04, 350 RxErr = 0x02, 351 RxOK = 0x01, 352 353 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 354}; 355 356enum TxStatusBits { 357 TxHostOwns = 0x2000, 358 TxUnderrun = 0x4000, 359 TxStatOK = 0x8000, 360 TxOutOfWindow = 0x20000000, 361 TxAborted = 0x40000000, 362 TxCarrierLost = 0x80000000, 363}; 364enum RxStatusBits { 365 RxMulticast = 0x8000, 366 RxPhysical = 0x4000, 367 RxBroadcast = 0x2000, 368 RxBadSymbol = 0x0020, 369 RxRunt = 0x0010, 370 RxTooLong = 0x0008, 371 RxCRCErr = 0x0004, 372 RxBadAlign = 0x0002, 373 RxStatusOK = 0x0001, 374}; 375 376/* Bits in RxConfig. */ 377enum rx_mode_bits { 378 AcceptErr = 0x20, 379 AcceptRunt = 0x10, 380 AcceptBroadcast = 0x08, 381 AcceptMulticast = 0x04, 382 AcceptMyPhys = 0x02, 383 AcceptAllPhys = 0x01, 384}; 385 386/* Bits in TxConfig. */ 387enum tx_config_bits { 388 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 389 TxIFGShift = 24, 390 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 391 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 392 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 393 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 394 395 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 396 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */ 397 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 398 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */ 399 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */ 400 401 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 402}; 403 404/* Bits in Config1 */ 405enum Config1Bits { 406 Cfg1_PM_Enable = 0x01, 407 Cfg1_VPD_Enable = 0x02, 408 Cfg1_PIO = 0x04, 409 Cfg1_MMIO = 0x08, 410 LWAKE = 0x10, /* not on 8139, 8139A */ 411 Cfg1_Driver_Load = 0x20, 412 Cfg1_LED0 = 0x40, 413 Cfg1_LED1 = 0x80, 414 SLEEP = (1 << 1), /* only on 8139, 8139A */ 415 PWRDN = (1 << 0), /* only on 8139, 8139A */ 416}; 417 418/* Bits in Config3 */ 419enum Config3Bits { 420 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 421 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 422 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 423 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 424 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 425 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 426 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 427 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 428}; 429 430/* Bits in Config4 */ 431enum Config4Bits { 432 LWPTN = (1 << 2), /* not on 8139, 8139A */ 433}; 434 435/* Bits in Config5 */ 436enum Config5Bits { 437 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 438 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 439 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 440 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */ 441 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 442 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 443 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 444}; 445 446enum RxConfigBits { 447 /* rx fifo threshold */ 448 RxCfgFIFOShift = 13, 449 RxCfgFIFONone = (7 << RxCfgFIFOShift), 450 451 /* Max DMA burst */ 452 RxCfgDMAShift = 8, 453 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 454 455 /* rx ring buffer length */ 456 RxCfgRcv8K = 0, 457 RxCfgRcv16K = (1 << 11), 458 RxCfgRcv32K = (1 << 12), 459 RxCfgRcv64K = (1 << 11) | (1 << 12), 460 461 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 462 RxNoWrap = (1 << 7), 463}; 464 465/* Twister tuning parameters from RealTek. 466 Completely undocumented, but required to tune bad links on some boards. */ 467enum CSCRBits { 468 CSCR_LinkOKBit = 0x0400, 469 CSCR_LinkChangeBit = 0x0800, 470 CSCR_LinkStatusBits = 0x0f000, 471 CSCR_LinkDownOffCmd = 0x003c0, 472 CSCR_LinkDownCmd = 0x0f3c0, 473}; 474 475enum Cfg9346Bits { 476 Cfg9346_Lock = 0x00, 477 Cfg9346_Unlock = 0xC0, 478}; 479 480typedef enum { 481 CH_8139 = 0, 482 CH_8139_K, 483 CH_8139A, 484 CH_8139A_G, 485 CH_8139B, 486 CH_8130, 487 CH_8139C, 488 CH_8100, 489 CH_8100B_8139D, 490 CH_8101, 491} chip_t; 492 493enum chip_flags { 494 HasHltClk = (1 << 0), 495 HasLWake = (1 << 1), 496}; 497 498#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 499 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 500#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 501 502/* directly indexed by chip_t, above */ 503static const struct { 504 const char *name; 505 u32 version; /* from RTL8139C/RTL8139D docs */ 506 u32 flags; 507} rtl_chip_info[] = { 508 { "RTL-8139", 509 HW_REVID(1, 0, 0, 0, 0, 0, 0), 510 HasHltClk, 511 }, 512 513 { "RTL-8139 rev K", 514 HW_REVID(1, 1, 0, 0, 0, 0, 0), 515 HasHltClk, 516 }, 517 518 { "RTL-8139A", 519 HW_REVID(1, 1, 1, 0, 0, 0, 0), 520 HasHltClk, 521 }, 522 523 { "RTL-8139A rev G", 524 HW_REVID(1, 1, 1, 0, 0, 1, 0), 525 HasHltClk, 526 }, 527 528 { "RTL-8139B", 529 HW_REVID(1, 1, 1, 1, 0, 0, 0), 530 HasLWake, 531 }, 532 533 { "RTL-8130", 534 HW_REVID(1, 1, 1, 1, 1, 0, 0), 535 HasLWake, 536 }, 537 538 { "RTL-8139C", 539 HW_REVID(1, 1, 1, 0, 1, 0, 0), 540 HasLWake, 541 }, 542 543 { "RTL-8100", 544 HW_REVID(1, 1, 1, 1, 0, 1, 0), 545 HasLWake, 546 }, 547 548 { "RTL-8100B/8139D", 549 HW_REVID(1, 1, 1, 0, 1, 0, 1), 550 HasHltClk 551 | HasLWake, 552 }, 553 554 { "RTL-8101", 555 HW_REVID(1, 1, 1, 0, 1, 1, 1), 556 HasLWake, 557 }, 558}; 559 560struct rtl_extra_stats { 561 unsigned long early_rx; 562 unsigned long tx_buf_mapped; 563 unsigned long tx_timeouts; 564 unsigned long rx_lost_in_ring; 565}; 566 567struct rtl8139_private { 568 void __iomem *mmio_addr; 569 int drv_flags; 570 struct pci_dev *pci_dev; 571 u32 msg_enable; 572 struct napi_struct napi; 573 struct net_device *dev; 574 575 unsigned char *rx_ring; 576 unsigned int cur_rx; /* RX buf index of next pkt */ 577 dma_addr_t rx_ring_dma; 578 579 unsigned int tx_flag; 580 unsigned long cur_tx; 581 unsigned long dirty_tx; 582 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */ 583 unsigned char *tx_bufs; /* Tx bounce buffer region. */ 584 dma_addr_t tx_bufs_dma; 585 586 signed char phys[4]; /* MII device addresses. */ 587 588 /* Twister tune state. */ 589 char twistie, twist_row, twist_col; 590 591 unsigned int watchdog_fired : 1; 592 unsigned int default_port : 4; /* Last dev->if_port value. */ 593 unsigned int have_thread : 1; 594 595 spinlock_t lock; 596 spinlock_t rx_lock; 597 598 chip_t chipset; 599 u32 rx_config; 600 struct rtl_extra_stats xstats; 601 602 struct delayed_work thread; 603 604 struct mii_if_info mii; 605 unsigned int regs_len; 606 unsigned long fifo_copy_timeout; 607}; 608 609MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>"); 610MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver"); 611MODULE_LICENSE("GPL"); 612MODULE_VERSION(DRV_VERSION); 613 614module_param(use_io, int, 0); 615MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO"); 616module_param(multicast_filter_limit, int, 0); 617module_param_array(media, int, NULL, 0); 618module_param_array(full_duplex, int, NULL, 0); 619module_param(debug, int, 0); 620MODULE_PARM_DESC (debug, "8139too bitmapped message enable number"); 621MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses"); 622MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); 623MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); 624 625static int read_eeprom (void __iomem *ioaddr, int location, int addr_len); 626static int rtl8139_open (struct net_device *dev); 627static int mdio_read (struct net_device *dev, int phy_id, int location); 628static void mdio_write (struct net_device *dev, int phy_id, int location, 629 int val); 630static void rtl8139_start_thread(struct rtl8139_private *tp); 631static void rtl8139_tx_timeout (struct net_device *dev); 632static void rtl8139_init_ring (struct net_device *dev); 633static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 634 struct net_device *dev); 635#ifdef CONFIG_NET_POLL_CONTROLLER 636static void rtl8139_poll_controller(struct net_device *dev); 637#endif 638static int rtl8139_set_mac_address(struct net_device *dev, void *p); 639static int rtl8139_poll(struct napi_struct *napi, int budget); 640static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance); 641static int rtl8139_close (struct net_device *dev); 642static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 643static struct net_device_stats *rtl8139_get_stats (struct net_device *dev); 644static void rtl8139_set_rx_mode (struct net_device *dev); 645static void __set_rx_mode (struct net_device *dev); 646static void rtl8139_hw_start (struct net_device *dev); 647static void rtl8139_thread (struct work_struct *work); 648static void rtl8139_tx_timeout_task(struct work_struct *work); 649static const struct ethtool_ops rtl8139_ethtool_ops; 650 651/* write MMIO register, with flush */ 652/* Flush avoids rtl8139 bug w/ posted MMIO writes */ 653#define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) 654#define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) 655#define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) 656 657/* write MMIO register */ 658#define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) 659#define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) 660#define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) 661 662/* read MMIO register */ 663#define RTL_R8(reg) ioread8 (ioaddr + (reg)) 664#define RTL_R16(reg) ioread16 (ioaddr + (reg)) 665#define RTL_R32(reg) ioread32 (ioaddr + (reg)) 666 667 668static const u16 rtl8139_intr_mask = 669 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | 670 TxErr | TxOK | RxErr | RxOK; 671 672static const u16 rtl8139_norx_intr_mask = 673 PCIErr | PCSTimeout | RxUnderrun | 674 TxErr | TxOK | RxErr ; 675 676#if RX_BUF_IDX == 0 677static const unsigned int rtl8139_rx_config = 678 RxCfgRcv8K | RxNoWrap | 679 (RX_FIFO_THRESH << RxCfgFIFOShift) | 680 (RX_DMA_BURST << RxCfgDMAShift); 681#elif RX_BUF_IDX == 1 682static const unsigned int rtl8139_rx_config = 683 RxCfgRcv16K | RxNoWrap | 684 (RX_FIFO_THRESH << RxCfgFIFOShift) | 685 (RX_DMA_BURST << RxCfgDMAShift); 686#elif RX_BUF_IDX == 2 687static const unsigned int rtl8139_rx_config = 688 RxCfgRcv32K | RxNoWrap | 689 (RX_FIFO_THRESH << RxCfgFIFOShift) | 690 (RX_DMA_BURST << RxCfgDMAShift); 691#elif RX_BUF_IDX == 3 692static const unsigned int rtl8139_rx_config = 693 RxCfgRcv64K | 694 (RX_FIFO_THRESH << RxCfgFIFOShift) | 695 (RX_DMA_BURST << RxCfgDMAShift); 696#else 697#error "Invalid configuration for 8139_RXBUF_IDX" 698#endif 699 700static const unsigned int rtl8139_tx_config = 701 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift); 702 703static void __rtl8139_cleanup_dev (struct net_device *dev) 704{ 705 struct rtl8139_private *tp = netdev_priv(dev); 706 struct pci_dev *pdev; 707 708 assert (dev != NULL); 709 assert (tp->pci_dev != NULL); 710 pdev = tp->pci_dev; 711 712 if (tp->mmio_addr) 713 pci_iounmap (pdev, tp->mmio_addr); 714 715 /* it's ok to call this even if we have no regions to free */ 716 pci_release_regions (pdev); 717 718 free_netdev(dev); 719 pci_set_drvdata (pdev, NULL); 720} 721 722 723static void rtl8139_chip_reset (void __iomem *ioaddr) 724{ 725 int i; 726 727 /* Soft reset the chip. */ 728 RTL_W8 (ChipCmd, CmdReset); 729 730 /* Check that the chip has finished the reset. */ 731 for (i = 1000; i > 0; i--) { 732 barrier(); 733 if ((RTL_R8 (ChipCmd) & CmdReset) == 0) 734 break; 735 udelay (10); 736 } 737} 738 739 740static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev) 741{ 742 void __iomem *ioaddr; 743 struct net_device *dev; 744 struct rtl8139_private *tp; 745 u8 tmp8; 746 int rc, disable_dev_on_err = 0; 747 unsigned int i; 748 unsigned long pio_start, pio_end, pio_flags, pio_len; 749 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len; 750 u32 version; 751 752 assert (pdev != NULL); 753 754 /* dev and priv zeroed in alloc_etherdev */ 755 dev = alloc_etherdev (sizeof (*tp)); 756 if (dev == NULL) { 757 dev_err(&pdev->dev, "Unable to alloc new net device\n"); 758 return ERR_PTR(-ENOMEM); 759 } 760 SET_NETDEV_DEV(dev, &pdev->dev); 761 762 tp = netdev_priv(dev); 763 tp->pci_dev = pdev; 764 765 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 766 rc = pci_enable_device (pdev); 767 if (rc) 768 goto err_out; 769 770 pio_start = pci_resource_start (pdev, 0); 771 pio_end = pci_resource_end (pdev, 0); 772 pio_flags = pci_resource_flags (pdev, 0); 773 pio_len = pci_resource_len (pdev, 0); 774 775 mmio_start = pci_resource_start (pdev, 1); 776 mmio_end = pci_resource_end (pdev, 1); 777 mmio_flags = pci_resource_flags (pdev, 1); 778 mmio_len = pci_resource_len (pdev, 1); 779 780 /* set this immediately, we need to know before 781 * we talk to the chip directly */ 782 pr_debug("PIO region size == 0x%02lX\n", pio_len); 783 pr_debug("MMIO region size == 0x%02lX\n", mmio_len); 784 785retry: 786 if (use_io) { 787 /* make sure PCI base addr 0 is PIO */ 788 if (!(pio_flags & IORESOURCE_IO)) { 789 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n"); 790 rc = -ENODEV; 791 goto err_out; 792 } 793 /* check for weird/broken PCI region reporting */ 794 if (pio_len < RTL_MIN_IO_SIZE) { 795 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n"); 796 rc = -ENODEV; 797 goto err_out; 798 } 799 } else { 800 /* make sure PCI base addr 1 is MMIO */ 801 if (!(mmio_flags & IORESOURCE_MEM)) { 802 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n"); 803 rc = -ENODEV; 804 goto err_out; 805 } 806 if (mmio_len < RTL_MIN_IO_SIZE) { 807 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n"); 808 rc = -ENODEV; 809 goto err_out; 810 } 811 } 812 813 rc = pci_request_regions (pdev, DRV_NAME); 814 if (rc) 815 goto err_out; 816 disable_dev_on_err = 1; 817 818 /* enable PCI bus-mastering */ 819 pci_set_master (pdev); 820 821 if (use_io) { 822 ioaddr = pci_iomap(pdev, 0, 0); 823 if (!ioaddr) { 824 dev_err(&pdev->dev, "cannot map PIO, aborting\n"); 825 rc = -EIO; 826 goto err_out; 827 } 828 dev->base_addr = pio_start; 829 tp->regs_len = pio_len; 830 } else { 831 /* ioremap MMIO region */ 832 ioaddr = pci_iomap(pdev, 1, 0); 833 if (ioaddr == NULL) { 834 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n"); 835 pci_release_regions(pdev); 836 use_io = 1; 837 goto retry; 838 } 839 dev->base_addr = (long) ioaddr; 840 tp->regs_len = mmio_len; 841 } 842 tp->mmio_addr = ioaddr; 843 844 /* Bring old chips out of low-power mode. */ 845 RTL_W8 (HltClk, 'R'); 846 847 /* check for missing/broken hardware */ 848 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { 849 dev_err(&pdev->dev, "Chip not responding, ignoring board\n"); 850 rc = -EIO; 851 goto err_out; 852 } 853 854 /* identify chip attached to board */ 855 version = RTL_R32 (TxConfig) & HW_REVID_MASK; 856 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++) 857 if (version == rtl_chip_info[i].version) { 858 tp->chipset = i; 859 goto match; 860 } 861 862 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 863 i = 0; 864 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); 865 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); 866 tp->chipset = 0; 867 868match: 869 pr_debug("chipset id (%d) == index %d, '%s'\n", 870 version, i, rtl_chip_info[i].name); 871 872 if (tp->chipset >= CH_8139B) { 873 u8 new_tmp8 = tmp8 = RTL_R8 (Config1); 874 pr_debug("PCI PM wakeup\n"); 875 if ((rtl_chip_info[tp->chipset].flags & HasLWake) && 876 (tmp8 & LWAKE)) 877 new_tmp8 &= ~LWAKE; 878 new_tmp8 |= Cfg1_PM_Enable; 879 if (new_tmp8 != tmp8) { 880 RTL_W8 (Cfg9346, Cfg9346_Unlock); 881 RTL_W8 (Config1, tmp8); 882 RTL_W8 (Cfg9346, Cfg9346_Lock); 883 } 884 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 885 tmp8 = RTL_R8 (Config4); 886 if (tmp8 & LWPTN) { 887 RTL_W8 (Cfg9346, Cfg9346_Unlock); 888 RTL_W8 (Config4, tmp8 & ~LWPTN); 889 RTL_W8 (Cfg9346, Cfg9346_Lock); 890 } 891 } 892 } else { 893 pr_debug("Old chip wakeup\n"); 894 tmp8 = RTL_R8 (Config1); 895 tmp8 &= ~(SLEEP | PWRDN); 896 RTL_W8 (Config1, tmp8); 897 } 898 899 rtl8139_chip_reset (ioaddr); 900 901 return dev; 902 903err_out: 904 __rtl8139_cleanup_dev (dev); 905 if (disable_dev_on_err) 906 pci_disable_device (pdev); 907 return ERR_PTR(rc); 908} 909 910static const struct net_device_ops rtl8139_netdev_ops = { 911 .ndo_open = rtl8139_open, 912 .ndo_stop = rtl8139_close, 913 .ndo_get_stats = rtl8139_get_stats, 914 .ndo_change_mtu = eth_change_mtu, 915 .ndo_validate_addr = eth_validate_addr, 916 .ndo_set_mac_address = rtl8139_set_mac_address, 917 .ndo_start_xmit = rtl8139_start_xmit, 918 .ndo_set_multicast_list = rtl8139_set_rx_mode, 919 .ndo_do_ioctl = netdev_ioctl, 920 .ndo_tx_timeout = rtl8139_tx_timeout, 921#ifdef CONFIG_NET_POLL_CONTROLLER 922 .ndo_poll_controller = rtl8139_poll_controller, 923#endif 924}; 925 926static int __devinit rtl8139_init_one (struct pci_dev *pdev, 927 const struct pci_device_id *ent) 928{ 929 struct net_device *dev = NULL; 930 struct rtl8139_private *tp; 931 int i, addr_len, option; 932 void __iomem *ioaddr; 933 static int board_idx = -1; 934 935 assert (pdev != NULL); 936 assert (ent != NULL); 937 938 board_idx++; 939 940 /* when we're built into the kernel, the driver version message 941 * is only printed if at least one 8139 board has been found 942 */ 943#ifndef MODULE 944 { 945 static int printed_version; 946 if (!printed_version++) 947 pr_info(RTL8139_DRIVER_NAME "\n"); 948 } 949#endif 950 951 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 952 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) { 953 dev_info(&pdev->dev, 954 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", 955 pdev->vendor, pdev->device, pdev->revision); 956 return -ENODEV; 957 } 958 959 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 960 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && 961 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS && 962 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) { 963 pr_info("OQO Model 2 detected. Forcing PIO\n"); 964 use_io = 1; 965 } 966 967 dev = rtl8139_init_board (pdev); 968 if (IS_ERR(dev)) 969 return PTR_ERR(dev); 970 971 assert (dev != NULL); 972 tp = netdev_priv(dev); 973 tp->dev = dev; 974 975 ioaddr = tp->mmio_addr; 976 assert (ioaddr != NULL); 977 978 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6; 979 for (i = 0; i < 3; i++) 980 ((__le16 *) (dev->dev_addr))[i] = 981 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len)); 982 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 983 984 /* The Rtl8139-specific entries in the device structure. */ 985 dev->netdev_ops = &rtl8139_netdev_ops; 986 dev->ethtool_ops = &rtl8139_ethtool_ops; 987 dev->watchdog_timeo = TX_TIMEOUT; 988 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64); 989 990 /* note: the hardware is not capable of sg/csum/highdma, however 991 * through the use of skb_copy_and_csum_dev we enable these 992 * features 993 */ 994 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; 995 996 dev->irq = pdev->irq; 997 998 /* tp zeroed and aligned in alloc_etherdev */ 999 tp = netdev_priv(dev); 1000 1001 /* note: tp->chipset set in rtl8139_init_board */ 1002 tp->drv_flags = board_info[ent->driver_data].hw_flags; 1003 tp->mmio_addr = ioaddr; 1004 tp->msg_enable = 1005 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1)); 1006 spin_lock_init (&tp->lock); 1007 spin_lock_init (&tp->rx_lock); 1008 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1009 tp->mii.dev = dev; 1010 tp->mii.mdio_read = mdio_read; 1011 tp->mii.mdio_write = mdio_write; 1012 tp->mii.phy_id_mask = 0x3f; 1013 tp->mii.reg_num_mask = 0x1f; 1014 1015 /* dev is fully set up and ready to use now */ 1016 pr_debug("about to register device named %s (%p)...\n", 1017 dev->name, dev); 1018 i = register_netdev (dev); 1019 if (i) goto err_out; 1020 1021 pci_set_drvdata (pdev, dev); 1022 1023 netdev_info(dev, "%s at 0x%lx, %pM, IRQ %d\n", 1024 board_info[ent->driver_data].name, 1025 dev->base_addr, dev->dev_addr, dev->irq); 1026 1027 netdev_dbg(dev, "Identified 8139 chip type '%s'\n", 1028 rtl_chip_info[tp->chipset].name); 1029 1030 /* Find the connected MII xcvrs. 1031 Doing this in open() would allow detecting external xcvrs later, but 1032 takes too much time. */ 1033#ifdef CONFIG_8139TOO_8129 1034 if (tp->drv_flags & HAS_MII_XCVR) { 1035 int phy, phy_idx = 0; 1036 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { 1037 int mii_status = mdio_read(dev, phy, 1); 1038 if (mii_status != 0xffff && mii_status != 0x0000) { 1039 u16 advertising = mdio_read(dev, phy, 4); 1040 tp->phys[phy_idx++] = phy; 1041 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n", 1042 phy, mii_status, advertising); 1043 } 1044 } 1045 if (phy_idx == 0) { 1046 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n"); 1047 tp->phys[0] = 32; 1048 } 1049 } else 1050#endif 1051 tp->phys[0] = 32; 1052 tp->mii.phy_id = tp->phys[0]; 1053 1054 /* The lower four bits are the media type. */ 1055 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 1056 if (option > 0) { 1057 tp->mii.full_duplex = (option & 0x210) ? 1 : 0; 1058 tp->default_port = option & 0xFF; 1059 if (tp->default_port) 1060 tp->mii.force_media = 1; 1061 } 1062 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0) 1063 tp->mii.full_duplex = full_duplex[board_idx]; 1064 if (tp->mii.full_duplex) { 1065 netdev_info(dev, "Media type forced to Full Duplex\n"); 1066 /* Changing the MII-advertised media because might prevent 1067 re-connection. */ 1068 tp->mii.force_media = 1; 1069 } 1070 if (tp->default_port) { 1071 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n", 1072 (option & 0x20 ? 100 : 10), 1073 (option & 0x10 ? "full" : "half")); 1074 mdio_write(dev, tp->phys[0], 0, 1075 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */ 1076 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */ 1077 } 1078 1079 /* Put the chip into low-power mode. */ 1080 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1081 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 1082 1083 return 0; 1084 1085err_out: 1086 __rtl8139_cleanup_dev (dev); 1087 pci_disable_device (pdev); 1088 return i; 1089} 1090 1091 1092static void __devexit rtl8139_remove_one (struct pci_dev *pdev) 1093{ 1094 struct net_device *dev = pci_get_drvdata (pdev); 1095 1096 assert (dev != NULL); 1097 1098 flush_scheduled_work(); 1099 1100 unregister_netdev (dev); 1101 1102 __rtl8139_cleanup_dev (dev); 1103 pci_disable_device (pdev); 1104} 1105 1106 1107/* Serial EEPROM section. */ 1108 1109/* EEPROM_Ctrl bits. */ 1110#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 1111#define EE_CS 0x08 /* EEPROM chip select. */ 1112#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 1113#define EE_WRITE_0 0x00 1114#define EE_WRITE_1 0x02 1115#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 1116#define EE_ENB (0x80 | EE_CS) 1117 1118/* Delay between EEPROM clock transitions. 1119 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1120 */ 1121 1122#define eeprom_delay() (void)RTL_R32(Cfg9346) 1123 1124/* The EEPROM commands include the alway-set leading bit. */ 1125#define EE_WRITE_CMD (5) 1126#define EE_READ_CMD (6) 1127#define EE_ERASE_CMD (7) 1128 1129static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len) 1130{ 1131 int i; 1132 unsigned retval = 0; 1133 int read_cmd = location | (EE_READ_CMD << addr_len); 1134 1135 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS); 1136 RTL_W8 (Cfg9346, EE_ENB); 1137 eeprom_delay (); 1138 1139 /* Shift the read command bits out. */ 1140 for (i = 4 + addr_len; i >= 0; i--) { 1141 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1142 RTL_W8 (Cfg9346, EE_ENB | dataval); 1143 eeprom_delay (); 1144 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK); 1145 eeprom_delay (); 1146 } 1147 RTL_W8 (Cfg9346, EE_ENB); 1148 eeprom_delay (); 1149 1150 for (i = 16; i > 0; i--) { 1151 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK); 1152 eeprom_delay (); 1153 retval = 1154 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 : 1155 0); 1156 RTL_W8 (Cfg9346, EE_ENB); 1157 eeprom_delay (); 1158 } 1159 1160 /* Terminate the EEPROM access. */ 1161 RTL_W8 (Cfg9346, ~EE_CS); 1162 eeprom_delay (); 1163 1164 return retval; 1165} 1166 1167/* MII serial management: mostly bogus for now. */ 1168/* Read and write the MII management registers using software-generated 1169 serial MDIO protocol. 1170 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 1171 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 1172 "overclocking" issues. */ 1173#define MDIO_DIR 0x80 1174#define MDIO_DATA_OUT 0x04 1175#define MDIO_DATA_IN 0x02 1176#define MDIO_CLK 0x01 1177#define MDIO_WRITE0 (MDIO_DIR) 1178#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) 1179 1180#define mdio_delay() RTL_R8(Config4) 1181 1182 1183static const char mii_2_8139_map[8] = { 1184 BasicModeCtrl, 1185 BasicModeStatus, 1186 0, 1187 0, 1188 NWayAdvert, 1189 NWayLPAR, 1190 NWayExpansion, 1191 0 1192}; 1193 1194 1195#ifdef CONFIG_8139TOO_8129 1196/* Syncronize the MII management interface by shifting 32 one bits out. */ 1197static void mdio_sync (void __iomem *ioaddr) 1198{ 1199 int i; 1200 1201 for (i = 32; i >= 0; i--) { 1202 RTL_W8 (Config4, MDIO_WRITE1); 1203 mdio_delay (); 1204 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK); 1205 mdio_delay (); 1206 } 1207} 1208#endif 1209 1210static int mdio_read (struct net_device *dev, int phy_id, int location) 1211{ 1212 struct rtl8139_private *tp = netdev_priv(dev); 1213 int retval = 0; 1214#ifdef CONFIG_8139TOO_8129 1215 void __iomem *ioaddr = tp->mmio_addr; 1216 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 1217 int i; 1218#endif 1219 1220 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1221 void __iomem *ioaddr = tp->mmio_addr; 1222 return location < 8 && mii_2_8139_map[location] ? 1223 RTL_R16 (mii_2_8139_map[location]) : 0; 1224 } 1225 1226#ifdef CONFIG_8139TOO_8129 1227 mdio_sync (ioaddr); 1228 /* Shift the read command bits out. */ 1229 for (i = 15; i >= 0; i--) { 1230 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; 1231 1232 RTL_W8 (Config4, MDIO_DIR | dataval); 1233 mdio_delay (); 1234 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK); 1235 mdio_delay (); 1236 } 1237 1238 /* Read the two transition, 16 data, and wire-idle bits. */ 1239 for (i = 19; i > 0; i--) { 1240 RTL_W8 (Config4, 0); 1241 mdio_delay (); 1242 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0); 1243 RTL_W8 (Config4, MDIO_CLK); 1244 mdio_delay (); 1245 } 1246#endif 1247 1248 return (retval >> 1) & 0xffff; 1249} 1250 1251 1252static void mdio_write (struct net_device *dev, int phy_id, int location, 1253 int value) 1254{ 1255 struct rtl8139_private *tp = netdev_priv(dev); 1256#ifdef CONFIG_8139TOO_8129 1257 void __iomem *ioaddr = tp->mmio_addr; 1258 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; 1259 int i; 1260#endif 1261 1262 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1263 void __iomem *ioaddr = tp->mmio_addr; 1264 if (location == 0) { 1265 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1266 RTL_W16 (BasicModeCtrl, value); 1267 RTL_W8 (Cfg9346, Cfg9346_Lock); 1268 } else if (location < 8 && mii_2_8139_map[location]) 1269 RTL_W16 (mii_2_8139_map[location], value); 1270 return; 1271 } 1272 1273#ifdef CONFIG_8139TOO_8129 1274 mdio_sync (ioaddr); 1275 1276 /* Shift the command bits out. */ 1277 for (i = 31; i >= 0; i--) { 1278 int dataval = 1279 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 1280 RTL_W8 (Config4, dataval); 1281 mdio_delay (); 1282 RTL_W8 (Config4, dataval | MDIO_CLK); 1283 mdio_delay (); 1284 } 1285 /* Clear out extra bits. */ 1286 for (i = 2; i > 0; i--) { 1287 RTL_W8 (Config4, 0); 1288 mdio_delay (); 1289 RTL_W8 (Config4, MDIO_CLK); 1290 mdio_delay (); 1291 } 1292#endif 1293} 1294 1295 1296static int rtl8139_open (struct net_device *dev) 1297{ 1298 struct rtl8139_private *tp = netdev_priv(dev); 1299 int retval; 1300 void __iomem *ioaddr = tp->mmio_addr; 1301 1302 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev); 1303 if (retval) 1304 return retval; 1305 1306 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1307 &tp->tx_bufs_dma, GFP_KERNEL); 1308 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1309 &tp->rx_ring_dma, GFP_KERNEL); 1310 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) { 1311 free_irq(dev->irq, dev); 1312 1313 if (tp->tx_bufs) 1314 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1315 tp->tx_bufs, tp->tx_bufs_dma); 1316 if (tp->rx_ring) 1317 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1318 tp->rx_ring, tp->rx_ring_dma); 1319 1320 return -ENOMEM; 1321 1322 } 1323 1324 napi_enable(&tp->napi); 1325 1326 tp->mii.full_duplex = tp->mii.force_media; 1327 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000; 1328 1329 rtl8139_init_ring (dev); 1330 rtl8139_hw_start (dev); 1331 netif_start_queue (dev); 1332 1333 netif_dbg(tp, ifup, dev, 1334 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n", 1335 __func__, 1336 (unsigned long long)pci_resource_start (tp->pci_dev, 1), 1337 dev->irq, RTL_R8 (MediaStatus), 1338 tp->mii.full_duplex ? "full" : "half"); 1339 1340 rtl8139_start_thread(tp); 1341 1342 return 0; 1343} 1344 1345 1346static void rtl_check_media (struct net_device *dev, unsigned int init_media) 1347{ 1348 struct rtl8139_private *tp = netdev_priv(dev); 1349 1350 if (tp->phys[0] >= 0) { 1351 mii_check_media(&tp->mii, netif_msg_link(tp), init_media); 1352 } 1353} 1354 1355/* Start the hardware at open or resume. */ 1356static void rtl8139_hw_start (struct net_device *dev) 1357{ 1358 struct rtl8139_private *tp = netdev_priv(dev); 1359 void __iomem *ioaddr = tp->mmio_addr; 1360 u32 i; 1361 u8 tmp; 1362 1363 /* Bring old chips out of low-power mode. */ 1364 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1365 RTL_W8 (HltClk, 'R'); 1366 1367 rtl8139_chip_reset (ioaddr); 1368 1369 /* unlock Config[01234] and BMCR register writes */ 1370 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1371 /* Restore our idea of the MAC address. */ 1372 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1373 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4))); 1374 1375 tp->cur_rx = 0; 1376 1377 /* init Rx ring buffer DMA address */ 1378 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1379 1380 /* Must enable Tx/Rx before setting transfer thresholds! */ 1381 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1382 1383 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1384 RTL_W32 (RxConfig, tp->rx_config); 1385 RTL_W32 (TxConfig, rtl8139_tx_config); 1386 1387 rtl_check_media (dev, 1); 1388 1389 if (tp->chipset >= CH_8139B) { 1390 /* Disable magic packet scanning, which is enabled 1391 * when PM is enabled in Config1. It can be reenabled 1392 * via ETHTOOL_SWOL if desired. */ 1393 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic); 1394 } 1395 1396 netdev_dbg(dev, "init buffer addresses\n"); 1397 1398 /* Lock Config[01234] and BMCR register writes */ 1399 RTL_W8 (Cfg9346, Cfg9346_Lock); 1400 1401 /* init Tx buffer DMA addresses */ 1402 for (i = 0; i < NUM_TX_DESC; i++) 1403 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs)); 1404 1405 RTL_W32 (RxMissed, 0); 1406 1407 rtl8139_set_rx_mode (dev); 1408 1409 /* no early-rx interrupts */ 1410 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear); 1411 1412 /* make sure RxTx has started */ 1413 tmp = RTL_R8 (ChipCmd); 1414 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb))) 1415 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1416 1417 /* Enable all known interrupts by setting the interrupt mask. */ 1418 RTL_W16 (IntrMask, rtl8139_intr_mask); 1419} 1420 1421 1422/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1423static void rtl8139_init_ring (struct net_device *dev) 1424{ 1425 struct rtl8139_private *tp = netdev_priv(dev); 1426 int i; 1427 1428 tp->cur_rx = 0; 1429 tp->cur_tx = 0; 1430 tp->dirty_tx = 0; 1431 1432 for (i = 0; i < NUM_TX_DESC; i++) 1433 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE]; 1434} 1435 1436 1437/* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */ 1438static int next_tick = 3 * HZ; 1439 1440#ifndef CONFIG_8139TOO_TUNE_TWISTER 1441static inline void rtl8139_tune_twister (struct net_device *dev, 1442 struct rtl8139_private *tp) {} 1443#else 1444enum TwisterParamVals { 1445 PARA78_default = 0x78fa8388, 1446 PARA7c_default = 0xcb38de43, /* param[0][3] */ 1447 PARA7c_xxx = 0xcb38de43, 1448}; 1449 1450static const unsigned long param[4][4] = { 1451 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1452 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1453 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1454 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1455}; 1456 1457static void rtl8139_tune_twister (struct net_device *dev, 1458 struct rtl8139_private *tp) 1459{ 1460 int linkcase; 1461 void __iomem *ioaddr = tp->mmio_addr; 1462 1463 /* This is a complicated state machine to configure the "twister" for 1464 impedance/echos based on the cable length. 1465 All of this is magic and undocumented. 1466 */ 1467 switch (tp->twistie) { 1468 case 1: 1469 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { 1470 /* We have link beat, let us tune the twister. */ 1471 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); 1472 tp->twistie = 2; /* Change to state 2. */ 1473 next_tick = HZ / 10; 1474 } else { 1475 /* Just put in some reasonable defaults for when beat returns. */ 1476 RTL_W16 (CSCR, CSCR_LinkDownCmd); 1477 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */ 1478 RTL_W32 (PARA78, PARA78_default); 1479 RTL_W32 (PARA7c, PARA7c_default); 1480 tp->twistie = 0; /* Bail from future actions. */ 1481 } 1482 break; 1483 case 2: 1484 /* Read how long it took to hear the echo. */ 1485 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; 1486 if (linkcase == 0x7000) 1487 tp->twist_row = 3; 1488 else if (linkcase == 0x3000) 1489 tp->twist_row = 2; 1490 else if (linkcase == 0x1000) 1491 tp->twist_row = 1; 1492 else 1493 tp->twist_row = 0; 1494 tp->twist_col = 0; 1495 tp->twistie = 3; /* Change to state 2. */ 1496 next_tick = HZ / 10; 1497 break; 1498 case 3: 1499 /* Put out four tuning parameters, one per 100msec. */ 1500 if (tp->twist_col == 0) 1501 RTL_W16 (FIFOTMS, 0); 1502 RTL_W32 (PARA7c, param[(int) tp->twist_row] 1503 [(int) tp->twist_col]); 1504 next_tick = HZ / 10; 1505 if (++tp->twist_col >= 4) { 1506 /* For short cables we are done. 1507 For long cables (row == 3) check for mistune. */ 1508 tp->twistie = 1509 (tp->twist_row == 3) ? 4 : 0; 1510 } 1511 break; 1512 case 4: 1513 /* Special case for long cables: check for mistune. */ 1514 if ((RTL_R16 (CSCR) & 1515 CSCR_LinkStatusBits) == 0x7000) { 1516 tp->twistie = 0; 1517 break; 1518 } else { 1519 RTL_W32 (PARA7c, 0xfb38de03); 1520 tp->twistie = 5; 1521 next_tick = HZ / 10; 1522 } 1523 break; 1524 case 5: 1525 /* Retune for shorter cable (column 2). */ 1526 RTL_W32 (FIFOTMS, 0x20); 1527 RTL_W32 (PARA78, PARA78_default); 1528 RTL_W32 (PARA7c, PARA7c_default); 1529 RTL_W32 (FIFOTMS, 0x00); 1530 tp->twist_row = 2; 1531 tp->twist_col = 0; 1532 tp->twistie = 3; 1533 next_tick = HZ / 10; 1534 break; 1535 1536 default: 1537 /* do nothing */ 1538 break; 1539 } 1540} 1541#endif /* CONFIG_8139TOO_TUNE_TWISTER */ 1542 1543static inline void rtl8139_thread_iter (struct net_device *dev, 1544 struct rtl8139_private *tp, 1545 void __iomem *ioaddr) 1546{ 1547 int mii_lpa; 1548 1549 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA); 1550 1551 if (!tp->mii.force_media && mii_lpa != 0xffff) { 1552 int duplex = ((mii_lpa & LPA_100FULL) || 1553 (mii_lpa & 0x01C0) == 0x0040); 1554 if (tp->mii.full_duplex != duplex) { 1555 tp->mii.full_duplex = duplex; 1556 1557 if (mii_lpa) { 1558 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n", 1559 tp->mii.full_duplex ? "full" : "half", 1560 tp->phys[0], mii_lpa); 1561 } else { 1562 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n"); 1563 } 1564 } 1565 } 1566 1567 next_tick = HZ * 60; 1568 1569 rtl8139_tune_twister (dev, tp); 1570 1571 netdev_dbg(dev, "Media selection tick, Link partner %04x\n", 1572 RTL_R16(NWayLPAR)); 1573 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n", 1574 RTL_R16(IntrMask), RTL_R16(IntrStatus)); 1575 netdev_dbg(dev, "Chip config %02x %02x\n", 1576 RTL_R8(Config0), RTL_R8(Config1)); 1577} 1578 1579static void rtl8139_thread (struct work_struct *work) 1580{ 1581 struct rtl8139_private *tp = 1582 container_of(work, struct rtl8139_private, thread.work); 1583 struct net_device *dev = tp->mii.dev; 1584 unsigned long thr_delay = next_tick; 1585 1586 rtnl_lock(); 1587 1588 if (!netif_running(dev)) 1589 goto out_unlock; 1590 1591 if (tp->watchdog_fired) { 1592 tp->watchdog_fired = 0; 1593 rtl8139_tx_timeout_task(work); 1594 } else 1595 rtl8139_thread_iter(dev, tp, tp->mmio_addr); 1596 1597 if (tp->have_thread) 1598 schedule_delayed_work(&tp->thread, thr_delay); 1599out_unlock: 1600 rtnl_unlock (); 1601} 1602 1603static void rtl8139_start_thread(struct rtl8139_private *tp) 1604{ 1605 tp->twistie = 0; 1606 if (tp->chipset == CH_8139_K) 1607 tp->twistie = 1; 1608 else if (tp->drv_flags & HAS_LNK_CHNG) 1609 return; 1610 1611 tp->have_thread = 1; 1612 tp->watchdog_fired = 0; 1613 1614 schedule_delayed_work(&tp->thread, next_tick); 1615} 1616 1617static inline void rtl8139_tx_clear (struct rtl8139_private *tp) 1618{ 1619 tp->cur_tx = 0; 1620 tp->dirty_tx = 0; 1621 1622} 1623 1624static void rtl8139_tx_timeout_task (struct work_struct *work) 1625{ 1626 struct rtl8139_private *tp = 1627 container_of(work, struct rtl8139_private, thread.work); 1628 struct net_device *dev = tp->mii.dev; 1629 void __iomem *ioaddr = tp->mmio_addr; 1630 int i; 1631 u8 tmp8; 1632 1633 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n", 1634 RTL_R8(ChipCmd), RTL_R16(IntrStatus), 1635 RTL_R16(IntrMask), RTL_R8(MediaStatus)); 1636 /* Emit info to figure out what went wrong. */ 1637 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n", 1638 tp->cur_tx, tp->dirty_tx); 1639 for (i = 0; i < NUM_TX_DESC; i++) 1640 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n", 1641 i, RTL_R32(TxStatus0 + (i * 4)), 1642 i == tp->dirty_tx % NUM_TX_DESC ? 1643 " (queue head)" : ""); 1644 1645 tp->xstats.tx_timeouts++; 1646 1647 /* disable Tx ASAP, if not already */ 1648 tmp8 = RTL_R8 (ChipCmd); 1649 if (tmp8 & CmdTxEnb) 1650 RTL_W8 (ChipCmd, CmdRxEnb); 1651 1652 spin_lock_bh(&tp->rx_lock); 1653 /* Disable interrupts by clearing the interrupt mask. */ 1654 RTL_W16 (IntrMask, 0x0000); 1655 1656 /* Stop a shared interrupt from scavenging while we are. */ 1657 spin_lock_irq(&tp->lock); 1658 rtl8139_tx_clear (tp); 1659 spin_unlock_irq(&tp->lock); 1660 1661 /* ...and finally, reset everything */ 1662 if (netif_running(dev)) { 1663 rtl8139_hw_start (dev); 1664 netif_wake_queue (dev); 1665 } 1666 spin_unlock_bh(&tp->rx_lock); 1667} 1668 1669static void rtl8139_tx_timeout (struct net_device *dev) 1670{ 1671 struct rtl8139_private *tp = netdev_priv(dev); 1672 1673 tp->watchdog_fired = 1; 1674 if (!tp->have_thread) { 1675 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1676 schedule_delayed_work(&tp->thread, next_tick); 1677 } 1678} 1679 1680static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 1681 struct net_device *dev) 1682{ 1683 struct rtl8139_private *tp = netdev_priv(dev); 1684 void __iomem *ioaddr = tp->mmio_addr; 1685 unsigned int entry; 1686 unsigned int len = skb->len; 1687 unsigned long flags; 1688 1689 /* Calculate the next Tx descriptor entry. */ 1690 entry = tp->cur_tx % NUM_TX_DESC; 1691 1692 /* Note: the chip doesn't have auto-pad! */ 1693 if (likely(len < TX_BUF_SIZE)) { 1694 if (len < ETH_ZLEN) 1695 memset(tp->tx_buf[entry], 0, ETH_ZLEN); 1696 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]); 1697 dev_kfree_skb(skb); 1698 } else { 1699 dev_kfree_skb(skb); 1700 dev->stats.tx_dropped++; 1701 return NETDEV_TX_OK; 1702 } 1703 1704 spin_lock_irqsave(&tp->lock, flags); 1705 /* 1706 * Writing to TxStatus triggers a DMA transfer of the data 1707 * copied to tp->tx_buf[entry] above. Use a memory barrier 1708 * to make sure that the device sees the updated data. 1709 */ 1710 wmb(); 1711 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), 1712 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); 1713 1714 tp->cur_tx++; 1715 1716 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) 1717 netif_stop_queue (dev); 1718 spin_unlock_irqrestore(&tp->lock, flags); 1719 1720 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n", 1721 len, entry); 1722 1723 return NETDEV_TX_OK; 1724} 1725 1726 1727static void rtl8139_tx_interrupt (struct net_device *dev, 1728 struct rtl8139_private *tp, 1729 void __iomem *ioaddr) 1730{ 1731 unsigned long dirty_tx, tx_left; 1732 1733 assert (dev != NULL); 1734 assert (ioaddr != NULL); 1735 1736 dirty_tx = tp->dirty_tx; 1737 tx_left = tp->cur_tx - dirty_tx; 1738 while (tx_left > 0) { 1739 int entry = dirty_tx % NUM_TX_DESC; 1740 int txstatus; 1741 1742 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); 1743 1744 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) 1745 break; /* It still hasn't been Txed */ 1746 1747 /* Note: TxCarrierLost is always asserted at 100mbps. */ 1748 if (txstatus & (TxOutOfWindow | TxAborted)) { 1749 /* There was an major error, log it. */ 1750 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n", 1751 txstatus); 1752 dev->stats.tx_errors++; 1753 if (txstatus & TxAborted) { 1754 dev->stats.tx_aborted_errors++; 1755 RTL_W32 (TxConfig, TxClearAbt); 1756 RTL_W16 (IntrStatus, TxErr); 1757 wmb(); 1758 } 1759 if (txstatus & TxCarrierLost) 1760 dev->stats.tx_carrier_errors++; 1761 if (txstatus & TxOutOfWindow) 1762 dev->stats.tx_window_errors++; 1763 } else { 1764 if (txstatus & TxUnderrun) { 1765 /* Add 64 to the Tx FIFO threshold. */ 1766 if (tp->tx_flag < 0x00300000) 1767 tp->tx_flag += 0x00020000; 1768 dev->stats.tx_fifo_errors++; 1769 } 1770 dev->stats.collisions += (txstatus >> 24) & 15; 1771 dev->stats.tx_bytes += txstatus & 0x7ff; 1772 dev->stats.tx_packets++; 1773 } 1774 1775 dirty_tx++; 1776 tx_left--; 1777 } 1778 1779#ifndef RTL8139_NDEBUG 1780 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) { 1781 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n", 1782 dirty_tx, tp->cur_tx); 1783 dirty_tx += NUM_TX_DESC; 1784 } 1785#endif /* RTL8139_NDEBUG */ 1786 1787 /* only wake the queue if we did work, and the queue is stopped */ 1788 if (tp->dirty_tx != dirty_tx) { 1789 tp->dirty_tx = dirty_tx; 1790 mb(); 1791 netif_wake_queue (dev); 1792 } 1793} 1794 1795 1796/* TODO: clean this up! Rx reset need not be this intensive */ 1797static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, 1798 struct rtl8139_private *tp, void __iomem *ioaddr) 1799{ 1800 u8 tmp8; 1801#ifdef CONFIG_8139_OLD_RX_RESET 1802 int tmp_work; 1803#endif 1804 1805 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n", 1806 rx_status); 1807 dev->stats.rx_errors++; 1808 if (!(rx_status & RxStatusOK)) { 1809 if (rx_status & RxTooLong) { 1810 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n", 1811 rx_status); 1812 /* A.C.: The chip hangs here. */ 1813 } 1814 if (rx_status & (RxBadSymbol | RxBadAlign)) 1815 dev->stats.rx_frame_errors++; 1816 if (rx_status & (RxRunt | RxTooLong)) 1817 dev->stats.rx_length_errors++; 1818 if (rx_status & RxCRCErr) 1819 dev->stats.rx_crc_errors++; 1820 } else { 1821 tp->xstats.rx_lost_in_ring++; 1822 } 1823 1824#ifndef CONFIG_8139_OLD_RX_RESET 1825 tmp8 = RTL_R8 (ChipCmd); 1826 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb); 1827 RTL_W8 (ChipCmd, tmp8); 1828 RTL_W32 (RxConfig, tp->rx_config); 1829 tp->cur_rx = 0; 1830#else 1831 /* Reset the receiver, based on RealTek recommendation. (Bug?) */ 1832 1833 /* disable receive */ 1834 RTL_W8_F (ChipCmd, CmdTxEnb); 1835 tmp_work = 200; 1836 while (--tmp_work > 0) { 1837 udelay(1); 1838 tmp8 = RTL_R8 (ChipCmd); 1839 if (!(tmp8 & CmdRxEnb)) 1840 break; 1841 } 1842 if (tmp_work <= 0) 1843 netdev_warn(dev, "rx stop wait too long\n"); 1844 /* restart receive */ 1845 tmp_work = 200; 1846 while (--tmp_work > 0) { 1847 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb); 1848 udelay(1); 1849 tmp8 = RTL_R8 (ChipCmd); 1850 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb)) 1851 break; 1852 } 1853 if (tmp_work <= 0) 1854 netdev_warn(dev, "tx/rx enable wait too long\n"); 1855 1856 /* and reinitialize all rx related registers */ 1857 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1858 /* Must enable Tx/Rx before setting transfer thresholds! */ 1859 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1860 1861 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1862 RTL_W32 (RxConfig, tp->rx_config); 1863 tp->cur_rx = 0; 1864 1865 netdev_dbg(dev, "init buffer addresses\n"); 1866 1867 /* Lock Config[01234] and BMCR register writes */ 1868 RTL_W8 (Cfg9346, Cfg9346_Lock); 1869 1870 /* init Rx ring buffer DMA address */ 1871 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1872 1873 /* A.C.: Reset the multicast list. */ 1874 __set_rx_mode (dev); 1875#endif 1876} 1877 1878#if RX_BUF_IDX == 3 1879static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring, 1880 u32 offset, unsigned int size) 1881{ 1882 u32 left = RX_BUF_LEN - offset; 1883 1884 if (size > left) { 1885 skb_copy_to_linear_data(skb, ring + offset, left); 1886 skb_copy_to_linear_data_offset(skb, left, ring, size - left); 1887 } else 1888 skb_copy_to_linear_data(skb, ring + offset, size); 1889} 1890#endif 1891 1892static void rtl8139_isr_ack(struct rtl8139_private *tp) 1893{ 1894 void __iomem *ioaddr = tp->mmio_addr; 1895 u16 status; 1896 1897 status = RTL_R16 (IntrStatus) & RxAckBits; 1898 1899 /* Clear out errors and receive interrupts */ 1900 if (likely(status != 0)) { 1901 if (unlikely(status & (RxFIFOOver | RxOverflow))) { 1902 tp->dev->stats.rx_errors++; 1903 if (status & RxFIFOOver) 1904 tp->dev->stats.rx_fifo_errors++; 1905 } 1906 RTL_W16_F (IntrStatus, RxAckBits); 1907 } 1908} 1909 1910static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, 1911 int budget) 1912{ 1913 void __iomem *ioaddr = tp->mmio_addr; 1914 int received = 0; 1915 unsigned char *rx_ring = tp->rx_ring; 1916 unsigned int cur_rx = tp->cur_rx; 1917 unsigned int rx_size = 0; 1918 1919 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 1920 __func__, (u16)cur_rx, 1921 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 1922 1923 while (netif_running(dev) && received < budget && 1924 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { 1925 u32 ring_offset = cur_rx % RX_BUF_LEN; 1926 u32 rx_status; 1927 unsigned int pkt_size; 1928 struct sk_buff *skb; 1929 1930 rmb(); 1931 1932 /* read size+status of next frame from DMA ring buffer */ 1933 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset)); 1934 rx_size = rx_status >> 16; 1935 pkt_size = rx_size - 4; 1936 1937 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n", 1938 __func__, rx_status, rx_size, cur_rx); 1939#if RTL8139_DEBUG > 2 1940 print_hex_dump(KERN_DEBUG, "Frame contents: ", 1941 DUMP_PREFIX_OFFSET, 16, 1, 1942 &rx_ring[ring_offset], 70, true); 1943#endif 1944 1945 /* Packet copy from FIFO still in progress. 1946 * Theoretically, this should never happen 1947 * since EarlyRx is disabled. 1948 */ 1949 if (unlikely(rx_size == 0xfff0)) { 1950 if (!tp->fifo_copy_timeout) 1951 tp->fifo_copy_timeout = jiffies + 2; 1952 else if (time_after(jiffies, tp->fifo_copy_timeout)) { 1953 netdev_dbg(dev, "hung FIFO. Reset\n"); 1954 rx_size = 0; 1955 goto no_early_rx; 1956 } 1957 netif_dbg(tp, intr, dev, "fifo copy in progress\n"); 1958 tp->xstats.early_rx++; 1959 break; 1960 } 1961 1962no_early_rx: 1963 tp->fifo_copy_timeout = 0; 1964 1965 /* If Rx err or invalid rx_size/rx_status received 1966 * (which happens if we get lost in the ring), 1967 * Rx process gets reset, so we abort any further 1968 * Rx processing. 1969 */ 1970 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) || 1971 (rx_size < 8) || 1972 (!(rx_status & RxStatusOK)))) { 1973 rtl8139_rx_err (rx_status, dev, tp, ioaddr); 1974 received = -1; 1975 goto out; 1976 } 1977 1978 /* Malloc up new buffer, compatible with net-2e. */ 1979 /* Omit the four octet CRC from the length. */ 1980 1981 skb = netdev_alloc_skb_ip_align(dev, pkt_size); 1982 if (likely(skb)) { 1983#if RX_BUF_IDX == 3 1984 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size); 1985#else 1986 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size); 1987#endif 1988 skb_put (skb, pkt_size); 1989 1990 skb->protocol = eth_type_trans (skb, dev); 1991 1992 dev->stats.rx_bytes += pkt_size; 1993 dev->stats.rx_packets++; 1994 1995 netif_receive_skb (skb); 1996 } else { 1997 if (net_ratelimit()) 1998 netdev_warn(dev, "Memory squeeze, dropping packet\n"); 1999 dev->stats.rx_dropped++; 2000 } 2001 received++; 2002 2003 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 2004 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16)); 2005 2006 rtl8139_isr_ack(tp); 2007 } 2008 2009 if (unlikely(!received || rx_size == 0xfff0)) 2010 rtl8139_isr_ack(tp); 2011 2012 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 2013 __func__, cur_rx, 2014 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 2015 2016 tp->cur_rx = cur_rx; 2017 2018 /* 2019 * The receive buffer should be mostly empty. 2020 * Tell NAPI to reenable the Rx irq. 2021 */ 2022 if (tp->fifo_copy_timeout) 2023 received = budget; 2024 2025out: 2026 return received; 2027} 2028 2029 2030static void rtl8139_weird_interrupt (struct net_device *dev, 2031 struct rtl8139_private *tp, 2032 void __iomem *ioaddr, 2033 int status, int link_changed) 2034{ 2035 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status); 2036 2037 assert (dev != NULL); 2038 assert (tp != NULL); 2039 assert (ioaddr != NULL); 2040 2041 /* Update the error count. */ 2042 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2043 RTL_W32 (RxMissed, 0); 2044 2045 if ((status & RxUnderrun) && link_changed && 2046 (tp->drv_flags & HAS_LNK_CHNG)) { 2047 rtl_check_media(dev, 0); 2048 status &= ~RxUnderrun; 2049 } 2050 2051 if (status & (RxUnderrun | RxErr)) 2052 dev->stats.rx_errors++; 2053 2054 if (status & PCSTimeout) 2055 dev->stats.rx_length_errors++; 2056 if (status & RxUnderrun) 2057 dev->stats.rx_fifo_errors++; 2058 if (status & PCIErr) { 2059 u16 pci_cmd_status; 2060 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); 2061 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status); 2062 2063 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status); 2064 } 2065} 2066 2067static int rtl8139_poll(struct napi_struct *napi, int budget) 2068{ 2069 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi); 2070 struct net_device *dev = tp->dev; 2071 void __iomem *ioaddr = tp->mmio_addr; 2072 int work_done; 2073 2074 spin_lock(&tp->rx_lock); 2075 work_done = 0; 2076 if (likely(RTL_R16(IntrStatus) & RxAckBits)) 2077 work_done += rtl8139_rx(dev, tp, budget); 2078 2079 if (work_done < budget) { 2080 unsigned long flags; 2081 /* 2082 * Order is important since data can get interrupted 2083 * again when we think we are done. 2084 */ 2085 spin_lock_irqsave(&tp->lock, flags); 2086 __napi_complete(napi); 2087 RTL_W16_F(IntrMask, rtl8139_intr_mask); 2088 spin_unlock_irqrestore(&tp->lock, flags); 2089 } 2090 spin_unlock(&tp->rx_lock); 2091 2092 return work_done; 2093} 2094 2095/* The interrupt handler does all of the Rx thread work and cleans up 2096 after the Tx thread. */ 2097static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance) 2098{ 2099 struct net_device *dev = (struct net_device *) dev_instance; 2100 struct rtl8139_private *tp = netdev_priv(dev); 2101 void __iomem *ioaddr = tp->mmio_addr; 2102 u16 status, ackstat; 2103 int link_changed = 0; /* avoid bogus "uninit" warning */ 2104 int handled = 0; 2105 2106 spin_lock (&tp->lock); 2107 status = RTL_R16 (IntrStatus); 2108 2109 /* shared irq? */ 2110 if (unlikely((status & rtl8139_intr_mask) == 0)) 2111 goto out; 2112 2113 handled = 1; 2114 2115 /* h/w no longer present (hotplug?) or major error, bail */ 2116 if (unlikely(status == 0xFFFF)) 2117 goto out; 2118 2119 /* close possible race's with dev_close */ 2120 if (unlikely(!netif_running(dev))) { 2121 RTL_W16 (IntrMask, 0); 2122 goto out; 2123 } 2124 2125 /* Acknowledge all of the current interrupt sources ASAP, but 2126 an first get an additional status bit from CSCR. */ 2127 if (unlikely(status & RxUnderrun)) 2128 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; 2129 2130 ackstat = status & ~(RxAckBits | TxErr); 2131 if (ackstat) 2132 RTL_W16 (IntrStatus, ackstat); 2133 2134 /* Receive packets are processed by poll routine. 2135 If not running start it now. */ 2136 if (status & RxAckBits){ 2137 if (napi_schedule_prep(&tp->napi)) { 2138 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask); 2139 __napi_schedule(&tp->napi); 2140 } 2141 } 2142 2143 /* Check uncommon events with one test. */ 2144 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr))) 2145 rtl8139_weird_interrupt (dev, tp, ioaddr, 2146 status, link_changed); 2147 2148 if (status & (TxOK | TxErr)) { 2149 rtl8139_tx_interrupt (dev, tp, ioaddr); 2150 if (status & TxErr) 2151 RTL_W16 (IntrStatus, TxErr); 2152 } 2153 out: 2154 spin_unlock (&tp->lock); 2155 2156 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n", 2157 RTL_R16(IntrStatus)); 2158 return IRQ_RETVAL(handled); 2159} 2160 2161#ifdef CONFIG_NET_POLL_CONTROLLER 2162/* 2163 * Polling receive - used by netconsole and other diagnostic tools 2164 * to allow network i/o with interrupts disabled. 2165 */ 2166static void rtl8139_poll_controller(struct net_device *dev) 2167{ 2168 disable_irq(dev->irq); 2169 rtl8139_interrupt(dev->irq, dev); 2170 enable_irq(dev->irq); 2171} 2172#endif 2173 2174static int rtl8139_set_mac_address(struct net_device *dev, void *p) 2175{ 2176 struct rtl8139_private *tp = netdev_priv(dev); 2177 void __iomem *ioaddr = tp->mmio_addr; 2178 struct sockaddr *addr = p; 2179 2180 if (!is_valid_ether_addr(addr->sa_data)) 2181 return -EADDRNOTAVAIL; 2182 2183 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2184 2185 spin_lock_irq(&tp->lock); 2186 2187 RTL_W8_F(Cfg9346, Cfg9346_Unlock); 2188 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); 2189 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); 2190 RTL_W8_F(Cfg9346, Cfg9346_Lock); 2191 2192 spin_unlock_irq(&tp->lock); 2193 2194 return 0; 2195} 2196 2197static int rtl8139_close (struct net_device *dev) 2198{ 2199 struct rtl8139_private *tp = netdev_priv(dev); 2200 void __iomem *ioaddr = tp->mmio_addr; 2201 unsigned long flags; 2202 2203 netif_stop_queue(dev); 2204 napi_disable(&tp->napi); 2205 2206 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n", 2207 RTL_R16(IntrStatus)); 2208 2209 spin_lock_irqsave (&tp->lock, flags); 2210 2211 /* Stop the chip's Tx and Rx DMA processes. */ 2212 RTL_W8 (ChipCmd, 0); 2213 2214 /* Disable interrupts by clearing the interrupt mask. */ 2215 RTL_W16 (IntrMask, 0); 2216 2217 /* Update the error counts. */ 2218 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2219 RTL_W32 (RxMissed, 0); 2220 2221 spin_unlock_irqrestore (&tp->lock, flags); 2222 2223 free_irq (dev->irq, dev); 2224 2225 rtl8139_tx_clear (tp); 2226 2227 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 2228 tp->rx_ring, tp->rx_ring_dma); 2229 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 2230 tp->tx_bufs, tp->tx_bufs_dma); 2231 tp->rx_ring = NULL; 2232 tp->tx_bufs = NULL; 2233 2234 /* Green! Put the chip in low-power mode. */ 2235 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2236 2237 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 2238 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 2239 2240 return 0; 2241} 2242 2243 2244/* Get the ethtool Wake-on-LAN settings. Assumes that wol points to 2245 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and 2246 other threads or interrupts aren't messing with the 8139. */ 2247static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2248{ 2249 struct rtl8139_private *tp = netdev_priv(dev); 2250 void __iomem *ioaddr = tp->mmio_addr; 2251 2252 spin_lock_irq(&tp->lock); 2253 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 2254 u8 cfg3 = RTL_R8 (Config3); 2255 u8 cfg5 = RTL_R8 (Config5); 2256 2257 wol->supported = WAKE_PHY | WAKE_MAGIC 2258 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 2259 2260 wol->wolopts = 0; 2261 if (cfg3 & Cfg3_LinkUp) 2262 wol->wolopts |= WAKE_PHY; 2263 if (cfg3 & Cfg3_Magic) 2264 wol->wolopts |= WAKE_MAGIC; 2265 if (cfg5 & Cfg5_UWF) 2266 wol->wolopts |= WAKE_UCAST; 2267 if (cfg5 & Cfg5_MWF) 2268 wol->wolopts |= WAKE_MCAST; 2269 if (cfg5 & Cfg5_BWF) 2270 wol->wolopts |= WAKE_BCAST; 2271 } 2272 spin_unlock_irq(&tp->lock); 2273} 2274 2275 2276/* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes 2277 that wol points to kernel memory and other threads or interrupts 2278 aren't messing with the 8139. */ 2279static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2280{ 2281 struct rtl8139_private *tp = netdev_priv(dev); 2282 void __iomem *ioaddr = tp->mmio_addr; 2283 u32 support; 2284 u8 cfg3, cfg5; 2285 2286 support = ((rtl_chip_info[tp->chipset].flags & HasLWake) 2287 ? (WAKE_PHY | WAKE_MAGIC 2288 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST) 2289 : 0); 2290 if (wol->wolopts & ~support) 2291 return -EINVAL; 2292 2293 spin_lock_irq(&tp->lock); 2294 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic); 2295 if (wol->wolopts & WAKE_PHY) 2296 cfg3 |= Cfg3_LinkUp; 2297 if (wol->wolopts & WAKE_MAGIC) 2298 cfg3 |= Cfg3_Magic; 2299 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2300 RTL_W8 (Config3, cfg3); 2301 RTL_W8 (Cfg9346, Cfg9346_Lock); 2302 2303 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); 2304 if (wol->wolopts & WAKE_UCAST) 2305 cfg5 |= Cfg5_UWF; 2306 if (wol->wolopts & WAKE_MCAST) 2307 cfg5 |= Cfg5_MWF; 2308 if (wol->wolopts & WAKE_BCAST) 2309 cfg5 |= Cfg5_BWF; 2310 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ 2311 spin_unlock_irq(&tp->lock); 2312 2313 return 0; 2314} 2315 2316static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2317{ 2318 struct rtl8139_private *tp = netdev_priv(dev); 2319 strcpy(info->driver, DRV_NAME); 2320 strcpy(info->version, DRV_VERSION); 2321 strcpy(info->bus_info, pci_name(tp->pci_dev)); 2322 info->regdump_len = tp->regs_len; 2323} 2324 2325static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2326{ 2327 struct rtl8139_private *tp = netdev_priv(dev); 2328 spin_lock_irq(&tp->lock); 2329 mii_ethtool_gset(&tp->mii, cmd); 2330 spin_unlock_irq(&tp->lock); 2331 return 0; 2332} 2333 2334static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2335{ 2336 struct rtl8139_private *tp = netdev_priv(dev); 2337 int rc; 2338 spin_lock_irq(&tp->lock); 2339 rc = mii_ethtool_sset(&tp->mii, cmd); 2340 spin_unlock_irq(&tp->lock); 2341 return rc; 2342} 2343 2344static int rtl8139_nway_reset(struct net_device *dev) 2345{ 2346 struct rtl8139_private *tp = netdev_priv(dev); 2347 return mii_nway_restart(&tp->mii); 2348} 2349 2350static u32 rtl8139_get_link(struct net_device *dev) 2351{ 2352 struct rtl8139_private *tp = netdev_priv(dev); 2353 return mii_link_ok(&tp->mii); 2354} 2355 2356static u32 rtl8139_get_msglevel(struct net_device *dev) 2357{ 2358 struct rtl8139_private *tp = netdev_priv(dev); 2359 return tp->msg_enable; 2360} 2361 2362static void rtl8139_set_msglevel(struct net_device *dev, u32 datum) 2363{ 2364 struct rtl8139_private *tp = netdev_priv(dev); 2365 tp->msg_enable = datum; 2366} 2367 2368static int rtl8139_get_regs_len(struct net_device *dev) 2369{ 2370 struct rtl8139_private *tp; 2371 /* TODO: we are too slack to do reg dumping for pio, for now */ 2372 if (use_io) 2373 return 0; 2374 tp = netdev_priv(dev); 2375 return tp->regs_len; 2376} 2377 2378static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) 2379{ 2380 struct rtl8139_private *tp; 2381 2382 /* TODO: we are too slack to do reg dumping for pio, for now */ 2383 if (use_io) 2384 return; 2385 tp = netdev_priv(dev); 2386 2387 regs->version = RTL_REGS_VER; 2388 2389 spin_lock_irq(&tp->lock); 2390 memcpy_fromio(regbuf, tp->mmio_addr, regs->len); 2391 spin_unlock_irq(&tp->lock); 2392} 2393 2394static int rtl8139_get_sset_count(struct net_device *dev, int sset) 2395{ 2396 switch (sset) { 2397 case ETH_SS_STATS: 2398 return RTL_NUM_STATS; 2399 default: 2400 return -EOPNOTSUPP; 2401 } 2402} 2403 2404static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2405{ 2406 struct rtl8139_private *tp = netdev_priv(dev); 2407 2408 data[0] = tp->xstats.early_rx; 2409 data[1] = tp->xstats.tx_buf_mapped; 2410 data[2] = tp->xstats.tx_timeouts; 2411 data[3] = tp->xstats.rx_lost_in_ring; 2412} 2413 2414static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2415{ 2416 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2417} 2418 2419static const struct ethtool_ops rtl8139_ethtool_ops = { 2420 .get_drvinfo = rtl8139_get_drvinfo, 2421 .get_settings = rtl8139_get_settings, 2422 .set_settings = rtl8139_set_settings, 2423 .get_regs_len = rtl8139_get_regs_len, 2424 .get_regs = rtl8139_get_regs, 2425 .nway_reset = rtl8139_nway_reset, 2426 .get_link = rtl8139_get_link, 2427 .get_msglevel = rtl8139_get_msglevel, 2428 .set_msglevel = rtl8139_set_msglevel, 2429 .get_wol = rtl8139_get_wol, 2430 .set_wol = rtl8139_set_wol, 2431 .get_strings = rtl8139_get_strings, 2432 .get_sset_count = rtl8139_get_sset_count, 2433 .get_ethtool_stats = rtl8139_get_ethtool_stats, 2434}; 2435 2436static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2437{ 2438 struct rtl8139_private *tp = netdev_priv(dev); 2439 int rc; 2440 2441 if (!netif_running(dev)) 2442 return -EINVAL; 2443 2444 spin_lock_irq(&tp->lock); 2445 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL); 2446 spin_unlock_irq(&tp->lock); 2447 2448 return rc; 2449} 2450 2451 2452static struct net_device_stats *rtl8139_get_stats (struct net_device *dev) 2453{ 2454 struct rtl8139_private *tp = netdev_priv(dev); 2455 void __iomem *ioaddr = tp->mmio_addr; 2456 unsigned long flags; 2457 2458 if (netif_running(dev)) { 2459 spin_lock_irqsave (&tp->lock, flags); 2460 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2461 RTL_W32 (RxMissed, 0); 2462 spin_unlock_irqrestore (&tp->lock, flags); 2463 } 2464 2465 return &dev->stats; 2466} 2467 2468/* Set or clear the multicast filter for this adaptor. 2469 This routine is not state sensitive and need not be SMP locked. */ 2470 2471static void __set_rx_mode (struct net_device *dev) 2472{ 2473 struct rtl8139_private *tp = netdev_priv(dev); 2474 void __iomem *ioaddr = tp->mmio_addr; 2475 u32 mc_filter[2]; /* Multicast hash filter */ 2476 int rx_mode; 2477 u32 tmp; 2478 2479 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n", 2480 dev->flags, RTL_R32(RxConfig)); 2481 2482 /* Note: do not reorder, GCC is clever about common statements. */ 2483 if (dev->flags & IFF_PROMISC) { 2484 rx_mode = 2485 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2486 AcceptAllPhys; 2487 mc_filter[1] = mc_filter[0] = 0xffffffff; 2488 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2489 (dev->flags & IFF_ALLMULTI)) { 2490 /* Too many to filter perfectly -- accept all multicasts. */ 2491 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 2492 mc_filter[1] = mc_filter[0] = 0xffffffff; 2493 } else { 2494 struct netdev_hw_addr *ha; 2495 rx_mode = AcceptBroadcast | AcceptMyPhys; 2496 mc_filter[1] = mc_filter[0] = 0; 2497 netdev_for_each_mc_addr(ha, dev) { 2498 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2499 2500 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2501 rx_mode |= AcceptMulticast; 2502 } 2503 } 2504 2505 /* We can safely update without stopping the chip. */ 2506 tmp = rtl8139_rx_config | rx_mode; 2507 if (tp->rx_config != tmp) { 2508 RTL_W32_F (RxConfig, tmp); 2509 tp->rx_config = tmp; 2510 } 2511 RTL_W32_F (MAR0 + 0, mc_filter[0]); 2512 RTL_W32_F (MAR0 + 4, mc_filter[1]); 2513} 2514 2515static void rtl8139_set_rx_mode (struct net_device *dev) 2516{ 2517 unsigned long flags; 2518 struct rtl8139_private *tp = netdev_priv(dev); 2519 2520 spin_lock_irqsave (&tp->lock, flags); 2521 __set_rx_mode(dev); 2522 spin_unlock_irqrestore (&tp->lock, flags); 2523} 2524 2525#ifdef CONFIG_PM 2526 2527static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state) 2528{ 2529 struct net_device *dev = pci_get_drvdata (pdev); 2530 struct rtl8139_private *tp = netdev_priv(dev); 2531 void __iomem *ioaddr = tp->mmio_addr; 2532 unsigned long flags; 2533 2534 pci_save_state (pdev); 2535 2536 if (!netif_running (dev)) 2537 return 0; 2538 2539 netif_device_detach (dev); 2540 2541 spin_lock_irqsave (&tp->lock, flags); 2542 2543 /* Disable interrupts, stop Tx and Rx. */ 2544 RTL_W16 (IntrMask, 0); 2545 RTL_W8 (ChipCmd, 0); 2546 2547 /* Update the error counts. */ 2548 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2549 RTL_W32 (RxMissed, 0); 2550 2551 spin_unlock_irqrestore (&tp->lock, flags); 2552 2553 pci_set_power_state (pdev, PCI_D3hot); 2554 2555 return 0; 2556} 2557 2558 2559static int rtl8139_resume (struct pci_dev *pdev) 2560{ 2561 struct net_device *dev = pci_get_drvdata (pdev); 2562 2563 pci_restore_state (pdev); 2564 if (!netif_running (dev)) 2565 return 0; 2566 pci_set_power_state (pdev, PCI_D0); 2567 rtl8139_init_ring (dev); 2568 rtl8139_hw_start (dev); 2569 netif_device_attach (dev); 2570 return 0; 2571} 2572 2573#endif /* CONFIG_PM */ 2574 2575 2576static struct pci_driver rtl8139_pci_driver = { 2577 .name = DRV_NAME, 2578 .id_table = rtl8139_pci_tbl, 2579 .probe = rtl8139_init_one, 2580 .remove = __devexit_p(rtl8139_remove_one), 2581#ifdef CONFIG_PM 2582 .suspend = rtl8139_suspend, 2583 .resume = rtl8139_resume, 2584#endif /* CONFIG_PM */ 2585}; 2586 2587 2588static int __init rtl8139_init_module (void) 2589{ 2590 /* when we're a module, we always print a version message, 2591 * even if no 8139 board is found. 2592 */ 2593#ifdef MODULE 2594 pr_info(RTL8139_DRIVER_NAME "\n"); 2595#endif 2596 2597 return pci_register_driver(&rtl8139_pci_driver); 2598} 2599 2600 2601static void __exit rtl8139_cleanup_module (void) 2602{ 2603 pci_unregister_driver (&rtl8139_pci_driver); 2604} 2605 2606 2607module_init(rtl8139_init_module); 2608module_exit(rtl8139_cleanup_module); 2609