1/* 2 * drivers/mtd/nand.c 3 * 4 * Overview: 5 * This is the generic MTD driver for NAND flash devices. It should be 6 * capable of working with almost all NAND chips currently available. 7 * Basic support for AG-AND chips is provided. 8 * 9 * Additional technical information is available on 10 * http://www.linux-mtd.infradead.org/doc/nand.html 11 * 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 14 * 15 * Credits: 16 * David Woodhouse for adding multichip support 17 * 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 19 * rework for 2K page size chips 20 * 21 * TODO: 22 * Enable cached programming for 2k page size chips 23 * Check, if mtd->ecctype should be set to MTD_ECC_HW 24 * if we have HW ecc support. 25 * The AG-AND chips have nice features for speed improvement, 26 * which are not supported yet. Read / program 4 pages in one go. 27 * BBT table is not serialized, has to be fixed 28 * 29 * This program is free software; you can redistribute it and/or modify 30 * it under the terms of the GNU General Public License version 2 as 31 * published by the Free Software Foundation. 32 * 33 */ 34 35#include <linux/module.h> 36#include <linux/delay.h> 37#include <linux/errno.h> 38#include <linux/err.h> 39#include <linux/sched.h> 40#include <linux/slab.h> 41#include <linux/types.h> 42#include <linux/mtd/mtd.h> 43#include <linux/mtd/nand.h> 44#include <linux/mtd/nand_ecc.h> 45#include <linux/interrupt.h> 46#include <linux/bitops.h> 47#include <linux/leds.h> 48#include <asm/io.h> 49 50#ifdef CONFIG_MTD_PARTITIONS 51#include <linux/mtd/partitions.h> 52#endif 53 54/* Define default oob placement schemes for large and small page devices */ 55static struct nand_ecclayout nand_oob_8 = { 56 .eccbytes = 3, 57 .eccpos = {0, 1, 2}, 58 .oobfree = { 59 {.offset = 3, 60 .length = 2}, 61 {.offset = 6, 62 .length = 2}} 63}; 64 65static struct nand_ecclayout nand_oob_16 = { 66 .eccbytes = 6, 67 .eccpos = {0, 1, 2, 3, 6, 7}, 68 .oobfree = { 69 {.offset = 8, 70 . length = 8}} 71}; 72 73static struct nand_ecclayout nand_oob_64 = { 74 .eccbytes = 24, 75 .eccpos = { 76 40, 41, 42, 43, 44, 45, 46, 47, 77 48, 49, 50, 51, 52, 53, 54, 55, 78 56, 57, 58, 59, 60, 61, 62, 63}, 79 .oobfree = { 80 {.offset = 2, 81 .length = 38}} 82}; 83 84static struct nand_ecclayout nand_oob_128 = { 85 .eccbytes = 48, 86 .eccpos = { 87 80, 81, 82, 83, 84, 85, 86, 87, 88 88, 89, 90, 91, 92, 93, 94, 95, 89 96, 97, 98, 99, 100, 101, 102, 103, 90 104, 105, 106, 107, 108, 109, 110, 111, 91 112, 113, 114, 115, 116, 117, 118, 119, 92 120, 121, 122, 123, 124, 125, 126, 127}, 93 .oobfree = { 94 {.offset = 2, 95 .length = 78}} 96}; 97 98static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, 99 int new_state); 100 101static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 102 struct mtd_oob_ops *ops); 103 104/* 105 * For devices which display every fart in the system on a separate LED. Is 106 * compiled away when LED support is disabled. 107 */ 108DEFINE_LED_TRIGGER(nand_led_trigger); 109 110static int check_offs_len(struct mtd_info *mtd, 111 loff_t ofs, uint64_t len) 112{ 113 struct nand_chip *chip = mtd->priv; 114 int ret = 0; 115 116 /* Start address must align on block boundary */ 117 if (ofs & ((1 << chip->phys_erase_shift) - 1)) { 118 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__); 119 ret = -EINVAL; 120 } 121 122 /* Length must align on block boundary */ 123 if (len & ((1 << chip->phys_erase_shift) - 1)) { 124 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n", 125 __func__); 126 ret = -EINVAL; 127 } 128 129 /* Do not allow past end of device */ 130 if (ofs + len > mtd->size) { 131 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n", 132 __func__); 133 ret = -EINVAL; 134 } 135 136 return ret; 137} 138 139/** 140 * nand_release_device - [GENERIC] release chip 141 * @mtd: MTD device structure 142 * 143 * Deselect, release chip lock and wake up anyone waiting on the device 144 */ 145static void nand_release_device(struct mtd_info *mtd) 146{ 147 struct nand_chip *chip = mtd->priv; 148 149 /* De-select the NAND device */ 150 chip->select_chip(mtd, -1); 151 152 /* Release the controller and the chip */ 153 spin_lock(&chip->controller->lock); 154 chip->controller->active = NULL; 155 chip->state = FL_READY; 156 wake_up(&chip->controller->wq); 157 spin_unlock(&chip->controller->lock); 158} 159 160/** 161 * nand_read_byte - [DEFAULT] read one byte from the chip 162 * @mtd: MTD device structure 163 * 164 * Default read function for 8bit buswith 165 */ 166static uint8_t nand_read_byte(struct mtd_info *mtd) 167{ 168 struct nand_chip *chip = mtd->priv; 169 return readb(chip->IO_ADDR_R); 170} 171 172/** 173 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip 174 * @mtd: MTD device structure 175 * 176 * Default read function for 16bit buswith with 177 * endianess conversion 178 */ 179static uint8_t nand_read_byte16(struct mtd_info *mtd) 180{ 181 struct nand_chip *chip = mtd->priv; 182 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); 183} 184 185/** 186 * nand_read_word - [DEFAULT] read one word from the chip 187 * @mtd: MTD device structure 188 * 189 * Default read function for 16bit buswith without 190 * endianess conversion 191 */ 192static u16 nand_read_word(struct mtd_info *mtd) 193{ 194 struct nand_chip *chip = mtd->priv; 195 return readw(chip->IO_ADDR_R); 196} 197 198/** 199 * nand_select_chip - [DEFAULT] control CE line 200 * @mtd: MTD device structure 201 * @chipnr: chipnumber to select, -1 for deselect 202 * 203 * Default select function for 1 chip devices. 204 */ 205static void nand_select_chip(struct mtd_info *mtd, int chipnr) 206{ 207 struct nand_chip *chip = mtd->priv; 208 209 switch (chipnr) { 210 case -1: 211 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); 212 break; 213 case 0: 214 break; 215 216 default: 217 BUG(); 218 } 219} 220 221/** 222 * nand_write_buf - [DEFAULT] write buffer to chip 223 * @mtd: MTD device structure 224 * @buf: data buffer 225 * @len: number of bytes to write 226 * 227 * Default write function for 8bit buswith 228 */ 229static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 230{ 231 int i; 232 struct nand_chip *chip = mtd->priv; 233 234 for (i = 0; i < len; i++) 235 writeb(buf[i], chip->IO_ADDR_W); 236} 237 238/** 239 * nand_read_buf - [DEFAULT] read chip data into buffer 240 * @mtd: MTD device structure 241 * @buf: buffer to store date 242 * @len: number of bytes to read 243 * 244 * Default read function for 8bit buswith 245 */ 246static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 247{ 248 int i; 249 struct nand_chip *chip = mtd->priv; 250 251 for (i = 0; i < len; i++) 252 buf[i] = readb(chip->IO_ADDR_R); 253} 254 255/** 256 * nand_verify_buf - [DEFAULT] Verify chip data against buffer 257 * @mtd: MTD device structure 258 * @buf: buffer containing the data to compare 259 * @len: number of bytes to compare 260 * 261 * Default verify function for 8bit buswith 262 */ 263static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 264{ 265 int i; 266 struct nand_chip *chip = mtd->priv; 267 268 for (i = 0; i < len; i++) 269 if (buf[i] != readb(chip->IO_ADDR_R)) 270 return -EFAULT; 271 return 0; 272} 273 274/** 275 * nand_write_buf16 - [DEFAULT] write buffer to chip 276 * @mtd: MTD device structure 277 * @buf: data buffer 278 * @len: number of bytes to write 279 * 280 * Default write function for 16bit buswith 281 */ 282static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) 283{ 284 int i; 285 struct nand_chip *chip = mtd->priv; 286 u16 *p = (u16 *) buf; 287 len >>= 1; 288 289 for (i = 0; i < len; i++) 290 writew(p[i], chip->IO_ADDR_W); 291 292} 293 294/** 295 * nand_read_buf16 - [DEFAULT] read chip data into buffer 296 * @mtd: MTD device structure 297 * @buf: buffer to store date 298 * @len: number of bytes to read 299 * 300 * Default read function for 16bit buswith 301 */ 302static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) 303{ 304 int i; 305 struct nand_chip *chip = mtd->priv; 306 u16 *p = (u16 *) buf; 307 len >>= 1; 308 309 for (i = 0; i < len; i++) 310 p[i] = readw(chip->IO_ADDR_R); 311} 312 313/** 314 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer 315 * @mtd: MTD device structure 316 * @buf: buffer containing the data to compare 317 * @len: number of bytes to compare 318 * 319 * Default verify function for 16bit buswith 320 */ 321static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) 322{ 323 int i; 324 struct nand_chip *chip = mtd->priv; 325 u16 *p = (u16 *) buf; 326 len >>= 1; 327 328 for (i = 0; i < len; i++) 329 if (p[i] != readw(chip->IO_ADDR_R)) 330 return -EFAULT; 331 332 return 0; 333} 334 335/** 336 * nand_block_bad - [DEFAULT] Read bad block marker from the chip 337 * @mtd: MTD device structure 338 * @ofs: offset from device start 339 * @getchip: 0, if the chip is already selected 340 * 341 * Check, if the block is bad. 342 */ 343static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) 344{ 345 int page, chipnr, res = 0; 346 struct nand_chip *chip = mtd->priv; 347 u16 bad; 348 349 if (chip->options & NAND_BBT_SCANLASTPAGE) 350 ofs += mtd->erasesize - mtd->writesize; 351 352 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 353 354 if (getchip) { 355 chipnr = (int)(ofs >> chip->chip_shift); 356 357 nand_get_device(chip, mtd, FL_READING); 358 359 /* Select the NAND device */ 360 chip->select_chip(mtd, chipnr); 361 } 362 363 if (chip->options & NAND_BUSWIDTH_16) { 364 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, 365 page); 366 bad = cpu_to_le16(chip->read_word(mtd)); 367 if (chip->badblockpos & 0x1) 368 bad >>= 8; 369 else 370 bad &= 0xFF; 371 } else { 372 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); 373 bad = chip->read_byte(mtd); 374 } 375 376 if (likely(chip->badblockbits == 8)) 377 res = bad != 0xFF; 378 else 379 res = hweight8(bad) < chip->badblockbits; 380 381 if (getchip) 382 nand_release_device(mtd); 383 384 return res; 385} 386 387/** 388 * nand_default_block_markbad - [DEFAULT] mark a block bad 389 * @mtd: MTD device structure 390 * @ofs: offset from device start 391 * 392 * This is the default implementation, which can be overridden by 393 * a hardware specific driver. 394*/ 395static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) 396{ 397 struct nand_chip *chip = mtd->priv; 398 uint8_t buf[2] = { 0, 0 }; 399 int block, ret, i = 0; 400 401 if (chip->options & NAND_BBT_SCANLASTPAGE) 402 ofs += mtd->erasesize - mtd->writesize; 403 404 /* Get block number */ 405 block = (int)(ofs >> chip->bbt_erase_shift); 406 if (chip->bbt) 407 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); 408 409 /* Do we have a flash based bad block table ? */ 410 if (chip->options & NAND_USE_FLASH_BBT) 411 ret = nand_update_bbt(mtd, ofs); 412 else { 413 nand_get_device(chip, mtd, FL_WRITING); 414 415 /* Write to first two pages and to byte 1 and 6 if necessary. 416 * If we write to more than one location, the first error 417 * encountered quits the procedure. We write two bytes per 418 * location, so we dont have to mess with 16 bit access. 419 */ 420 do { 421 chip->ops.len = chip->ops.ooblen = 2; 422 chip->ops.datbuf = NULL; 423 chip->ops.oobbuf = buf; 424 chip->ops.ooboffs = chip->badblockpos & ~0x01; 425 426 ret = nand_do_write_oob(mtd, ofs, &chip->ops); 427 428 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) { 429 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS 430 & ~0x01; 431 ret = nand_do_write_oob(mtd, ofs, &chip->ops); 432 } 433 i++; 434 ofs += mtd->writesize; 435 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) && 436 i < 2); 437 438 nand_release_device(mtd); 439 } 440 if (!ret) 441 mtd->ecc_stats.badblocks++; 442 443 return ret; 444} 445 446/** 447 * nand_check_wp - [GENERIC] check if the chip is write protected 448 * @mtd: MTD device structure 449 * Check, if the device is write protected 450 * 451 * The function expects, that the device is already selected 452 */ 453static int nand_check_wp(struct mtd_info *mtd) 454{ 455 struct nand_chip *chip = mtd->priv; 456 457 /* broken xD cards report WP despite being writable */ 458 if (chip->options & NAND_BROKEN_XD) 459 return 0; 460 461 /* Check the WP bit */ 462 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 463 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; 464} 465 466/** 467 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 468 * @mtd: MTD device structure 469 * @ofs: offset from device start 470 * @getchip: 0, if the chip is already selected 471 * @allowbbt: 1, if its allowed to access the bbt area 472 * 473 * Check, if the block is bad. Either by reading the bad block table or 474 * calling of the scan function. 475 */ 476static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, 477 int allowbbt) 478{ 479 struct nand_chip *chip = mtd->priv; 480 481 if (!chip->bbt) 482 return chip->block_bad(mtd, ofs, getchip); 483 484 /* Return info from the table */ 485 return nand_isbad_bbt(mtd, ofs, allowbbt); 486} 487 488/** 489 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. 490 * @mtd: MTD device structure 491 * @timeo: Timeout 492 * 493 * Helper function for nand_wait_ready used when needing to wait in interrupt 494 * context. 495 */ 496static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) 497{ 498 struct nand_chip *chip = mtd->priv; 499 int i; 500 501 /* Wait for the device to get ready */ 502 for (i = 0; i < timeo; i++) { 503 if (chip->dev_ready(mtd)) 504 break; 505 touch_softlockup_watchdog(); 506 mdelay(1); 507 } 508} 509 510/* 511 * Wait for the ready pin, after a command 512 * The timeout is catched later. 513 */ 514void nand_wait_ready(struct mtd_info *mtd) 515{ 516 struct nand_chip *chip = mtd->priv; 517 unsigned long timeo = jiffies + 2; 518 519 /* 400ms timeout */ 520 if (in_interrupt() || oops_in_progress) 521 return panic_nand_wait_ready(mtd, 400); 522 523 led_trigger_event(nand_led_trigger, LED_FULL); 524 /* wait until command is processed or timeout occures */ 525 do { 526 if (chip->dev_ready(mtd)) 527 break; 528 touch_softlockup_watchdog(); 529 } while (time_before(jiffies, timeo)); 530 led_trigger_event(nand_led_trigger, LED_OFF); 531} 532EXPORT_SYMBOL_GPL(nand_wait_ready); 533 534/** 535 * nand_command - [DEFAULT] Send command to NAND device 536 * @mtd: MTD device structure 537 * @command: the command to be sent 538 * @column: the column address for this command, -1 if none 539 * @page_addr: the page address for this command, -1 if none 540 * 541 * Send command to NAND device. This function is used for small page 542 * devices (256/512 Bytes per page) 543 */ 544static void nand_command(struct mtd_info *mtd, unsigned int command, 545 int column, int page_addr) 546{ 547 register struct nand_chip *chip = mtd->priv; 548 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; 549 550 /* 551 * Write out the command to the device. 552 */ 553 if (command == NAND_CMD_SEQIN) { 554 int readcmd; 555 556 if (column >= mtd->writesize) { 557 /* OOB area */ 558 column -= mtd->writesize; 559 readcmd = NAND_CMD_READOOB; 560 } else if (column < 256) { 561 /* First 256 bytes --> READ0 */ 562 readcmd = NAND_CMD_READ0; 563 } else { 564 column -= 256; 565 readcmd = NAND_CMD_READ1; 566 } 567 chip->cmd_ctrl(mtd, readcmd, ctrl); 568 ctrl &= ~NAND_CTRL_CHANGE; 569 } 570 chip->cmd_ctrl(mtd, command, ctrl); 571 572 /* 573 * Address cycle, when necessary 574 */ 575 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; 576 /* Serially input address */ 577 if (column != -1) { 578 /* Adjust columns for 16 bit buswidth */ 579 if (chip->options & NAND_BUSWIDTH_16) 580 column >>= 1; 581 chip->cmd_ctrl(mtd, column, ctrl); 582 ctrl &= ~NAND_CTRL_CHANGE; 583 } 584 if (page_addr != -1) { 585 chip->cmd_ctrl(mtd, page_addr, ctrl); 586 ctrl &= ~NAND_CTRL_CHANGE; 587 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); 588 /* One more address cycle for devices > 32MiB */ 589 if (chip->chipsize > (32 << 20)) 590 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); 591 } 592 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 593 594 /* 595 * program and erase have their own busy handlers 596 * status and sequential in needs no delay 597 */ 598 switch (command) { 599 600 case NAND_CMD_PAGEPROG: 601 case NAND_CMD_ERASE1: 602 case NAND_CMD_ERASE2: 603 case NAND_CMD_SEQIN: 604 case NAND_CMD_STATUS: 605 return; 606 607 case NAND_CMD_RESET: 608 if (chip->dev_ready) 609 break; 610 udelay(chip->chip_delay); 611 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 612 NAND_CTRL_CLE | NAND_CTRL_CHANGE); 613 chip->cmd_ctrl(mtd, 614 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 615 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; 616 return; 617 618 /* This applies to read commands */ 619 default: 620 /* 621 * If we don't have access to the busy pin, we apply the given 622 * command delay 623 */ 624 if (!chip->dev_ready) { 625 udelay(chip->chip_delay); 626 return; 627 } 628 } 629 /* Apply this short delay always to ensure that we do wait tWB in 630 * any case on any machine. */ 631 ndelay(100); 632 633 nand_wait_ready(mtd); 634} 635 636/** 637 * nand_command_lp - [DEFAULT] Send command to NAND large page device 638 * @mtd: MTD device structure 639 * @command: the command to be sent 640 * @column: the column address for this command, -1 if none 641 * @page_addr: the page address for this command, -1 if none 642 * 643 * Send command to NAND device. This is the version for the new large page 644 * devices We dont have the separate regions as we have in the small page 645 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. 646 */ 647static void nand_command_lp(struct mtd_info *mtd, unsigned int command, 648 int column, int page_addr) 649{ 650 register struct nand_chip *chip = mtd->priv; 651 652 /* Emulate NAND_CMD_READOOB */ 653 if (command == NAND_CMD_READOOB) { 654 column += mtd->writesize; 655 command = NAND_CMD_READ0; 656 } 657 658 /* Command latch cycle */ 659 chip->cmd_ctrl(mtd, command & 0xff, 660 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 661 662 if (column != -1 || page_addr != -1) { 663 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; 664 665 /* Serially input address */ 666 if (column != -1) { 667 /* Adjust columns for 16 bit buswidth */ 668 if (chip->options & NAND_BUSWIDTH_16) 669 column >>= 1; 670 chip->cmd_ctrl(mtd, column, ctrl); 671 ctrl &= ~NAND_CTRL_CHANGE; 672 chip->cmd_ctrl(mtd, column >> 8, ctrl); 673 } 674 if (page_addr != -1) { 675 chip->cmd_ctrl(mtd, page_addr, ctrl); 676 chip->cmd_ctrl(mtd, page_addr >> 8, 677 NAND_NCE | NAND_ALE); 678 /* One more address cycle for devices > 128MiB */ 679 if (chip->chipsize > (128 << 20)) 680 chip->cmd_ctrl(mtd, page_addr >> 16, 681 NAND_NCE | NAND_ALE); 682 } 683 } 684 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 685 686 /* 687 * program and erase have their own busy handlers 688 * status, sequential in, and deplete1 need no delay 689 */ 690 switch (command) { 691 692 case NAND_CMD_CACHEDPROG: 693 case NAND_CMD_PAGEPROG: 694 case NAND_CMD_ERASE1: 695 case NAND_CMD_ERASE2: 696 case NAND_CMD_SEQIN: 697 case NAND_CMD_RNDIN: 698 case NAND_CMD_STATUS: 699 case NAND_CMD_DEPLETE1: 700 return; 701 702 /* 703 * read error status commands require only a short delay 704 */ 705 case NAND_CMD_STATUS_ERROR: 706 case NAND_CMD_STATUS_ERROR0: 707 case NAND_CMD_STATUS_ERROR1: 708 case NAND_CMD_STATUS_ERROR2: 709 case NAND_CMD_STATUS_ERROR3: 710 udelay(chip->chip_delay); 711 return; 712 713 case NAND_CMD_RESET: 714 if (chip->dev_ready) 715 break; 716 udelay(chip->chip_delay); 717 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 718 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 719 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 720 NAND_NCE | NAND_CTRL_CHANGE); 721 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; 722 return; 723 724 case NAND_CMD_RNDOUT: 725 /* No ready / busy check necessary */ 726 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, 727 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 728 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 729 NAND_NCE | NAND_CTRL_CHANGE); 730 return; 731 732 case NAND_CMD_READ0: 733 chip->cmd_ctrl(mtd, NAND_CMD_READSTART, 734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 735 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 736 NAND_NCE | NAND_CTRL_CHANGE); 737 738 /* This applies to read commands */ 739 default: 740 /* 741 * If we don't have access to the busy pin, we apply the given 742 * command delay 743 */ 744 if (!chip->dev_ready) { 745 udelay(chip->chip_delay); 746 return; 747 } 748 } 749 750 /* Apply this short delay always to ensure that we do wait tWB in 751 * any case on any machine. */ 752 ndelay(100); 753 754 nand_wait_ready(mtd); 755} 756 757/** 758 * panic_nand_get_device - [GENERIC] Get chip for selected access 759 * @chip: the nand chip descriptor 760 * @mtd: MTD device structure 761 * @new_state: the state which is requested 762 * 763 * Used when in panic, no locks are taken. 764 */ 765static void panic_nand_get_device(struct nand_chip *chip, 766 struct mtd_info *mtd, int new_state) 767{ 768 /* Hardware controller shared among independend devices */ 769 chip->controller->active = chip; 770 chip->state = new_state; 771} 772 773/** 774 * nand_get_device - [GENERIC] Get chip for selected access 775 * @chip: the nand chip descriptor 776 * @mtd: MTD device structure 777 * @new_state: the state which is requested 778 * 779 * Get the device and lock it for exclusive access 780 */ 781static int 782nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) 783{ 784 spinlock_t *lock = &chip->controller->lock; 785 wait_queue_head_t *wq = &chip->controller->wq; 786 DECLARE_WAITQUEUE(wait, current); 787 retry: 788 spin_lock(lock); 789 790 /* Hardware controller shared among independent devices */ 791 if (!chip->controller->active) 792 chip->controller->active = chip; 793 794 if (chip->controller->active == chip && chip->state == FL_READY) { 795 chip->state = new_state; 796 spin_unlock(lock); 797 return 0; 798 } 799 if (new_state == FL_PM_SUSPENDED) { 800 if (chip->controller->active->state == FL_PM_SUSPENDED) { 801 chip->state = FL_PM_SUSPENDED; 802 spin_unlock(lock); 803 return 0; 804 } 805 } 806 set_current_state(TASK_UNINTERRUPTIBLE); 807 add_wait_queue(wq, &wait); 808 spin_unlock(lock); 809 schedule(); 810 remove_wait_queue(wq, &wait); 811 goto retry; 812} 813 814/** 815 * panic_nand_wait - [GENERIC] wait until the command is done 816 * @mtd: MTD device structure 817 * @chip: NAND chip structure 818 * @timeo: Timeout 819 * 820 * Wait for command done. This is a helper function for nand_wait used when 821 * we are in interrupt context. May happen when in panic and trying to write 822 * an oops trough mtdoops. 823 */ 824static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, 825 unsigned long timeo) 826{ 827 int i; 828 for (i = 0; i < timeo; i++) { 829 if (chip->dev_ready) { 830 if (chip->dev_ready(mtd)) 831 break; 832 } else { 833 if (chip->read_byte(mtd) & NAND_STATUS_READY) 834 break; 835 } 836 mdelay(1); 837 } 838} 839 840/** 841 * nand_wait - [DEFAULT] wait until the command is done 842 * @mtd: MTD device structure 843 * @chip: NAND chip structure 844 * 845 * Wait for command done. This applies to erase and program only 846 * Erase can take up to 400ms and program up to 20ms according to 847 * general NAND and SmartMedia specs 848 */ 849static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) 850{ 851 852 unsigned long timeo = jiffies; 853 int status, state = chip->state; 854 855 if (state == FL_ERASING) 856 timeo += (HZ * 400) / 1000; 857 else 858 timeo += (HZ * 20) / 1000; 859 860 led_trigger_event(nand_led_trigger, LED_FULL); 861 862 /* Apply this short delay always to ensure that we do wait tWB in 863 * any case on any machine. */ 864 ndelay(100); 865 866 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) 867 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); 868 else 869 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 870 871 if (in_interrupt() || oops_in_progress) 872 panic_nand_wait(mtd, chip, timeo); 873 else { 874 while (time_before(jiffies, timeo)) { 875 if (chip->dev_ready) { 876 if (chip->dev_ready(mtd)) 877 break; 878 } else { 879 if (chip->read_byte(mtd) & NAND_STATUS_READY) 880 break; 881 } 882 cond_resched(); 883 } 884 } 885 led_trigger_event(nand_led_trigger, LED_OFF); 886 887 status = (int)chip->read_byte(mtd); 888 return status; 889} 890 891/** 892 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks 893 * 894 * @mtd: mtd info 895 * @ofs: offset to start unlock from 896 * @len: length to unlock 897 * @invert: when = 0, unlock the range of blocks within the lower and 898 * upper boundary address 899 * when = 1, unlock the range of blocks outside the boundaries 900 * of the lower and upper boundary address 901 * 902 * return - unlock status 903 */ 904static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, 905 uint64_t len, int invert) 906{ 907 int ret = 0; 908 int status, page; 909 struct nand_chip *chip = mtd->priv; 910 911 /* Submit address of first page to unlock */ 912 page = ofs >> chip->page_shift; 913 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); 914 915 /* Submit address of last page to unlock */ 916 page = (ofs + len) >> chip->page_shift; 917 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, 918 (page | invert) & chip->pagemask); 919 920 /* Call wait ready function */ 921 status = chip->waitfunc(mtd, chip); 922 udelay(1000); 923 /* See if device thinks it succeeded */ 924 if (status & 0x01) { 925 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", 926 __func__, status); 927 ret = -EIO; 928 } 929 930 return ret; 931} 932 933/** 934 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks 935 * 936 * @mtd: mtd info 937 * @ofs: offset to start unlock from 938 * @len: length to unlock 939 * 940 * return - unlock status 941 */ 942int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 943{ 944 int ret = 0; 945 int chipnr; 946 struct nand_chip *chip = mtd->priv; 947 948 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", 949 __func__, (unsigned long long)ofs, len); 950 951 if (check_offs_len(mtd, ofs, len)) 952 ret = -EINVAL; 953 954 /* Align to last block address if size addresses end of the device */ 955 if (ofs + len == mtd->size) 956 len -= mtd->erasesize; 957 958 nand_get_device(chip, mtd, FL_UNLOCKING); 959 960 /* Shift to get chip number */ 961 chipnr = ofs >> chip->chip_shift; 962 963 chip->select_chip(mtd, chipnr); 964 965 /* Check, if it is write protected */ 966 if (nand_check_wp(mtd)) { 967 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", 968 __func__); 969 ret = -EIO; 970 goto out; 971 } 972 973 ret = __nand_unlock(mtd, ofs, len, 0); 974 975out: 976 /* de-select the NAND device */ 977 chip->select_chip(mtd, -1); 978 979 nand_release_device(mtd); 980 981 return ret; 982} 983 984/** 985 * nand_lock - [REPLACEABLE] locks all blocks present in the device 986 * 987 * @mtd: mtd info 988 * @ofs: offset to start unlock from 989 * @len: length to unlock 990 * 991 * return - lock status 992 * 993 * This feature is not supported in many NAND parts. 'Micron' NAND parts 994 * do have this feature, but it allows only to lock all blocks, not for 995 * specified range for block. 996 * 997 * Implementing 'lock' feature by making use of 'unlock', for now. 998 */ 999int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 1000{ 1001 int ret = 0; 1002 int chipnr, status, page; 1003 struct nand_chip *chip = mtd->priv; 1004 1005 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", 1006 __func__, (unsigned long long)ofs, len); 1007 1008 if (check_offs_len(mtd, ofs, len)) 1009 ret = -EINVAL; 1010 1011 nand_get_device(chip, mtd, FL_LOCKING); 1012 1013 /* Shift to get chip number */ 1014 chipnr = ofs >> chip->chip_shift; 1015 1016 chip->select_chip(mtd, chipnr); 1017 1018 /* Check, if it is write protected */ 1019 if (nand_check_wp(mtd)) { 1020 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", 1021 __func__); 1022 status = MTD_ERASE_FAILED; 1023 ret = -EIO; 1024 goto out; 1025 } 1026 1027 /* Submit address of first page to lock */ 1028 page = ofs >> chip->page_shift; 1029 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); 1030 1031 /* Call wait ready function */ 1032 status = chip->waitfunc(mtd, chip); 1033 udelay(1000); 1034 /* See if device thinks it succeeded */ 1035 if (status & 0x01) { 1036 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", 1037 __func__, status); 1038 ret = -EIO; 1039 goto out; 1040 } 1041 1042 ret = __nand_unlock(mtd, ofs, len, 0x1); 1043 1044out: 1045 /* de-select the NAND device */ 1046 chip->select_chip(mtd, -1); 1047 1048 nand_release_device(mtd); 1049 1050 return ret; 1051} 1052 1053/** 1054 * nand_read_page_raw - [Intern] read raw page data without ecc 1055 * @mtd: mtd info structure 1056 * @chip: nand chip info structure 1057 * @buf: buffer to store read data 1058 * @page: page number to read 1059 * 1060 * Not for syndrome calculating ecc controllers, which use a special oob layout 1061 */ 1062static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1063 uint8_t *buf, int page) 1064{ 1065 chip->read_buf(mtd, buf, mtd->writesize); 1066 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1067 return 0; 1068} 1069 1070/** 1071 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc 1072 * @mtd: mtd info structure 1073 * @chip: nand chip info structure 1074 * @buf: buffer to store read data 1075 * @page: page number to read 1076 * 1077 * We need a special oob layout and handling even when OOB isn't used. 1078 */ 1079static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1080 uint8_t *buf, int page) 1081{ 1082 int eccsize = chip->ecc.size; 1083 int eccbytes = chip->ecc.bytes; 1084 uint8_t *oob = chip->oob_poi; 1085 int steps, size; 1086 1087 for (steps = chip->ecc.steps; steps > 0; steps--) { 1088 chip->read_buf(mtd, buf, eccsize); 1089 buf += eccsize; 1090 1091 if (chip->ecc.prepad) { 1092 chip->read_buf(mtd, oob, chip->ecc.prepad); 1093 oob += chip->ecc.prepad; 1094 } 1095 1096 chip->read_buf(mtd, oob, eccbytes); 1097 oob += eccbytes; 1098 1099 if (chip->ecc.postpad) { 1100 chip->read_buf(mtd, oob, chip->ecc.postpad); 1101 oob += chip->ecc.postpad; 1102 } 1103 } 1104 1105 size = mtd->oobsize - (oob - chip->oob_poi); 1106 if (size) 1107 chip->read_buf(mtd, oob, size); 1108 1109 return 0; 1110} 1111 1112/** 1113 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function 1114 * @mtd: mtd info structure 1115 * @chip: nand chip info structure 1116 * @buf: buffer to store read data 1117 * @page: page number to read 1118 */ 1119static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 1120 uint8_t *buf, int page) 1121{ 1122 int i, eccsize = chip->ecc.size; 1123 int eccbytes = chip->ecc.bytes; 1124 int eccsteps = chip->ecc.steps; 1125 uint8_t *p = buf; 1126 uint8_t *ecc_calc = chip->buffers->ecccalc; 1127 uint8_t *ecc_code = chip->buffers->ecccode; 1128 uint32_t *eccpos = chip->ecc.layout->eccpos; 1129 1130 chip->ecc.read_page_raw(mtd, chip, buf, page); 1131 1132 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 1133 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1134 1135 for (i = 0; i < chip->ecc.total; i++) 1136 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1137 1138 eccsteps = chip->ecc.steps; 1139 p = buf; 1140 1141 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1142 int stat; 1143 1144 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 1145 if (stat < 0) 1146 mtd->ecc_stats.failed++; 1147 else 1148 mtd->ecc_stats.corrected += stat; 1149 } 1150 return 0; 1151} 1152 1153/** 1154 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function 1155 * @mtd: mtd info structure 1156 * @chip: nand chip info structure 1157 * @data_offs: offset of requested data within the page 1158 * @readlen: data length 1159 * @bufpoi: buffer to store read data 1160 */ 1161static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) 1162{ 1163 int start_step, end_step, num_steps; 1164 uint32_t *eccpos = chip->ecc.layout->eccpos; 1165 uint8_t *p; 1166 int data_col_addr, i, gaps = 0; 1167 int datafrag_len, eccfrag_len, aligned_len, aligned_pos; 1168 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; 1169 1170 /* Column address wihin the page aligned to ECC size (256bytes). */ 1171 start_step = data_offs / chip->ecc.size; 1172 end_step = (data_offs + readlen - 1) / chip->ecc.size; 1173 num_steps = end_step - start_step + 1; 1174 1175 /* Data size aligned to ECC ecc.size*/ 1176 datafrag_len = num_steps * chip->ecc.size; 1177 eccfrag_len = num_steps * chip->ecc.bytes; 1178 1179 data_col_addr = start_step * chip->ecc.size; 1180 /* If we read not a page aligned data */ 1181 if (data_col_addr != 0) 1182 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); 1183 1184 p = bufpoi + data_col_addr; 1185 chip->read_buf(mtd, p, datafrag_len); 1186 1187 /* Calculate ECC */ 1188 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) 1189 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); 1190 1191 /* The performance is faster if to position offsets 1192 according to ecc.pos. Let make sure here that 1193 there are no gaps in ecc positions */ 1194 for (i = 0; i < eccfrag_len - 1; i++) { 1195 if (eccpos[i + start_step * chip->ecc.bytes] + 1 != 1196 eccpos[i + start_step * chip->ecc.bytes + 1]) { 1197 gaps = 1; 1198 break; 1199 } 1200 } 1201 if (gaps) { 1202 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); 1203 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1204 } else { 1205 /* send the command to read the particular ecc bytes */ 1206 /* take care about buswidth alignment in read_buf */ 1207 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1); 1208 aligned_len = eccfrag_len; 1209 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1)) 1210 aligned_len++; 1211 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1)) 1212 aligned_len++; 1213 1214 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1); 1215 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); 1216 } 1217 1218 for (i = 0; i < eccfrag_len; i++) 1219 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]]; 1220 1221 p = bufpoi + data_col_addr; 1222 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { 1223 int stat; 1224 1225 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); 1226 if (stat == -1) 1227 mtd->ecc_stats.failed++; 1228 else 1229 mtd->ecc_stats.corrected += stat; 1230 } 1231 return 0; 1232} 1233 1234/** 1235 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function 1236 * @mtd: mtd info structure 1237 * @chip: nand chip info structure 1238 * @buf: buffer to store read data 1239 * @page: page number to read 1240 * 1241 * Not for syndrome calculating ecc controllers which need a special oob layout 1242 */ 1243static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 1244 uint8_t *buf, int page) 1245{ 1246 int i, eccsize = chip->ecc.size; 1247 int eccbytes = chip->ecc.bytes; 1248 int eccsteps = chip->ecc.steps; 1249 uint8_t *p = buf; 1250 uint8_t *ecc_calc = chip->buffers->ecccalc; 1251 uint8_t *ecc_code = chip->buffers->ecccode; 1252 uint32_t *eccpos = chip->ecc.layout->eccpos; 1253 1254 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1255 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1256 chip->read_buf(mtd, p, eccsize); 1257 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1258 } 1259 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1260 1261 for (i = 0; i < chip->ecc.total; i++) 1262 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1263 1264 eccsteps = chip->ecc.steps; 1265 p = buf; 1266 1267 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1268 int stat; 1269 1270 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 1271 if (stat < 0) 1272 mtd->ecc_stats.failed++; 1273 else 1274 mtd->ecc_stats.corrected += stat; 1275 } 1276 return 0; 1277} 1278 1279/** 1280 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first 1281 * @mtd: mtd info structure 1282 * @chip: nand chip info structure 1283 * @buf: buffer to store read data 1284 * @page: page number to read 1285 * 1286 * Hardware ECC for large page chips, require OOB to be read first. 1287 * For this ECC mode, the write_page method is re-used from ECC_HW. 1288 * These methods read/write ECC from the OOB area, unlike the 1289 * ECC_HW_SYNDROME support with multiple ECC steps, follows the 1290 * "infix ECC" scheme and reads/writes ECC from the data area, by 1291 * overwriting the NAND manufacturer bad block markings. 1292 */ 1293static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, 1294 struct nand_chip *chip, uint8_t *buf, int page) 1295{ 1296 int i, eccsize = chip->ecc.size; 1297 int eccbytes = chip->ecc.bytes; 1298 int eccsteps = chip->ecc.steps; 1299 uint8_t *p = buf; 1300 uint8_t *ecc_code = chip->buffers->ecccode; 1301 uint32_t *eccpos = chip->ecc.layout->eccpos; 1302 uint8_t *ecc_calc = chip->buffers->ecccalc; 1303 1304 /* Read the OOB area first */ 1305 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 1306 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1307 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); 1308 1309 for (i = 0; i < chip->ecc.total; i++) 1310 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1311 1312 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1313 int stat; 1314 1315 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1316 chip->read_buf(mtd, p, eccsize); 1317 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1318 1319 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); 1320 if (stat < 0) 1321 mtd->ecc_stats.failed++; 1322 else 1323 mtd->ecc_stats.corrected += stat; 1324 } 1325 return 0; 1326} 1327 1328/** 1329 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read 1330 * @mtd: mtd info structure 1331 * @chip: nand chip info structure 1332 * @buf: buffer to store read data 1333 * @page: page number to read 1334 * 1335 * The hw generator calculates the error syndrome automatically. Therefor 1336 * we need a special oob layout and handling. 1337 */ 1338static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1339 uint8_t *buf, int page) 1340{ 1341 int i, eccsize = chip->ecc.size; 1342 int eccbytes = chip->ecc.bytes; 1343 int eccsteps = chip->ecc.steps; 1344 uint8_t *p = buf; 1345 uint8_t *oob = chip->oob_poi; 1346 1347 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1348 int stat; 1349 1350 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1351 chip->read_buf(mtd, p, eccsize); 1352 1353 if (chip->ecc.prepad) { 1354 chip->read_buf(mtd, oob, chip->ecc.prepad); 1355 oob += chip->ecc.prepad; 1356 } 1357 1358 chip->ecc.hwctl(mtd, NAND_ECC_READSYN); 1359 chip->read_buf(mtd, oob, eccbytes); 1360 stat = chip->ecc.correct(mtd, p, oob, NULL); 1361 1362 if (stat < 0) 1363 mtd->ecc_stats.failed++; 1364 else 1365 mtd->ecc_stats.corrected += stat; 1366 1367 oob += eccbytes; 1368 1369 if (chip->ecc.postpad) { 1370 chip->read_buf(mtd, oob, chip->ecc.postpad); 1371 oob += chip->ecc.postpad; 1372 } 1373 } 1374 1375 /* Calculate remaining oob bytes */ 1376 i = mtd->oobsize - (oob - chip->oob_poi); 1377 if (i) 1378 chip->read_buf(mtd, oob, i); 1379 1380 return 0; 1381} 1382 1383/** 1384 * nand_transfer_oob - [Internal] Transfer oob to client buffer 1385 * @chip: nand chip structure 1386 * @oob: oob destination address 1387 * @ops: oob ops structure 1388 * @len: size of oob to transfer 1389 */ 1390static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, 1391 struct mtd_oob_ops *ops, size_t len) 1392{ 1393 switch(ops->mode) { 1394 1395 case MTD_OOB_PLACE: 1396 case MTD_OOB_RAW: 1397 memcpy(oob, chip->oob_poi + ops->ooboffs, len); 1398 return oob + len; 1399 1400 case MTD_OOB_AUTO: { 1401 struct nand_oobfree *free = chip->ecc.layout->oobfree; 1402 uint32_t boffs = 0, roffs = ops->ooboffs; 1403 size_t bytes = 0; 1404 1405 for(; free->length && len; free++, len -= bytes) { 1406 /* Read request not from offset 0 ? */ 1407 if (unlikely(roffs)) { 1408 if (roffs >= free->length) { 1409 roffs -= free->length; 1410 continue; 1411 } 1412 boffs = free->offset + roffs; 1413 bytes = min_t(size_t, len, 1414 (free->length - roffs)); 1415 roffs = 0; 1416 } else { 1417 bytes = min_t(size_t, len, free->length); 1418 boffs = free->offset; 1419 } 1420 memcpy(oob, chip->oob_poi + boffs, bytes); 1421 oob += bytes; 1422 } 1423 return oob; 1424 } 1425 default: 1426 BUG(); 1427 } 1428 return NULL; 1429} 1430 1431/** 1432 * nand_do_read_ops - [Internal] Read data with ECC 1433 * 1434 * @mtd: MTD device structure 1435 * @from: offset to read from 1436 * @ops: oob ops structure 1437 * 1438 * Internal function. Called with chip held. 1439 */ 1440static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, 1441 struct mtd_oob_ops *ops) 1442{ 1443 int chipnr, page, realpage, col, bytes, aligned; 1444 struct nand_chip *chip = mtd->priv; 1445 struct mtd_ecc_stats stats; 1446 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; 1447 int sndcmd = 1; 1448 int ret = 0; 1449 uint32_t readlen = ops->len; 1450 uint32_t oobreadlen = ops->ooblen; 1451 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ? 1452 mtd->oobavail : mtd->oobsize; 1453 1454 uint8_t *bufpoi, *oob, *buf; 1455 1456 stats = mtd->ecc_stats; 1457 1458 chipnr = (int)(from >> chip->chip_shift); 1459 chip->select_chip(mtd, chipnr); 1460 1461 realpage = (int)(from >> chip->page_shift); 1462 page = realpage & chip->pagemask; 1463 1464 col = (int)(from & (mtd->writesize - 1)); 1465 1466 buf = ops->datbuf; 1467 oob = ops->oobbuf; 1468 1469 while(1) { 1470 bytes = min(mtd->writesize - col, readlen); 1471 aligned = (bytes == mtd->writesize); 1472 1473 /* Is the current page in the buffer ? */ 1474 if (realpage != chip->pagebuf || oob) { 1475 bufpoi = aligned ? buf : chip->buffers->databuf; 1476 1477 if (likely(sndcmd)) { 1478 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 1479 sndcmd = 0; 1480 } 1481 1482 /* Now read the page into the buffer */ 1483 if (unlikely(ops->mode == MTD_OOB_RAW)) 1484 ret = chip->ecc.read_page_raw(mtd, chip, 1485 bufpoi, page); 1486 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) 1487 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); 1488 else 1489 ret = chip->ecc.read_page(mtd, chip, bufpoi, 1490 page); 1491 if (ret < 0) 1492 break; 1493 1494 /* Transfer not aligned data */ 1495 if (!aligned) { 1496 if (!NAND_SUBPAGE_READ(chip) && !oob) 1497 chip->pagebuf = realpage; 1498 memcpy(buf, chip->buffers->databuf + col, bytes); 1499 } 1500 1501 buf += bytes; 1502 1503 if (unlikely(oob)) { 1504 1505 int toread = min(oobreadlen, max_oobsize); 1506 1507 if (toread) { 1508 oob = nand_transfer_oob(chip, 1509 oob, ops, toread); 1510 oobreadlen -= toread; 1511 } 1512 } 1513 1514 if (!(chip->options & NAND_NO_READRDY)) { 1515 /* 1516 * Apply delay or wait for ready/busy pin. Do 1517 * this before the AUTOINCR check, so no 1518 * problems arise if a chip which does auto 1519 * increment is marked as NOAUTOINCR by the 1520 * board driver. 1521 */ 1522 if (!chip->dev_ready) 1523 udelay(chip->chip_delay); 1524 else 1525 nand_wait_ready(mtd); 1526 } 1527 } else { 1528 memcpy(buf, chip->buffers->databuf + col, bytes); 1529 buf += bytes; 1530 } 1531 1532 readlen -= bytes; 1533 1534 if (!readlen) 1535 break; 1536 1537 /* For subsequent reads align to page boundary. */ 1538 col = 0; 1539 /* Increment page address */ 1540 realpage++; 1541 1542 page = realpage & chip->pagemask; 1543 /* Check, if we cross a chip boundary */ 1544 if (!page) { 1545 chipnr++; 1546 chip->select_chip(mtd, -1); 1547 chip->select_chip(mtd, chipnr); 1548 } 1549 1550 /* Check, if the chip supports auto page increment 1551 * or if we have hit a block boundary. 1552 */ 1553 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) 1554 sndcmd = 1; 1555 } 1556 1557 ops->retlen = ops->len - (size_t) readlen; 1558 if (oob) 1559 ops->oobretlen = ops->ooblen - oobreadlen; 1560 1561 if (ret) 1562 return ret; 1563 1564 if (mtd->ecc_stats.failed - stats.failed) 1565 return -EBADMSG; 1566 1567 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; 1568} 1569 1570/** 1571 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc 1572 * @mtd: MTD device structure 1573 * @from: offset to read from 1574 * @len: number of bytes to read 1575 * @retlen: pointer to variable to store the number of read bytes 1576 * @buf: the databuffer to put data 1577 * 1578 * Get hold of the chip and call nand_do_read 1579 */ 1580static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, 1581 size_t *retlen, uint8_t *buf) 1582{ 1583 struct nand_chip *chip = mtd->priv; 1584 int ret; 1585 1586 /* Do not allow reads past end of device */ 1587 if ((from + len) > mtd->size) 1588 return -EINVAL; 1589 if (!len) 1590 return 0; 1591 1592 nand_get_device(chip, mtd, FL_READING); 1593 1594 chip->ops.len = len; 1595 chip->ops.datbuf = buf; 1596 chip->ops.oobbuf = NULL; 1597 1598 ret = nand_do_read_ops(mtd, from, &chip->ops); 1599 1600 *retlen = chip->ops.retlen; 1601 1602 nand_release_device(mtd); 1603 1604 return ret; 1605} 1606 1607/** 1608 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function 1609 * @mtd: mtd info structure 1610 * @chip: nand chip info structure 1611 * @page: page number to read 1612 * @sndcmd: flag whether to issue read command or not 1613 */ 1614static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1615 int page, int sndcmd) 1616{ 1617 if (sndcmd) { 1618 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 1619 sndcmd = 0; 1620 } 1621 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1622 return sndcmd; 1623} 1624 1625/** 1626 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC 1627 * with syndromes 1628 * @mtd: mtd info structure 1629 * @chip: nand chip info structure 1630 * @page: page number to read 1631 * @sndcmd: flag whether to issue read command or not 1632 */ 1633static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1634 int page, int sndcmd) 1635{ 1636 uint8_t *buf = chip->oob_poi; 1637 int length = mtd->oobsize; 1638 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 1639 int eccsize = chip->ecc.size; 1640 uint8_t *bufpoi = buf; 1641 int i, toread, sndrnd = 0, pos; 1642 1643 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); 1644 for (i = 0; i < chip->ecc.steps; i++) { 1645 if (sndrnd) { 1646 pos = eccsize + i * (eccsize + chunk); 1647 if (mtd->writesize > 512) 1648 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); 1649 else 1650 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); 1651 } else 1652 sndrnd = 1; 1653 toread = min_t(int, length, chunk); 1654 chip->read_buf(mtd, bufpoi, toread); 1655 bufpoi += toread; 1656 length -= toread; 1657 } 1658 if (length > 0) 1659 chip->read_buf(mtd, bufpoi, length); 1660 1661 return 1; 1662} 1663 1664/** 1665 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function 1666 * @mtd: mtd info structure 1667 * @chip: nand chip info structure 1668 * @page: page number to write 1669 */ 1670static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1671 int page) 1672{ 1673 int status = 0; 1674 const uint8_t *buf = chip->oob_poi; 1675 int length = mtd->oobsize; 1676 1677 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 1678 chip->write_buf(mtd, buf, length); 1679 /* Send command to program the OOB data */ 1680 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1681 1682 status = chip->waitfunc(mtd, chip); 1683 1684 return status & NAND_STATUS_FAIL ? -EIO : 0; 1685} 1686 1687/** 1688 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC 1689 * with syndrome - only for large page flash ! 1690 * @mtd: mtd info structure 1691 * @chip: nand chip info structure 1692 * @page: page number to write 1693 */ 1694static int nand_write_oob_syndrome(struct mtd_info *mtd, 1695 struct nand_chip *chip, int page) 1696{ 1697 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 1698 int eccsize = chip->ecc.size, length = mtd->oobsize; 1699 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; 1700 const uint8_t *bufpoi = chip->oob_poi; 1701 1702 /* 1703 * data-ecc-data-ecc ... ecc-oob 1704 * or 1705 * data-pad-ecc-pad-data-pad .... ecc-pad-oob 1706 */ 1707 if (!chip->ecc.prepad && !chip->ecc.postpad) { 1708 pos = steps * (eccsize + chunk); 1709 steps = 0; 1710 } else 1711 pos = eccsize; 1712 1713 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); 1714 for (i = 0; i < steps; i++) { 1715 if (sndcmd) { 1716 if (mtd->writesize <= 512) { 1717 uint32_t fill = 0xFFFFFFFF; 1718 1719 len = eccsize; 1720 while (len > 0) { 1721 int num = min_t(int, len, 4); 1722 chip->write_buf(mtd, (uint8_t *)&fill, 1723 num); 1724 len -= num; 1725 } 1726 } else { 1727 pos = eccsize + i * (eccsize + chunk); 1728 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); 1729 } 1730 } else 1731 sndcmd = 1; 1732 len = min_t(int, length, chunk); 1733 chip->write_buf(mtd, bufpoi, len); 1734 bufpoi += len; 1735 length -= len; 1736 } 1737 if (length > 0) 1738 chip->write_buf(mtd, bufpoi, length); 1739 1740 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1741 status = chip->waitfunc(mtd, chip); 1742 1743 return status & NAND_STATUS_FAIL ? -EIO : 0; 1744} 1745 1746/** 1747 * nand_do_read_oob - [Intern] NAND read out-of-band 1748 * @mtd: MTD device structure 1749 * @from: offset to read from 1750 * @ops: oob operations description structure 1751 * 1752 * NAND read out-of-band data from the spare area 1753 */ 1754static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, 1755 struct mtd_oob_ops *ops) 1756{ 1757 int page, realpage, chipnr, sndcmd = 1; 1758 struct nand_chip *chip = mtd->priv; 1759 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; 1760 int readlen = ops->ooblen; 1761 int len; 1762 uint8_t *buf = ops->oobbuf; 1763 1764 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n", 1765 __func__, (unsigned long long)from, readlen); 1766 1767 if (ops->mode == MTD_OOB_AUTO) 1768 len = chip->ecc.layout->oobavail; 1769 else 1770 len = mtd->oobsize; 1771 1772 if (unlikely(ops->ooboffs >= len)) { 1773 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read " 1774 "outside oob\n", __func__); 1775 return -EINVAL; 1776 } 1777 1778 /* Do not allow reads past end of device */ 1779 if (unlikely(from >= mtd->size || 1780 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - 1781 (from >> chip->page_shift)) * len)) { 1782 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end " 1783 "of device\n", __func__); 1784 return -EINVAL; 1785 } 1786 1787 chipnr = (int)(from >> chip->chip_shift); 1788 chip->select_chip(mtd, chipnr); 1789 1790 /* Shift to get page */ 1791 realpage = (int)(from >> chip->page_shift); 1792 page = realpage & chip->pagemask; 1793 1794 while(1) { 1795 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); 1796 1797 len = min(len, readlen); 1798 buf = nand_transfer_oob(chip, buf, ops, len); 1799 1800 if (!(chip->options & NAND_NO_READRDY)) { 1801 /* 1802 * Apply delay or wait for ready/busy pin. Do this 1803 * before the AUTOINCR check, so no problems arise if a 1804 * chip which does auto increment is marked as 1805 * NOAUTOINCR by the board driver. 1806 */ 1807 if (!chip->dev_ready) 1808 udelay(chip->chip_delay); 1809 else 1810 nand_wait_ready(mtd); 1811 } 1812 1813 readlen -= len; 1814 if (!readlen) 1815 break; 1816 1817 /* Increment page address */ 1818 realpage++; 1819 1820 page = realpage & chip->pagemask; 1821 /* Check, if we cross a chip boundary */ 1822 if (!page) { 1823 chipnr++; 1824 chip->select_chip(mtd, -1); 1825 chip->select_chip(mtd, chipnr); 1826 } 1827 1828 /* Check, if the chip supports auto page increment 1829 * or if we have hit a block boundary. 1830 */ 1831 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) 1832 sndcmd = 1; 1833 } 1834 1835 ops->oobretlen = ops->ooblen; 1836 return 0; 1837} 1838 1839/** 1840 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band 1841 * @mtd: MTD device structure 1842 * @from: offset to read from 1843 * @ops: oob operation description structure 1844 * 1845 * NAND read data and/or out-of-band data 1846 */ 1847static int nand_read_oob(struct mtd_info *mtd, loff_t from, 1848 struct mtd_oob_ops *ops) 1849{ 1850 struct nand_chip *chip = mtd->priv; 1851 int ret = -ENOTSUPP; 1852 1853 ops->retlen = 0; 1854 1855 /* Do not allow reads past end of device */ 1856 if (ops->datbuf && (from + ops->len) > mtd->size) { 1857 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read " 1858 "beyond end of device\n", __func__); 1859 return -EINVAL; 1860 } 1861 1862 nand_get_device(chip, mtd, FL_READING); 1863 1864 switch(ops->mode) { 1865 case MTD_OOB_PLACE: 1866 case MTD_OOB_AUTO: 1867 case MTD_OOB_RAW: 1868 break; 1869 1870 default: 1871 goto out; 1872 } 1873 1874 if (!ops->datbuf) 1875 ret = nand_do_read_oob(mtd, from, ops); 1876 else 1877 ret = nand_do_read_ops(mtd, from, ops); 1878 1879 out: 1880 nand_release_device(mtd); 1881 return ret; 1882} 1883 1884 1885/** 1886 * nand_write_page_raw - [Intern] raw page write function 1887 * @mtd: mtd info structure 1888 * @chip: nand chip info structure 1889 * @buf: data buffer 1890 * 1891 * Not for syndrome calculating ecc controllers, which use a special oob layout 1892 */ 1893static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1894 const uint8_t *buf) 1895{ 1896 chip->write_buf(mtd, buf, mtd->writesize); 1897 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 1898} 1899 1900/** 1901 * nand_write_page_raw_syndrome - [Intern] raw page write function 1902 * @mtd: mtd info structure 1903 * @chip: nand chip info structure 1904 * @buf: data buffer 1905 * 1906 * We need a special oob layout and handling even when ECC isn't checked. 1907 */ 1908static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1909 const uint8_t *buf) 1910{ 1911 int eccsize = chip->ecc.size; 1912 int eccbytes = chip->ecc.bytes; 1913 uint8_t *oob = chip->oob_poi; 1914 int steps, size; 1915 1916 for (steps = chip->ecc.steps; steps > 0; steps--) { 1917 chip->write_buf(mtd, buf, eccsize); 1918 buf += eccsize; 1919 1920 if (chip->ecc.prepad) { 1921 chip->write_buf(mtd, oob, chip->ecc.prepad); 1922 oob += chip->ecc.prepad; 1923 } 1924 1925 chip->read_buf(mtd, oob, eccbytes); 1926 oob += eccbytes; 1927 1928 if (chip->ecc.postpad) { 1929 chip->write_buf(mtd, oob, chip->ecc.postpad); 1930 oob += chip->ecc.postpad; 1931 } 1932 } 1933 1934 size = mtd->oobsize - (oob - chip->oob_poi); 1935 if (size) 1936 chip->write_buf(mtd, oob, size); 1937} 1938/** 1939 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function 1940 * @mtd: mtd info structure 1941 * @chip: nand chip info structure 1942 * @buf: data buffer 1943 */ 1944static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 1945 const uint8_t *buf) 1946{ 1947 int i, eccsize = chip->ecc.size; 1948 int eccbytes = chip->ecc.bytes; 1949 int eccsteps = chip->ecc.steps; 1950 uint8_t *ecc_calc = chip->buffers->ecccalc; 1951 const uint8_t *p = buf; 1952 uint32_t *eccpos = chip->ecc.layout->eccpos; 1953 1954 /* Software ecc calculation */ 1955 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 1956 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1957 1958 for (i = 0; i < chip->ecc.total; i++) 1959 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 1960 1961 chip->ecc.write_page_raw(mtd, chip, buf); 1962} 1963 1964/** 1965 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function 1966 * @mtd: mtd info structure 1967 * @chip: nand chip info structure 1968 * @buf: data buffer 1969 */ 1970static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 1971 const uint8_t *buf) 1972{ 1973 int i, eccsize = chip->ecc.size; 1974 int eccbytes = chip->ecc.bytes; 1975 int eccsteps = chip->ecc.steps; 1976 uint8_t *ecc_calc = chip->buffers->ecccalc; 1977 const uint8_t *p = buf; 1978 uint32_t *eccpos = chip->ecc.layout->eccpos; 1979 1980 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1981 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 1982 chip->write_buf(mtd, p, eccsize); 1983 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1984 } 1985 1986 for (i = 0; i < chip->ecc.total; i++) 1987 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 1988 1989 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 1990} 1991 1992/** 1993 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write 1994 * @mtd: mtd info structure 1995 * @chip: nand chip info structure 1996 * @buf: data buffer 1997 * 1998 * The hw generator calculates the error syndrome automatically. Therefor 1999 * we need a special oob layout and handling. 2000 */ 2001static void nand_write_page_syndrome(struct mtd_info *mtd, 2002 struct nand_chip *chip, const uint8_t *buf) 2003{ 2004 int i, eccsize = chip->ecc.size; 2005 int eccbytes = chip->ecc.bytes; 2006 int eccsteps = chip->ecc.steps; 2007 const uint8_t *p = buf; 2008 uint8_t *oob = chip->oob_poi; 2009 2010 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2011 2012 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2013 chip->write_buf(mtd, p, eccsize); 2014 2015 if (chip->ecc.prepad) { 2016 chip->write_buf(mtd, oob, chip->ecc.prepad); 2017 oob += chip->ecc.prepad; 2018 } 2019 2020 chip->ecc.calculate(mtd, p, oob); 2021 chip->write_buf(mtd, oob, eccbytes); 2022 oob += eccbytes; 2023 2024 if (chip->ecc.postpad) { 2025 chip->write_buf(mtd, oob, chip->ecc.postpad); 2026 oob += chip->ecc.postpad; 2027 } 2028 } 2029 2030 /* Calculate remaining oob bytes */ 2031 i = mtd->oobsize - (oob - chip->oob_poi); 2032 if (i) 2033 chip->write_buf(mtd, oob, i); 2034} 2035 2036/** 2037 * nand_write_page - [REPLACEABLE] write one page 2038 * @mtd: MTD device structure 2039 * @chip: NAND chip descriptor 2040 * @buf: the data to write 2041 * @page: page number to write 2042 * @cached: cached programming 2043 * @raw: use _raw version of write_page 2044 */ 2045static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, 2046 const uint8_t *buf, int page, int cached, int raw) 2047{ 2048 int status; 2049 2050 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); 2051 2052 if (unlikely(raw)) 2053 chip->ecc.write_page_raw(mtd, chip, buf); 2054 else 2055 chip->ecc.write_page(mtd, chip, buf); 2056 2057 /* 2058 * Cached progamming disabled for now, Not sure if its worth the 2059 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) 2060 */ 2061 cached = 0; 2062 2063 if (!cached || !(chip->options & NAND_CACHEPRG)) { 2064 2065 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 2066 status = chip->waitfunc(mtd, chip); 2067 /* 2068 * See if operation failed and additional status checks are 2069 * available 2070 */ 2071 if ((status & NAND_STATUS_FAIL) && (chip->errstat)) 2072 status = chip->errstat(mtd, chip, FL_WRITING, status, 2073 page); 2074 2075 if (status & NAND_STATUS_FAIL) 2076 return -EIO; 2077 } else { 2078 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); 2079 status = chip->waitfunc(mtd, chip); 2080 } 2081 2082#ifdef CONFIG_MTD_NAND_VERIFY_WRITE 2083 /* Send command to read back the data */ 2084 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); 2085 2086 if (chip->verify_buf(mtd, buf, mtd->writesize)) 2087 return -EIO; 2088#endif 2089 return 0; 2090} 2091 2092/** 2093 * nand_fill_oob - [Internal] Transfer client buffer to oob 2094 * @chip: nand chip structure 2095 * @oob: oob data buffer 2096 * @len: oob data write length 2097 * @ops: oob ops structure 2098 */ 2099static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len, 2100 struct mtd_oob_ops *ops) 2101{ 2102 switch(ops->mode) { 2103 2104 case MTD_OOB_PLACE: 2105 case MTD_OOB_RAW: 2106 memcpy(chip->oob_poi + ops->ooboffs, oob, len); 2107 return oob + len; 2108 2109 case MTD_OOB_AUTO: { 2110 struct nand_oobfree *free = chip->ecc.layout->oobfree; 2111 uint32_t boffs = 0, woffs = ops->ooboffs; 2112 size_t bytes = 0; 2113 2114 for(; free->length && len; free++, len -= bytes) { 2115 /* Write request not from offset 0 ? */ 2116 if (unlikely(woffs)) { 2117 if (woffs >= free->length) { 2118 woffs -= free->length; 2119 continue; 2120 } 2121 boffs = free->offset + woffs; 2122 bytes = min_t(size_t, len, 2123 (free->length - woffs)); 2124 woffs = 0; 2125 } else { 2126 bytes = min_t(size_t, len, free->length); 2127 boffs = free->offset; 2128 } 2129 memcpy(chip->oob_poi + boffs, oob, bytes); 2130 oob += bytes; 2131 } 2132 return oob; 2133 } 2134 default: 2135 BUG(); 2136 } 2137 return NULL; 2138} 2139 2140#define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0 2141 2142/** 2143 * nand_do_write_ops - [Internal] NAND write with ECC 2144 * @mtd: MTD device structure 2145 * @to: offset to write to 2146 * @ops: oob operations description structure 2147 * 2148 * NAND write with ECC 2149 */ 2150static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, 2151 struct mtd_oob_ops *ops) 2152{ 2153 int chipnr, realpage, page, blockmask, column; 2154 struct nand_chip *chip = mtd->priv; 2155 uint32_t writelen = ops->len; 2156 2157 uint32_t oobwritelen = ops->ooblen; 2158 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ? 2159 mtd->oobavail : mtd->oobsize; 2160 2161 uint8_t *oob = ops->oobbuf; 2162 uint8_t *buf = ops->datbuf; 2163 int ret, subpage; 2164 2165 ops->retlen = 0; 2166 if (!writelen) 2167 return 0; 2168 2169 /* reject writes, which are not page aligned */ 2170 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { 2171 printk(KERN_NOTICE "%s: Attempt to write not " 2172 "page aligned data\n", __func__); 2173 return -EINVAL; 2174 } 2175 2176 column = to & (mtd->writesize - 1); 2177 subpage = column || (writelen & (mtd->writesize - 1)); 2178 2179 if (subpage && oob) 2180 return -EINVAL; 2181 2182 chipnr = (int)(to >> chip->chip_shift); 2183 chip->select_chip(mtd, chipnr); 2184 2185 /* Check, if it is write protected */ 2186 if (nand_check_wp(mtd)) 2187 return -EIO; 2188 2189 realpage = (int)(to >> chip->page_shift); 2190 page = realpage & chip->pagemask; 2191 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; 2192 2193 /* Invalidate the page cache, when we write to the cached page */ 2194 if (to <= (chip->pagebuf << chip->page_shift) && 2195 (chip->pagebuf << chip->page_shift) < (to + ops->len)) 2196 chip->pagebuf = -1; 2197 2198 /* If we're not given explicit OOB data, let it be 0xFF */ 2199 if (likely(!oob)) 2200 memset(chip->oob_poi, 0xff, mtd->oobsize); 2201 2202 /* Don't allow multipage oob writes with offset */ 2203 if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) 2204 return -EINVAL; 2205 2206 while(1) { 2207 int bytes = mtd->writesize; 2208 int cached = writelen > bytes && page != blockmask; 2209 uint8_t *wbuf = buf; 2210 2211 /* Partial page write ? */ 2212 if (unlikely(column || writelen < (mtd->writesize - 1))) { 2213 cached = 0; 2214 bytes = min_t(int, bytes - column, (int) writelen); 2215 chip->pagebuf = -1; 2216 memset(chip->buffers->databuf, 0xff, mtd->writesize); 2217 memcpy(&chip->buffers->databuf[column], buf, bytes); 2218 wbuf = chip->buffers->databuf; 2219 } 2220 2221 if (unlikely(oob)) { 2222 size_t len = min(oobwritelen, oobmaxlen); 2223 oob = nand_fill_oob(chip, oob, len, ops); 2224 oobwritelen -= len; 2225 } 2226 2227 ret = chip->write_page(mtd, chip, wbuf, page, cached, 2228 (ops->mode == MTD_OOB_RAW)); 2229 if (ret) 2230 break; 2231 2232 writelen -= bytes; 2233 if (!writelen) 2234 break; 2235 2236 column = 0; 2237 buf += bytes; 2238 realpage++; 2239 2240 page = realpage & chip->pagemask; 2241 /* Check, if we cross a chip boundary */ 2242 if (!page) { 2243 chipnr++; 2244 chip->select_chip(mtd, -1); 2245 chip->select_chip(mtd, chipnr); 2246 } 2247 } 2248 2249 ops->retlen = ops->len - writelen; 2250 if (unlikely(oob)) 2251 ops->oobretlen = ops->ooblen; 2252 return ret; 2253} 2254 2255/** 2256 * panic_nand_write - [MTD Interface] NAND write with ECC 2257 * @mtd: MTD device structure 2258 * @to: offset to write to 2259 * @len: number of bytes to write 2260 * @retlen: pointer to variable to store the number of written bytes 2261 * @buf: the data to write 2262 * 2263 * NAND write with ECC. Used when performing writes in interrupt context, this 2264 * may for example be called by mtdoops when writing an oops while in panic. 2265 */ 2266static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, 2267 size_t *retlen, const uint8_t *buf) 2268{ 2269 struct nand_chip *chip = mtd->priv; 2270 int ret; 2271 2272 /* Do not allow reads past end of device */ 2273 if ((to + len) > mtd->size) 2274 return -EINVAL; 2275 if (!len) 2276 return 0; 2277 2278 /* Wait for the device to get ready. */ 2279 panic_nand_wait(mtd, chip, 400); 2280 2281 /* Grab the device. */ 2282 panic_nand_get_device(chip, mtd, FL_WRITING); 2283 2284 chip->ops.len = len; 2285 chip->ops.datbuf = (uint8_t *)buf; 2286 chip->ops.oobbuf = NULL; 2287 2288 ret = nand_do_write_ops(mtd, to, &chip->ops); 2289 2290 *retlen = chip->ops.retlen; 2291 return ret; 2292} 2293 2294/** 2295 * nand_write - [MTD Interface] NAND write with ECC 2296 * @mtd: MTD device structure 2297 * @to: offset to write to 2298 * @len: number of bytes to write 2299 * @retlen: pointer to variable to store the number of written bytes 2300 * @buf: the data to write 2301 * 2302 * NAND write with ECC 2303 */ 2304static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, 2305 size_t *retlen, const uint8_t *buf) 2306{ 2307 struct nand_chip *chip = mtd->priv; 2308 int ret; 2309 2310 /* Do not allow reads past end of device */ 2311 if ((to + len) > mtd->size) 2312 return -EINVAL; 2313 if (!len) 2314 return 0; 2315 2316 nand_get_device(chip, mtd, FL_WRITING); 2317 2318 chip->ops.len = len; 2319 chip->ops.datbuf = (uint8_t *)buf; 2320 chip->ops.oobbuf = NULL; 2321 2322 ret = nand_do_write_ops(mtd, to, &chip->ops); 2323 2324 *retlen = chip->ops.retlen; 2325 2326 nand_release_device(mtd); 2327 2328 return ret; 2329} 2330 2331/** 2332 * nand_do_write_oob - [MTD Interface] NAND write out-of-band 2333 * @mtd: MTD device structure 2334 * @to: offset to write to 2335 * @ops: oob operation description structure 2336 * 2337 * NAND write out-of-band 2338 */ 2339static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 2340 struct mtd_oob_ops *ops) 2341{ 2342 int chipnr, page, status, len; 2343 struct nand_chip *chip = mtd->priv; 2344 2345 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n", 2346 __func__, (unsigned int)to, (int)ops->ooblen); 2347 2348 if (ops->mode == MTD_OOB_AUTO) 2349 len = chip->ecc.layout->oobavail; 2350 else 2351 len = mtd->oobsize; 2352 2353 /* Do not allow write past end of page */ 2354 if ((ops->ooboffs + ops->ooblen) > len) { 2355 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write " 2356 "past end of page\n", __func__); 2357 return -EINVAL; 2358 } 2359 2360 if (unlikely(ops->ooboffs >= len)) { 2361 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start " 2362 "write outside oob\n", __func__); 2363 return -EINVAL; 2364 } 2365 2366 /* Do not allow reads past end of device */ 2367 if (unlikely(to >= mtd->size || 2368 ops->ooboffs + ops->ooblen > 2369 ((mtd->size >> chip->page_shift) - 2370 (to >> chip->page_shift)) * len)) { 2371 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " 2372 "end of device\n", __func__); 2373 return -EINVAL; 2374 } 2375 2376 chipnr = (int)(to >> chip->chip_shift); 2377 chip->select_chip(mtd, chipnr); 2378 2379 /* Shift to get page */ 2380 page = (int)(to >> chip->page_shift); 2381 2382 /* 2383 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one 2384 * of my DiskOnChip 2000 test units) will clear the whole data page too 2385 * if we don't do this. I have no clue why, but I seem to have 'fixed' 2386 * it in the doc2000 driver in August 1999. dwmw2. 2387 */ 2388 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 2389 2390 /* Check, if it is write protected */ 2391 if (nand_check_wp(mtd)) 2392 return -EROFS; 2393 2394 /* Invalidate the page cache, if we write to the cached page */ 2395 if (page == chip->pagebuf) 2396 chip->pagebuf = -1; 2397 2398 memset(chip->oob_poi, 0xff, mtd->oobsize); 2399 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); 2400 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); 2401 memset(chip->oob_poi, 0xff, mtd->oobsize); 2402 2403 if (status) 2404 return status; 2405 2406 ops->oobretlen = ops->ooblen; 2407 2408 return 0; 2409} 2410 2411/** 2412 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band 2413 * @mtd: MTD device structure 2414 * @to: offset to write to 2415 * @ops: oob operation description structure 2416 */ 2417static int nand_write_oob(struct mtd_info *mtd, loff_t to, 2418 struct mtd_oob_ops *ops) 2419{ 2420 struct nand_chip *chip = mtd->priv; 2421 int ret = -ENOTSUPP; 2422 2423 ops->retlen = 0; 2424 2425 /* Do not allow writes past end of device */ 2426 if (ops->datbuf && (to + ops->len) > mtd->size) { 2427 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " 2428 "end of device\n", __func__); 2429 return -EINVAL; 2430 } 2431 2432 nand_get_device(chip, mtd, FL_WRITING); 2433 2434 switch(ops->mode) { 2435 case MTD_OOB_PLACE: 2436 case MTD_OOB_AUTO: 2437 case MTD_OOB_RAW: 2438 break; 2439 2440 default: 2441 goto out; 2442 } 2443 2444 if (!ops->datbuf) 2445 ret = nand_do_write_oob(mtd, to, ops); 2446 else 2447 ret = nand_do_write_ops(mtd, to, ops); 2448 2449 out: 2450 nand_release_device(mtd); 2451 return ret; 2452} 2453 2454/** 2455 * single_erease_cmd - [GENERIC] NAND standard block erase command function 2456 * @mtd: MTD device structure 2457 * @page: the page address of the block which will be erased 2458 * 2459 * Standard erase command for NAND chips 2460 */ 2461static void single_erase_cmd(struct mtd_info *mtd, int page) 2462{ 2463 struct nand_chip *chip = mtd->priv; 2464 /* Send commands to erase a block */ 2465 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); 2466 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); 2467} 2468 2469/** 2470 * multi_erease_cmd - [GENERIC] AND specific block erase command function 2471 * @mtd: MTD device structure 2472 * @page: the page address of the block which will be erased 2473 * 2474 * AND multi block erase command function 2475 * Erase 4 consecutive blocks 2476 */ 2477static void multi_erase_cmd(struct mtd_info *mtd, int page) 2478{ 2479 struct nand_chip *chip = mtd->priv; 2480 /* Send commands to erase a block */ 2481 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); 2482 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); 2483 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); 2484 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); 2485 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); 2486} 2487 2488/** 2489 * nand_erase - [MTD Interface] erase block(s) 2490 * @mtd: MTD device structure 2491 * @instr: erase instruction 2492 * 2493 * Erase one ore more blocks 2494 */ 2495static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) 2496{ 2497 return nand_erase_nand(mtd, instr, 0); 2498} 2499 2500#define BBT_PAGE_MASK 0xffffff3f 2501/** 2502 * nand_erase_nand - [Internal] erase block(s) 2503 * @mtd: MTD device structure 2504 * @instr: erase instruction 2505 * @allowbbt: allow erasing the bbt area 2506 * 2507 * Erase one ore more blocks 2508 */ 2509int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 2510 int allowbbt) 2511{ 2512 int page, status, pages_per_block, ret, chipnr; 2513 struct nand_chip *chip = mtd->priv; 2514 loff_t rewrite_bbt[NAND_MAX_CHIPS]={0}; 2515 unsigned int bbt_masked_page = 0xffffffff; 2516 loff_t len; 2517 2518 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", 2519 __func__, (unsigned long long)instr->addr, 2520 (unsigned long long)instr->len); 2521 2522 if (check_offs_len(mtd, instr->addr, instr->len)) 2523 return -EINVAL; 2524 2525 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; 2526 2527 /* Grab the lock and see if the device is available */ 2528 nand_get_device(chip, mtd, FL_ERASING); 2529 2530 /* Shift to get first page */ 2531 page = (int)(instr->addr >> chip->page_shift); 2532 chipnr = (int)(instr->addr >> chip->chip_shift); 2533 2534 /* Calculate pages in each block */ 2535 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 2536 2537 /* Select the NAND device */ 2538 chip->select_chip(mtd, chipnr); 2539 2540 /* Check, if it is write protected */ 2541 if (nand_check_wp(mtd)) { 2542 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", 2543 __func__); 2544 instr->state = MTD_ERASE_FAILED; 2545 goto erase_exit; 2546 } 2547 2548 /* 2549 * If BBT requires refresh, set the BBT page mask to see if the BBT 2550 * should be rewritten. Otherwise the mask is set to 0xffffffff which 2551 * can not be matched. This is also done when the bbt is actually 2552 * erased to avoid recusrsive updates 2553 */ 2554 if (chip->options & BBT_AUTO_REFRESH && !allowbbt) 2555 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; 2556 2557 /* Loop through the pages */ 2558 len = instr->len; 2559 2560 instr->state = MTD_ERASING; 2561 2562 while (len) { 2563 /* 2564 * heck if we have a bad block, we do not erase bad blocks ! 2565 */ 2566 if (nand_block_checkbad(mtd, ((loff_t) page) << 2567 chip->page_shift, 0, allowbbt)) { 2568 printk(KERN_WARNING "%s: attempt to erase a bad block " 2569 "at page 0x%08x\n", __func__, page); 2570 instr->state = MTD_ERASE_FAILED; 2571 goto erase_exit; 2572 } 2573 2574 /* 2575 * Invalidate the page cache, if we erase the block which 2576 * contains the current cached page 2577 */ 2578 if (page <= chip->pagebuf && chip->pagebuf < 2579 (page + pages_per_block)) 2580 chip->pagebuf = -1; 2581 2582 chip->erase_cmd(mtd, page & chip->pagemask); 2583 2584 status = chip->waitfunc(mtd, chip); 2585 2586 /* 2587 * See if operation failed and additional status checks are 2588 * available 2589 */ 2590 if ((status & NAND_STATUS_FAIL) && (chip->errstat)) 2591 status = chip->errstat(mtd, chip, FL_ERASING, 2592 status, page); 2593 2594 /* See if block erase succeeded */ 2595 if (status & NAND_STATUS_FAIL) { 2596 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, " 2597 "page 0x%08x\n", __func__, page); 2598 instr->state = MTD_ERASE_FAILED; 2599 instr->fail_addr = 2600 ((loff_t)page << chip->page_shift); 2601 goto erase_exit; 2602 } 2603 2604 /* 2605 * If BBT requires refresh, set the BBT rewrite flag to the 2606 * page being erased 2607 */ 2608 if (bbt_masked_page != 0xffffffff && 2609 (page & BBT_PAGE_MASK) == bbt_masked_page) 2610 rewrite_bbt[chipnr] = 2611 ((loff_t)page << chip->page_shift); 2612 2613 /* Increment page address and decrement length */ 2614 len -= (1 << chip->phys_erase_shift); 2615 page += pages_per_block; 2616 2617 /* Check, if we cross a chip boundary */ 2618 if (len && !(page & chip->pagemask)) { 2619 chipnr++; 2620 chip->select_chip(mtd, -1); 2621 chip->select_chip(mtd, chipnr); 2622 2623 /* 2624 * If BBT requires refresh and BBT-PERCHIP, set the BBT 2625 * page mask to see if this BBT should be rewritten 2626 */ 2627 if (bbt_masked_page != 0xffffffff && 2628 (chip->bbt_td->options & NAND_BBT_PERCHIP)) 2629 bbt_masked_page = chip->bbt_td->pages[chipnr] & 2630 BBT_PAGE_MASK; 2631 } 2632 } 2633 instr->state = MTD_ERASE_DONE; 2634 2635 erase_exit: 2636 2637 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; 2638 2639 /* Deselect and wake up anyone waiting on the device */ 2640 nand_release_device(mtd); 2641 2642 /* Do call back function */ 2643 if (!ret) 2644 mtd_erase_callback(instr); 2645 2646 /* 2647 * If BBT requires refresh and erase was successful, rewrite any 2648 * selected bad block tables 2649 */ 2650 if (bbt_masked_page == 0xffffffff || ret) 2651 return ret; 2652 2653 for (chipnr = 0; chipnr < chip->numchips; chipnr++) { 2654 if (!rewrite_bbt[chipnr]) 2655 continue; 2656 /* update the BBT for chip */ 2657 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt " 2658 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr, 2659 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]); 2660 nand_update_bbt(mtd, rewrite_bbt[chipnr]); 2661 } 2662 2663 /* Return more or less happy */ 2664 return ret; 2665} 2666 2667/** 2668 * nand_sync - [MTD Interface] sync 2669 * @mtd: MTD device structure 2670 * 2671 * Sync is actually a wait for chip ready function 2672 */ 2673static void nand_sync(struct mtd_info *mtd) 2674{ 2675 struct nand_chip *chip = mtd->priv; 2676 2677 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__); 2678 2679 /* Grab the lock and see if the device is available */ 2680 nand_get_device(chip, mtd, FL_SYNCING); 2681 /* Release it and go back */ 2682 nand_release_device(mtd); 2683} 2684 2685/** 2686 * nand_block_isbad - [MTD Interface] Check if block at offset is bad 2687 * @mtd: MTD device structure 2688 * @offs: offset relative to mtd start 2689 */ 2690static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 2691{ 2692 /* Check for invalid offset */ 2693 if (offs > mtd->size) 2694 return -EINVAL; 2695 2696 return nand_block_checkbad(mtd, offs, 1, 0); 2697} 2698 2699/** 2700 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad 2701 * @mtd: MTD device structure 2702 * @ofs: offset relative to mtd start 2703 */ 2704static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) 2705{ 2706 struct nand_chip *chip = mtd->priv; 2707 int ret; 2708 2709 if ((ret = nand_block_isbad(mtd, ofs))) { 2710 /* If it was bad already, return success and do nothing. */ 2711 if (ret > 0) 2712 return 0; 2713 return ret; 2714 } 2715 2716 return chip->block_markbad(mtd, ofs); 2717} 2718 2719/** 2720 * nand_suspend - [MTD Interface] Suspend the NAND flash 2721 * @mtd: MTD device structure 2722 */ 2723static int nand_suspend(struct mtd_info *mtd) 2724{ 2725 struct nand_chip *chip = mtd->priv; 2726 2727 return nand_get_device(chip, mtd, FL_PM_SUSPENDED); 2728} 2729 2730/** 2731 * nand_resume - [MTD Interface] Resume the NAND flash 2732 * @mtd: MTD device structure 2733 */ 2734static void nand_resume(struct mtd_info *mtd) 2735{ 2736 struct nand_chip *chip = mtd->priv; 2737 2738 if (chip->state == FL_PM_SUSPENDED) 2739 nand_release_device(mtd); 2740 else 2741 printk(KERN_ERR "%s called for a chip which is not " 2742 "in suspended state\n", __func__); 2743} 2744 2745/* 2746 * Set default functions 2747 */ 2748static void nand_set_defaults(struct nand_chip *chip, int busw) 2749{ 2750 /* check for proper chip_delay setup, set 20us if not */ 2751 if (!chip->chip_delay) 2752 chip->chip_delay = 20; 2753 2754 /* check, if a user supplied command function given */ 2755 if (chip->cmdfunc == NULL) 2756 chip->cmdfunc = nand_command; 2757 2758 /* check, if a user supplied wait function given */ 2759 if (chip->waitfunc == NULL) 2760 chip->waitfunc = nand_wait; 2761 2762 if (!chip->select_chip) 2763 chip->select_chip = nand_select_chip; 2764 if (!chip->read_byte) 2765 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; 2766 if (!chip->read_word) 2767 chip->read_word = nand_read_word; 2768 if (!chip->block_bad) 2769 chip->block_bad = nand_block_bad; 2770 if (!chip->block_markbad) 2771 chip->block_markbad = nand_default_block_markbad; 2772 if (!chip->write_buf) 2773 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; 2774 if (!chip->read_buf) 2775 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; 2776 if (!chip->verify_buf) 2777 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; 2778 if (!chip->scan_bbt) 2779 chip->scan_bbt = nand_default_bbt; 2780 2781 if (!chip->controller) { 2782 chip->controller = &chip->hwcontrol; 2783 spin_lock_init(&chip->controller->lock); 2784 init_waitqueue_head(&chip->controller->wq); 2785 } 2786 2787} 2788 2789/* 2790 * Get the flash and manufacturer id and lookup if the type is supported 2791 */ 2792static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, 2793 struct nand_chip *chip, 2794 int busw, int *maf_id, 2795 struct nand_flash_dev *type) 2796{ 2797 int i, dev_id, maf_idx; 2798 u8 id_data[8]; 2799 2800 /* Select the device */ 2801 chip->select_chip(mtd, 0); 2802 2803 /* 2804 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 2805 * after power-up 2806 */ 2807 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 2808 2809 /* Send the command for reading device ID */ 2810 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 2811 2812 /* Read manufacturer and device IDs */ 2813 *maf_id = chip->read_byte(mtd); 2814 dev_id = chip->read_byte(mtd); 2815 2816 /* Try again to make sure, as some systems the bus-hold or other 2817 * interface concerns can cause random data which looks like a 2818 * possibly credible NAND flash to appear. If the two results do 2819 * not match, ignore the device completely. 2820 */ 2821 2822 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 2823 2824 /* Read entire ID string */ 2825 2826 for (i = 0; i < 8; i++) 2827 id_data[i] = chip->read_byte(mtd); 2828 2829 if (id_data[0] != *maf_id || id_data[1] != dev_id) { 2830 printk(KERN_INFO "%s: second ID read did not match " 2831 "%02x,%02x against %02x,%02x\n", __func__, 2832 *maf_id, dev_id, id_data[0], id_data[1]); 2833 return ERR_PTR(-ENODEV); 2834 } 2835 2836 if (!type) 2837 type = nand_flash_ids; 2838 2839 for (; type->name != NULL; type++) 2840 if (dev_id == type->id) 2841 break; 2842 2843 if (!type->name) 2844 return ERR_PTR(-ENODEV); 2845 2846 if (!mtd->name) 2847 mtd->name = type->name; 2848 2849 chip->chipsize = (uint64_t)type->chipsize << 20; 2850 2851 /* Newer devices have all the information in additional id bytes */ 2852 if (!type->pagesize) { 2853 int extid; 2854 /* The 3rd id byte holds MLC / multichip data */ 2855 chip->cellinfo = id_data[2]; 2856 /* The 4th id byte is the important one */ 2857 extid = id_data[3]; 2858 2859 /* 2860 * Field definitions are in the following datasheets: 2861 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) 2862 * New style (6 byte ID): Samsung K9GAG08U0D (p.40) 2863 * 2864 * Check for wraparound + Samsung ID + nonzero 6th byte 2865 * to decide what to do. 2866 */ 2867 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && 2868 id_data[0] == NAND_MFR_SAMSUNG && 2869 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && 2870 id_data[5] != 0x00) { 2871 /* Calc pagesize */ 2872 mtd->writesize = 2048 << (extid & 0x03); 2873 extid >>= 2; 2874 /* Calc oobsize */ 2875 mtd->oobsize = (extid & 0x03) == 0x01 ? 128 : 218; 2876 extid >>= 2; 2877 /* Calc blocksize */ 2878 mtd->erasesize = (128 * 1024) << 2879 (((extid >> 1) & 0x04) | (extid & 0x03)); 2880 busw = 0; 2881 } else { 2882 /* Calc pagesize */ 2883 mtd->writesize = 1024 << (extid & 0x03); 2884 extid >>= 2; 2885 /* Calc oobsize */ 2886 mtd->oobsize = (8 << (extid & 0x01)) * 2887 (mtd->writesize >> 9); 2888 extid >>= 2; 2889 /* Calc blocksize. Blocksize is multiples of 64KiB */ 2890 mtd->erasesize = (64 * 1024) << (extid & 0x03); 2891 extid >>= 2; 2892 /* Get buswidth information */ 2893 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; 2894 } 2895 } else { 2896 /* 2897 * Old devices have chip data hardcoded in the device id table 2898 */ 2899 mtd->erasesize = type->erasesize; 2900 mtd->writesize = type->pagesize; 2901 mtd->oobsize = mtd->writesize / 32; 2902 busw = type->options & NAND_BUSWIDTH_16; 2903 } 2904 2905#ifdef CONFIG_BCM47XX 2906 /* Override for specific Samsung K9LCG08U0B, Micron MT29F64G08CBABA */ 2907 if ((id_data[0] == 0xec && id_data[1] == 0xde && id_data[2] == 0xd5 && 2908 id_data[3] == 0x7e && id_data[4] == 0x68 && id_data[5] == 0x44) || 2909 (id_data[0] == 0x2c && id_data[1] == 0x64 && id_data[2] == 0x44 && 2910 id_data[3] == 0x4b && id_data[4] == 0xa9)) 2911 mtd->oobsize = 720; 2912#endif /* CONFIG_BCM47XX */ 2913 2914 /* Try to identify manufacturer */ 2915 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { 2916 if (nand_manuf_ids[maf_idx].id == *maf_id) 2917 break; 2918 } 2919 2920 /* 2921 * Check, if buswidth is correct. Hardware drivers should set 2922 * chip correct ! 2923 */ 2924 if (busw != (chip->options & NAND_BUSWIDTH_16)) { 2925 printk(KERN_INFO "NAND device: Manufacturer ID:" 2926 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, 2927 dev_id, nand_manuf_ids[maf_idx].name, mtd->name); 2928 printk(KERN_WARNING "NAND bus width %d instead %d bit\n", 2929 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, 2930 busw ? 16 : 8); 2931 return ERR_PTR(-EINVAL); 2932 } 2933 2934 /* Calculate the address shift from the page size */ 2935 chip->page_shift = ffs(mtd->writesize) - 1; 2936 /* Convert chipsize to number of pages per chip -1. */ 2937 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; 2938 2939 chip->bbt_erase_shift = chip->phys_erase_shift = 2940 ffs(mtd->erasesize) - 1; 2941 if (chip->chipsize & 0xffffffff) 2942 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; 2943 else 2944 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1; 2945 2946 /* Set the bad block position */ 2947 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16)) 2948 chip->badblockpos = NAND_LARGE_BADBLOCK_POS; 2949 else 2950 chip->badblockpos = NAND_SMALL_BADBLOCK_POS; 2951 2952 /* Get chip options, preserve non chip based options */ 2953 chip->options &= ~NAND_CHIPOPTIONS_MSK; 2954 chip->options |= type->options & NAND_CHIPOPTIONS_MSK; 2955 2956 /* 2957 * Set chip as a default. Board drivers can override it, if necessary 2958 */ 2959 chip->options |= NAND_NO_AUTOINCR; 2960 2961 /* Check if chip is a not a samsung device. Do not clear the 2962 * options for chips which are not having an extended id. 2963 */ 2964 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) 2965 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; 2966 2967 /* 2968 * Bad block marker is stored in the last page of each block 2969 * on Samsung and Hynix MLC devices; stored in first two pages 2970 * of each block on Micron devices with 2KiB pages and on 2971 * SLC Samsung, Hynix, and AMD/Spansion. All others scan only 2972 * the first page. 2973 */ 2974 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && 2975 (*maf_id == NAND_MFR_SAMSUNG || 2976 *maf_id == NAND_MFR_HYNIX)) 2977 chip->options |= NAND_BBT_SCANLASTPAGE; 2978 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && 2979 (*maf_id == NAND_MFR_SAMSUNG || 2980 *maf_id == NAND_MFR_HYNIX || 2981 *maf_id == NAND_MFR_AMD)) || 2982 (mtd->writesize == 2048 && 2983 *maf_id == NAND_MFR_MICRON)) 2984 chip->options |= NAND_BBT_SCAN2NDPAGE; 2985 2986 /* 2987 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6 2988 */ 2989 if (!(busw & NAND_BUSWIDTH_16) && 2990 *maf_id == NAND_MFR_STMICRO && 2991 mtd->writesize == 2048) { 2992 chip->options |= NAND_BBT_SCANBYTE1AND6; 2993 chip->badblockpos = 0; 2994 } 2995 2996 /* Check for AND chips with 4 page planes */ 2997 if (chip->options & NAND_4PAGE_ARRAY) 2998 chip->erase_cmd = multi_erase_cmd; 2999 else 3000 chip->erase_cmd = single_erase_cmd; 3001 3002 /* Do not replace user supplied command function ! */ 3003 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 3004 chip->cmdfunc = nand_command_lp; 3005 3006 printk(KERN_INFO "NAND device: Manufacturer ID:" 3007 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, 3008 nand_manuf_ids[maf_idx].name, type->name); 3009 3010 return type; 3011} 3012 3013/** 3014 * nand_scan_ident - [NAND Interface] Scan for the NAND device 3015 * @mtd: MTD device structure 3016 * @maxchips: Number of chips to scan for 3017 * @table: Alternative NAND ID table 3018 * 3019 * This is the first phase of the normal nand_scan() function. It 3020 * reads the flash ID and sets up MTD fields accordingly. 3021 * 3022 * The mtd->owner field must be set to the module of the caller. 3023 */ 3024int nand_scan_ident(struct mtd_info *mtd, int maxchips, 3025 struct nand_flash_dev *table) 3026{ 3027 int i, busw, nand_maf_id; 3028 struct nand_chip *chip = mtd->priv; 3029 struct nand_flash_dev *type; 3030 3031 /* Get buswidth to select the correct functions */ 3032 busw = chip->options & NAND_BUSWIDTH_16; 3033 /* Set the default functions */ 3034 nand_set_defaults(chip, busw); 3035 3036 /* Read the flash type */ 3037 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table); 3038 3039 if (IS_ERR(type)) { 3040 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) 3041 printk(KERN_WARNING "No NAND device found.\n"); 3042 chip->select_chip(mtd, -1); 3043 return PTR_ERR(type); 3044 } 3045 3046 /* Check for a chip array */ 3047 for (i = 1; i < maxchips; i++) { 3048 chip->select_chip(mtd, i); 3049 /* See comment in nand_get_flash_type for reset */ 3050 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 3051 /* Send the command for reading device ID */ 3052 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 3053 /* Read manufacturer and device IDs */ 3054 if (nand_maf_id != chip->read_byte(mtd) || 3055 type->id != chip->read_byte(mtd)) 3056 break; 3057 } 3058 if (i > 1) 3059 printk(KERN_INFO "%d NAND chips detected\n", i); 3060 3061 /* Store the number of chips and calc total size for mtd */ 3062 chip->numchips = i; 3063 mtd->size = i * chip->chipsize; 3064 3065 return 0; 3066} 3067 3068 3069/** 3070 * nand_scan_tail - [NAND Interface] Scan for the NAND device 3071 * @mtd: MTD device structure 3072 * 3073 * This is the second phase of the normal nand_scan() function. It 3074 * fills out all the uninitialized function pointers with the defaults 3075 * and scans for a bad block table if appropriate. 3076 */ 3077int nand_scan_tail(struct mtd_info *mtd) 3078{ 3079 int i; 3080 struct nand_chip *chip = mtd->priv; 3081 3082 if (!(chip->options & NAND_OWN_BUFFERS)) 3083 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); 3084 if (!chip->buffers) 3085 return -ENOMEM; 3086 3087 /* Set the internal oob buffer location, just after the page data */ 3088 chip->oob_poi = chip->buffers->databuf + mtd->writesize; 3089 3090 /* 3091 * If no default placement scheme is given, select an appropriate one 3092 */ 3093 if (!chip->ecc.layout) { 3094 switch (mtd->oobsize) { 3095 case 8: 3096 chip->ecc.layout = &nand_oob_8; 3097 break; 3098 case 16: 3099 chip->ecc.layout = &nand_oob_16; 3100 break; 3101 case 64: 3102 chip->ecc.layout = &nand_oob_64; 3103 break; 3104 case 128: 3105 chip->ecc.layout = &nand_oob_128; 3106 break; 3107 default: 3108 printk(KERN_WARNING "No oob scheme defined for " 3109 "oobsize %d\n", mtd->oobsize); 3110 BUG(); 3111 } 3112 } 3113 3114 if (!chip->write_page) 3115 chip->write_page = nand_write_page; 3116 3117 /* 3118 * check ECC mode, default to software if 3byte/512byte hardware ECC is 3119 * selected and we have 256 byte pagesize fallback to software ECC 3120 */ 3121 3122 switch (chip->ecc.mode) { 3123 case NAND_ECC_HW_OOB_FIRST: 3124 /* Similar to NAND_ECC_HW, but a separate read_page handle */ 3125 if (!chip->ecc.calculate || !chip->ecc.correct || 3126 !chip->ecc.hwctl) { 3127 printk(KERN_WARNING "No ECC functions supplied; " 3128 "Hardware ECC not possible\n"); 3129 BUG(); 3130 } 3131 if (!chip->ecc.read_page) 3132 chip->ecc.read_page = nand_read_page_hwecc_oob_first; 3133 3134 case NAND_ECC_HW: 3135 /* Use standard hwecc read page function ? */ 3136 if (!chip->ecc.read_page) 3137 chip->ecc.read_page = nand_read_page_hwecc; 3138 if (!chip->ecc.write_page) 3139 chip->ecc.write_page = nand_write_page_hwecc; 3140 if (!chip->ecc.read_page_raw) 3141 chip->ecc.read_page_raw = nand_read_page_raw; 3142 if (!chip->ecc.write_page_raw) 3143 chip->ecc.write_page_raw = nand_write_page_raw; 3144 if (!chip->ecc.read_oob) 3145 chip->ecc.read_oob = nand_read_oob_std; 3146 if (!chip->ecc.write_oob) 3147 chip->ecc.write_oob = nand_write_oob_std; 3148 3149 case NAND_ECC_HW_SYNDROME: 3150 if ((!chip->ecc.calculate || !chip->ecc.correct || 3151 !chip->ecc.hwctl) && 3152 (!chip->ecc.read_page || 3153 chip->ecc.read_page == nand_read_page_hwecc || 3154 !chip->ecc.write_page || 3155 chip->ecc.write_page == nand_write_page_hwecc)) { 3156 printk(KERN_WARNING "No ECC functions supplied; " 3157 "Hardware ECC not possible\n"); 3158 BUG(); 3159 } 3160 /* Use standard syndrome read/write page function ? */ 3161 if (!chip->ecc.read_page) 3162 chip->ecc.read_page = nand_read_page_syndrome; 3163 if (!chip->ecc.write_page) 3164 chip->ecc.write_page = nand_write_page_syndrome; 3165 if (!chip->ecc.read_page_raw) 3166 chip->ecc.read_page_raw = nand_read_page_raw_syndrome; 3167 if (!chip->ecc.write_page_raw) 3168 chip->ecc.write_page_raw = nand_write_page_raw_syndrome; 3169 if (!chip->ecc.read_oob) 3170 chip->ecc.read_oob = nand_read_oob_syndrome; 3171 if (!chip->ecc.write_oob) 3172 chip->ecc.write_oob = nand_write_oob_syndrome; 3173 3174 if (mtd->writesize >= chip->ecc.size) 3175 break; 3176 printk(KERN_WARNING "%d byte HW ECC not possible on " 3177 "%d byte page size, fallback to SW ECC\n", 3178 chip->ecc.size, mtd->writesize); 3179 chip->ecc.mode = NAND_ECC_SOFT; 3180 3181 case NAND_ECC_SOFT: 3182 chip->ecc.calculate = nand_calculate_ecc; 3183 chip->ecc.correct = nand_correct_data; 3184 chip->ecc.read_page = nand_read_page_swecc; 3185 chip->ecc.read_subpage = nand_read_subpage; 3186 chip->ecc.write_page = nand_write_page_swecc; 3187 chip->ecc.read_page_raw = nand_read_page_raw; 3188 chip->ecc.write_page_raw = nand_write_page_raw; 3189 chip->ecc.read_oob = nand_read_oob_std; 3190 chip->ecc.write_oob = nand_write_oob_std; 3191 if (!chip->ecc.size) 3192 chip->ecc.size = 256; 3193 chip->ecc.bytes = 3; 3194 break; 3195 3196 case NAND_ECC_NONE: 3197 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " 3198 "This is not recommended !!\n"); 3199 chip->ecc.read_page = nand_read_page_raw; 3200 chip->ecc.write_page = nand_write_page_raw; 3201 chip->ecc.read_oob = nand_read_oob_std; 3202 chip->ecc.read_page_raw = nand_read_page_raw; 3203 chip->ecc.write_page_raw = nand_write_page_raw; 3204 chip->ecc.write_oob = nand_write_oob_std; 3205 chip->ecc.size = mtd->writesize; 3206 chip->ecc.bytes = 0; 3207 break; 3208 3209 default: 3210 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", 3211 chip->ecc.mode); 3212 BUG(); 3213 } 3214 3215 /* 3216 * The number of bytes available for a client to place data into 3217 * the out of band area 3218 */ 3219 chip->ecc.layout->oobavail = 0; 3220 for (i = 0; chip->ecc.layout->oobfree[i].length 3221 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) 3222 chip->ecc.layout->oobavail += 3223 chip->ecc.layout->oobfree[i].length; 3224 mtd->oobavail = chip->ecc.layout->oobavail; 3225 3226 /* 3227 * Set the number of read / write steps for one page depending on ECC 3228 * mode 3229 */ 3230 chip->ecc.steps = mtd->writesize / chip->ecc.size; 3231 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { 3232 printk(KERN_WARNING "Invalid ecc parameters\n"); 3233 BUG(); 3234 } 3235 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; 3236 3237 /* 3238 * Allow subpage writes up to ecc.steps. Not possible for MLC 3239 * FLASH. 3240 */ 3241 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && 3242 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { 3243 switch(chip->ecc.steps) { 3244 case 2: 3245 mtd->subpage_sft = 1; 3246 break; 3247 case 4: 3248 case 8: 3249 case 16: 3250 mtd->subpage_sft = 2; 3251 break; 3252 } 3253 } 3254 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; 3255 3256 /* Initialize state */ 3257 chip->state = FL_READY; 3258 3259 /* De-select the device */ 3260 chip->select_chip(mtd, -1); 3261 3262 /* Invalidate the pagebuffer reference */ 3263 chip->pagebuf = -1; 3264 3265 /* Fill in remaining MTD driver data */ 3266 mtd->type = MTD_NANDFLASH; 3267 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : 3268 MTD_CAP_NANDFLASH; 3269 mtd->erase = nand_erase; 3270 mtd->point = NULL; 3271 mtd->unpoint = NULL; 3272 mtd->read = nand_read; 3273 mtd->write = nand_write; 3274 mtd->panic_write = panic_nand_write; 3275 mtd->read_oob = nand_read_oob; 3276 mtd->write_oob = nand_write_oob; 3277 mtd->sync = nand_sync; 3278 mtd->lock = NULL; 3279 mtd->unlock = NULL; 3280 mtd->suspend = nand_suspend; 3281 mtd->resume = nand_resume; 3282 mtd->block_isbad = nand_block_isbad; 3283 mtd->block_markbad = nand_block_markbad; 3284 3285 /* propagate ecc.layout to mtd_info */ 3286 mtd->ecclayout = chip->ecc.layout; 3287 3288 /* Check, if we should skip the bad block table scan */ 3289 if (chip->options & NAND_SKIP_BBTSCAN) 3290 return 0; 3291 3292 /* Build bad block table */ 3293 return chip->scan_bbt(mtd); 3294} 3295 3296/* is_module_text_address() isn't exported, and it's mostly a pointless 3297 test if this is a module _anyway_ -- they'd have to try _really_ hard 3298 to call us from in-kernel code if the core NAND support is modular. */ 3299#ifdef MODULE 3300#define caller_is_module() (1) 3301#else 3302#define caller_is_module() \ 3303 is_module_text_address((unsigned long)__builtin_return_address(0)) 3304#endif 3305 3306/** 3307 * nand_scan - [NAND Interface] Scan for the NAND device 3308 * @mtd: MTD device structure 3309 * @maxchips: Number of chips to scan for 3310 * 3311 * This fills out all the uninitialized function pointers 3312 * with the defaults. 3313 * The flash ID is read and the mtd/chip structures are 3314 * filled with the appropriate values. 3315 * The mtd->owner field must be set to the module of the caller 3316 * 3317 */ 3318int nand_scan(struct mtd_info *mtd, int maxchips) 3319{ 3320 int ret; 3321 3322 /* Many callers got this wrong, so check for it for a while... */ 3323 if (!mtd->owner && caller_is_module()) { 3324 printk(KERN_CRIT "%s called with NULL mtd->owner!\n", 3325 __func__); 3326 BUG(); 3327 } 3328 3329 ret = nand_scan_ident(mtd, maxchips, NULL); 3330 if (!ret) 3331 ret = nand_scan_tail(mtd); 3332 return ret; 3333} 3334 3335/** 3336 * nand_release - [NAND Interface] Free resources held by the NAND device 3337 * @mtd: MTD device structure 3338*/ 3339void nand_release(struct mtd_info *mtd) 3340{ 3341 struct nand_chip *chip = mtd->priv; 3342 3343#ifdef CONFIG_MTD_PARTITIONS 3344 /* Deregister partitions */ 3345 del_mtd_partitions(mtd); 3346#endif 3347 /* Deregister the device */ 3348 del_mtd_device(mtd); 3349 3350 /* Free bad block table memory */ 3351 kfree(chip->bbt); 3352 if (!(chip->options & NAND_OWN_BUFFERS)) 3353 kfree(chip->buffers); 3354 3355 /* Free bad block descriptor memory */ 3356 if (chip->badblock_pattern && chip->badblock_pattern->options 3357 & NAND_BBT_DYNAMICSTRUCT) 3358 kfree(chip->badblock_pattern); 3359} 3360 3361EXPORT_SYMBOL_GPL(nand_lock); 3362EXPORT_SYMBOL_GPL(nand_unlock); 3363EXPORT_SYMBOL_GPL(nand_scan); 3364EXPORT_SYMBOL_GPL(nand_scan_ident); 3365EXPORT_SYMBOL_GPL(nand_scan_tail); 3366EXPORT_SYMBOL_GPL(nand_release); 3367 3368static int __init nand_base_init(void) 3369{ 3370 led_trigger_register_simple("nand-disk", &nand_led_trigger); 3371 return 0; 3372} 3373 3374static void __exit nand_base_exit(void) 3375{ 3376 led_trigger_unregister_simple(nand_led_trigger); 3377} 3378 3379module_init(nand_base_init); 3380module_exit(nand_base_exit); 3381 3382MODULE_LICENSE("GPL"); 3383MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); 3384MODULE_DESCRIPTION("Generic NAND flash driver code"); 3385