1/* 2 * drivers/mtd/nand/cs553x_nand.c 3 * 4 * (C) 2005, 2006 Red Hat Inc. 5 * 6 * Author: David Woodhouse <dwmw2@infradead.org> 7 * Tom Sylla <tom.sylla@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Overview: 14 * This is a device driver for the NAND flash controller found on 15 * the AMD CS5535/CS5536 companion chipsets for the Geode processor. 16 * mtd-id for command line partitioning is cs553x_nand_cs[0-3] 17 * where 0-3 reflects the chip select for NAND. 18 * 19 */ 20 21#include <linux/kernel.h> 22#include <linux/slab.h> 23#include <linux/init.h> 24#include <linux/module.h> 25#include <linux/delay.h> 26#include <linux/mtd/mtd.h> 27#include <linux/mtd/nand.h> 28#include <linux/mtd/nand_ecc.h> 29#include <linux/mtd/partitions.h> 30 31#include <asm/msr.h> 32#include <asm/io.h> 33 34#define NR_CS553X_CONTROLLERS 4 35 36#define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */ 37#define CAP_CS5535 0x2df000ULL 38#define CAP_CS5536 0x5df500ULL 39 40/* NAND Timing MSRs */ 41#define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */ 42#define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */ 43#define MSR_NANDF_RSVD 0x5140001d /* Reserved */ 44 45/* NAND BAR MSRs */ 46#define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */ 47#define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */ 48#define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */ 49#define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */ 50 /* Each made up of... */ 51#define FLSH_LBAR_EN (1ULL<<32) 52#define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */ 53#define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */ 54 /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */ 55 /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */ 56 57/* Pin function selection MSR (IDE vs. flash on the IDE pins) */ 58#define MSR_DIVIL_BALL_OPTS 0x51400015 59#define PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */ 60 61/* Registers within the NAND flash controller BAR -- memory mapped */ 62#define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */ 63#define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */ 64#define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */ 65#define MM_NAND_STS 0x810 66#define MM_NAND_ECC_LSB 0x811 67#define MM_NAND_ECC_MSB 0x812 68#define MM_NAND_ECC_COL 0x813 69#define MM_NAND_LAC 0x814 70#define MM_NAND_ECC_CTL 0x815 71 72/* Registers within the NAND flash controller BAR -- I/O mapped */ 73#define IO_NAND_DATA 0x00 /* 0 to 3, in fact */ 74#define IO_NAND_CTL 0x04 75#define IO_NAND_IO 0x05 76#define IO_NAND_STS 0x06 77#define IO_NAND_ECC_CTL 0x08 78#define IO_NAND_ECC_LSB 0x09 79#define IO_NAND_ECC_MSB 0x0a 80#define IO_NAND_ECC_COL 0x0b 81#define IO_NAND_LAC 0x0c 82 83#define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */ 84#define CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */ 85#define CS_NAND_CTL_ALE (1<<2) 86#define CS_NAND_CTL_CLE (1<<1) 87#define CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */ 88 89#define CS_NAND_STS_FLASH_RDY (1<<3) 90#define CS_NAND_CTLR_BUSY (1<<2) 91#define CS_NAND_CMD_COMP (1<<1) 92#define CS_NAND_DIST_ST (1<<0) 93 94#define CS_NAND_ECC_PARITY (1<<2) 95#define CS_NAND_ECC_CLRECC (1<<1) 96#define CS_NAND_ECC_ENECC (1<<0) 97 98static void cs553x_read_buf(struct mtd_info *mtd, u_char *buf, int len) 99{ 100 struct nand_chip *this = mtd->priv; 101 102 while (unlikely(len > 0x800)) { 103 memcpy_fromio(buf, this->IO_ADDR_R, 0x800); 104 buf += 0x800; 105 len -= 0x800; 106 } 107 memcpy_fromio(buf, this->IO_ADDR_R, len); 108} 109 110static void cs553x_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 111{ 112 struct nand_chip *this = mtd->priv; 113 114 while (unlikely(len > 0x800)) { 115 memcpy_toio(this->IO_ADDR_R, buf, 0x800); 116 buf += 0x800; 117 len -= 0x800; 118 } 119 memcpy_toio(this->IO_ADDR_R, buf, len); 120} 121 122static unsigned char cs553x_read_byte(struct mtd_info *mtd) 123{ 124 struct nand_chip *this = mtd->priv; 125 return readb(this->IO_ADDR_R); 126} 127 128static void cs553x_write_byte(struct mtd_info *mtd, u_char byte) 129{ 130 struct nand_chip *this = mtd->priv; 131 int i = 100000; 132 133 while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) { 134 udelay(1); 135 i--; 136 } 137 writeb(byte, this->IO_ADDR_W + 0x801); 138} 139 140static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd, 141 unsigned int ctrl) 142{ 143 struct nand_chip *this = mtd->priv; 144 void __iomem *mmio_base = this->IO_ADDR_R; 145 if (ctrl & NAND_CTRL_CHANGE) { 146 unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01; 147 writeb(ctl, mmio_base + MM_NAND_CTL); 148 } 149 if (cmd != NAND_CMD_NONE) 150 cs553x_write_byte(mtd, cmd); 151} 152 153static int cs553x_device_ready(struct mtd_info *mtd) 154{ 155 struct nand_chip *this = mtd->priv; 156 void __iomem *mmio_base = this->IO_ADDR_R; 157 unsigned char foo = readb(mmio_base + MM_NAND_STS); 158 159 return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY); 160} 161 162static void cs_enable_hwecc(struct mtd_info *mtd, int mode) 163{ 164 struct nand_chip *this = mtd->priv; 165 void __iomem *mmio_base = this->IO_ADDR_R; 166 167 writeb(0x07, mmio_base + MM_NAND_ECC_CTL); 168} 169 170static int cs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) 171{ 172 uint32_t ecc; 173 struct nand_chip *this = mtd->priv; 174 void __iomem *mmio_base = this->IO_ADDR_R; 175 176 ecc = readl(mmio_base + MM_NAND_STS); 177 178 ecc_code[1] = ecc >> 8; 179 ecc_code[0] = ecc >> 16; 180 ecc_code[2] = ecc >> 24; 181 return 0; 182} 183 184static struct mtd_info *cs553x_mtd[4]; 185 186static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) 187{ 188 int err = 0; 189 struct nand_chip *this; 190 struct mtd_info *new_mtd; 191 192 printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr); 193 194 if (!mmio) { 195 printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n"); 196 return -ENXIO; 197 } 198 199 /* Allocate memory for MTD device structure and private data */ 200 new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); 201 if (!new_mtd) { 202 printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n"); 203 err = -ENOMEM; 204 goto out; 205 } 206 207 /* Get pointer to private data */ 208 this = (struct nand_chip *)(&new_mtd[1]); 209 210 /* Initialize structures */ 211 memset(new_mtd, 0, sizeof(struct mtd_info)); 212 memset(this, 0, sizeof(struct nand_chip)); 213 214 /* Link the private data with the MTD structure */ 215 new_mtd->priv = this; 216 new_mtd->owner = THIS_MODULE; 217 218 /* map physical address */ 219 this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096); 220 if (!this->IO_ADDR_R) { 221 printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr); 222 err = -EIO; 223 goto out_mtd; 224 } 225 226 this->cmd_ctrl = cs553x_hwcontrol; 227 this->dev_ready = cs553x_device_ready; 228 this->read_byte = cs553x_read_byte; 229 this->read_buf = cs553x_read_buf; 230 this->write_buf = cs553x_write_buf; 231 232 this->chip_delay = 0; 233 234 this->ecc.mode = NAND_ECC_HW; 235 this->ecc.size = 256; 236 this->ecc.bytes = 3; 237 this->ecc.hwctl = cs_enable_hwecc; 238 this->ecc.calculate = cs_calculate_ecc; 239 this->ecc.correct = nand_correct_data; 240 241 /* Enable the following for a flash based bad block table */ 242 this->options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR; 243 244 /* Scan to find existance of the device */ 245 if (nand_scan(new_mtd, 1)) { 246 err = -ENXIO; 247 goto out_ior; 248 } 249 250 new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs); 251 252 cs553x_mtd[cs] = new_mtd; 253 goto out; 254 255out_ior: 256 iounmap(this->IO_ADDR_R); 257out_mtd: 258 kfree(new_mtd); 259out: 260 return err; 261} 262 263static int is_geode(void) 264{ 265 /* These are the CPUs which will have a CS553[56] companion chip */ 266 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 267 boot_cpu_data.x86 == 5 && 268 boot_cpu_data.x86_model == 10) 269 return 1; /* Geode LX */ 270 271 if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC || 272 boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) && 273 boot_cpu_data.x86 == 5 && 274 boot_cpu_data.x86_model == 5) 275 return 1; /* Geode GX (n��e GX2) */ 276 277 return 0; 278} 279 280 281#ifdef CONFIG_MTD_PARTITIONS 282static const char *part_probes[] = { "cmdlinepart", NULL }; 283#endif 284 285 286static int __init cs553x_init(void) 287{ 288 int err = -ENXIO; 289 int i; 290 uint64_t val; 291 292#ifdef CONFIG_MTD_PARTITIONS 293 int mtd_parts_nb = 0; 294 struct mtd_partition *mtd_parts = NULL; 295#endif 296 297 /* If the CPU isn't a Geode GX or LX, abort */ 298 if (!is_geode()) 299 return -ENXIO; 300 301 /* If it doesn't have the CS553[56], abort */ 302 rdmsrl(MSR_DIVIL_GLD_CAP, val); 303 val &= ~0xFFULL; 304 if (val != CAP_CS5535 && val != CAP_CS5536) 305 return -ENXIO; 306 307 /* If it doesn't have the NAND controller enabled, abort */ 308 rdmsrl(MSR_DIVIL_BALL_OPTS, val); 309 if (val & PIN_OPT_IDE) { 310 printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n"); 311 return -ENXIO; 312 } 313 314 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) { 315 rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val); 316 317 if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND)) 318 err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF); 319 } 320 321 /* Register all devices together here. This means we can easily hack it to 322 do mtdconcat etc. if we want to. */ 323 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) { 324 if (cs553x_mtd[i]) { 325 326 /* If any devices registered, return success. Else the last error. */ 327#ifdef CONFIG_MTD_PARTITIONS 328 mtd_parts_nb = parse_mtd_partitions(cs553x_mtd[i], part_probes, &mtd_parts, 0); 329 if (mtd_parts_nb > 0) { 330 printk(KERN_NOTICE "Using command line partition definition\n"); 331 add_mtd_partitions(cs553x_mtd[i], mtd_parts, mtd_parts_nb); 332 } else { 333 add_mtd_device(cs553x_mtd[i]); 334 } 335#else 336 add_mtd_device(cs553x_mtd[i]); 337#endif 338 err = 0; 339 } 340 } 341 342 return err; 343} 344 345module_init(cs553x_init); 346 347static void __exit cs553x_cleanup(void) 348{ 349 int i; 350 351 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) { 352 struct mtd_info *mtd = cs553x_mtd[i]; 353 struct nand_chip *this; 354 void __iomem *mmio_base; 355 356 if (!mtd) 357 continue; 358 359 this = cs553x_mtd[i]->priv; 360 mmio_base = this->IO_ADDR_R; 361 362 /* Release resources, unregister device */ 363 nand_release(cs553x_mtd[i]); 364 kfree(cs553x_mtd[i]->name); 365 cs553x_mtd[i] = NULL; 366 367 /* unmap physical address */ 368 iounmap(mmio_base); 369 370 /* Free the MTD device structure */ 371 kfree(mtd); 372 } 373} 374 375module_exit(cs553x_cleanup); 376 377MODULE_LICENSE("GPL"); 378MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); 379MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip"); 380