1/* 2 * drivers/mtd/nand/au1550nd.c 3 * 4 * Copyright (C) 2004 Embedded Edge, LLC 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 12#include <linux/slab.h> 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/interrupt.h> 16#include <linux/mtd/mtd.h> 17#include <linux/mtd/nand.h> 18#include <linux/mtd/partitions.h> 19#include <asm/io.h> 20 21#include <asm/mach-au1x00/au1xxx.h> 22#include <asm/mach-db1x00/bcsr.h> 23 24/* 25 * MTD structure for NAND controller 26 */ 27static struct mtd_info *au1550_mtd = NULL; 28static void __iomem *p_nand; 29static int nand_width = 1; /* default x8 */ 30static void (*au1550_write_byte)(struct mtd_info *, u_char); 31 32/* 33 * Define partitions for flash device 34 */ 35static const struct mtd_partition partition_info[] = { 36 { 37 .name = "NAND FS 0", 38 .offset = 0, 39 .size = 8 * 1024 * 1024}, 40 { 41 .name = "NAND FS 1", 42 .offset = MTDPART_OFS_APPEND, 43 .size = MTDPART_SIZ_FULL} 44}; 45 46/** 47 * au_read_byte - read one byte from the chip 48 * @mtd: MTD device structure 49 * 50 * read function for 8bit buswith 51 */ 52static u_char au_read_byte(struct mtd_info *mtd) 53{ 54 struct nand_chip *this = mtd->priv; 55 u_char ret = readb(this->IO_ADDR_R); 56 au_sync(); 57 return ret; 58} 59 60/** 61 * au_write_byte - write one byte to the chip 62 * @mtd: MTD device structure 63 * @byte: pointer to data byte to write 64 * 65 * write function for 8it buswith 66 */ 67static void au_write_byte(struct mtd_info *mtd, u_char byte) 68{ 69 struct nand_chip *this = mtd->priv; 70 writeb(byte, this->IO_ADDR_W); 71 au_sync(); 72} 73 74/** 75 * au_read_byte16 - read one byte endianess aware from the chip 76 * @mtd: MTD device structure 77 * 78 * read function for 16bit buswith with 79 * endianess conversion 80 */ 81static u_char au_read_byte16(struct mtd_info *mtd) 82{ 83 struct nand_chip *this = mtd->priv; 84 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); 85 au_sync(); 86 return ret; 87} 88 89/** 90 * au_write_byte16 - write one byte endianess aware to the chip 91 * @mtd: MTD device structure 92 * @byte: pointer to data byte to write 93 * 94 * write function for 16bit buswith with 95 * endianess conversion 96 */ 97static void au_write_byte16(struct mtd_info *mtd, u_char byte) 98{ 99 struct nand_chip *this = mtd->priv; 100 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); 101 au_sync(); 102} 103 104/** 105 * au_read_word - read one word from the chip 106 * @mtd: MTD device structure 107 * 108 * read function for 16bit buswith without 109 * endianess conversion 110 */ 111static u16 au_read_word(struct mtd_info *mtd) 112{ 113 struct nand_chip *this = mtd->priv; 114 u16 ret = readw(this->IO_ADDR_R); 115 au_sync(); 116 return ret; 117} 118 119/** 120 * au_write_buf - write buffer to chip 121 * @mtd: MTD device structure 122 * @buf: data buffer 123 * @len: number of bytes to write 124 * 125 * write function for 8bit buswith 126 */ 127static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 128{ 129 int i; 130 struct nand_chip *this = mtd->priv; 131 132 for (i = 0; i < len; i++) { 133 writeb(buf[i], this->IO_ADDR_W); 134 au_sync(); 135 } 136} 137 138/** 139 * au_read_buf - read chip data into buffer 140 * @mtd: MTD device structure 141 * @buf: buffer to store date 142 * @len: number of bytes to read 143 * 144 * read function for 8bit buswith 145 */ 146static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) 147{ 148 int i; 149 struct nand_chip *this = mtd->priv; 150 151 for (i = 0; i < len; i++) { 152 buf[i] = readb(this->IO_ADDR_R); 153 au_sync(); 154 } 155} 156 157/** 158 * au_verify_buf - Verify chip data against buffer 159 * @mtd: MTD device structure 160 * @buf: buffer containing the data to compare 161 * @len: number of bytes to compare 162 * 163 * verify function for 8bit buswith 164 */ 165static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) 166{ 167 int i; 168 struct nand_chip *this = mtd->priv; 169 170 for (i = 0; i < len; i++) { 171 if (buf[i] != readb(this->IO_ADDR_R)) 172 return -EFAULT; 173 au_sync(); 174 } 175 176 return 0; 177} 178 179/** 180 * au_write_buf16 - write buffer to chip 181 * @mtd: MTD device structure 182 * @buf: data buffer 183 * @len: number of bytes to write 184 * 185 * write function for 16bit buswith 186 */ 187static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) 188{ 189 int i; 190 struct nand_chip *this = mtd->priv; 191 u16 *p = (u16 *) buf; 192 len >>= 1; 193 194 for (i = 0; i < len; i++) { 195 writew(p[i], this->IO_ADDR_W); 196 au_sync(); 197 } 198 199} 200 201/** 202 * au_read_buf16 - read chip data into buffer 203 * @mtd: MTD device structure 204 * @buf: buffer to store date 205 * @len: number of bytes to read 206 * 207 * read function for 16bit buswith 208 */ 209static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) 210{ 211 int i; 212 struct nand_chip *this = mtd->priv; 213 u16 *p = (u16 *) buf; 214 len >>= 1; 215 216 for (i = 0; i < len; i++) { 217 p[i] = readw(this->IO_ADDR_R); 218 au_sync(); 219 } 220} 221 222/** 223 * au_verify_buf16 - Verify chip data against buffer 224 * @mtd: MTD device structure 225 * @buf: buffer containing the data to compare 226 * @len: number of bytes to compare 227 * 228 * verify function for 16bit buswith 229 */ 230static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) 231{ 232 int i; 233 struct nand_chip *this = mtd->priv; 234 u16 *p = (u16 *) buf; 235 len >>= 1; 236 237 for (i = 0; i < len; i++) { 238 if (p[i] != readw(this->IO_ADDR_R)) 239 return -EFAULT; 240 au_sync(); 241 } 242 return 0; 243} 244 245/* Select the chip by setting nCE to low */ 246#define NAND_CTL_SETNCE 1 247/* Deselect the chip by setting nCE to high */ 248#define NAND_CTL_CLRNCE 2 249/* Select the command latch by setting CLE to high */ 250#define NAND_CTL_SETCLE 3 251/* Deselect the command latch by setting CLE to low */ 252#define NAND_CTL_CLRCLE 4 253/* Select the address latch by setting ALE to high */ 254#define NAND_CTL_SETALE 5 255/* Deselect the address latch by setting ALE to low */ 256#define NAND_CTL_CLRALE 6 257 258static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) 259{ 260 register struct nand_chip *this = mtd->priv; 261 262 switch (cmd) { 263 264 case NAND_CTL_SETCLE: 265 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; 266 break; 267 268 case NAND_CTL_CLRCLE: 269 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; 270 break; 271 272 case NAND_CTL_SETALE: 273 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; 274 break; 275 276 case NAND_CTL_CLRALE: 277 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; 278 udelay(1); 279 break; 280 281 case NAND_CTL_SETNCE: 282 /* assert (force assert) chip enable */ 283 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL); 284 break; 285 286 case NAND_CTL_CLRNCE: 287 /* deassert chip enable */ 288 au_writel(0, MEM_STNDCTL); 289 break; 290 } 291 292 this->IO_ADDR_R = this->IO_ADDR_W; 293 294 /* Drain the writebuffer */ 295 au_sync(); 296} 297 298int au1550_device_ready(struct mtd_info *mtd) 299{ 300 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; 301 au_sync(); 302 return ret; 303} 304 305/** 306 * au1550_select_chip - control -CE line 307 * Forbid driving -CE manually permitting the NAND controller to do this. 308 * Keeping -CE asserted during the whole sector reads interferes with the 309 * NOR flash and PCMCIA drivers as it causes contention on the static bus. 310 * We only have to hold -CE low for the NAND read commands since the flash 311 * chip needs it to be asserted during chip not ready time but the NAND 312 * controller keeps it released. 313 * 314 * @mtd: MTD device structure 315 * @chip: chipnumber to select, -1 for deselect 316 */ 317static void au1550_select_chip(struct mtd_info *mtd, int chip) 318{ 319} 320 321/** 322 * au1550_command - Send command to NAND device 323 * @mtd: MTD device structure 324 * @command: the command to be sent 325 * @column: the column address for this command, -1 if none 326 * @page_addr: the page address for this command, -1 if none 327 */ 328static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) 329{ 330 register struct nand_chip *this = mtd->priv; 331 int ce_override = 0, i; 332 ulong flags; 333 334 /* Begin command latch cycle */ 335 au1550_hwcontrol(mtd, NAND_CTL_SETCLE); 336 /* 337 * Write out the command to the device. 338 */ 339 if (command == NAND_CMD_SEQIN) { 340 int readcmd; 341 342 if (column >= mtd->writesize) { 343 /* OOB area */ 344 column -= mtd->writesize; 345 readcmd = NAND_CMD_READOOB; 346 } else if (column < 256) { 347 /* First 256 bytes --> READ0 */ 348 readcmd = NAND_CMD_READ0; 349 } else { 350 column -= 256; 351 readcmd = NAND_CMD_READ1; 352 } 353 au1550_write_byte(mtd, readcmd); 354 } 355 au1550_write_byte(mtd, command); 356 357 /* Set ALE and clear CLE to start address cycle */ 358 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); 359 360 if (column != -1 || page_addr != -1) { 361 au1550_hwcontrol(mtd, NAND_CTL_SETALE); 362 363 /* Serially input address */ 364 if (column != -1) { 365 /* Adjust columns for 16 bit buswidth */ 366 if (this->options & NAND_BUSWIDTH_16) 367 column >>= 1; 368 au1550_write_byte(mtd, column); 369 } 370 if (page_addr != -1) { 371 au1550_write_byte(mtd, (u8)(page_addr & 0xff)); 372 373 if (command == NAND_CMD_READ0 || 374 command == NAND_CMD_READ1 || 375 command == NAND_CMD_READOOB) { 376 /* 377 * NAND controller will release -CE after 378 * the last address byte is written, so we'll 379 * have to forcibly assert it. No interrupts 380 * are allowed while we do this as we don't 381 * want the NOR flash or PCMCIA drivers to 382 * steal our precious bytes of data... 383 */ 384 ce_override = 1; 385 local_irq_save(flags); 386 au1550_hwcontrol(mtd, NAND_CTL_SETNCE); 387 } 388 389 au1550_write_byte(mtd, (u8)(page_addr >> 8)); 390 391 /* One more address cycle for devices > 32MiB */ 392 if (this->chipsize > (32 << 20)) 393 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); 394 } 395 /* Latch in address */ 396 au1550_hwcontrol(mtd, NAND_CTL_CLRALE); 397 } 398 399 /* 400 * Program and erase have their own busy handlers. 401 * Status and sequential in need no delay. 402 */ 403 switch (command) { 404 405 case NAND_CMD_PAGEPROG: 406 case NAND_CMD_ERASE1: 407 case NAND_CMD_ERASE2: 408 case NAND_CMD_SEQIN: 409 case NAND_CMD_STATUS: 410 return; 411 412 case NAND_CMD_RESET: 413 break; 414 415 case NAND_CMD_READ0: 416 case NAND_CMD_READ1: 417 case NAND_CMD_READOOB: 418 /* Check if we're really driving -CE low (just in case) */ 419 if (unlikely(!ce_override)) 420 break; 421 422 /* Apply a short delay always to ensure that we do wait tWB. */ 423 ndelay(100); 424 /* Wait for a chip to become ready... */ 425 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) 426 udelay(1); 427 428 /* Release -CE and re-enable interrupts. */ 429 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); 430 local_irq_restore(flags); 431 return; 432 } 433 /* Apply this short delay always to ensure that we do wait tWB. */ 434 ndelay(100); 435 436 while(!this->dev_ready(mtd)); 437} 438 439 440/* 441 * Main initialization routine 442 */ 443static int __init au1xxx_nand_init(void) 444{ 445 struct nand_chip *this; 446 u16 boot_swapboot = 0; /* default value */ 447 int retval; 448 u32 mem_staddr; 449 u32 nand_phys; 450 451 /* Allocate memory for MTD device structure and private data */ 452 au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); 453 if (!au1550_mtd) { 454 printk("Unable to allocate NAND MTD dev structure.\n"); 455 return -ENOMEM; 456 } 457 458 /* Get pointer to private data */ 459 this = (struct nand_chip *)(&au1550_mtd[1]); 460 461 /* Link the private data with the MTD structure */ 462 au1550_mtd->priv = this; 463 au1550_mtd->owner = THIS_MODULE; 464 465 466 /* MEM_STNDCTL: disable ints, disable nand boot */ 467 au_writel(0, MEM_STNDCTL); 468 469#ifdef CONFIG_MIPS_PB1550 470 /* set gpio206 high */ 471 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR); 472 473 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); 474 475 switch (boot_swapboot) { 476 case 0: 477 case 2: 478 case 8: 479 case 0xC: 480 case 0xD: 481 /* x16 NAND Flash */ 482 nand_width = 0; 483 break; 484 case 1: 485 case 9: 486 case 3: 487 case 0xE: 488 case 0xF: 489 /* x8 NAND Flash */ 490 nand_width = 1; 491 break; 492 default: 493 printk("Pb1550 NAND: bad boot:swap\n"); 494 retval = -EINVAL; 495 goto outmem; 496 } 497#endif 498 499 /* Configure chip-select; normally done by boot code, e.g. YAMON */ 500#ifdef NAND_STCFG 501 if (NAND_CS == 0) { 502 au_writel(NAND_STCFG, MEM_STCFG0); 503 au_writel(NAND_STTIME, MEM_STTIME0); 504 au_writel(NAND_STADDR, MEM_STADDR0); 505 } 506 if (NAND_CS == 1) { 507 au_writel(NAND_STCFG, MEM_STCFG1); 508 au_writel(NAND_STTIME, MEM_STTIME1); 509 au_writel(NAND_STADDR, MEM_STADDR1); 510 } 511 if (NAND_CS == 2) { 512 au_writel(NAND_STCFG, MEM_STCFG2); 513 au_writel(NAND_STTIME, MEM_STTIME2); 514 au_writel(NAND_STADDR, MEM_STADDR2); 515 } 516 if (NAND_CS == 3) { 517 au_writel(NAND_STCFG, MEM_STCFG3); 518 au_writel(NAND_STTIME, MEM_STTIME3); 519 au_writel(NAND_STADDR, MEM_STADDR3); 520 } 521#endif 522 523 /* Locate NAND chip-select in order to determine NAND phys address */ 524 mem_staddr = 0x00000000; 525 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0)) 526 mem_staddr = au_readl(MEM_STADDR0); 527 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1)) 528 mem_staddr = au_readl(MEM_STADDR1); 529 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2)) 530 mem_staddr = au_readl(MEM_STADDR2); 531 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3)) 532 mem_staddr = au_readl(MEM_STADDR3); 533 534 if (mem_staddr == 0x00000000) { 535 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n"); 536 kfree(au1550_mtd); 537 return 1; 538 } 539 nand_phys = (mem_staddr << 4) & 0xFFFC0000; 540 541 p_nand = ioremap(nand_phys, 0x1000); 542 543 /* make controller and MTD agree */ 544 if (NAND_CS == 0) 545 nand_width = au_readl(MEM_STCFG0) & (1 << 22); 546 if (NAND_CS == 1) 547 nand_width = au_readl(MEM_STCFG1) & (1 << 22); 548 if (NAND_CS == 2) 549 nand_width = au_readl(MEM_STCFG2) & (1 << 22); 550 if (NAND_CS == 3) 551 nand_width = au_readl(MEM_STCFG3) & (1 << 22); 552 553 /* Set address of hardware control function */ 554 this->dev_ready = au1550_device_ready; 555 this->select_chip = au1550_select_chip; 556 this->cmdfunc = au1550_command; 557 558 /* 30 us command delay time */ 559 this->chip_delay = 30; 560 this->ecc.mode = NAND_ECC_SOFT; 561 562 this->options = NAND_NO_AUTOINCR; 563 564 if (!nand_width) 565 this->options |= NAND_BUSWIDTH_16; 566 567 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte; 568 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte; 569 this->read_word = au_read_word; 570 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf; 571 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf; 572 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf; 573 574 /* Scan to find existence of the device */ 575 if (nand_scan(au1550_mtd, 1)) { 576 retval = -ENXIO; 577 goto outio; 578 } 579 580 /* Register the partitions */ 581 add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info)); 582 583 return 0; 584 585 outio: 586 iounmap(p_nand); 587 588 outmem: 589 kfree(au1550_mtd); 590 return retval; 591} 592 593module_init(au1xxx_nand_init); 594 595/* 596 * Clean up routine 597 */ 598static void __exit au1550_cleanup(void) 599{ 600 /* Release resources, unregister device */ 601 nand_release(au1550_mtd); 602 603 /* Free the MTD device structure */ 604 kfree(au1550_mtd); 605 606 /* Unmap */ 607 iounmap(p_nand); 608} 609 610module_exit(au1550_cleanup); 611 612MODULE_LICENSE("GPL"); 613MODULE_AUTHOR("Embedded Edge, LLC"); 614MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); 615