1/* 2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 3 * 4 * This is a driver for the SDHC controller found in Freescale MX2/MX3 5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 6 * Unlike the hardware found on MX1, this hardware just works and does 7 * not need all the quirks found in imxmmc.c, hence the separate driver. 8 * 9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 11 * 12 * derived from pxamci.c by Russell King 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 */ 19 20#include <linux/module.h> 21#include <linux/init.h> 22#include <linux/ioport.h> 23#include <linux/platform_device.h> 24#include <linux/interrupt.h> 25#include <linux/irq.h> 26#include <linux/blkdev.h> 27#include <linux/dma-mapping.h> 28#include <linux/mmc/host.h> 29#include <linux/mmc/card.h> 30#include <linux/delay.h> 31#include <linux/clk.h> 32#include <linux/io.h> 33#include <linux/gpio.h> 34 35#include <asm/dma.h> 36#include <asm/irq.h> 37#include <asm/sizes.h> 38#include <mach/mmc.h> 39 40#ifdef CONFIG_ARCH_MX2 41#include <mach/dma-mx1-mx2.h> 42#define HAS_DMA 43#endif 44 45#define DRIVER_NAME "mxc-mmc" 46 47#define MMC_REG_STR_STP_CLK 0x00 48#define MMC_REG_STATUS 0x04 49#define MMC_REG_CLK_RATE 0x08 50#define MMC_REG_CMD_DAT_CONT 0x0C 51#define MMC_REG_RES_TO 0x10 52#define MMC_REG_READ_TO 0x14 53#define MMC_REG_BLK_LEN 0x18 54#define MMC_REG_NOB 0x1C 55#define MMC_REG_REV_NO 0x20 56#define MMC_REG_INT_CNTR 0x24 57#define MMC_REG_CMD 0x28 58#define MMC_REG_ARG 0x2C 59#define MMC_REG_RES_FIFO 0x34 60#define MMC_REG_BUFFER_ACCESS 0x38 61 62#define STR_STP_CLK_RESET (1 << 3) 63#define STR_STP_CLK_START_CLK (1 << 1) 64#define STR_STP_CLK_STOP_CLK (1 << 0) 65 66#define STATUS_CARD_INSERTION (1 << 31) 67#define STATUS_CARD_REMOVAL (1 << 30) 68#define STATUS_YBUF_EMPTY (1 << 29) 69#define STATUS_XBUF_EMPTY (1 << 28) 70#define STATUS_YBUF_FULL (1 << 27) 71#define STATUS_XBUF_FULL (1 << 26) 72#define STATUS_BUF_UND_RUN (1 << 25) 73#define STATUS_BUF_OVFL (1 << 24) 74#define STATUS_SDIO_INT_ACTIVE (1 << 14) 75#define STATUS_END_CMD_RESP (1 << 13) 76#define STATUS_WRITE_OP_DONE (1 << 12) 77#define STATUS_DATA_TRANS_DONE (1 << 11) 78#define STATUS_READ_OP_DONE (1 << 11) 79#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) 80#define STATUS_CARD_BUS_CLK_RUN (1 << 8) 81#define STATUS_BUF_READ_RDY (1 << 7) 82#define STATUS_BUF_WRITE_RDY (1 << 6) 83#define STATUS_RESP_CRC_ERR (1 << 5) 84#define STATUS_CRC_READ_ERR (1 << 3) 85#define STATUS_CRC_WRITE_ERR (1 << 2) 86#define STATUS_TIME_OUT_RESP (1 << 1) 87#define STATUS_TIME_OUT_READ (1 << 0) 88#define STATUS_ERR_MASK 0x2f 89 90#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) 91#define CMD_DAT_CONT_STOP_READWAIT (1 << 11) 92#define CMD_DAT_CONT_START_READWAIT (1 << 10) 93#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) 94#define CMD_DAT_CONT_INIT (1 << 7) 95#define CMD_DAT_CONT_WRITE (1 << 4) 96#define CMD_DAT_CONT_DATA_ENABLE (1 << 3) 97#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) 98#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) 99#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) 100 101#define INT_SDIO_INT_WKP_EN (1 << 18) 102#define INT_CARD_INSERTION_WKP_EN (1 << 17) 103#define INT_CARD_REMOVAL_WKP_EN (1 << 16) 104#define INT_CARD_INSERTION_EN (1 << 15) 105#define INT_CARD_REMOVAL_EN (1 << 14) 106#define INT_SDIO_IRQ_EN (1 << 13) 107#define INT_DAT0_EN (1 << 12) 108#define INT_BUF_READ_EN (1 << 4) 109#define INT_BUF_WRITE_EN (1 << 3) 110#define INT_END_CMD_RES_EN (1 << 2) 111#define INT_WRITE_OP_DONE_EN (1 << 1) 112#define INT_READ_OP_EN (1 << 0) 113 114struct mxcmci_host { 115 struct mmc_host *mmc; 116 struct resource *res; 117 void __iomem *base; 118 int irq; 119 int detect_irq; 120 int dma; 121 int do_dma; 122 int default_irq_mask; 123 int use_sdio; 124 unsigned int power_mode; 125 struct imxmmc_platform_data *pdata; 126 127 struct mmc_request *req; 128 struct mmc_command *cmd; 129 struct mmc_data *data; 130 131 unsigned int dma_nents; 132 unsigned int datasize; 133 unsigned int dma_dir; 134 135 u16 rev_no; 136 unsigned int cmdat; 137 138 struct clk *clk; 139 140 int clock; 141 142 struct work_struct datawork; 143 spinlock_t lock; 144}; 145 146static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 147 148static inline int mxcmci_use_dma(struct mxcmci_host *host) 149{ 150 return host->do_dma; 151} 152 153static void mxcmci_softreset(struct mxcmci_host *host) 154{ 155 int i; 156 157 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 158 159 /* reset sequence */ 160 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK); 161 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 162 host->base + MMC_REG_STR_STP_CLK); 163 164 for (i = 0; i < 8; i++) 165 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 166 167 writew(0xff, host->base + MMC_REG_RES_TO); 168} 169 170static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 171{ 172 unsigned int nob = data->blocks; 173 unsigned int blksz = data->blksz; 174 unsigned int datasize = nob * blksz; 175#ifdef HAS_DMA 176 struct scatterlist *sg; 177 int i; 178 int ret; 179#endif 180 if (data->flags & MMC_DATA_STREAM) 181 nob = 0xffff; 182 183 host->data = data; 184 data->bytes_xfered = 0; 185 186 writew(nob, host->base + MMC_REG_NOB); 187 writew(blksz, host->base + MMC_REG_BLK_LEN); 188 host->datasize = datasize; 189 190#ifdef HAS_DMA 191 for_each_sg(data->sg, sg, data->sg_len, i) { 192 if (sg->offset & 3 || sg->length & 3) { 193 host->do_dma = 0; 194 return 0; 195 } 196 } 197 198 if (data->flags & MMC_DATA_READ) { 199 host->dma_dir = DMA_FROM_DEVICE; 200 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 201 data->sg_len, host->dma_dir); 202 203 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, 204 datasize, 205 host->res->start + MMC_REG_BUFFER_ACCESS, 206 DMA_MODE_READ); 207 } else { 208 host->dma_dir = DMA_TO_DEVICE; 209 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 210 data->sg_len, host->dma_dir); 211 212 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, 213 datasize, 214 host->res->start + MMC_REG_BUFFER_ACCESS, 215 DMA_MODE_WRITE); 216 } 217 218 if (ret) { 219 dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret); 220 return ret; 221 } 222 wmb(); 223 224 imx_dma_enable(host->dma); 225#endif /* HAS_DMA */ 226 return 0; 227} 228 229static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 230 unsigned int cmdat) 231{ 232 u32 int_cntr = host->default_irq_mask; 233 unsigned long flags; 234 235 WARN_ON(host->cmd != NULL); 236 host->cmd = cmd; 237 238 switch (mmc_resp_type(cmd)) { 239 case MMC_RSP_R1: /* short CRC, OPCODE */ 240 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 241 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; 242 break; 243 case MMC_RSP_R2: /* long 136 bit + CRC */ 244 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; 245 break; 246 case MMC_RSP_R3: /* short */ 247 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; 248 break; 249 case MMC_RSP_NONE: 250 break; 251 default: 252 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", 253 mmc_resp_type(cmd)); 254 cmd->error = -EINVAL; 255 return -EINVAL; 256 } 257 258 int_cntr = INT_END_CMD_RES_EN; 259 260 if (mxcmci_use_dma(host)) 261 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN; 262 263 spin_lock_irqsave(&host->lock, flags); 264 if (host->use_sdio) 265 int_cntr |= INT_SDIO_IRQ_EN; 266 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 267 spin_unlock_irqrestore(&host->lock, flags); 268 269 writew(cmd->opcode, host->base + MMC_REG_CMD); 270 writel(cmd->arg, host->base + MMC_REG_ARG); 271 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); 272 273 return 0; 274} 275 276static void mxcmci_finish_request(struct mxcmci_host *host, 277 struct mmc_request *req) 278{ 279 u32 int_cntr = host->default_irq_mask; 280 unsigned long flags; 281 282 spin_lock_irqsave(&host->lock, flags); 283 if (host->use_sdio) 284 int_cntr |= INT_SDIO_IRQ_EN; 285 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 286 spin_unlock_irqrestore(&host->lock, flags); 287 288 host->req = NULL; 289 host->cmd = NULL; 290 host->data = NULL; 291 292 mmc_request_done(host->mmc, req); 293} 294 295static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) 296{ 297 struct mmc_data *data = host->data; 298 int data_error; 299 300#ifdef HAS_DMA 301 if (mxcmci_use_dma(host)) { 302 imx_dma_disable(host->dma); 303 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, 304 host->dma_dir); 305 } 306#endif 307 308 if (stat & STATUS_ERR_MASK) { 309 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 310 stat); 311 if (stat & STATUS_CRC_READ_ERR) { 312 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); 313 data->error = -EILSEQ; 314 } else if (stat & STATUS_CRC_WRITE_ERR) { 315 u32 err_code = (stat >> 9) & 0x3; 316 if (err_code == 2) { /* No CRC response */ 317 dev_err(mmc_dev(host->mmc), 318 "%s: No CRC -ETIMEDOUT\n", __func__); 319 data->error = -ETIMEDOUT; 320 } else { 321 dev_err(mmc_dev(host->mmc), 322 "%s: -EILSEQ\n", __func__); 323 data->error = -EILSEQ; 324 } 325 } else if (stat & STATUS_TIME_OUT_READ) { 326 dev_err(mmc_dev(host->mmc), 327 "%s: read -ETIMEDOUT\n", __func__); 328 data->error = -ETIMEDOUT; 329 } else { 330 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); 331 data->error = -EIO; 332 } 333 } else { 334 data->bytes_xfered = host->datasize; 335 } 336 337 data_error = data->error; 338 339 host->data = NULL; 340 341 return data_error; 342} 343 344static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) 345{ 346 struct mmc_command *cmd = host->cmd; 347 int i; 348 u32 a, b, c; 349 350 if (!cmd) 351 return; 352 353 if (stat & STATUS_TIME_OUT_RESP) { 354 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 355 cmd->error = -ETIMEDOUT; 356 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 357 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 358 cmd->error = -EILSEQ; 359 } 360 361 if (cmd->flags & MMC_RSP_PRESENT) { 362 if (cmd->flags & MMC_RSP_136) { 363 for (i = 0; i < 4; i++) { 364 a = readw(host->base + MMC_REG_RES_FIFO); 365 b = readw(host->base + MMC_REG_RES_FIFO); 366 cmd->resp[i] = a << 16 | b; 367 } 368 } else { 369 a = readw(host->base + MMC_REG_RES_FIFO); 370 b = readw(host->base + MMC_REG_RES_FIFO); 371 c = readw(host->base + MMC_REG_RES_FIFO); 372 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 373 } 374 } 375} 376 377static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 378{ 379 u32 stat; 380 unsigned long timeout = jiffies + HZ; 381 382 do { 383 stat = readl(host->base + MMC_REG_STATUS); 384 if (stat & STATUS_ERR_MASK) 385 return stat; 386 if (time_after(jiffies, timeout)) { 387 mxcmci_softreset(host); 388 mxcmci_set_clk_rate(host, host->clock); 389 return STATUS_TIME_OUT_READ; 390 } 391 if (stat & mask) 392 return 0; 393 cpu_relax(); 394 } while (1); 395} 396 397static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) 398{ 399 unsigned int stat; 400 u32 *buf = _buf; 401 402 while (bytes > 3) { 403 stat = mxcmci_poll_status(host, 404 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 405 if (stat) 406 return stat; 407 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS); 408 bytes -= 4; 409 } 410 411 if (bytes) { 412 u8 *b = (u8 *)buf; 413 u32 tmp; 414 415 stat = mxcmci_poll_status(host, 416 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 417 if (stat) 418 return stat; 419 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS); 420 memcpy(b, &tmp, bytes); 421 } 422 423 return 0; 424} 425 426static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 427{ 428 unsigned int stat; 429 u32 *buf = _buf; 430 431 while (bytes > 3) { 432 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 433 if (stat) 434 return stat; 435 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS); 436 bytes -= 4; 437 } 438 439 if (bytes) { 440 u8 *b = (u8 *)buf; 441 u32 tmp; 442 443 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 444 if (stat) 445 return stat; 446 447 memcpy(&tmp, b, bytes); 448 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS); 449 } 450 451 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 452 if (stat) 453 return stat; 454 455 return 0; 456} 457 458static int mxcmci_transfer_data(struct mxcmci_host *host) 459{ 460 struct mmc_data *data = host->req->data; 461 struct scatterlist *sg; 462 int stat, i; 463 464 host->data = data; 465 host->datasize = 0; 466 467 if (data->flags & MMC_DATA_READ) { 468 for_each_sg(data->sg, sg, data->sg_len, i) { 469 stat = mxcmci_pull(host, sg_virt(sg), sg->length); 470 if (stat) 471 return stat; 472 host->datasize += sg->length; 473 } 474 } else { 475 for_each_sg(data->sg, sg, data->sg_len, i) { 476 stat = mxcmci_push(host, sg_virt(sg), sg->length); 477 if (stat) 478 return stat; 479 host->datasize += sg->length; 480 } 481 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); 482 if (stat) 483 return stat; 484 } 485 return 0; 486} 487 488static void mxcmci_datawork(struct work_struct *work) 489{ 490 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 491 datawork); 492 int datastat = mxcmci_transfer_data(host); 493 494 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 495 host->base + MMC_REG_STATUS); 496 mxcmci_finish_data(host, datastat); 497 498 if (host->req->stop) { 499 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 500 mxcmci_finish_request(host, host->req); 501 return; 502 } 503 } else { 504 mxcmci_finish_request(host, host->req); 505 } 506} 507 508#ifdef HAS_DMA 509static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) 510{ 511 struct mmc_data *data = host->data; 512 int data_error; 513 514 if (!data) 515 return; 516 517 data_error = mxcmci_finish_data(host, stat); 518 519 mxcmci_read_response(host, stat); 520 host->cmd = NULL; 521 522 if (host->req->stop) { 523 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 524 mxcmci_finish_request(host, host->req); 525 return; 526 } 527 } else { 528 mxcmci_finish_request(host, host->req); 529 } 530} 531#endif /* HAS_DMA */ 532 533static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) 534{ 535 mxcmci_read_response(host, stat); 536 host->cmd = NULL; 537 538 if (!host->data && host->req) { 539 mxcmci_finish_request(host, host->req); 540 return; 541 } 542 543 /* For the DMA case the DMA engine handles the data transfer 544 * automatically. For non DMA we have to do it ourselves. 545 * Don't do it in interrupt context though. 546 */ 547 if (!mxcmci_use_dma(host) && host->data) 548 schedule_work(&host->datawork); 549 550} 551 552static irqreturn_t mxcmci_irq(int irq, void *devid) 553{ 554 struct mxcmci_host *host = devid; 555 unsigned long flags; 556 bool sdio_irq; 557 u32 stat; 558 559 stat = readl(host->base + MMC_REG_STATUS); 560 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 561 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS); 562 563 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 564 565 spin_lock_irqsave(&host->lock, flags); 566 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 567 spin_unlock_irqrestore(&host->lock, flags); 568 569#ifdef HAS_DMA 570 if (mxcmci_use_dma(host) && 571 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE))) 572 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 573 host->base + MMC_REG_STATUS); 574#endif 575 576 if (sdio_irq) { 577 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS); 578 mmc_signal_sdio_irq(host->mmc); 579 } 580 581 if (stat & STATUS_END_CMD_RESP) 582 mxcmci_cmd_done(host, stat); 583 584#ifdef HAS_DMA 585 if (mxcmci_use_dma(host) && 586 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) 587 mxcmci_data_done(host, stat); 588#endif 589 if (host->default_irq_mask && 590 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) 591 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 592 return IRQ_HANDLED; 593} 594 595static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) 596{ 597 struct mxcmci_host *host = mmc_priv(mmc); 598 unsigned int cmdat = host->cmdat; 599 int error; 600 601 WARN_ON(host->req != NULL); 602 603 host->req = req; 604 host->cmdat &= ~CMD_DAT_CONT_INIT; 605#ifdef HAS_DMA 606 host->do_dma = 1; 607#endif 608 if (req->data) { 609 error = mxcmci_setup_data(host, req->data); 610 if (error) { 611 req->cmd->error = error; 612 goto out; 613 } 614 615 616 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 617 618 if (req->data->flags & MMC_DATA_WRITE) 619 cmdat |= CMD_DAT_CONT_WRITE; 620 } 621 622 error = mxcmci_start_cmd(host, req->cmd, cmdat); 623out: 624 if (error) 625 mxcmci_finish_request(host, req); 626} 627 628static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) 629{ 630 unsigned int divider; 631 int prescaler = 0; 632 unsigned int clk_in = clk_get_rate(host->clk); 633 634 while (prescaler <= 0x800) { 635 for (divider = 1; divider <= 0xF; divider++) { 636 int x; 637 638 x = (clk_in / (divider + 1)); 639 640 if (prescaler) 641 x /= (prescaler * 2); 642 643 if (x <= clk_ios) 644 break; 645 } 646 if (divider < 0x10) 647 break; 648 649 if (prescaler == 0) 650 prescaler = 1; 651 else 652 prescaler <<= 1; 653 } 654 655 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE); 656 657 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 658 prescaler, divider, clk_in, clk_ios); 659} 660 661static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 662{ 663 struct mxcmci_host *host = mmc_priv(mmc); 664#ifdef HAS_DMA 665 unsigned int blen; 666 /* 667 * use burstlen of 64 in 4 bit mode (--> reg value 0) 668 * use burstlen of 16 in 1 bit mode (--> reg value 16) 669 */ 670 if (ios->bus_width == MMC_BUS_WIDTH_4) 671 blen = 0; 672 else 673 blen = 16; 674 675 imx_dma_config_burstlen(host->dma, blen); 676#endif 677 if (ios->bus_width == MMC_BUS_WIDTH_4) 678 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 679 else 680 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; 681 682 if (host->power_mode != ios->power_mode) { 683 if (host->pdata && host->pdata->setpower) 684 host->pdata->setpower(mmc_dev(mmc), ios->vdd); 685 host->power_mode = ios->power_mode; 686 if (ios->power_mode == MMC_POWER_ON) 687 host->cmdat |= CMD_DAT_CONT_INIT; 688 } 689 690 if (ios->clock) { 691 mxcmci_set_clk_rate(host, ios->clock); 692 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 693 } else { 694 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); 695 } 696 697 host->clock = ios->clock; 698} 699 700static irqreturn_t mxcmci_detect_irq(int irq, void *data) 701{ 702 struct mmc_host *mmc = data; 703 704 dev_dbg(mmc_dev(mmc), "%s\n", __func__); 705 706 mmc_detect_change(mmc, msecs_to_jiffies(250)); 707 return IRQ_HANDLED; 708} 709 710static int mxcmci_get_ro(struct mmc_host *mmc) 711{ 712 struct mxcmci_host *host = mmc_priv(mmc); 713 714 if (host->pdata && host->pdata->get_ro) 715 return !!host->pdata->get_ro(mmc_dev(mmc)); 716 /* 717 * Board doesn't support read only detection; let the mmc core 718 * decide what to do. 719 */ 720 return -ENOSYS; 721} 722 723static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 724{ 725 struct mxcmci_host *host = mmc_priv(mmc); 726 unsigned long flags; 727 u32 int_cntr; 728 729 spin_lock_irqsave(&host->lock, flags); 730 host->use_sdio = enable; 731 int_cntr = readl(host->base + MMC_REG_INT_CNTR); 732 733 if (enable) 734 int_cntr |= INT_SDIO_IRQ_EN; 735 else 736 int_cntr &= ~INT_SDIO_IRQ_EN; 737 738 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 739 spin_unlock_irqrestore(&host->lock, flags); 740} 741 742static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 743{ 744 /* 745 * MX3 SoCs have a silicon bug which corrupts CRC calculation of 746 * multi-block transfers when connected SDIO peripheral doesn't 747 * drive the BUSY line as required by the specs. 748 * One way to prevent this is to only allow 1-bit transfers. 749 */ 750 751 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO) 752 host->caps &= ~MMC_CAP_4_BIT_DATA; 753 else 754 host->caps |= MMC_CAP_4_BIT_DATA; 755} 756 757static const struct mmc_host_ops mxcmci_ops = { 758 .request = mxcmci_request, 759 .set_ios = mxcmci_set_ios, 760 .get_ro = mxcmci_get_ro, 761 .enable_sdio_irq = mxcmci_enable_sdio_irq, 762 .init_card = mxcmci_init_card, 763}; 764 765static int mxcmci_probe(struct platform_device *pdev) 766{ 767 struct mmc_host *mmc; 768 struct mxcmci_host *host = NULL; 769 struct resource *iores, *r; 770 int ret = 0, irq; 771 772 printk(KERN_INFO "i.MX SDHC driver\n"); 773 774 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 775 irq = platform_get_irq(pdev, 0); 776 if (!iores || irq < 0) 777 return -EINVAL; 778 779 r = request_mem_region(iores->start, resource_size(iores), pdev->name); 780 if (!r) 781 return -EBUSY; 782 783 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev); 784 if (!mmc) { 785 ret = -ENOMEM; 786 goto out_release_mem; 787 } 788 789 mmc->ops = &mxcmci_ops; 790 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 791 792 /* MMC core transfer sizes tunable parameters */ 793 mmc->max_hw_segs = 64; 794 mmc->max_phys_segs = 64; 795 mmc->max_blk_size = 2048; 796 mmc->max_blk_count = 65535; 797 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 798 mmc->max_seg_size = mmc->max_req_size; 799 800 host = mmc_priv(mmc); 801 host->base = ioremap(r->start, resource_size(r)); 802 if (!host->base) { 803 ret = -ENOMEM; 804 goto out_free; 805 } 806 807 host->mmc = mmc; 808 host->pdata = pdev->dev.platform_data; 809 spin_lock_init(&host->lock); 810 811 if (host->pdata && host->pdata->ocr_avail) 812 mmc->ocr_avail = host->pdata->ocr_avail; 813 else 814 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 815 816 if (host->pdata && host->pdata->dat3_card_detect) 817 host->default_irq_mask = 818 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; 819 else 820 host->default_irq_mask = 0; 821 822 host->res = r; 823 host->irq = irq; 824 825 host->clk = clk_get(&pdev->dev, NULL); 826 if (IS_ERR(host->clk)) { 827 ret = PTR_ERR(host->clk); 828 goto out_iounmap; 829 } 830 clk_enable(host->clk); 831 832 mxcmci_softreset(host); 833 834 host->rev_no = readw(host->base + MMC_REG_REV_NO); 835 if (host->rev_no != 0x400) { 836 ret = -ENODEV; 837 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 838 host->rev_no); 839 goto out_clk_put; 840 } 841 842 mmc->f_min = clk_get_rate(host->clk) >> 16; 843 mmc->f_max = clk_get_rate(host->clk) >> 1; 844 845 /* recommended in data sheet */ 846 writew(0x2db4, host->base + MMC_REG_READ_TO); 847 848 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR); 849 850#ifdef HAS_DMA 851 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); 852 if (host->dma < 0) { 853 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n"); 854 ret = -EBUSY; 855 goto out_clk_put; 856 } 857 858 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 859 if (!r) { 860 ret = -EINVAL; 861 goto out_free_dma; 862 } 863 864 ret = imx_dma_config_channel(host->dma, 865 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO, 866 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 867 r->start, 0); 868 if (ret) { 869 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n"); 870 goto out_free_dma; 871 } 872#endif 873 INIT_WORK(&host->datawork, mxcmci_datawork); 874 875 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host); 876 if (ret) 877 goto out_free_dma; 878 879 platform_set_drvdata(pdev, mmc); 880 881 if (host->pdata && host->pdata->init) { 882 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, 883 host->mmc); 884 if (ret) 885 goto out_free_irq; 886 } 887 888 mmc_add_host(mmc); 889 890 return 0; 891 892out_free_irq: 893 free_irq(host->irq, host); 894out_free_dma: 895#ifdef HAS_DMA 896 imx_dma_free(host->dma); 897#endif 898out_clk_put: 899 clk_disable(host->clk); 900 clk_put(host->clk); 901out_iounmap: 902 iounmap(host->base); 903out_free: 904 mmc_free_host(mmc); 905out_release_mem: 906 release_mem_region(iores->start, resource_size(iores)); 907 return ret; 908} 909 910static int mxcmci_remove(struct platform_device *pdev) 911{ 912 struct mmc_host *mmc = platform_get_drvdata(pdev); 913 struct mxcmci_host *host = mmc_priv(mmc); 914 915 platform_set_drvdata(pdev, NULL); 916 917 mmc_remove_host(mmc); 918 919 if (host->pdata && host->pdata->exit) 920 host->pdata->exit(&pdev->dev, mmc); 921 922 free_irq(host->irq, host); 923 iounmap(host->base); 924#ifdef HAS_DMA 925 imx_dma_free(host->dma); 926#endif 927 clk_disable(host->clk); 928 clk_put(host->clk); 929 930 release_mem_region(host->res->start, resource_size(host->res)); 931 release_resource(host->res); 932 933 mmc_free_host(mmc); 934 935 return 0; 936} 937 938#ifdef CONFIG_PM 939static int mxcmci_suspend(struct device *dev) 940{ 941 struct mmc_host *mmc = dev_get_drvdata(dev); 942 struct mxcmci_host *host = mmc_priv(mmc); 943 int ret = 0; 944 945 if (mmc) 946 ret = mmc_suspend_host(mmc); 947 clk_disable(host->clk); 948 949 return ret; 950} 951 952static int mxcmci_resume(struct device *dev) 953{ 954 struct mmc_host *mmc = dev_get_drvdata(dev); 955 struct mxcmci_host *host = mmc_priv(mmc); 956 int ret = 0; 957 958 clk_enable(host->clk); 959 if (mmc) 960 ret = mmc_resume_host(mmc); 961 962 return ret; 963} 964 965static const struct dev_pm_ops mxcmci_pm_ops = { 966 .suspend = mxcmci_suspend, 967 .resume = mxcmci_resume, 968}; 969#endif 970 971static struct platform_driver mxcmci_driver = { 972 .probe = mxcmci_probe, 973 .remove = mxcmci_remove, 974 .driver = { 975 .name = DRIVER_NAME, 976 .owner = THIS_MODULE, 977#ifdef CONFIG_PM 978 .pm = &mxcmci_pm_ops, 979#endif 980 } 981}; 982 983static int __init mxcmci_init(void) 984{ 985 return platform_driver_register(&mxcmci_driver); 986} 987 988static void __exit mxcmci_exit(void) 989{ 990 platform_driver_unregister(&mxcmci_driver); 991} 992 993module_init(mxcmci_init); 994module_exit(mxcmci_exit); 995 996MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 997MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 998MODULE_LICENSE("GPL"); 999MODULE_ALIAS("platform:imx-mmc"); 1000