1/* 2 * linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver 3 * 4 * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de> 5 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 6 * 7 * derived from pxamci.c by Russell King 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 */ 14 15#include <linux/module.h> 16#include <linux/init.h> 17#include <linux/ioport.h> 18#include <linux/platform_device.h> 19#include <linux/interrupt.h> 20#include <linux/blkdev.h> 21#include <linux/dma-mapping.h> 22#include <linux/mmc/host.h> 23#include <linux/mmc/card.h> 24#include <linux/delay.h> 25#include <linux/clk.h> 26#include <linux/io.h> 27 28#include <asm/dma.h> 29#include <asm/irq.h> 30#include <asm/sizes.h> 31#include <mach/mmc.h> 32#include <mach/imx-dma.h> 33 34#include "imxmmc.h" 35 36#define DRIVER_NAME "imx-mmc" 37 38#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \ 39 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ 40 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) 41 42struct imxmci_host { 43 struct mmc_host *mmc; 44 spinlock_t lock; 45 struct resource *res; 46 void __iomem *base; 47 int irq; 48 imx_dmach_t dma; 49 volatile unsigned int imask; 50 unsigned int power_mode; 51 unsigned int present; 52 struct imxmmc_platform_data *pdata; 53 54 struct mmc_request *req; 55 struct mmc_command *cmd; 56 struct mmc_data *data; 57 58 struct timer_list timer; 59 struct tasklet_struct tasklet; 60 unsigned int status_reg; 61 unsigned long pending_events; 62 /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */ 63 u16 *data_ptr; 64 unsigned int data_cnt; 65 atomic_t stuck_timeout; 66 67 unsigned int dma_nents; 68 unsigned int dma_size; 69 unsigned int dma_dir; 70 int dma_allocated; 71 72 unsigned char actual_bus_width; 73 74 int prev_cmd_code; 75 76 struct clk *clk; 77}; 78 79#define IMXMCI_PEND_IRQ_b 0 80#define IMXMCI_PEND_DMA_END_b 1 81#define IMXMCI_PEND_DMA_ERR_b 2 82#define IMXMCI_PEND_WAIT_RESP_b 3 83#define IMXMCI_PEND_DMA_DATA_b 4 84#define IMXMCI_PEND_CPU_DATA_b 5 85#define IMXMCI_PEND_CARD_XCHG_b 6 86#define IMXMCI_PEND_SET_INIT_b 7 87#define IMXMCI_PEND_STARTED_b 8 88 89#define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b) 90#define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b) 91#define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b) 92#define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b) 93#define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b) 94#define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b) 95#define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b) 96#define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b) 97#define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b) 98 99static void imxmci_stop_clock(struct imxmci_host *host) 100{ 101 int i = 0; 102 u16 reg; 103 104 reg = readw(host->base + MMC_REG_STR_STP_CLK); 105 writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 106 while (i < 0x1000) { 107 if (!(i & 0x7f)) { 108 reg = readw(host->base + MMC_REG_STR_STP_CLK); 109 writew(reg | STR_STP_CLK_STOP_CLK, 110 host->base + MMC_REG_STR_STP_CLK); 111 } 112 113 reg = readw(host->base + MMC_REG_STATUS); 114 if (!(reg & STATUS_CARD_BUS_CLK_RUN)) { 115 /* Check twice before cut */ 116 reg = readw(host->base + MMC_REG_STATUS); 117 if (!(reg & STATUS_CARD_BUS_CLK_RUN)) 118 return; 119 } 120 121 i++; 122 } 123 dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n"); 124} 125 126static int imxmci_start_clock(struct imxmci_host *host) 127{ 128 unsigned int trials = 0; 129 unsigned int delay_limit = 128; 130 unsigned long flags; 131 u16 reg; 132 133 reg = readw(host->base + MMC_REG_STR_STP_CLK); 134 writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); 135 136 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); 137 138 /* 139 * Command start of the clock, this usually succeeds in less 140 * then 6 delay loops, but during card detection (low clockrate) 141 * it takes up to 5000 delay loops and sometimes fails for the first time 142 */ 143 reg = readw(host->base + MMC_REG_STR_STP_CLK); 144 writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 145 146 do { 147 unsigned int delay = delay_limit; 148 149 while (delay--) { 150 reg = readw(host->base + MMC_REG_STATUS); 151 if (reg & STATUS_CARD_BUS_CLK_RUN) { 152 /* Check twice before cut */ 153 reg = readw(host->base + MMC_REG_STATUS); 154 if (reg & STATUS_CARD_BUS_CLK_RUN) 155 return 0; 156 } 157 158 if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) 159 return 0; 160 } 161 162 local_irq_save(flags); 163 /* 164 * Ensure, that request is not doubled under all possible circumstances. 165 * It is possible, that cock running state is missed, because some other 166 * IRQ or schedule delays this function execution and the clocks has 167 * been already stopped by other means (response processing, SDHC HW) 168 */ 169 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) { 170 reg = readw(host->base + MMC_REG_STR_STP_CLK); 171 writew(reg | STR_STP_CLK_START_CLK, 172 host->base + MMC_REG_STR_STP_CLK); 173 } 174 local_irq_restore(flags); 175 176 } while (++trials < 256); 177 178 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n"); 179 180 return -1; 181} 182 183static void imxmci_softreset(struct imxmci_host *host) 184{ 185 int i; 186 187 /* reset sequence */ 188 writew(0x08, host->base + MMC_REG_STR_STP_CLK); 189 writew(0x0D, host->base + MMC_REG_STR_STP_CLK); 190 191 for (i = 0; i < 8; i++) 192 writew(0x05, host->base + MMC_REG_STR_STP_CLK); 193 194 writew(0xff, host->base + MMC_REG_RES_TO); 195 writew(512, host->base + MMC_REG_BLK_LEN); 196 writew(1, host->base + MMC_REG_NOB); 197} 198 199static int imxmci_busy_wait_for_status(struct imxmci_host *host, 200 unsigned int *pstat, unsigned int stat_mask, 201 int timeout, const char *where) 202{ 203 int loops = 0; 204 205 while (!(*pstat & stat_mask)) { 206 loops += 2; 207 if (loops >= timeout) { 208 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n", 209 where, *pstat, stat_mask); 210 return -1; 211 } 212 udelay(2); 213 *pstat |= readw(host->base + MMC_REG_STATUS); 214 } 215 if (!loops) 216 return 0; 217 218 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */ 219 if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000)) 220 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n", 221 loops, where, *pstat, stat_mask); 222 return loops; 223} 224 225static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) 226{ 227 unsigned int nob = data->blocks; 228 unsigned int blksz = data->blksz; 229 unsigned int datasz = nob * blksz; 230 int i; 231 232 if (data->flags & MMC_DATA_STREAM) 233 nob = 0xffff; 234 235 host->data = data; 236 data->bytes_xfered = 0; 237 238 writew(nob, host->base + MMC_REG_NOB); 239 writew(blksz, host->base + MMC_REG_BLK_LEN); 240 241 /* 242 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise. 243 * We are in big troubles for non-512 byte transfers according to note in the paragraph 244 * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least. 245 * The situation is even more complex in reality. The SDHC in not able to handle wll 246 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple. 247 * This is required for SCR read at least. 248 */ 249 if (datasz < 512) { 250 host->dma_size = datasz; 251 if (data->flags & MMC_DATA_READ) { 252 host->dma_dir = DMA_FROM_DEVICE; 253 254 /* Hack to enable read SCR */ 255 writew(1, host->base + MMC_REG_NOB); 256 writew(512, host->base + MMC_REG_BLK_LEN); 257 } else { 258 host->dma_dir = DMA_TO_DEVICE; 259 } 260 261 /* Convert back to virtual address */ 262 host->data_ptr = (u16 *)sg_virt(data->sg); 263 host->data_cnt = 0; 264 265 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); 266 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); 267 268 return; 269 } 270 271 if (data->flags & MMC_DATA_READ) { 272 host->dma_dir = DMA_FROM_DEVICE; 273 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 274 data->sg_len, host->dma_dir); 275 276 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, 277 host->res->start + MMC_REG_BUFFER_ACCESS, 278 DMA_MODE_READ); 279 280 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/ 281 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN; 282 } else { 283 host->dma_dir = DMA_TO_DEVICE; 284 285 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 286 data->sg_len, host->dma_dir); 287 288 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, 289 host->res->start + MMC_REG_BUFFER_ACCESS, 290 DMA_MODE_WRITE); 291 292 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/ 293 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN; 294 } 295 296 host->dma_size = 0; 297 for (i = 0; i < host->dma_nents; i++) 298 host->dma_size += data->sg[i].length; 299 300 if (datasz > host->dma_size) { 301 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n", 302 datasz, host->dma_size); 303 } 304 305 host->dma_size = datasz; 306 307 wmb(); 308 309 set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); 310 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); 311 312 /* start DMA engine for read, write is delayed after initial response */ 313 if (host->dma_dir == DMA_FROM_DEVICE) 314 imx_dma_enable(host->dma); 315} 316 317static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat) 318{ 319 unsigned long flags; 320 u32 imask; 321 322 WARN_ON(host->cmd != NULL); 323 host->cmd = cmd; 324 325 /* Ensure, that clock are stopped else command programming and start fails */ 326 imxmci_stop_clock(host); 327 328 if (cmd->flags & MMC_RSP_BUSY) 329 cmdat |= CMD_DAT_CONT_BUSY; 330 331 switch (mmc_resp_type(cmd)) { 332 case MMC_RSP_R1: /* short CRC, OPCODE */ 333 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 334 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1; 335 break; 336 case MMC_RSP_R2: /* long 136 bit + CRC */ 337 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2; 338 break; 339 case MMC_RSP_R3: /* short */ 340 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3; 341 break; 342 default: 343 break; 344 } 345 346 if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events)) 347 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ 348 349 if (host->actual_bus_width == MMC_BUS_WIDTH_4) 350 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 351 352 writew(cmd->opcode, host->base + MMC_REG_CMD); 353 writew(cmd->arg >> 16, host->base + MMC_REG_ARGH); 354 writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL); 355 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); 356 357 atomic_set(&host->stuck_timeout, 0); 358 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events); 359 360 361 imask = IMXMCI_INT_MASK_DEFAULT; 362 imask &= ~INT_MASK_END_CMD_RES; 363 if (cmdat & CMD_DAT_CONT_DATA_ENABLE) { 364 /* imask &= ~INT_MASK_BUF_READY; */ 365 imask &= ~INT_MASK_DATA_TRAN; 366 if (cmdat & CMD_DAT_CONT_WRITE) 367 imask &= ~INT_MASK_WRITE_OP_DONE; 368 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) 369 imask &= ~INT_MASK_BUF_READY; 370 } 371 372 spin_lock_irqsave(&host->lock, flags); 373 host->imask = imask; 374 writew(host->imask, host->base + MMC_REG_INT_MASK); 375 spin_unlock_irqrestore(&host->lock, flags); 376 377 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n", 378 cmd->opcode, cmd->opcode, imask); 379 380 imxmci_start_clock(host); 381} 382 383static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req) 384{ 385 unsigned long flags; 386 387 spin_lock_irqsave(&host->lock, flags); 388 389 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m | 390 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); 391 392 host->imask = IMXMCI_INT_MASK_DEFAULT; 393 writew(host->imask, host->base + MMC_REG_INT_MASK); 394 395 spin_unlock_irqrestore(&host->lock, flags); 396 397 if (req && req->cmd) 398 host->prev_cmd_code = req->cmd->opcode; 399 400 host->req = NULL; 401 host->cmd = NULL; 402 host->data = NULL; 403 mmc_request_done(host->mmc, req); 404} 405 406static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat) 407{ 408 struct mmc_data *data = host->data; 409 int data_error; 410 411 if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { 412 imx_dma_disable(host->dma); 413 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, 414 host->dma_dir); 415 } 416 417 if (stat & STATUS_ERR_MASK) { 418 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat); 419 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) 420 data->error = -EILSEQ; 421 else if (stat & STATUS_TIME_OUT_READ) 422 data->error = -ETIMEDOUT; 423 else 424 data->error = -EIO; 425 } else { 426 data->bytes_xfered = host->dma_size; 427 } 428 429 data_error = data->error; 430 431 host->data = NULL; 432 433 return data_error; 434} 435 436static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) 437{ 438 struct mmc_command *cmd = host->cmd; 439 int i; 440 u32 a, b, c; 441 struct mmc_data *data = host->data; 442 443 if (!cmd) 444 return 0; 445 446 host->cmd = NULL; 447 448 if (stat & STATUS_TIME_OUT_RESP) { 449 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 450 cmd->error = -ETIMEDOUT; 451 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 452 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 453 cmd->error = -EILSEQ; 454 } 455 456 if (cmd->flags & MMC_RSP_PRESENT) { 457 if (cmd->flags & MMC_RSP_136) { 458 for (i = 0; i < 4; i++) { 459 a = readw(host->base + MMC_REG_RES_FIFO); 460 b = readw(host->base + MMC_REG_RES_FIFO); 461 cmd->resp[i] = a << 16 | b; 462 } 463 } else { 464 a = readw(host->base + MMC_REG_RES_FIFO); 465 b = readw(host->base + MMC_REG_RES_FIFO); 466 c = readw(host->base + MMC_REG_RES_FIFO); 467 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 468 } 469 } 470 471 dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n", 472 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error); 473 474 if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) { 475 if (host->req->data->flags & MMC_DATA_WRITE) { 476 477 /* Wait for FIFO to be empty before starting DMA write */ 478 479 stat = readw(host->base + MMC_REG_STATUS); 480 if (imxmci_busy_wait_for_status(host, &stat, 481 STATUS_APPL_BUFF_FE, 482 40, "imxmci_cmd_done DMA WR") < 0) { 483 cmd->error = -EIO; 484 imxmci_finish_data(host, stat); 485 if (host->req) 486 imxmci_finish_request(host, host->req); 487 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n", 488 stat); 489 return 0; 490 } 491 492 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) 493 imx_dma_enable(host->dma); 494 } 495 } else { 496 struct mmc_request *req; 497 imxmci_stop_clock(host); 498 req = host->req; 499 500 if (data) 501 imxmci_finish_data(host, stat); 502 503 if (req) 504 imxmci_finish_request(host, req); 505 else 506 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n"); 507 } 508 509 return 1; 510} 511 512static int imxmci_data_done(struct imxmci_host *host, unsigned int stat) 513{ 514 struct mmc_data *data = host->data; 515 int data_error; 516 517 if (!data) 518 return 0; 519 520 data_error = imxmci_finish_data(host, stat); 521 522 if (host->req->stop) { 523 imxmci_stop_clock(host); 524 imxmci_start_cmd(host, host->req->stop, 0); 525 } else { 526 struct mmc_request *req; 527 req = host->req; 528 if (req) 529 imxmci_finish_request(host, req); 530 else 531 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n"); 532 } 533 534 return 1; 535} 536 537static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) 538{ 539 int i; 540 int burst_len; 541 int trans_done = 0; 542 unsigned int stat = *pstat; 543 544 if (host->actual_bus_width != MMC_BUS_WIDTH_4) 545 burst_len = 16; 546 else 547 burst_len = 64; 548 549 /* This is unfortunately required */ 550 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n", 551 stat); 552 553 udelay(20); /* required for clocks < 8MHz*/ 554 555 if (host->dma_dir == DMA_FROM_DEVICE) { 556 imxmci_busy_wait_for_status(host, &stat, 557 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE | 558 STATUS_TIME_OUT_READ, 559 50, "imxmci_cpu_driven_data read"); 560 561 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && 562 !(stat & STATUS_TIME_OUT_READ) && 563 (host->data_cnt < 512)) { 564 565 udelay(20); /* required for clocks < 8MHz*/ 566 567 for (i = burst_len; i >= 2 ; i -= 2) { 568 u16 data; 569 data = readw(host->base + MMC_REG_BUFFER_ACCESS); 570 udelay(10); /* required for clocks < 8MHz*/ 571 if (host->data_cnt+2 <= host->dma_size) { 572 *(host->data_ptr++) = data; 573 } else { 574 if (host->data_cnt < host->dma_size) 575 *(u8 *)(host->data_ptr) = data; 576 } 577 host->data_cnt += 2; 578 } 579 580 stat = readw(host->base + MMC_REG_STATUS); 581 582 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n", 583 host->data_cnt, burst_len, stat); 584 } 585 586 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) 587 trans_done = 1; 588 589 if (host->dma_size & 0x1ff) 590 stat &= ~STATUS_CRC_READ_ERR; 591 592 if (stat & STATUS_TIME_OUT_READ) { 593 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n", 594 stat); 595 trans_done = -1; 596 } 597 598 } else { 599 imxmci_busy_wait_for_status(host, &stat, 600 STATUS_APPL_BUFF_FE, 601 20, "imxmci_cpu_driven_data write"); 602 603 while ((stat & STATUS_APPL_BUFF_FE) && 604 (host->data_cnt < host->dma_size)) { 605 if (burst_len >= host->dma_size - host->data_cnt) { 606 burst_len = host->dma_size - host->data_cnt; 607 host->data_cnt = host->dma_size; 608 trans_done = 1; 609 } else { 610 host->data_cnt += burst_len; 611 } 612 613 for (i = burst_len; i > 0 ; i -= 2) 614 writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS); 615 616 stat = readw(host->base + MMC_REG_STATUS); 617 618 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n", 619 burst_len, stat); 620 } 621 } 622 623 *pstat = stat; 624 625 return trans_done; 626} 627 628static void imxmci_dma_irq(int dma, void *devid) 629{ 630 struct imxmci_host *host = devid; 631 u32 stat = readw(host->base + MMC_REG_STATUS); 632 633 atomic_set(&host->stuck_timeout, 0); 634 host->status_reg = stat; 635 set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); 636 tasklet_schedule(&host->tasklet); 637} 638 639static irqreturn_t imxmci_irq(int irq, void *devid) 640{ 641 struct imxmci_host *host = devid; 642 u32 stat = readw(host->base + MMC_REG_STATUS); 643 int handled = 1; 644 645 writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT, 646 host->base + MMC_REG_INT_MASK); 647 648 atomic_set(&host->stuck_timeout, 0); 649 host->status_reg = stat; 650 set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); 651 set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); 652 tasklet_schedule(&host->tasklet); 653 654 return IRQ_RETVAL(handled); 655} 656 657static void imxmci_tasklet_fnc(unsigned long data) 658{ 659 struct imxmci_host *host = (struct imxmci_host *)data; 660 u32 stat; 661 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */ 662 int timeout = 0; 663 664 if (atomic_read(&host->stuck_timeout) > 4) { 665 char *what; 666 timeout = 1; 667 stat = readw(host->base + MMC_REG_STATUS); 668 host->status_reg = stat; 669 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 670 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) 671 what = "RESP+DMA"; 672 else 673 what = "RESP"; 674 else 675 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) 676 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) 677 what = "DATA"; 678 else 679 what = "DMA"; 680 else 681 what = "???"; 682 683 dev_err(mmc_dev(host->mmc), 684 "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", 685 what, stat, 686 readw(host->base + MMC_REG_INT_MASK)); 687 dev_err(mmc_dev(host->mmc), 688 "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", 689 readw(host->base + MMC_REG_CMD_DAT_CONT), 690 readw(host->base + MMC_REG_BLK_LEN), 691 readw(host->base + MMC_REG_NOB), 692 CCR(host->dma)); 693 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n", 694 host->cmd ? host->cmd->opcode : 0, 695 host->prev_cmd_code, 696 1 << host->actual_bus_width, host->dma_size); 697 } 698 699 if (!host->present || timeout) 700 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ | 701 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; 702 703 if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { 704 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); 705 706 stat = readw(host->base + MMC_REG_STATUS); 707 /* 708 * This is not required in theory, but there is chance to miss some flag 709 * which clears automatically by mask write, FreeScale original code keeps 710 * stat from IRQ time so do I 711 */ 712 stat |= host->status_reg; 713 714 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) 715 stat &= ~STATUS_CRC_READ_ERR; 716 717 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { 718 imxmci_busy_wait_for_status(host, &stat, 719 STATUS_END_CMD_RESP | STATUS_ERR_MASK, 720 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); 721 } 722 723 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { 724 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 725 imxmci_cmd_done(host, stat); 726 if (host->data && (stat & STATUS_ERR_MASK)) 727 imxmci_data_done(host, stat); 728 } 729 730 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { 731 stat |= readw(host->base + MMC_REG_STATUS); 732 if (imxmci_cpu_driven_data(host, &stat)) { 733 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 734 imxmci_cmd_done(host, stat); 735 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m, 736 &host->pending_events); 737 imxmci_data_done(host, stat); 738 } 739 } 740 } 741 742 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && 743 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { 744 745 stat = readw(host->base + MMC_REG_STATUS); 746 /* Same as above */ 747 stat |= host->status_reg; 748 749 if (host->dma_dir == DMA_TO_DEVICE) 750 data_dir_mask = STATUS_WRITE_OP_DONE; 751 else 752 data_dir_mask = STATUS_DATA_TRANS_DONE; 753 754 if (stat & data_dir_mask) { 755 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); 756 imxmci_data_done(host, stat); 757 } 758 } 759 760 if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { 761 762 if (host->cmd) 763 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP); 764 765 if (host->data) 766 imxmci_data_done(host, STATUS_TIME_OUT_READ | 767 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR); 768 769 if (host->req) 770 imxmci_finish_request(host, host->req); 771 772 mmc_detect_change(host->mmc, msecs_to_jiffies(100)); 773 774 } 775} 776 777static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req) 778{ 779 struct imxmci_host *host = mmc_priv(mmc); 780 unsigned int cmdat; 781 782 WARN_ON(host->req != NULL); 783 784 host->req = req; 785 786 cmdat = 0; 787 788 if (req->data) { 789 imxmci_setup_data(host, req->data); 790 791 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 792 793 if (req->data->flags & MMC_DATA_WRITE) 794 cmdat |= CMD_DAT_CONT_WRITE; 795 796 if (req->data->flags & MMC_DATA_STREAM) 797 cmdat |= CMD_DAT_CONT_STREAM_BLOCK; 798 } 799 800 imxmci_start_cmd(host, req->cmd, cmdat); 801} 802 803#define CLK_RATE 19200000 804 805static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 806{ 807 struct imxmci_host *host = mmc_priv(mmc); 808 int prescaler; 809 810 if (ios->bus_width == MMC_BUS_WIDTH_4) { 811 host->actual_bus_width = MMC_BUS_WIDTH_4; 812 imx_gpio_mode(PB11_PF_SD_DAT3); 813 BLR(host->dma) = 0; /* burst 64 byte read/write */ 814 } else { 815 host->actual_bus_width = MMC_BUS_WIDTH_1; 816 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); 817 BLR(host->dma) = 16; /* burst 16 byte read/write */ 818 } 819 820 if (host->power_mode != ios->power_mode) { 821 switch (ios->power_mode) { 822 case MMC_POWER_OFF: 823 break; 824 case MMC_POWER_UP: 825 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); 826 break; 827 case MMC_POWER_ON: 828 break; 829 } 830 host->power_mode = ios->power_mode; 831 } 832 833 if (ios->clock) { 834 unsigned int clk; 835 u16 reg; 836 837 /* The prescaler is 5 for PERCLK2 equal to 96MHz 838 * then 96MHz / 5 = 19.2 MHz 839 */ 840 clk = clk_get_rate(host->clk); 841 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE; 842 switch (prescaler) { 843 case 0: 844 case 1: prescaler = 0; 845 break; 846 case 2: prescaler = 1; 847 break; 848 case 3: prescaler = 2; 849 break; 850 case 4: prescaler = 4; 851 break; 852 default: 853 case 5: prescaler = 5; 854 break; 855 } 856 857 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n", 858 clk, prescaler); 859 860 for (clk = 0; clk < 8; clk++) { 861 int x; 862 x = CLK_RATE / (1 << clk); 863 if (x <= ios->clock) 864 break; 865 } 866 867 /* enable controller */ 868 reg = readw(host->base + MMC_REG_STR_STP_CLK); 869 writew(reg | STR_STP_CLK_ENABLE, 870 host->base + MMC_REG_STR_STP_CLK); 871 872 imxmci_stop_clock(host); 873 writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE); 874 /* 875 * Under my understanding, clock should not be started there, because it would 876 * initiate SDHC sequencer and send last or random command into card 877 */ 878 /* imxmci_start_clock(host); */ 879 880 dev_dbg(mmc_dev(host->mmc), 881 "MMC_CLK_RATE: 0x%08x\n", 882 readw(host->base + MMC_REG_CLK_RATE)); 883 } else { 884 imxmci_stop_clock(host); 885 } 886} 887 888static int imxmci_get_ro(struct mmc_host *mmc) 889{ 890 struct imxmci_host *host = mmc_priv(mmc); 891 892 if (host->pdata && host->pdata->get_ro) 893 return !!host->pdata->get_ro(mmc_dev(mmc)); 894 /* 895 * Board doesn't support read only detection; let the mmc core 896 * decide what to do. 897 */ 898 return -ENOSYS; 899} 900 901 902static const struct mmc_host_ops imxmci_ops = { 903 .request = imxmci_request, 904 .set_ios = imxmci_set_ios, 905 .get_ro = imxmci_get_ro, 906}; 907 908static void imxmci_check_status(unsigned long data) 909{ 910 struct imxmci_host *host = (struct imxmci_host *)data; 911 912 if (host->pdata && host->pdata->card_present && 913 host->pdata->card_present(mmc_dev(host->mmc)) != host->present) { 914 host->present ^= 1; 915 dev_info(mmc_dev(host->mmc), "card %s\n", 916 host->present ? "inserted" : "removed"); 917 918 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events); 919 tasklet_schedule(&host->tasklet); 920 } 921 922 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || 923 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { 924 atomic_inc(&host->stuck_timeout); 925 if (atomic_read(&host->stuck_timeout) > 4) 926 tasklet_schedule(&host->tasklet); 927 } else { 928 atomic_set(&host->stuck_timeout, 0); 929 930 } 931 932 mod_timer(&host->timer, jiffies + (HZ>>1)); 933} 934 935static int __init imxmci_probe(struct platform_device *pdev) 936{ 937 struct mmc_host *mmc; 938 struct imxmci_host *host = NULL; 939 struct resource *r; 940 int ret = 0, irq; 941 u16 rev_no; 942 943 printk(KERN_INFO "i.MX mmc driver\n"); 944 945 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 946 irq = platform_get_irq(pdev, 0); 947 if (!r || irq < 0) 948 return -ENXIO; 949 950 r = request_mem_region(r->start, resource_size(r), pdev->name); 951 if (!r) 952 return -EBUSY; 953 954 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev); 955 if (!mmc) { 956 ret = -ENOMEM; 957 goto out; 958 } 959 960 mmc->ops = &imxmci_ops; 961 mmc->f_min = 150000; 962 mmc->f_max = CLK_RATE/2; 963 mmc->ocr_avail = MMC_VDD_32_33; 964 mmc->caps = MMC_CAP_4_BIT_DATA; 965 966 /* MMC core transfer sizes tunable parameters */ 967 mmc->max_hw_segs = 64; 968 mmc->max_phys_segs = 64; 969 mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */ 970 mmc->max_req_size = 64*512; /* default PAGE_CACHE_SIZE */ 971 mmc->max_blk_size = 2048; 972 mmc->max_blk_count = 65535; 973 974 host = mmc_priv(mmc); 975 host->base = ioremap(r->start, resource_size(r)); 976 if (!host->base) { 977 ret = -ENOMEM; 978 goto out; 979 } 980 981 host->mmc = mmc; 982 host->dma_allocated = 0; 983 host->pdata = pdev->dev.platform_data; 984 if (!host->pdata) 985 dev_warn(&pdev->dev, "No platform data provided!\n"); 986 987 spin_lock_init(&host->lock); 988 host->res = r; 989 host->irq = irq; 990 991 host->clk = clk_get(&pdev->dev, "perclk2"); 992 if (IS_ERR(host->clk)) { 993 ret = PTR_ERR(host->clk); 994 goto out; 995 } 996 clk_enable(host->clk); 997 998 imx_gpio_mode(PB8_PF_SD_DAT0); 999 imx_gpio_mode(PB9_PF_SD_DAT1); 1000 imx_gpio_mode(PB10_PF_SD_DAT2); 1001 /* Configured as GPIO with pull-up to ensure right MCC card mode */ 1002 /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */ 1003 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); 1004 /* imx_gpio_mode(PB11_PF_SD_DAT3); */ 1005 imx_gpio_mode(PB12_PF_SD_CLK); 1006 imx_gpio_mode(PB13_PF_SD_CMD); 1007 1008 imxmci_softreset(host); 1009 1010 rev_no = readw(host->base + MMC_REG_REV_NO); 1011 if (rev_no != 0x390) { 1012 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 1013 readw(host->base + MMC_REG_REV_NO)); 1014 goto out; 1015 } 1016 1017 /* recommended in data sheet */ 1018 writew(0x2db4, host->base + MMC_REG_READ_TO); 1019 1020 host->imask = IMXMCI_INT_MASK_DEFAULT; 1021 writew(host->imask, host->base + MMC_REG_INT_MASK); 1022 1023 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); 1024 if(host->dma < 0) { 1025 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n"); 1026 ret = -EBUSY; 1027 goto out; 1028 } 1029 host->dma_allocated = 1; 1030 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host); 1031 RSSR(host->dma) = DMA_REQ_SDHC; 1032 1033 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host); 1034 host->status_reg=0; 1035 host->pending_events=0; 1036 1037 ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host); 1038 if (ret) 1039 goto out; 1040 1041 if (host->pdata && host->pdata->card_present) 1042 host->present = host->pdata->card_present(mmc_dev(mmc)); 1043 else /* if there is no way to detect assume that card is present */ 1044 host->present = 1; 1045 1046 init_timer(&host->timer); 1047 host->timer.data = (unsigned long)host; 1048 host->timer.function = imxmci_check_status; 1049 add_timer(&host->timer); 1050 mod_timer(&host->timer, jiffies + (HZ >> 1)); 1051 1052 platform_set_drvdata(pdev, mmc); 1053 1054 mmc_add_host(mmc); 1055 1056 return 0; 1057 1058out: 1059 if (host) { 1060 if (host->dma_allocated) { 1061 imx_dma_free(host->dma); 1062 host->dma_allocated = 0; 1063 } 1064 if (host->clk) { 1065 clk_disable(host->clk); 1066 clk_put(host->clk); 1067 } 1068 if (host->base) 1069 iounmap(host->base); 1070 } 1071 if (mmc) 1072 mmc_free_host(mmc); 1073 release_mem_region(r->start, resource_size(r)); 1074 return ret; 1075} 1076 1077static int __exit imxmci_remove(struct platform_device *pdev) 1078{ 1079 struct mmc_host *mmc = platform_get_drvdata(pdev); 1080 1081 platform_set_drvdata(pdev, NULL); 1082 1083 if (mmc) { 1084 struct imxmci_host *host = mmc_priv(mmc); 1085 1086 tasklet_disable(&host->tasklet); 1087 1088 del_timer_sync(&host->timer); 1089 mmc_remove_host(mmc); 1090 1091 free_irq(host->irq, host); 1092 iounmap(host->base); 1093 if (host->dma_allocated) { 1094 imx_dma_free(host->dma); 1095 host->dma_allocated = 0; 1096 } 1097 1098 tasklet_kill(&host->tasklet); 1099 1100 clk_disable(host->clk); 1101 clk_put(host->clk); 1102 1103 release_mem_region(host->res->start, resource_size(host->res)); 1104 1105 mmc_free_host(mmc); 1106 } 1107 return 0; 1108} 1109 1110#ifdef CONFIG_PM 1111static int imxmci_suspend(struct platform_device *dev, pm_message_t state) 1112{ 1113 struct mmc_host *mmc = platform_get_drvdata(dev); 1114 int ret = 0; 1115 1116 if (mmc) 1117 ret = mmc_suspend_host(mmc); 1118 1119 return ret; 1120} 1121 1122static int imxmci_resume(struct platform_device *dev) 1123{ 1124 struct mmc_host *mmc = platform_get_drvdata(dev); 1125 struct imxmci_host *host; 1126 int ret = 0; 1127 1128 if (mmc) { 1129 host = mmc_priv(mmc); 1130 if (host) 1131 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); 1132 ret = mmc_resume_host(mmc); 1133 } 1134 1135 return ret; 1136} 1137#else 1138#define imxmci_suspend NULL 1139#define imxmci_resume NULL 1140#endif /* CONFIG_PM */ 1141 1142static struct platform_driver imxmci_driver = { 1143 .remove = __exit_p(imxmci_remove), 1144 .suspend = imxmci_suspend, 1145 .resume = imxmci_resume, 1146 .driver = { 1147 .name = DRIVER_NAME, 1148 .owner = THIS_MODULE, 1149 } 1150}; 1151 1152static int __init imxmci_init(void) 1153{ 1154 return platform_driver_probe(&imxmci_driver, imxmci_probe); 1155} 1156 1157static void __exit imxmci_exit(void) 1158{ 1159 platform_driver_unregister(&imxmci_driver); 1160} 1161 1162module_init(imxmci_init); 1163module_exit(imxmci_exit); 1164 1165MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 1166MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1167MODULE_LICENSE("GPL"); 1168MODULE_ALIAS("platform:imx-mmc"); 1169