1/* 2 * Atmel MultiMedia Card Interface driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11/* 12 * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors 13 * Registers and bitfields marked with [2] are only available in MCI2 14 */ 15 16#ifndef __DRIVERS_MMC_ATMEL_MCI_H__ 17#define __DRIVERS_MMC_ATMEL_MCI_H__ 18 19/* MCI Register Definitions */ 20#define MCI_CR 0x0000 /* Control */ 21# define MCI_CR_MCIEN ( 1 << 0) /* MCI Enable */ 22# define MCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */ 23# define MCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */ 24# define MCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */ 25# define MCI_CR_SWRST ( 1 << 7) /* Software Reset */ 26#define MCI_MR 0x0004 /* Mode */ 27# define MCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */ 28# define MCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */ 29# define MCI_MR_RDPROOF ( 1 << 11) /* Read Proof */ 30# define MCI_MR_WRPROOF ( 1 << 12) /* Write Proof */ 31# define MCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */ 32# define MCI_MR_PDCPADV ( 1 << 14) /* Padding Value */ 33# define MCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */ 34#define MCI_DTOR 0x0008 /* Data Timeout */ 35# define MCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */ 36# define MCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */ 37#define MCI_SDCR 0x000c /* SD Card / SDIO */ 38# define MCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */ 39# define MCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */ 40# define MCI_SDCSEL_MASK ( 3 << 0) 41# define MCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */ 42# define MCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */ 43# define MCI_SDCBUS_8BIT ( 3 << 6) /* 8-bit data bus[2] */ 44# define MCI_SDCBUS_MASK ( 3 << 6) 45#define MCI_ARGR 0x0010 /* Command Argument */ 46#define MCI_CMDR 0x0014 /* Command */ 47# define MCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */ 48# define MCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */ 49# define MCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */ 50# define MCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */ 51# define MCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */ 52# define MCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */ 53# define MCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */ 54# define MCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */ 55# define MCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */ 56# define MCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */ 57# define MCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */ 58# define MCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */ 59# define MCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */ 60# define MCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */ 61# define MCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */ 62# define MCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */ 63# define MCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */ 64# define MCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */ 65# define MCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */ 66# define MCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */ 67# define MCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */ 68# define MCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */ 69#define MCI_BLKR 0x0018 /* Block */ 70# define MCI_BCNT(x) ((x) << 0) /* Data Block Count */ 71# define MCI_BLKLEN(x) ((x) << 16) /* Data Block Length */ 72#define MCI_CSTOR 0x001c /* Completion Signal Timeout[2] */ 73# define MCI_CSTOCYC(x) ((x) << 0) /* CST cycles */ 74# define MCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */ 75#define MCI_RSPR 0x0020 /* Response 0 */ 76#define MCI_RSPR1 0x0024 /* Response 1 */ 77#define MCI_RSPR2 0x0028 /* Response 2 */ 78#define MCI_RSPR3 0x002c /* Response 3 */ 79#define MCI_RDR 0x0030 /* Receive Data */ 80#define MCI_TDR 0x0034 /* Transmit Data */ 81#define MCI_SR 0x0040 /* Status */ 82#define MCI_IER 0x0044 /* Interrupt Enable */ 83#define MCI_IDR 0x0048 /* Interrupt Disable */ 84#define MCI_IMR 0x004c /* Interrupt Mask */ 85# define MCI_CMDRDY ( 1 << 0) /* Command Ready */ 86# define MCI_RXRDY ( 1 << 1) /* Receiver Ready */ 87# define MCI_TXRDY ( 1 << 2) /* Transmitter Ready */ 88# define MCI_BLKE ( 1 << 3) /* Data Block Ended */ 89# define MCI_DTIP ( 1 << 4) /* Data Transfer In Progress */ 90# define MCI_NOTBUSY ( 1 << 5) /* Data Not Busy */ 91# define MCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */ 92# define MCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */ 93# define MCI_RINDE ( 1 << 16) /* Response Index Error */ 94# define MCI_RDIRE ( 1 << 17) /* Response Direction Error */ 95# define MCI_RCRCE ( 1 << 18) /* Response CRC Error */ 96# define MCI_RENDE ( 1 << 19) /* Response End Bit Error */ 97# define MCI_RTOE ( 1 << 20) /* Response Time-Out Error */ 98# define MCI_DCRCE ( 1 << 21) /* Data CRC Error */ 99# define MCI_DTOE ( 1 << 22) /* Data Time-Out Error */ 100# define MCI_OVRE ( 1 << 30) /* RX Overrun Error */ 101# define MCI_UNRE ( 1 << 31) /* TX Underrun Error */ 102#define MCI_DMA 0x0050 /* DMA Configuration[2] */ 103# define MCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */ 104# define MCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */ 105# define MCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */ 106#define MCI_CFG 0x0054 /* Configuration[2] */ 107# define MCI_CFG_FIFOMODE_1DATA ( 1 << 0) /* MCI Internal FIFO control mode */ 108# define MCI_CFG_FERRCTRL_COR ( 1 << 4) /* Flow Error flag reset control mode */ 109# define MCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */ 110# define MCI_CFG_LSYNC ( 1 << 12) /* Synchronize on the last block */ 111#define MCI_WPMR 0x00e4 /* Write Protection Mode[2] */ 112# define MCI_WP_EN ( 1 << 0) /* WP Enable */ 113# define MCI_WP_KEY (0x4d4349 << 8) /* WP Key */ 114#define MCI_WPSR 0x00e8 /* Write Protection Status[2] */ 115# define MCI_GET_WP_VS(x) ((x) & 0x0f) 116# define MCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff) 117#define MCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */ 118 119/* This is not including the FIFO Aperture on MCI2 */ 120#define MCI_REGS_SIZE 0x100 121 122/* Register access macros */ 123#define mci_readl(port,reg) \ 124 __raw_readl((port)->regs + MCI_##reg) 125#define mci_writel(port,reg,value) \ 126 __raw_writel((value), (port)->regs + MCI_##reg) 127 128#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */ 129