1/* 2 STB0899 Multistandard Frontend driver 3 Copyright (C) Manu Abraham (abraham.manu@gmail.com) 4 5 Copyright (C) ST Microelectronics 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20*/ 21 22#include "stb0899_drv.h" 23#include "stb0899_priv.h" 24#include "stb0899_reg.h" 25 26inline u32 stb0899_do_div(u64 n, u32 d) 27{ 28 /* wrap do_div() for ease of use */ 29 30 do_div(n, d); 31 return n; 32} 33 34 35/* 36 * stb0899_set_srate 37 * Set symbol frequency 38 * MasterClock: master clock frequency (hz) 39 * SymbolRate: symbol rate (bauds) 40 * return symbol frequency 41 */ 42static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate) 43{ 44 u32 tmp; 45 u8 sfr[3]; 46 47 dprintk(state->verbose, FE_DEBUG, 1, "-->"); 48 /* 49 * in order to have the maximum precision, the symbol rate entered into 50 * the chip is computed as the closest value of the "true value". 51 * In this purpose, the symbol rate value is rounded (1 is added on the bit 52 * below the LSB ) 53 * 54 * srate = (SFR * master_clk) >> 20 55 * <=> 56 * SFR = srate << 20 / master_clk 57 * 58 * rounded: 59 * SFR = (srate << 21 + master_clk) / (2 * master_clk) 60 * 61 * stored as 20 bit number with an offset of 4 bit: 62 * sfr = SFR << 4; 63 */ 64 65 tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk); 66 tmp <<= 4; 67 68 sfr[0] = tmp >> 16; 69 sfr[1] = tmp >> 8; 70 sfr[2] = tmp; 71 72 stb0899_write_regs(state, STB0899_SFRH, sfr, 3); 73 74 return srate; 75} 76 77/* 78 * stb0899_calc_derot_time 79 * Compute the amount of time needed by the derotator to lock 80 * SymbolRate: Symbol rate 81 * return: derotator time constant (ms) 82 */ 83static long stb0899_calc_derot_time(long srate) 84{ 85 if (srate > 0) 86 return (100000 / (srate / 1000)); 87 else 88 return 0; 89} 90 91/* 92 * stb0899_carr_width 93 * Compute the width of the carrier 94 * return: width of carrier (kHz or Mhz) 95 */ 96long stb0899_carr_width(struct stb0899_state *state) 97{ 98 struct stb0899_internal *internal = &state->internal; 99 100 return (internal->srate + (internal->srate * internal->rolloff) / 100); 101} 102 103/* 104 * stb0899_first_subrange 105 * Compute the first subrange of the search 106 */ 107static void stb0899_first_subrange(struct stb0899_state *state) 108{ 109 struct stb0899_internal *internal = &state->internal; 110 struct stb0899_params *params = &state->params; 111 struct stb0899_config *config = state->config; 112 113 int range = 0; 114 u32 bandwidth = 0; 115 116 if (config->tuner_get_bandwidth) { 117 stb0899_i2c_gate_ctrl(&state->frontend, 1); 118 config->tuner_get_bandwidth(&state->frontend, &bandwidth); 119 stb0899_i2c_gate_ctrl(&state->frontend, 0); 120 range = bandwidth - stb0899_carr_width(state) / 2; 121 } 122 123 if (range > 0) 124 internal->sub_range = min(internal->srch_range, range); 125 else 126 internal->sub_range = 0; 127 128 internal->freq = params->freq; 129 internal->tuner_offst = 0L; 130 internal->sub_dir = 1; 131} 132 133/* 134 * stb0899_check_tmg 135 * check for timing lock 136 * internal.Ttiming: time to wait for loop lock 137 */ 138static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state) 139{ 140 struct stb0899_internal *internal = &state->internal; 141 int lock; 142 u8 reg; 143 s8 timing; 144 145 msleep(internal->t_derot); 146 147 stb0899_write_reg(state, STB0899_RTF, 0xf2); 148 reg = stb0899_read_reg(state, STB0899_TLIR); 149 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg); 150 timing = stb0899_read_reg(state, STB0899_RTF); 151 152 if (lock >= 42) { 153 if ((lock > 48) && (abs(timing) >= 110)) { 154 internal->status = ANALOGCARRIER; 155 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !"); 156 } else { 157 internal->status = TIMINGOK; 158 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !"); 159 } 160 } else { 161 internal->status = NOTIMING; 162 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !"); 163 } 164 return internal->status; 165} 166 167/* 168 * stb0899_search_tmg 169 * perform a fs/2 zig-zag to find timing 170 */ 171static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state) 172{ 173 struct stb0899_internal *internal = &state->internal; 174 struct stb0899_params *params = &state->params; 175 176 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3; 177 int index = 0; 178 u8 cfr[2]; 179 180 internal->status = NOTIMING; 181 182 /* timing loop computation & symbol rate optimisation */ 183 derot_limit = (internal->sub_range / 2L) / internal->mclk; 184 derot_step = (params->srate / 2L) / internal->mclk; 185 186 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) { 187 index++; 188 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */ 189 190 if (abs(derot_freq) > derot_limit) 191 next_loop--; 192 193 if (next_loop) { 194 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq)); 195 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq)); 196 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ 197 } 198 internal->direction = -internal->direction; /* Change zigzag direction */ 199 } 200 201 if (internal->status == TIMINGOK) { 202 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ 203 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]); 204 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq); 205 } 206 207 return internal->status; 208} 209 210/* 211 * stb0899_check_carrier 212 * Check for carrier found 213 */ 214static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state) 215{ 216 struct stb0899_internal *internal = &state->internal; 217 u8 reg; 218 219 msleep(internal->t_derot); /* wait for derotator ok */ 220 221 reg = stb0899_read_reg(state, STB0899_CFD); 222 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); 223 stb0899_write_reg(state, STB0899_CFD, reg); 224 225 reg = stb0899_read_reg(state, STB0899_DSTATUS); 226 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg); 227 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) { 228 internal->status = CARRIEROK; 229 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !"); 230 } else { 231 internal->status = NOCARRIER; 232 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !"); 233 } 234 235 return internal->status; 236} 237 238/* 239 * stb0899_search_carrier 240 * Search for a QPSK carrier with the derotator 241 */ 242static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state) 243{ 244 struct stb0899_internal *internal = &state->internal; 245 246 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3; 247 int index = 0; 248 u8 cfr[2]; 249 u8 reg; 250 251 internal->status = NOCARRIER; 252 derot_limit = (internal->sub_range / 2L) / internal->mclk; 253 derot_freq = internal->derot_freq; 254 255 reg = stb0899_read_reg(state, STB0899_CFD); 256 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); 257 stb0899_write_reg(state, STB0899_CFD, reg); 258 259 do { 260 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk); 261 if (stb0899_check_carrier(state) == NOCARRIER) { 262 index++; 263 last_derot_freq = derot_freq; 264 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */ 265 266 if(abs(derot_freq) > derot_limit) 267 next_loop--; 268 269 if (next_loop) { 270 reg = stb0899_read_reg(state, STB0899_CFD); 271 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); 272 stb0899_write_reg(state, STB0899_CFD, reg); 273 274 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq)); 275 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq)); 276 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ 277 } 278 } 279 280 internal->direction = -internal->direction; /* Change zigzag direction */ 281 } while ((internal->status != CARRIEROK) && next_loop); 282 283 if (internal->status == CARRIEROK) { 284 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ 285 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]); 286 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq); 287 } else { 288 internal->derot_freq = last_derot_freq; 289 } 290 291 return internal->status; 292} 293 294/* 295 * stb0899_check_data 296 * Check for data found 297 */ 298static enum stb0899_status stb0899_check_data(struct stb0899_state *state) 299{ 300 struct stb0899_internal *internal = &state->internal; 301 struct stb0899_params *params = &state->params; 302 303 int lock = 0, index = 0, dataTime = 500, loop; 304 u8 reg; 305 306 internal->status = NODATA; 307 308 /* RESET FEC */ 309 reg = stb0899_read_reg(state, STB0899_TSTRES); 310 STB0899_SETFIELD_VAL(FRESACS, reg, 1); 311 stb0899_write_reg(state, STB0899_TSTRES, reg); 312 msleep(1); 313 reg = stb0899_read_reg(state, STB0899_TSTRES); 314 STB0899_SETFIELD_VAL(FRESACS, reg, 0); 315 stb0899_write_reg(state, STB0899_TSTRES, reg); 316 317 if (params->srate <= 2000000) 318 dataTime = 2000; 319 else if (params->srate <= 5000000) 320 dataTime = 1500; 321 else if (params->srate <= 15000000) 322 dataTime = 1000; 323 else 324 dataTime = 500; 325 326 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */ 327 while (1) { 328 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */ 329 reg = stb0899_read_reg(state, STB0899_VSTATUS); 330 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg); 331 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg); 332 333 if (lock || loop || (index > dataTime)) 334 break; 335 index++; 336 } 337 338 if (lock) { /* DATA LOCK indicator */ 339 internal->status = DATAOK; 340 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !"); 341 } 342 343 return internal->status; 344} 345 346/* 347 * stb0899_search_data 348 * Search for a QPSK carrier with the derotator 349 */ 350static enum stb0899_status stb0899_search_data(struct stb0899_state *state) 351{ 352 short int derot_freq, derot_step, derot_limit, next_loop = 3; 353 u8 cfr[2]; 354 u8 reg; 355 int index = 1; 356 357 struct stb0899_internal *internal = &state->internal; 358 struct stb0899_params *params = &state->params; 359 360 derot_step = (params->srate / 4L) / internal->mclk; 361 derot_limit = (internal->sub_range / 2L) / internal->mclk; 362 derot_freq = internal->derot_freq; 363 364 do { 365 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) { 366 367 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */ 368 if (abs(derot_freq) > derot_limit) 369 next_loop--; 370 371 if (next_loop) { 372 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk); 373 reg = stb0899_read_reg(state, STB0899_CFD); 374 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); 375 stb0899_write_reg(state, STB0899_CFD, reg); 376 377 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq)); 378 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq)); 379 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ 380 381 stb0899_check_carrier(state); 382 index++; 383 } 384 } 385 internal->direction = -internal->direction; /* change zig zag direction */ 386 } while ((internal->status != DATAOK) && next_loop); 387 388 if (internal->status == DATAOK) { 389 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ 390 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]); 391 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq); 392 } 393 394 return internal->status; 395} 396 397/* 398 * stb0899_check_range 399 * check if the found frequency is in the correct range 400 */ 401static enum stb0899_status stb0899_check_range(struct stb0899_state *state) 402{ 403 struct stb0899_internal *internal = &state->internal; 404 struct stb0899_params *params = &state->params; 405 406 int range_offst, tp_freq; 407 408 range_offst = internal->srch_range / 2000; 409 tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000; 410 411 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) { 412 internal->status = RANGEOK; 413 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !"); 414 } else { 415 internal->status = OUTOFRANGE; 416 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !"); 417 } 418 419 return internal->status; 420} 421 422/* 423 * NextSubRange 424 * Compute the next subrange of the search 425 */ 426static void next_sub_range(struct stb0899_state *state) 427{ 428 struct stb0899_internal *internal = &state->internal; 429 struct stb0899_params *params = &state->params; 430 431 long old_sub_range; 432 433 if (internal->sub_dir > 0) { 434 old_sub_range = internal->sub_range; 435 internal->sub_range = min((internal->srch_range / 2) - 436 (internal->tuner_offst + internal->sub_range / 2), 437 internal->sub_range); 438 439 if (internal->sub_range < 0) 440 internal->sub_range = 0; 441 442 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2; 443 } 444 445 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000; 446 internal->sub_dir = -internal->sub_dir; 447} 448 449/* 450 * stb0899_dvbs_algo 451 * Search for a signal, timing, carrier and data for a 452 * given frequency in a given range 453 */ 454enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state) 455{ 456 struct stb0899_params *params = &state->params; 457 struct stb0899_internal *internal = &state->internal; 458 struct stb0899_config *config = state->config; 459 460 u8 bclc, reg; 461 u8 cfr[2]; 462 u8 eq_const[10]; 463 s32 clnI = 3; 464 u32 bandwidth = 0; 465 466 /* BETA values rated @ 99MHz */ 467 s32 betaTab[5][4] = { 468 /* 5 10 20 30MBps */ 469 { 37, 34, 32, 31 }, /* QPSK 1/2 */ 470 { 37, 35, 33, 31 }, /* QPSK 2/3 */ 471 { 37, 35, 33, 31 }, /* QPSK 3/4 */ 472 { 37, 36, 33, 32 }, /* QPSK 5/6 */ 473 { 37, 36, 33, 32 } /* QPSK 7/8 */ 474 }; 475 476 internal->direction = 1; 477 478 stb0899_set_srate(state, internal->master_clk, params->srate); 479 /* Carrier loop optimization versus symbol rate for acquisition*/ 480 if (params->srate <= 5000000) { 481 stb0899_write_reg(state, STB0899_ACLC, 0x89); 482 bclc = stb0899_read_reg(state, STB0899_BCLC); 483 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c); 484 stb0899_write_reg(state, STB0899_BCLC, bclc); 485 clnI = 0; 486 } else if (params->srate <= 15000000) { 487 stb0899_write_reg(state, STB0899_ACLC, 0xc9); 488 bclc = stb0899_read_reg(state, STB0899_BCLC); 489 STB0899_SETFIELD_VAL(BETA, bclc, 0x22); 490 stb0899_write_reg(state, STB0899_BCLC, bclc); 491 clnI = 1; 492 } else if(params->srate <= 25000000) { 493 stb0899_write_reg(state, STB0899_ACLC, 0x89); 494 bclc = stb0899_read_reg(state, STB0899_BCLC); 495 STB0899_SETFIELD_VAL(BETA, bclc, 0x27); 496 stb0899_write_reg(state, STB0899_BCLC, bclc); 497 clnI = 2; 498 } else { 499 stb0899_write_reg(state, STB0899_ACLC, 0xc8); 500 bclc = stb0899_read_reg(state, STB0899_BCLC); 501 STB0899_SETFIELD_VAL(BETA, bclc, 0x29); 502 stb0899_write_reg(state, STB0899_BCLC, bclc); 503 clnI = 3; 504 } 505 506 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition"); 507 /* Set the timing loop to acquisition */ 508 stb0899_write_reg(state, STB0899_RTC, 0x46); 509 stb0899_write_reg(state, STB0899_CFD, 0xee); 510 511 /* !! WARNING !! 512 * Do not read any status variables while acquisition, 513 * If any needed, read before the acquisition starts 514 * querying status while acquiring causes the 515 * acquisition to go bad and hence no locks. 516 */ 517 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d", 518 internal->derot_percent, params->srate, internal->mclk); 519 520 /* Initial calculations */ 521 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */ 522 internal->t_derot = stb0899_calc_derot_time(params->srate); 523 internal->t_data = 500; 524 525 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger"); 526 /* RESET Stream merger */ 527 reg = stb0899_read_reg(state, STB0899_TSTRES); 528 STB0899_SETFIELD_VAL(FRESRS, reg, 1); 529 stb0899_write_reg(state, STB0899_TSTRES, reg); 530 531 /* 532 * Set KDIVIDER to an intermediate value between 533 * 1/2 and 7/8 for acquisition 534 */ 535 reg = stb0899_read_reg(state, STB0899_DEMAPVIT); 536 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60); 537 stb0899_write_reg(state, STB0899_DEMAPVIT, reg); 538 539 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */ 540 stb0899_write_reg(state, STB0899_VITSYNC, 0x19); 541 542 stb0899_first_subrange(state); 543 do { 544 /* Initialisations */ 545 cfr[0] = cfr[1] = 0; 546 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */ 547 548 stb0899_write_reg(state, STB0899_RTF, 0); 549 reg = stb0899_read_reg(state, STB0899_CFD); 550 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); 551 stb0899_write_reg(state, STB0899_CFD, reg); 552 553 internal->derot_freq = 0; 554 internal->status = NOAGC1; 555 556 /* enable tuner I/O */ 557 stb0899_i2c_gate_ctrl(&state->frontend, 1); 558 559 /* Move tuner to frequency */ 560 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency"); 561 if (state->config->tuner_set_frequency) 562 state->config->tuner_set_frequency(&state->frontend, internal->freq); 563 564 if (state->config->tuner_get_frequency) 565 state->config->tuner_get_frequency(&state->frontend, &internal->freq); 566 567 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */ 568 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq); 569 internal->status = AGC1OK; 570 571 /* There is signal in the band */ 572 if (config->tuner_get_bandwidth) 573 config->tuner_get_bandwidth(&state->frontend, &bandwidth); 574 575 /* disable tuner I/O */ 576 stb0899_i2c_gate_ctrl(&state->frontend, 0); 577 578 if (params->srate <= bandwidth / 2) 579 stb0899_search_tmg(state); /* For low rates (SCPC) */ 580 else 581 stb0899_check_tmg(state); /* For high rates (MCPC) */ 582 583 if (internal->status == TIMINGOK) { 584 dprintk(state->verbose, FE_DEBUG, 1, 585 "TIMING OK ! Derot freq=%d, mclk=%d", 586 internal->derot_freq, internal->mclk); 587 588 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */ 589 dprintk(state->verbose, FE_DEBUG, 1, 590 "CARRIER OK ! Derot freq=%d, mclk=%d", 591 internal->derot_freq, internal->mclk); 592 593 if (stb0899_search_data(state) == DATAOK) { /* Check for data */ 594 dprintk(state->verbose, FE_DEBUG, 1, 595 "DATA OK ! Derot freq=%d, mclk=%d", 596 internal->derot_freq, internal->mclk); 597 598 if (stb0899_check_range(state) == RANGEOK) { 599 dprintk(state->verbose, FE_DEBUG, 1, 600 "RANGE OK ! derot freq=%d, mclk=%d", 601 internal->derot_freq, internal->mclk); 602 603 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000); 604 reg = stb0899_read_reg(state, STB0899_PLPARM); 605 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg); 606 dprintk(state->verbose, FE_DEBUG, 1, 607 "freq=%d, internal resultant freq=%d", 608 params->freq, internal->freq); 609 610 dprintk(state->verbose, FE_DEBUG, 1, 611 "internal puncture rate=%d", 612 internal->fecrate); 613 } 614 } 615 } 616 } 617 if (internal->status != RANGEOK) 618 next_sub_range(state); 619 620 } while (internal->sub_range && internal->status != RANGEOK); 621 622 /* Set the timing loop to tracking */ 623 stb0899_write_reg(state, STB0899_RTC, 0x33); 624 stb0899_write_reg(state, STB0899_CFD, 0xf7); 625 /* if locked and range ok, set Kdiv */ 626 if (internal->status == RANGEOK) { 627 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !"); 628 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */ 629 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */ 630 631 /* 632 * Carrier loop optimization versus 633 * symbol Rate/Puncture Rate for Tracking 634 */ 635 reg = stb0899_read_reg(state, STB0899_BCLC); 636 switch (internal->fecrate) { 637 case STB0899_FEC_1_2: /* 13 */ 638 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a); 639 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]); 640 stb0899_write_reg(state, STB0899_BCLC, reg); 641 break; 642 case STB0899_FEC_2_3: /* 18 */ 643 stb0899_write_reg(state, STB0899_DEMAPVIT, 44); 644 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]); 645 stb0899_write_reg(state, STB0899_BCLC, reg); 646 break; 647 case STB0899_FEC_3_4: /* 21 */ 648 stb0899_write_reg(state, STB0899_DEMAPVIT, 60); 649 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]); 650 stb0899_write_reg(state, STB0899_BCLC, reg); 651 break; 652 case STB0899_FEC_5_6: /* 24 */ 653 stb0899_write_reg(state, STB0899_DEMAPVIT, 75); 654 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]); 655 stb0899_write_reg(state, STB0899_BCLC, reg); 656 break; 657 case STB0899_FEC_6_7: /* 25 */ 658 stb0899_write_reg(state, STB0899_DEMAPVIT, 88); 659 stb0899_write_reg(state, STB0899_ACLC, 0x88); 660 stb0899_write_reg(state, STB0899_BCLC, 0x9a); 661 break; 662 case STB0899_FEC_7_8: /* 26 */ 663 stb0899_write_reg(state, STB0899_DEMAPVIT, 94); 664 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]); 665 stb0899_write_reg(state, STB0899_BCLC, reg); 666 break; 667 default: 668 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate"); 669 break; 670 } 671 /* release stream merger RESET */ 672 reg = stb0899_read_reg(state, STB0899_TSTRES); 673 STB0899_SETFIELD_VAL(FRESRS, reg, 0); 674 stb0899_write_reg(state, STB0899_TSTRES, reg); 675 676 /* disable carrier detector */ 677 reg = stb0899_read_reg(state, STB0899_CFD); 678 STB0899_SETFIELD_VAL(CFD_ON, reg, 0); 679 stb0899_write_reg(state, STB0899_CFD, reg); 680 681 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10); 682 } 683 684 return internal->status; 685} 686 687/* 688 * stb0899_dvbs2_config_uwp 689 * Configure UWP state machine 690 */ 691static void stb0899_dvbs2_config_uwp(struct stb0899_state *state) 692{ 693 struct stb0899_internal *internal = &state->internal; 694 struct stb0899_config *config = state->config; 695 u32 uwp1, uwp2, uwp3, reg; 696 697 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1); 698 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2); 699 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3); 700 701 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave); 702 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant); 703 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof); 704 705 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse); 706 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine); 707 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold); 708 709 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq); 710 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track); 711 712 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1); 713 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2); 714 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3); 715 716 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO); 717 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout); 718 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg); 719} 720 721/* 722 * stb0899_dvbs2_config_csm_auto 723 * Set CSM to AUTO mode 724 */ 725static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state) 726{ 727 u32 reg; 728 729 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); 730 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1); 731 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg); 732} 733 734static long Log2Int(int number) 735{ 736 int i; 737 738 i = 0; 739 while ((1 << i) <= abs(number)) 740 i++; 741 742 if (number == 0) 743 i = 1; 744 745 return i - 1; 746} 747 748/* 749 * stb0899_dvbs2_calc_srate 750 * compute BTR_NOM_FREQ for the symbol rate 751 */ 752static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state) 753{ 754 struct stb0899_internal *internal = &state->internal; 755 struct stb0899_config *config = state->config; 756 757 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq; 758 u32 master_clk, srate; 759 760 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate); 761 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio; 762 dec_rate = Log2Int(dec_ratio); 763 decim = 1 << dec_rate; 764 master_clk = internal->master_clk / 1000; 765 srate = internal->srate / 1000; 766 767 if (decim <= 4) { 768 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk; 769 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk; 770 } else { 771 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100; 772 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk; 773 } 774 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk); 775 776 return btr_nom_freq; 777} 778 779/* 780 * stb0899_dvbs2_calc_dev 781 * compute the correction to be applied to symbol rate 782 */ 783static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state) 784{ 785 struct stb0899_internal *internal = &state->internal; 786 u32 dec_ratio, correction, master_clk, srate; 787 788 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate); 789 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio; 790 791 master_clk = internal->master_clk / 1000; /* for integer Caculation*/ 792 srate = internal->srate / 1000; /* for integer Caculation*/ 793 correction = (512 * master_clk) / (2 * dec_ratio * srate); 794 795 return correction; 796} 797 798/* 799 * stb0899_dvbs2_set_srate 800 * Set DVBS2 symbol rate 801 */ 802static void stb0899_dvbs2_set_srate(struct stb0899_state *state) 803{ 804 struct stb0899_internal *internal = &state->internal; 805 806 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq; 807 u32 correction, freq_adj, band_lim, decim_cntrl, reg; 808 u8 anti_alias; 809 810 /*set decimation to 1*/ 811 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate); 812 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio; 813 dec_rate = Log2Int(dec_ratio); 814 815 win_sel = 0; 816 if (dec_rate >= 5) 817 win_sel = dec_rate - 4; 818 819 decim = (1 << dec_rate); 820 /* (FSamp/Fsymbol *100) for integer Caculation */ 821 f_sym = internal->master_clk / ((decim * internal->srate) / 1000); 822 823 if (f_sym <= 2250) /* don't band limit signal going into btr block*/ 824 band_lim = 1; 825 else 826 band_lim = 0; /* band limit signal going into btr block*/ 827 828 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7); 829 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl); 830 831 if (f_sym <= 3450) 832 anti_alias = 0; 833 else if (f_sym <= 4250) 834 anti_alias = 1; 835 else 836 anti_alias = 2; 837 838 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias); 839 btr_nom_freq = stb0899_dvbs2_calc_srate(state); 840 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq); 841 842 correction = stb0899_dvbs2_calc_dev(state); 843 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL); 844 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction); 845 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); 846 847 /* scale UWP+CSM frequency to sample rate*/ 848 freq_adj = internal->srate / (internal->master_clk / 4096); 849 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj); 850} 851 852/* 853 * stb0899_dvbs2_set_btr_loopbw 854 * set bit timing loop bandwidth as a percentage of the symbol rate 855 */ 856static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state) 857{ 858 struct stb0899_internal *internal = &state->internal; 859 struct stb0899_config *config = state->config; 860 861 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60; 862 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft; 863 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift; 864 u32 decim, K, wn, k_direct, k_indirect; 865 u32 reg; 866 867 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate); 868 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio; 869 dec_rate = Log2Int(dec_ratio); 870 decim = (1 << dec_rate); 871 872 sym_peak *= 576000; 873 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000); 874 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/ 875 876 if (K != 0) { 877 K = sym_peak / K; 878 wn = (4 * zeta * zeta) + 1000000; 879 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/ 880 881 k_indirect = (wn * wn) / K; 882 k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/ 883 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/ 884 k_direct *= 100; 885 886 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2; 887 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset; 888 k_btr1 = k_direct / (1 << k_direct_shift); 889 k_btr1 /= 10000; 890 891 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/; 892 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset; 893 k_btr0 = k_indirect * (1 << (-k_indirect_shift)); 894 k_btr0 /= 1000000; 895 896 k_btr2_rshft = 0; 897 if (k_btr0_rshft > 15) { 898 k_btr2_rshft = k_btr0_rshft - 15; 899 k_btr0_rshft = 15; 900 } 901 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN); 902 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft); 903 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0); 904 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft); 905 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1); 906 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft); 907 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg); 908 } else 909 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f); 910} 911 912/* 913 * stb0899_dvbs2_set_carr_freq 914 * set nominal frequency for carrier search 915 */ 916static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk) 917{ 918 struct stb0899_config *config = state->config; 919 s32 crl_nom_freq; 920 u32 reg; 921 922 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk; 923 crl_nom_freq *= carr_freq; 924 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); 925 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq); 926 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); 927} 928 929/* 930 * stb0899_dvbs2_init_calc 931 * Initialize DVBS2 UWP, CSM, carrier and timing loops 932 */ 933static void stb0899_dvbs2_init_calc(struct stb0899_state *state) 934{ 935 struct stb0899_internal *internal = &state->internal; 936 s32 steps, step_size; 937 u32 range, reg; 938 939 /* config uwp and csm */ 940 stb0899_dvbs2_config_uwp(state); 941 stb0899_dvbs2_config_csm_auto(state); 942 943 /* initialize BTR */ 944 stb0899_dvbs2_set_srate(state); 945 stb0899_dvbs2_set_btr_loopbw(state); 946 947 if (internal->srate / 1000000 >= 15) 948 step_size = (1 << 17) / 5; 949 else if (internal->srate / 1000000 >= 10) 950 step_size = (1 << 17) / 7; 951 else if (internal->srate / 1000000 >= 5) 952 step_size = (1 << 17) / 10; 953 else 954 step_size = (1 << 17) / 4; 955 956 range = internal->srch_range / 1000000; 957 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000)); 958 steps = (steps + 6) / 10; 959 steps = (steps == 0) ? 1 : steps; 960 if (steps % 2 == 0) 961 stb0899_dvbs2_set_carr_freq(state, internal->center_freq - 962 (internal->step_size * (internal->srate / 20000000)), 963 (internal->master_clk) / 1000000); 964 else 965 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000); 966 967 /*Set Carrier Search params (zigzag, num steps and freq step size*/ 968 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2); 969 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1); 970 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps); 971 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size); 972 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg); 973} 974 975/* 976 * stb0899_dvbs2_btr_init 977 * initialize the timing loop 978 */ 979static void stb0899_dvbs2_btr_init(struct stb0899_state *state) 980{ 981 u32 reg; 982 983 /* set enable BTR loopback */ 984 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL); 985 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1); 986 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1); 987 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); 988 989 /* fix btr freq accum at 0 */ 990 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000); 991 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000); 992 993 /* fix btr freq accum at 0 */ 994 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000); 995 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000); 996} 997 998/* 999 * stb0899_dvbs2_reacquire 1000 * trigger a DVB-S2 acquisition 1001 */ 1002static void stb0899_dvbs2_reacquire(struct stb0899_state *state) 1003{ 1004 u32 reg = 0; 1005 1006 /* demod soft reset */ 1007 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1); 1008 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); 1009 1010 /*Reset Timing Loop */ 1011 stb0899_dvbs2_btr_init(state); 1012 1013 /* reset Carrier loop */ 1014 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30)); 1015 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0); 1016 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0); 1017 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30)); 1018 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0); 1019 1020 /*release demod soft reset */ 1021 reg = 0; 1022 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0); 1023 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); 1024 1025 /* start acquisition process */ 1026 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1); 1027 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0); 1028 1029 /* equalizer Init */ 1030 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1); 1031 1032 /*Start equilizer */ 1033 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0); 1034 1035 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); 1036 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0); 1037 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0); 1038 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05); 1039 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01); 1040 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); 1041 1042 /* RESET Packet delineator */ 1043 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a); 1044} 1045 1046/* 1047 * stb0899_dvbs2_get_dmd_status 1048 * get DVB-S2 Demod LOCK status 1049 */ 1050static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout) 1051{ 1052 int time = -10, lock = 0, uwp, csm; 1053 u32 reg; 1054 1055 do { 1056 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS); 1057 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg); 1058 if (STB0899_GETFIELD(IF_AGC_LOCK, reg)) 1059 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !"); 1060 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2); 1061 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg); 1062 uwp = STB0899_GETFIELD(UWP_LOCK, reg); 1063 csm = STB0899_GETFIELD(CSM_LOCK, reg); 1064 if (uwp && csm) 1065 lock = 1; 1066 1067 time += 10; 1068 msleep(10); 1069 1070 } while ((!lock) && (time <= timeout)); 1071 1072 if (lock) { 1073 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !"); 1074 return DVBS2_DEMOD_LOCK; 1075 } else { 1076 return DVBS2_DEMOD_NOLOCK; 1077 } 1078} 1079 1080/* 1081 * stb0899_dvbs2_get_data_lock 1082 * get FEC status 1083 */ 1084static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout) 1085{ 1086 int time = 0, lock = 0; 1087 u8 reg; 1088 1089 while ((!lock) && (time < timeout)) { 1090 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1); 1091 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg); 1092 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg); 1093 time++; 1094 } 1095 1096 return lock; 1097} 1098 1099/* 1100 * stb0899_dvbs2_get_fec_status 1101 * get DVB-S2 FEC LOCK status 1102 */ 1103static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout) 1104{ 1105 int time = 0, Locked; 1106 1107 do { 1108 Locked = stb0899_dvbs2_get_data_lock(state, 1); 1109 time++; 1110 msleep(1); 1111 1112 } while ((!Locked) && (time < timeout)); 1113 1114 if (Locked) { 1115 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !"); 1116 return DVBS2_FEC_LOCK; 1117 } else { 1118 return DVBS2_FEC_NOLOCK; 1119 } 1120} 1121 1122 1123/* 1124 * stb0899_dvbs2_init_csm 1125 * set parameters for manual mode 1126 */ 1127static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod) 1128{ 1129 struct stb0899_internal *internal = &state->internal; 1130 1131 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80; 1132 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr; 1133 u32 csm1, csm2, csm3, csm4; 1134 1135 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) { 1136 switch (modcod) { 1137 case STB0899_QPSK_12: 1138 gamma_acq = 25; 1139 gamma_rho_acq = 2700; 1140 gamma_trk = 12; 1141 gamma_rho_trk = 180; 1142 lock_count_thr = 8; 1143 break; 1144 case STB0899_QPSK_35: 1145 gamma_acq = 38; 1146 gamma_rho_acq = 7182; 1147 gamma_trk = 14; 1148 gamma_rho_trk = 308; 1149 lock_count_thr = 8; 1150 break; 1151 case STB0899_QPSK_23: 1152 gamma_acq = 42; 1153 gamma_rho_acq = 9408; 1154 gamma_trk = 17; 1155 gamma_rho_trk = 476; 1156 lock_count_thr = 8; 1157 break; 1158 case STB0899_QPSK_34: 1159 gamma_acq = 53; 1160 gamma_rho_acq = 16642; 1161 gamma_trk = 19; 1162 gamma_rho_trk = 646; 1163 lock_count_thr = 8; 1164 break; 1165 case STB0899_QPSK_45: 1166 gamma_acq = 53; 1167 gamma_rho_acq = 17119; 1168 gamma_trk = 22; 1169 gamma_rho_trk = 880; 1170 lock_count_thr = 8; 1171 break; 1172 case STB0899_QPSK_56: 1173 gamma_acq = 55; 1174 gamma_rho_acq = 19250; 1175 gamma_trk = 23; 1176 gamma_rho_trk = 989; 1177 lock_count_thr = 8; 1178 break; 1179 case STB0899_QPSK_89: 1180 gamma_acq = 60; 1181 gamma_rho_acq = 24240; 1182 gamma_trk = 24; 1183 gamma_rho_trk = 1176; 1184 lock_count_thr = 8; 1185 break; 1186 case STB0899_QPSK_910: 1187 gamma_acq = 66; 1188 gamma_rho_acq = 29634; 1189 gamma_trk = 24; 1190 gamma_rho_trk = 1176; 1191 lock_count_thr = 8; 1192 break; 1193 default: 1194 gamma_acq = 66; 1195 gamma_rho_acq = 29634; 1196 gamma_trk = 24; 1197 gamma_rho_trk = 1176; 1198 lock_count_thr = 8; 1199 break; 1200 } 1201 1202 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); 1203 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0); 1204 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); 1205 1206 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); 1207 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2); 1208 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3); 1209 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4); 1210 1211 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl); 1212 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass); 1213 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain); 1214 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift); 1215 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift); 1216 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq); 1217 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq); 1218 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk); 1219 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk); 1220 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr); 1221 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr); 1222 1223 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); 1224 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2); 1225 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3); 1226 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4); 1227 } 1228} 1229 1230/* 1231 * stb0899_dvbs2_get_srate 1232 * get DVB-S2 Symbol Rate 1233 */ 1234static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state) 1235{ 1236 struct stb0899_internal *internal = &state->internal; 1237 struct stb0899_config *config = state->config; 1238 1239 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg; 1240 int div1, div2, rem1, rem2; 1241 1242 div1 = config->btr_nco_bits / 2; 1243 div2 = config->btr_nco_bits - div1 - 1; 1244 1245 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ); 1246 1247 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL); 1248 decimRate = STB0899_GETFIELD(DECIM_RATE, reg); 1249 decimRate = (1 << decimRate); 1250 1251 intval1 = internal->master_clk / (1 << div1); 1252 intval2 = bTrNomFreq / (1 << div2); 1253 1254 rem1 = internal->master_clk % (1 << div1); 1255 rem2 = bTrNomFreq % (1 << div2); 1256 /* only for integer calculation */ 1257 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1)); 1258 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */ 1259 1260 return srate; 1261} 1262 1263/* 1264 * stb0899_dvbs2_algo 1265 * Search for signal, timing, carrier and data for a given 1266 * frequency in a given range 1267 */ 1268enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state) 1269{ 1270 struct stb0899_internal *internal = &state->internal; 1271 enum stb0899_modcod modcod; 1272 1273 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum; 1274 int i = 0; 1275 u32 reg, csm1; 1276 1277 if (internal->srate <= 2000000) { 1278 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */ 1279 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */ 1280 } else if (internal->srate <= 5000000) { 1281 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */ 1282 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */ 1283 } else if (internal->srate <= 10000000) { 1284 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */ 1285 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */ 1286 } else if (internal->srate <= 15000000) { 1287 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */ 1288 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */ 1289 } else if (internal->srate <= 20000000) { 1290 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */ 1291 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */ 1292 } else if (internal->srate <= 25000000) { 1293 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */ 1294 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */ 1295 } else { 1296 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */ 1297 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */ 1298 } 1299 1300 /* Maintain Stream Merger in reset during acquisition */ 1301 reg = stb0899_read_reg(state, STB0899_TSTRES); 1302 STB0899_SETFIELD_VAL(FRESRS, reg, 1); 1303 stb0899_write_reg(state, STB0899_TSTRES, reg); 1304 1305 /* enable tuner I/O */ 1306 stb0899_i2c_gate_ctrl(&state->frontend, 1); 1307 1308 /* Move tuner to frequency */ 1309 if (state->config->tuner_set_frequency) 1310 state->config->tuner_set_frequency(&state->frontend, internal->freq); 1311 if (state->config->tuner_get_frequency) 1312 state->config->tuner_get_frequency(&state->frontend, &internal->freq); 1313 1314 /* disable tuner I/O */ 1315 stb0899_i2c_gate_ctrl(&state->frontend, 0); 1316 1317 /* Set IF AGC to acquisition */ 1318 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); 1319 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4); 1320 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32); 1321 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); 1322 1323 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2); 1324 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0); 1325 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); 1326 1327 /* Initialisation */ 1328 stb0899_dvbs2_init_calc(state); 1329 1330 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); 1331 switch (internal->inversion) { 1332 case IQ_SWAP_OFF: 1333 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0); 1334 break; 1335 case IQ_SWAP_ON: 1336 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1); 1337 break; 1338 case IQ_SWAP_AUTO: /* use last successful search first */ 1339 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1); 1340 break; 1341 } 1342 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); 1343 stb0899_dvbs2_reacquire(state); 1344 1345 /* Wait for demod lock (UWP and CSM) */ 1346 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime); 1347 1348 if (internal->status == DVBS2_DEMOD_LOCK) { 1349 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !"); 1350 i = 0; 1351 /* Demod Locked, check FEC status */ 1352 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); 1353 1354 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/ 1355 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) { 1356 /* Read the frequency offset*/ 1357 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ); 1358 1359 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/ 1360 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); 1361 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq); 1362 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); 1363 stb0899_dvbs2_reacquire(state); 1364 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime); 1365 i++; 1366 } 1367 } 1368 1369 if (internal->status != DVBS2_FEC_LOCK) { 1370 if (internal->inversion == IQ_SWAP_AUTO) { 1371 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); 1372 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg); 1373 /* IQ Spectrum Inversion */ 1374 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum); 1375 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); 1376 /* start acquistion process */ 1377 stb0899_dvbs2_reacquire(state); 1378 1379 /* Wait for demod lock (UWP and CSM) */ 1380 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime); 1381 if (internal->status == DVBS2_DEMOD_LOCK) { 1382 i = 0; 1383 /* Demod Locked, check FEC */ 1384 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); 1385 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */ 1386 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) { 1387 /* Read the frequency offset*/ 1388 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ); 1389 1390 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/ 1391 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); 1392 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq); 1393 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); 1394 1395 stb0899_dvbs2_reacquire(state); 1396 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime); 1397 i++; 1398 } 1399 } 1400/* 1401 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED) 1402 pParams->IQLocked = !iqSpectrum; 1403*/ 1404 } 1405 } 1406 if (internal->status == DVBS2_FEC_LOCK) { 1407 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !"); 1408 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); 1409 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2; 1410 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01; 1411 1412 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) && 1413 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) && 1414 (pilots == 1)) { 1415 1416 stb0899_dvbs2_init_csm(state, pilots, modcod); 1417 /* Wait for UWP,CSM and data LOCK 20ms max */ 1418 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); 1419 1420 i = 0; 1421 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) { 1422 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); 1423 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1); 1424 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); 1425 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); 1426 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0); 1427 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); 1428 1429 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); 1430 i++; 1431 } 1432 } 1433 1434 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) && 1435 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) && 1436 (pilots == 1)) { 1437 1438 /* Equalizer Disable update */ 1439 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); 1440 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1); 1441 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); 1442 } 1443 1444 /* slow down the Equalizer once locked */ 1445 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); 1446 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02); 1447 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); 1448 1449 /* Store signal parameters */ 1450 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ); 1451 1452 offsetfreq = offsetfreq / ((1 << 30) / 1000); 1453 offsetfreq *= (internal->master_clk / 1000000); 1454 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); 1455 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg)) 1456 offsetfreq *= -1; 1457 1458 internal->freq = internal->freq - offsetfreq; 1459 internal->srate = stb0899_dvbs2_get_srate(state); 1460 1461 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); 1462 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2; 1463 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01; 1464 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01; 1465 1466 /* Set IF AGC to tracking */ 1467 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); 1468 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3); 1469 1470 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/ 1471 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23)) 1472 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16); 1473 1474 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); 1475 1476 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2); 1477 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7); 1478 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); 1479 } 1480 1481 /* Release Stream Merger Reset */ 1482 reg = stb0899_read_reg(state, STB0899_TSTRES); 1483 STB0899_SETFIELD_VAL(FRESRS, reg, 0); 1484 stb0899_write_reg(state, STB0899_TSTRES, reg); 1485 1486 return internal->status; 1487} 1488