1#include <media/saa7146_vv.h> 2 3static int vbi_pixel_to_capture = 720 * 2; 4 5static int vbi_workaround(struct saa7146_dev *dev) 6{ 7 struct saa7146_vv *vv = dev->vv_data; 8 9 u32 *cpu; 10 dma_addr_t dma_addr; 11 12 int count = 0; 13 int i; 14 15 DECLARE_WAITQUEUE(wait, current); 16 17 DEB_VBI(("dev:%p\n",dev)); 18 19 20 cpu = pci_alloc_consistent(dev->pci, 4096, &dma_addr); 21 if (NULL == cpu) 22 return -ENOMEM; 23 24 saa7146_write(dev, BASE_EVEN3, dma_addr); 25 saa7146_write(dev, BASE_ODD3, dma_addr+vbi_pixel_to_capture); 26 saa7146_write(dev, PROT_ADDR3, dma_addr+4096); 27 saa7146_write(dev, PITCH3, vbi_pixel_to_capture); 28 saa7146_write(dev, BASE_PAGE3, 0x0); 29 saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0)); 30 saa7146_write(dev, MC2, MASK_04|MASK_20); 31 32 /* load brs-control register */ 33 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); 34 /* BXO = 1h, BRS to outbound */ 35 WRITE_RPS1(0xc000008c); 36 /* wait for vbi_a or vbi_b*/ 37 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) { 38 DEB_D(("...using port b\n")); 39 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_E_FID_B); 40 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_O_FID_B); 41/* 42 WRITE_RPS1(CMD_PAUSE | MASK_09); 43*/ 44 } else { 45 DEB_D(("...using port a\n")); 46 WRITE_RPS1(CMD_PAUSE | MASK_10); 47 } 48 /* upload brs */ 49 WRITE_RPS1(CMD_UPLOAD | MASK_08); 50 /* load brs-control register */ 51 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); 52 /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */ 53 WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19); 54 /* wait for brs_done */ 55 WRITE_RPS1(CMD_PAUSE | MASK_08); 56 /* upload brs */ 57 WRITE_RPS1(CMD_UPLOAD | MASK_08); 58 /* load video-dma3 NumLines3 and NumBytes3 */ 59 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4)); 60 /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */ 61 WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture)); 62 /* load brs-control register */ 63 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4)); 64 /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */ 65 WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start 66 /* wait for brs_done */ 67 WRITE_RPS1(CMD_PAUSE | MASK_08); 68 /* upload brs and video-dma3*/ 69 WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04); 70 /* load mc2 register: enable dma3 */ 71 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4)); 72 WRITE_RPS1(MASK_20 | MASK_04); 73 /* generate interrupt */ 74 WRITE_RPS1(CMD_INTERRUPT); 75 /* stop rps1 */ 76 WRITE_RPS1(CMD_STOP); 77 78 for(i = 0; i < 2; i++) { 79 80 saa7146_write(dev, MC2, MASK_31|MASK_15); 81 82 saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0)); 83 saa7146_write(dev, MC2, MASK_04|MASK_20); 84 85 /* enable rps1 irqs */ 86 SAA7146_IER_ENABLE(dev,MASK_28); 87 88 /* prepare to wait to be woken up by the irq-handler */ 89 add_wait_queue(&vv->vbi_wq, &wait); 90 current->state = TASK_INTERRUPTIBLE; 91 92 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); 93 saa7146_write(dev, MC1, (MASK_13 | MASK_29)); 94 95 schedule(); 96 97 DEB_VBI(("brs bug workaround %d/1.\n",i)); 98 99 remove_wait_queue(&vv->vbi_wq, &wait); 100 current->state = TASK_RUNNING; 101 102 /* disable rps1 irqs */ 103 SAA7146_IER_DISABLE(dev,MASK_28); 104 105 /* stop video-dma3 */ 106 saa7146_write(dev, MC1, MASK_20); 107 108 if(signal_pending(current)) { 109 110 DEB_VBI(("aborted (rps:0x%08x).\n",saa7146_read(dev,RPS_ADDR1))); 111 112 /* stop rps1 for sure */ 113 saa7146_write(dev, MC1, MASK_29); 114 115 pci_free_consistent(dev->pci, 4096, cpu, dma_addr); 116 return -EINTR; 117 } 118 } 119 120 pci_free_consistent(dev->pci, 4096, cpu, dma_addr); 121 return 0; 122} 123 124static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next) 125{ 126 struct saa7146_vv *vv = dev->vv_data; 127 128 struct saa7146_video_dma vdma3; 129 130 int count = 0; 131 unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B; 132 unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B; 133 134/* 135 vdma3.base_even = 0xc8000000+2560*70; 136 vdma3.base_odd = 0xc8000000; 137 vdma3.prot_addr = 0xc8000000+2560*164; 138 vdma3.pitch = 2560; 139 vdma3.base_page = 0; 140 vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above! 141*/ 142 vdma3.base_even = buf->pt[2].offset; 143 vdma3.base_odd = buf->pt[2].offset + 16 * vbi_pixel_to_capture; 144 vdma3.prot_addr = buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture; 145 vdma3.pitch = vbi_pixel_to_capture; 146 vdma3.base_page = buf->pt[2].dma | ME1; 147 vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture; 148 149 saa7146_write_out_dma(dev, 3, &vdma3); 150 151 /* write beginning of rps-program */ 152 count = 0; 153 154 /* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */ 155 156 /* we don't wait here for the first field anymore. this is different from the video 157 capture and might cause that the first buffer is only half filled (with only 158 one field). but since this is some sort of streaming data, this is not that negative. 159 but by doing this, we can use the whole engine from videobuf-dma-sg.c... */ 160 161/* 162 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait); 163 WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait); 164*/ 165 /* set bit 1 */ 166 WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4)); 167 WRITE_RPS1(MASK_28 | MASK_12); 168 169 /* turn on video-dma3 */ 170 WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4)); 171 WRITE_RPS1(MASK_04 | MASK_20); /* => mask */ 172 WRITE_RPS1(MASK_04 | MASK_20); /* => values */ 173 174 /* wait for o_fid_a/b / e_fid_a/b toggle */ 175 WRITE_RPS1(CMD_PAUSE | o_wait); 176 WRITE_RPS1(CMD_PAUSE | e_wait); 177 178 /* generate interrupt */ 179 WRITE_RPS1(CMD_INTERRUPT); 180 181 /* stop */ 182 WRITE_RPS1(CMD_STOP); 183 184 /* enable rps1 irqs */ 185 SAA7146_IER_ENABLE(dev, MASK_28); 186 187 /* write the address of the rps-program */ 188 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle); 189 190 /* turn on rps */ 191 saa7146_write(dev, MC1, (MASK_13 | MASK_29)); 192} 193 194static int buffer_activate(struct saa7146_dev *dev, 195 struct saa7146_buf *buf, 196 struct saa7146_buf *next) 197{ 198 struct saa7146_vv *vv = dev->vv_data; 199 buf->vb.state = VIDEOBUF_ACTIVE; 200 201 DEB_VBI(("dev:%p, buf:%p, next:%p\n",dev,buf,next)); 202 saa7146_set_vbi_capture(dev,buf,next); 203 204 mod_timer(&vv->vbi_q.timeout, jiffies+BUFFER_TIMEOUT); 205 return 0; 206} 207 208static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,enum v4l2_field field) 209{ 210 struct file *file = q->priv_data; 211 struct saa7146_fh *fh = file->private_data; 212 struct saa7146_dev *dev = fh->dev; 213 struct saa7146_buf *buf = (struct saa7146_buf *)vb; 214 215 int err = 0; 216 int lines, llength, size; 217 218 lines = 16 * 2 ; /* 2 fields */ 219 llength = vbi_pixel_to_capture; 220 size = lines * llength; 221 222 DEB_VBI(("vb:%p\n",vb)); 223 224 if (0 != buf->vb.baddr && buf->vb.bsize < size) { 225 DEB_VBI(("size mismatch.\n")); 226 return -EINVAL; 227 } 228 229 if (buf->vb.size != size) 230 saa7146_dma_free(dev,q,buf); 231 232 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) { 233 struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb); 234 235 buf->vb.width = llength; 236 buf->vb.height = lines; 237 buf->vb.size = size; 238 buf->vb.field = field; 239 240 saa7146_pgtable_free(dev->pci, &buf->pt[2]); 241 saa7146_pgtable_alloc(dev->pci, &buf->pt[2]); 242 243 err = videobuf_iolock(q,&buf->vb, NULL); 244 if (err) 245 goto oops; 246 err = saa7146_pgtable_build_single(dev->pci, &buf->pt[2], 247 dma->sglist, dma->sglen); 248 if (0 != err) 249 return err; 250 } 251 buf->vb.state = VIDEOBUF_PREPARED; 252 buf->activate = buffer_activate; 253 254 return 0; 255 256 oops: 257 DEB_VBI(("error out.\n")); 258 saa7146_dma_free(dev,q,buf); 259 260 return err; 261} 262 263static int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size) 264{ 265 int llength,lines; 266 267 lines = 16 * 2 ; /* 2 fields */ 268 llength = vbi_pixel_to_capture; 269 270 *size = lines * llength; 271 *count = 2; 272 273 DEB_VBI(("count:%d, size:%d\n",*count,*size)); 274 275 return 0; 276} 277 278static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) 279{ 280 struct file *file = q->priv_data; 281 struct saa7146_fh *fh = file->private_data; 282 struct saa7146_dev *dev = fh->dev; 283 struct saa7146_vv *vv = dev->vv_data; 284 struct saa7146_buf *buf = (struct saa7146_buf *)vb; 285 286 DEB_VBI(("vb:%p\n",vb)); 287 saa7146_buffer_queue(dev,&vv->vbi_q,buf); 288} 289 290static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) 291{ 292 struct file *file = q->priv_data; 293 struct saa7146_fh *fh = file->private_data; 294 struct saa7146_dev *dev = fh->dev; 295 struct saa7146_buf *buf = (struct saa7146_buf *)vb; 296 297 DEB_VBI(("vb:%p\n",vb)); 298 saa7146_dma_free(dev,q,buf); 299} 300 301static struct videobuf_queue_ops vbi_qops = { 302 .buf_setup = buffer_setup, 303 .buf_prepare = buffer_prepare, 304 .buf_queue = buffer_queue, 305 .buf_release = buffer_release, 306}; 307 308/* ------------------------------------------------------------------ */ 309 310static void vbi_stop(struct saa7146_fh *fh, struct file *file) 311{ 312 struct saa7146_dev *dev = fh->dev; 313 struct saa7146_vv *vv = dev->vv_data; 314 unsigned long flags; 315 DEB_VBI(("dev:%p, fh:%p\n",dev, fh)); 316 317 spin_lock_irqsave(&dev->slock,flags); 318 319 /* disable rps1 */ 320 saa7146_write(dev, MC1, MASK_29); 321 322 /* disable rps1 irqs */ 323 SAA7146_IER_DISABLE(dev, MASK_28); 324 325 /* shut down dma 3 transfers */ 326 saa7146_write(dev, MC1, MASK_20); 327 328 if (vv->vbi_q.curr) { 329 saa7146_buffer_finish(dev,&vv->vbi_q,VIDEOBUF_DONE); 330 } 331 332 videobuf_queue_cancel(&fh->vbi_q); 333 334 vv->vbi_streaming = NULL; 335 336 del_timer(&vv->vbi_q.timeout); 337 del_timer(&fh->vbi_read_timeout); 338 339 spin_unlock_irqrestore(&dev->slock, flags); 340} 341 342static void vbi_read_timeout(unsigned long data) 343{ 344 struct file *file = (struct file*)data; 345 struct saa7146_fh *fh = file->private_data; 346 struct saa7146_dev *dev = fh->dev; 347 348 DEB_VBI(("dev:%p, fh:%p\n",dev, fh)); 349 350 vbi_stop(fh, file); 351} 352 353static void vbi_init(struct saa7146_dev *dev, struct saa7146_vv *vv) 354{ 355 DEB_VBI(("dev:%p\n",dev)); 356 357 INIT_LIST_HEAD(&vv->vbi_q.queue); 358 359 init_timer(&vv->vbi_q.timeout); 360 vv->vbi_q.timeout.function = saa7146_buffer_timeout; 361 vv->vbi_q.timeout.data = (unsigned long)(&vv->vbi_q); 362 vv->vbi_q.dev = dev; 363 364 init_waitqueue_head(&vv->vbi_wq); 365} 366 367static int vbi_open(struct saa7146_dev *dev, struct file *file) 368{ 369 struct saa7146_fh *fh = file->private_data; 370 371 u32 arbtr_ctrl = saa7146_read(dev, PCI_BT_V1); 372 int ret = 0; 373 374 DEB_VBI(("dev:%p, fh:%p\n",dev,fh)); 375 376 ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS); 377 if (0 == ret) { 378 DEB_S(("cannot get vbi RESOURCE_DMA3_BRS resource\n")); 379 return -EBUSY; 380 } 381 382 /* adjust arbitrition control for video dma 3 */ 383 arbtr_ctrl &= ~0x1f0000; 384 arbtr_ctrl |= 0x1d0000; 385 saa7146_write(dev, PCI_BT_V1, arbtr_ctrl); 386 saa7146_write(dev, MC2, (MASK_04|MASK_20)); 387 388 memset(&fh->vbi_fmt,0,sizeof(fh->vbi_fmt)); 389 390 fh->vbi_fmt.sampling_rate = 27000000; 391 fh->vbi_fmt.offset = 248; /* todo */ 392 fh->vbi_fmt.samples_per_line = vbi_pixel_to_capture; 393 fh->vbi_fmt.sample_format = V4L2_PIX_FMT_GREY; 394 395 fh->vbi_fmt.start[0] = 5; 396 fh->vbi_fmt.count[0] = 16; 397 fh->vbi_fmt.start[1] = 312; 398 fh->vbi_fmt.count[1] = 16; 399 400 videobuf_queue_sg_init(&fh->vbi_q, &vbi_qops, 401 &dev->pci->dev, &dev->slock, 402 V4L2_BUF_TYPE_VBI_CAPTURE, 403 V4L2_FIELD_SEQ_TB, 404 sizeof(struct saa7146_buf), 405 file); 406 407 init_timer(&fh->vbi_read_timeout); 408 fh->vbi_read_timeout.function = vbi_read_timeout; 409 fh->vbi_read_timeout.data = (unsigned long)file; 410 411 /* initialize the brs */ 412 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) { 413 saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19)); 414 } else { 415 saa7146_write(dev, BRS_CTRL, 0x00000001); 416 417 if (0 != (ret = vbi_workaround(dev))) { 418 DEB_VBI(("vbi workaround failed!\n")); 419 /* return ret;*/ 420 } 421 } 422 423 /* upload brs register */ 424 saa7146_write(dev, MC2, (MASK_08|MASK_24)); 425 return 0; 426} 427 428static void vbi_close(struct saa7146_dev *dev, struct file *file) 429{ 430 struct saa7146_fh *fh = file->private_data; 431 struct saa7146_vv *vv = dev->vv_data; 432 DEB_VBI(("dev:%p, fh:%p\n",dev,fh)); 433 434 if( fh == vv->vbi_streaming ) { 435 vbi_stop(fh, file); 436 } 437 saa7146_res_free(fh, RESOURCE_DMA3_BRS); 438} 439 440static void vbi_irq_done(struct saa7146_dev *dev, unsigned long status) 441{ 442 struct saa7146_vv *vv = dev->vv_data; 443 spin_lock(&dev->slock); 444 445 if (vv->vbi_q.curr) { 446 DEB_VBI(("dev:%p, curr:%p\n",dev,vv->vbi_q.curr)); 447 /* this must be += 2, one count for each field */ 448 vv->vbi_fieldcount+=2; 449 vv->vbi_q.curr->vb.field_count = vv->vbi_fieldcount; 450 saa7146_buffer_finish(dev,&vv->vbi_q,VIDEOBUF_DONE); 451 } else { 452 DEB_VBI(("dev:%p\n",dev)); 453 } 454 saa7146_buffer_next(dev,&vv->vbi_q,1); 455 456 spin_unlock(&dev->slock); 457} 458 459static ssize_t vbi_read(struct file *file, char __user *data, size_t count, loff_t *ppos) 460{ 461 struct saa7146_fh *fh = file->private_data; 462 struct saa7146_dev *dev = fh->dev; 463 struct saa7146_vv *vv = dev->vv_data; 464 ssize_t ret = 0; 465 466 DEB_VBI(("dev:%p, fh:%p\n",dev,fh)); 467 468 if( NULL == vv->vbi_streaming ) { 469 vv->vbi_streaming = fh; 470 } 471 472 if( fh != vv->vbi_streaming ) { 473 DEB_VBI(("open %p is already using vbi capture.",vv->vbi_streaming)); 474 return -EBUSY; 475 } 476 477 mod_timer(&fh->vbi_read_timeout, jiffies+BUFFER_TIMEOUT); 478 ret = videobuf_read_stream(&fh->vbi_q, data, count, ppos, 1, 479 file->f_flags & O_NONBLOCK); 480/* 481 printk("BASE_ODD3: 0x%08x\n", saa7146_read(dev, BASE_ODD3)); 482 printk("BASE_EVEN3: 0x%08x\n", saa7146_read(dev, BASE_EVEN3)); 483 printk("PROT_ADDR3: 0x%08x\n", saa7146_read(dev, PROT_ADDR3)); 484 printk("PITCH3: 0x%08x\n", saa7146_read(dev, PITCH3)); 485 printk("BASE_PAGE3: 0x%08x\n", saa7146_read(dev, BASE_PAGE3)); 486 printk("NUM_LINE_BYTE3: 0x%08x\n", saa7146_read(dev, NUM_LINE_BYTE3)); 487 printk("BRS_CTRL: 0x%08x\n", saa7146_read(dev, BRS_CTRL)); 488*/ 489 return ret; 490} 491 492struct saa7146_use_ops saa7146_vbi_uops = { 493 .init = vbi_init, 494 .open = vbi_open, 495 .release = vbi_close, 496 .irq_done = vbi_irq_done, 497 .read = vbi_read, 498}; 499