1/* 2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards 3 * 4 * Author Andreas Eversberg (jolly@eversberg.eu) 5 * ported to mqueue mechanism: 6 * Peter Sprenger (sprengermoving-bytes.de) 7 * 8 * inspired by existing hfc-pci driver: 9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de) 10 * Copyright 2008 by Karsten Keil (kkeil@suse.de) 11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu) 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2, or (at your option) 16 * any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * 28 * Thanks to Cologne Chip AG for this great controller! 29 */ 30 31/* 32 * module parameters: 33 * type: 34 * By default (0), the card is automatically detected. 35 * Or use the following combinations: 36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port) 37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports) 38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports) 39 * Bit 8 = 0x00100 = uLaw (instead of aLaw) 40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware 41 * Bit 10 = spare 42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto) 43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto) 44 * Bit 13 = spare 45 * Bit 14 = 0x04000 = Use external ram (128K) 46 * Bit 15 = 0x08000 = Use external ram (512K) 47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32 48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else 49 * Bit 18 = spare 50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog) 51 * (all other bits are reserved and shall be 0) 52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM 53 * bus (PCM master) 54 * 55 * port: (optional or required for all ports on all installed cards) 56 * HFC-4S/HFC-8S only bits: 57 * Bit 0 = 0x001 = Use master clock for this S/T interface 58 * (ony once per chip). 59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode) 60 * Don't use this unless you know what you are doing! 61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing) 62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock 63 * received from port 1 64 * 65 * HFC-E1 only bits: 66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical 67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode) 68 * Bit 2 = 0x0004 = Report LOS 69 * Bit 3 = 0x0008 = Report AIS 70 * Bit 4 = 0x0010 = Report SLIP 71 * Bit 5 = 0x0020 = Report RDI 72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame 73 * mode instead. 74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode. 75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode. 76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL. 77 * (E1 only) 78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0 79 * for default. 80 * (all other bits are reserved and shall be 0) 81 * 82 * debug: 83 * NOTE: only one debug value must be given for all cards 84 * enable debugging (see hfc_multi.h for debug options) 85 * 86 * poll: 87 * NOTE: only one poll value must be given for all cards 88 * Give the number of samples for each fifo process. 89 * By default 128 is used. Decrease to reduce delay, increase to 90 * reduce cpu load. If unsure, don't mess with it! 91 * Valid is 8, 16, 32, 64, 128, 256. 92 * 93 * pcm: 94 * NOTE: only one pcm value must be given for every card. 95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus. 96 * By default (0), the PCM bus id is 100 for the card that is PCM master. 97 * If multiple cards are PCM master (because they are not interconnected), 98 * each card with PCM master will have increasing PCM id. 99 * All PCM busses with the same ID are expected to be connected and have 100 * common time slots slots. 101 * Only one chip of the PCM bus must be master, the others slave. 102 * -1 means no support of PCM bus not even. 103 * Omit this value, if all cards are interconnected or none is connected. 104 * If unsure, don't give this parameter. 105 * 106 * dslot: 107 * NOTE: only one dslot value must be given for every card. 108 * Also this value must be given for non-E1 cards. If omitted, the E1 109 * card has D-channel on time slot 16, which is default. 110 * If 1..15 or 17..31, an alternate time slot is used for D-channel. 111 * In this case, the application must be able to handle this. 112 * If -1 is given, the D-channel is disabled and all 31 slots can be used 113 * for B-channel. (only for specific applications) 114 * If you don't know how to use it, you don't need it! 115 * 116 * iomode: 117 * NOTE: only one mode value must be given for every card. 118 * -> See hfc_multi.h for HFC_IO_MODE_* values 119 * By default, the IO mode is pci memory IO (MEMIO). 120 * Some cards require specific IO mode, so it cannot be changed. 121 * It may be usefull to set IO mode to register io (REGIO) to solve 122 * PCI bridge problems. 123 * If unsure, don't give this parameter. 124 * 125 * clockdelay_nt: 126 * NOTE: only one clockdelay_nt value must be given once for all cards. 127 * Give the value of the clock control register (A_ST_CLK_DLY) 128 * of the S/T interfaces in NT mode. 129 * This register is needed for the TBR3 certification, so don't change it. 130 * 131 * clockdelay_te: 132 * NOTE: only one clockdelay_te value must be given once 133 * Give the value of the clock control register (A_ST_CLK_DLY) 134 * of the S/T interfaces in TE mode. 135 * This register is needed for the TBR3 certification, so don't change it. 136 * 137 * clock: 138 * NOTE: only one clock value must be given once 139 * Selects interface with clock source for mISDN and applications. 140 * Set to card number starting with 1. Set to -1 to disable. 141 * By default, the first card is used as clock source. 142 * 143 * hwid: 144 * NOTE: only one hwid value must be given once 145 * Enable special embedded devices with XHFC controllers. 146 */ 147 148/* 149 * debug register access (never use this, it will flood your system log) 150 * #define HFC_REGISTER_DEBUG 151 */ 152 153#define HFC_MULTI_VERSION "2.03" 154 155#include <linux/module.h> 156#include <linux/slab.h> 157#include <linux/pci.h> 158#include <linux/delay.h> 159#include <linux/mISDNhw.h> 160#include <linux/mISDNdsp.h> 161 162/* 163#define IRQCOUNT_DEBUG 164#define IRQ_DEBUG 165*/ 166 167#include "hfc_multi.h" 168#ifdef ECHOPREP 169#include "gaintab.h" 170#endif 171 172#define MAX_CARDS 8 173#define MAX_PORTS (8 * MAX_CARDS) 174 175static LIST_HEAD(HFClist); 176static spinlock_t HFClock; /* global hfc list lock */ 177 178static void ph_state_change(struct dchannel *); 179 180static struct hfc_multi *syncmaster; 181static int plxsd_master; /* if we have a master card (yet) */ 182static spinlock_t plx_lock; /* may not acquire other lock inside */ 183 184#define TYP_E1 1 185#define TYP_4S 4 186#define TYP_8S 8 187 188static int poll_timer = 6; /* default = 128 samples = 16ms */ 189/* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */ 190static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 }; 191#define CLKDEL_TE 0x0f /* CLKDEL in TE mode */ 192#define CLKDEL_NT 0x6c /* CLKDEL in NT mode 193 (0x60 MUST be included!) */ 194 195#define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */ 196#define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */ 197#define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */ 198 199/* 200 * module stuff 201 */ 202 203static uint type[MAX_CARDS]; 204static int pcm[MAX_CARDS]; 205static int dslot[MAX_CARDS]; 206static uint iomode[MAX_CARDS]; 207static uint port[MAX_PORTS]; 208static uint debug; 209static uint poll; 210static int clock; 211static uint timer; 212static uint clockdelay_te = CLKDEL_TE; 213static uint clockdelay_nt = CLKDEL_NT; 214#define HWID_NONE 0 215#define HWID_MINIP4 1 216#define HWID_MINIP8 2 217#define HWID_MINIP16 3 218static uint hwid = HWID_NONE; 219 220static int HFC_cnt, Port_cnt, PCM_cnt = 99; 221 222MODULE_AUTHOR("Andreas Eversberg"); 223MODULE_LICENSE("GPL"); 224MODULE_VERSION(HFC_MULTI_VERSION); 225module_param(debug, uint, S_IRUGO | S_IWUSR); 226module_param(poll, uint, S_IRUGO | S_IWUSR); 227module_param(clock, int, S_IRUGO | S_IWUSR); 228module_param(timer, uint, S_IRUGO | S_IWUSR); 229module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR); 230module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR); 231module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR); 232module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR); 233module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR); 234module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR); 235module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR); 236module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */ 237 238#ifdef HFC_REGISTER_DEBUG 239#define HFC_outb(hc, reg, val) \ 240 (hc->HFC_outb(hc, reg, val, __func__, __LINE__)) 241#define HFC_outb_nodebug(hc, reg, val) \ 242 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__)) 243#define HFC_inb(hc, reg) \ 244 (hc->HFC_inb(hc, reg, __func__, __LINE__)) 245#define HFC_inb_nodebug(hc, reg) \ 246 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__)) 247#define HFC_inw(hc, reg) \ 248 (hc->HFC_inw(hc, reg, __func__, __LINE__)) 249#define HFC_inw_nodebug(hc, reg) \ 250 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__)) 251#define HFC_wait(hc) \ 252 (hc->HFC_wait(hc, __func__, __LINE__)) 253#define HFC_wait_nodebug(hc) \ 254 (hc->HFC_wait_nodebug(hc, __func__, __LINE__)) 255#else 256#define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val)) 257#define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val)) 258#define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg)) 259#define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg)) 260#define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg)) 261#define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg)) 262#define HFC_wait(hc) (hc->HFC_wait(hc)) 263#define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc)) 264#endif 265 266#ifdef CONFIG_MISDN_HFCMULTI_8xx 267#include "hfc_multi_8xx.h" 268#endif 269 270/* HFC_IO_MODE_PCIMEM */ 271static void 272#ifdef HFC_REGISTER_DEBUG 273HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, 274 const char *function, int line) 275#else 276HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) 277#endif 278{ 279 writeb(val, hc->pci_membase + reg); 280} 281static u_char 282#ifdef HFC_REGISTER_DEBUG 283HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) 284#else 285HFC_inb_pcimem(struct hfc_multi *hc, u_char reg) 286#endif 287{ 288 return readb(hc->pci_membase + reg); 289} 290static u_short 291#ifdef HFC_REGISTER_DEBUG 292HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) 293#else 294HFC_inw_pcimem(struct hfc_multi *hc, u_char reg) 295#endif 296{ 297 return readw(hc->pci_membase + reg); 298} 299static void 300#ifdef HFC_REGISTER_DEBUG 301HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line) 302#else 303HFC_wait_pcimem(struct hfc_multi *hc) 304#endif 305{ 306 while (readb(hc->pci_membase + R_STATUS) & V_BUSY) 307 cpu_relax(); 308} 309 310/* HFC_IO_MODE_REGIO */ 311static void 312#ifdef HFC_REGISTER_DEBUG 313HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, 314 const char *function, int line) 315#else 316HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) 317#endif 318{ 319 outb(reg, hc->pci_iobase + 4); 320 outb(val, hc->pci_iobase); 321} 322static u_char 323#ifdef HFC_REGISTER_DEBUG 324HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) 325#else 326HFC_inb_regio(struct hfc_multi *hc, u_char reg) 327#endif 328{ 329 outb(reg, hc->pci_iobase + 4); 330 return inb(hc->pci_iobase); 331} 332static u_short 333#ifdef HFC_REGISTER_DEBUG 334HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) 335#else 336HFC_inw_regio(struct hfc_multi *hc, u_char reg) 337#endif 338{ 339 outb(reg, hc->pci_iobase + 4); 340 return inw(hc->pci_iobase); 341} 342static void 343#ifdef HFC_REGISTER_DEBUG 344HFC_wait_regio(struct hfc_multi *hc, const char *function, int line) 345#else 346HFC_wait_regio(struct hfc_multi *hc) 347#endif 348{ 349 outb(R_STATUS, hc->pci_iobase + 4); 350 while (inb(hc->pci_iobase) & V_BUSY) 351 cpu_relax(); 352} 353 354#ifdef HFC_REGISTER_DEBUG 355static void 356HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, 357 const char *function, int line) 358{ 359 char regname[256] = "", bits[9] = "xxxxxxxx"; 360 int i; 361 362 i = -1; 363 while (hfc_register_names[++i].name) { 364 if (hfc_register_names[i].reg == reg) 365 strcat(regname, hfc_register_names[i].name); 366 } 367 if (regname[0] == '\0') 368 strcpy(regname, "register"); 369 370 bits[7] = '0' + (!!(val & 1)); 371 bits[6] = '0' + (!!(val & 2)); 372 bits[5] = '0' + (!!(val & 4)); 373 bits[4] = '0' + (!!(val & 8)); 374 bits[3] = '0' + (!!(val & 16)); 375 bits[2] = '0' + (!!(val & 32)); 376 bits[1] = '0' + (!!(val & 64)); 377 bits[0] = '0' + (!!(val & 128)); 378 printk(KERN_DEBUG 379 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n", 380 hc->id, reg, regname, val, bits, function, line); 381 HFC_outb_nodebug(hc, reg, val); 382} 383static u_char 384HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) 385{ 386 char regname[256] = "", bits[9] = "xxxxxxxx"; 387 u_char val = HFC_inb_nodebug(hc, reg); 388 int i; 389 390 i = 0; 391 while (hfc_register_names[i++].name) 392 ; 393 while (hfc_register_names[++i].name) { 394 if (hfc_register_names[i].reg == reg) 395 strcat(regname, hfc_register_names[i].name); 396 } 397 if (regname[0] == '\0') 398 strcpy(regname, "register"); 399 400 bits[7] = '0' + (!!(val & 1)); 401 bits[6] = '0' + (!!(val & 2)); 402 bits[5] = '0' + (!!(val & 4)); 403 bits[4] = '0' + (!!(val & 8)); 404 bits[3] = '0' + (!!(val & 16)); 405 bits[2] = '0' + (!!(val & 32)); 406 bits[1] = '0' + (!!(val & 64)); 407 bits[0] = '0' + (!!(val & 128)); 408 printk(KERN_DEBUG 409 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n", 410 hc->id, reg, regname, val, bits, function, line); 411 return val; 412} 413static u_short 414HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) 415{ 416 char regname[256] = ""; 417 u_short val = HFC_inw_nodebug(hc, reg); 418 int i; 419 420 i = 0; 421 while (hfc_register_names[i++].name) 422 ; 423 while (hfc_register_names[++i].name) { 424 if (hfc_register_names[i].reg == reg) 425 strcat(regname, hfc_register_names[i].name); 426 } 427 if (regname[0] == '\0') 428 strcpy(regname, "register"); 429 430 printk(KERN_DEBUG 431 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n", 432 hc->id, reg, regname, val, function, line); 433 return val; 434} 435static void 436HFC_wait_debug(struct hfc_multi *hc, const char *function, int line) 437{ 438 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n", 439 hc->id, function, line); 440 HFC_wait_nodebug(hc); 441} 442#endif 443 444/* write fifo data (REGIO) */ 445static void 446write_fifo_regio(struct hfc_multi *hc, u_char *data, int len) 447{ 448 outb(A_FIFO_DATA0, (hc->pci_iobase)+4); 449 while (len>>2) { 450 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase); 451 data += 4; 452 len -= 4; 453 } 454 while (len>>1) { 455 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase); 456 data += 2; 457 len -= 2; 458 } 459 while (len) { 460 outb(*data, hc->pci_iobase); 461 data++; 462 len--; 463 } 464} 465/* write fifo data (PCIMEM) */ 466static void 467write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) 468{ 469 while (len>>2) { 470 writel(cpu_to_le32(*(u32 *)data), 471 hc->pci_membase + A_FIFO_DATA0); 472 data += 4; 473 len -= 4; 474 } 475 while (len>>1) { 476 writew(cpu_to_le16(*(u16 *)data), 477 hc->pci_membase + A_FIFO_DATA0); 478 data += 2; 479 len -= 2; 480 } 481 while (len) { 482 writeb(*data, hc->pci_membase + A_FIFO_DATA0); 483 data++; 484 len--; 485 } 486} 487 488/* read fifo data (REGIO) */ 489static void 490read_fifo_regio(struct hfc_multi *hc, u_char *data, int len) 491{ 492 outb(A_FIFO_DATA0, (hc->pci_iobase)+4); 493 while (len>>2) { 494 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase)); 495 data += 4; 496 len -= 4; 497 } 498 while (len>>1) { 499 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase)); 500 data += 2; 501 len -= 2; 502 } 503 while (len) { 504 *data = inb(hc->pci_iobase); 505 data++; 506 len--; 507 } 508} 509 510/* read fifo data (PCIMEM) */ 511static void 512read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) 513{ 514 while (len>>2) { 515 *(u32 *)data = 516 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0)); 517 data += 4; 518 len -= 4; 519 } 520 while (len>>1) { 521 *(u16 *)data = 522 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0)); 523 data += 2; 524 len -= 2; 525 } 526 while (len) { 527 *data = readb(hc->pci_membase + A_FIFO_DATA0); 528 data++; 529 len--; 530 } 531} 532 533static void 534enable_hwirq(struct hfc_multi *hc) 535{ 536 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN; 537 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); 538} 539 540static void 541disable_hwirq(struct hfc_multi *hc) 542{ 543 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN); 544 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); 545} 546 547#define NUM_EC 2 548#define MAX_TDM_CHAN 32 549 550 551inline void 552enablepcibridge(struct hfc_multi *c) 553{ 554 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */ 555} 556 557inline void 558disablepcibridge(struct hfc_multi *c) 559{ 560 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */ 561} 562 563inline unsigned char 564readpcibridge(struct hfc_multi *hc, unsigned char address) 565{ 566 unsigned short cipv; 567 unsigned char data; 568 569 if (!hc->pci_iobase) 570 return 0; 571 572 /* slow down a PCI read access by 1 PCI clock cycle */ 573 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/ 574 575 if (address == 0) 576 cipv = 0x4000; 577 else 578 cipv = 0x5800; 579 580 /* select local bridge port address by writing to CIP port */ 581 /* data = HFC_inb(c, cipv); * was _io before */ 582 outw(cipv, hc->pci_iobase + 4); 583 data = inb(hc->pci_iobase); 584 585 /* restore R_CTRL for normal PCI read cycle speed */ 586 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */ 587 588 return data; 589} 590 591inline void 592writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data) 593{ 594 unsigned short cipv; 595 unsigned int datav; 596 597 if (!hc->pci_iobase) 598 return; 599 600 if (address == 0) 601 cipv = 0x4000; 602 else 603 cipv = 0x5800; 604 605 /* select local bridge port address by writing to CIP port */ 606 outw(cipv, hc->pci_iobase + 4); 607 /* define a 32 bit dword with 4 identical bytes for write sequence */ 608 datav = data | ((__u32) data << 8) | ((__u32) data << 16) | 609 ((__u32) data << 24); 610 611 /* 612 * write this 32 bit dword to the bridge data port 613 * this will initiate a write sequence of up to 4 writes to the same 614 * address on the local bus interface the number of write accesses 615 * is undefined but >=1 and depends on the next PCI transaction 616 * during write sequence on the local bus 617 */ 618 outl(datav, hc->pci_iobase); 619} 620 621inline void 622cpld_set_reg(struct hfc_multi *hc, unsigned char reg) 623{ 624 /* Do data pin read low byte */ 625 HFC_outb(hc, R_GPIO_OUT1, reg); 626} 627 628inline void 629cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) 630{ 631 cpld_set_reg(hc, reg); 632 633 enablepcibridge(hc); 634 writepcibridge(hc, 1, val); 635 disablepcibridge(hc); 636 637 return; 638} 639 640inline unsigned char 641cpld_read_reg(struct hfc_multi *hc, unsigned char reg) 642{ 643 unsigned char bytein; 644 645 cpld_set_reg(hc, reg); 646 647 /* Do data pin read low byte */ 648 HFC_outb(hc, R_GPIO_OUT1, reg); 649 650 enablepcibridge(hc); 651 bytein = readpcibridge(hc, 1); 652 disablepcibridge(hc); 653 654 return bytein; 655} 656 657inline void 658vpm_write_address(struct hfc_multi *hc, unsigned short addr) 659{ 660 cpld_write_reg(hc, 0, 0xff & addr); 661 cpld_write_reg(hc, 1, 0x01 & (addr >> 8)); 662} 663 664inline unsigned short 665vpm_read_address(struct hfc_multi *c) 666{ 667 unsigned short addr; 668 unsigned short highbit; 669 670 addr = cpld_read_reg(c, 0); 671 highbit = cpld_read_reg(c, 1); 672 673 addr = addr | (highbit << 8); 674 675 return addr & 0x1ff; 676} 677 678inline unsigned char 679vpm_in(struct hfc_multi *c, int which, unsigned short addr) 680{ 681 unsigned char res; 682 683 vpm_write_address(c, addr); 684 685 if (!which) 686 cpld_set_reg(c, 2); 687 else 688 cpld_set_reg(c, 3); 689 690 enablepcibridge(c); 691 res = readpcibridge(c, 1); 692 disablepcibridge(c); 693 694 cpld_set_reg(c, 0); 695 696 return res; 697} 698 699inline void 700vpm_out(struct hfc_multi *c, int which, unsigned short addr, 701 unsigned char data) 702{ 703 vpm_write_address(c, addr); 704 705 enablepcibridge(c); 706 707 if (!which) 708 cpld_set_reg(c, 2); 709 else 710 cpld_set_reg(c, 3); 711 712 writepcibridge(c, 1, data); 713 714 cpld_set_reg(c, 0); 715 716 disablepcibridge(c); 717 718 { 719 unsigned char regin; 720 regin = vpm_in(c, which, addr); 721 if (regin != data) 722 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back " 723 "0x%x\n", data, addr, regin); 724 } 725 726} 727 728 729static void 730vpm_init(struct hfc_multi *wc) 731{ 732 unsigned char reg; 733 unsigned int mask; 734 unsigned int i, x, y; 735 unsigned int ver; 736 737 for (x = 0; x < NUM_EC; x++) { 738 /* Setup GPIO's */ 739 if (!x) { 740 ver = vpm_in(wc, x, 0x1a0); 741 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver); 742 } 743 744 for (y = 0; y < 4; y++) { 745 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */ 746 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */ 747 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */ 748 } 749 750 /* Setup TDM path - sets fsync and tdm_clk as inputs */ 751 reg = vpm_in(wc, x, 0x1a3); /* misc_con */ 752 vpm_out(wc, x, 0x1a3, reg & ~2); 753 754 /* Setup Echo length (256 taps) */ 755 vpm_out(wc, x, 0x022, 1); 756 vpm_out(wc, x, 0x023, 0xff); 757 758 /* Setup timeslots */ 759 vpm_out(wc, x, 0x02f, 0x00); 760 mask = 0x02020202 << (x * 4); 761 762 /* Setup the tdm channel masks for all chips */ 763 for (i = 0; i < 4; i++) 764 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff); 765 766 /* Setup convergence rate */ 767 printk(KERN_DEBUG "VPM: A-law mode\n"); 768 reg = 0x00 | 0x10 | 0x01; 769 vpm_out(wc, x, 0x20, reg); 770 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg); 771 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */ 772 773 vpm_out(wc, x, 0x24, 0x02); 774 reg = vpm_in(wc, x, 0x24); 775 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg); 776 777 /* Initialize echo cans */ 778 for (i = 0; i < MAX_TDM_CHAN; i++) { 779 if (mask & (0x00000001 << i)) 780 vpm_out(wc, x, i, 0x00); 781 } 782 783 784 udelay(2000); 785 udelay(2000); 786 udelay(2000); 787 udelay(2000); 788 udelay(2000); 789 790 /* Put in bypass mode */ 791 for (i = 0; i < MAX_TDM_CHAN; i++) { 792 if (mask & (0x00000001 << i)) 793 vpm_out(wc, x, i, 0x01); 794 } 795 796 /* Enable bypass */ 797 for (i = 0; i < MAX_TDM_CHAN; i++) { 798 if (mask & (0x00000001 << i)) 799 vpm_out(wc, x, 0x78 + i, 0x01); 800 } 801 802 } 803} 804 805#ifdef UNUSED 806static void 807vpm_check(struct hfc_multi *hctmp) 808{ 809 unsigned char gpi2; 810 811 gpi2 = HFC_inb(hctmp, R_GPI_IN2); 812 813 if ((gpi2 & 0x3) != 0x3) 814 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2); 815} 816#endif /* UNUSED */ 817 818 819/* 820 * Interface to enable/disable the HW Echocan 821 * 822 * these functions are called within a spin_lock_irqsave on 823 * the channel instance lock, so we are not disturbed by irqs 824 * 825 * we can later easily change the interface to make other 826 * things configurable, for now we configure the taps 827 * 828 */ 829 830static void 831vpm_echocan_on(struct hfc_multi *hc, int ch, int taps) 832{ 833 unsigned int timeslot; 834 unsigned int unit; 835 struct bchannel *bch = hc->chan[ch].bch; 836#ifdef TXADJ 837 int txadj = -4; 838 struct sk_buff *skb; 839#endif 840 if (hc->chan[ch].protocol != ISDN_P_B_RAW) 841 return; 842 843 if (!bch) 844 return; 845 846#ifdef TXADJ 847 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, 848 sizeof(int), &txadj, GFP_ATOMIC); 849 if (skb) 850 recv_Bchannel_skb(bch, skb); 851#endif 852 853 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1; 854 unit = ch % 4; 855 856 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n", 857 taps, timeslot); 858 859 vpm_out(hc, unit, timeslot, 0x7e); 860} 861 862static void 863vpm_echocan_off(struct hfc_multi *hc, int ch) 864{ 865 unsigned int timeslot; 866 unsigned int unit; 867 struct bchannel *bch = hc->chan[ch].bch; 868#ifdef TXADJ 869 int txadj = 0; 870 struct sk_buff *skb; 871#endif 872 873 if (hc->chan[ch].protocol != ISDN_P_B_RAW) 874 return; 875 876 if (!bch) 877 return; 878 879#ifdef TXADJ 880 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, 881 sizeof(int), &txadj, GFP_ATOMIC); 882 if (skb) 883 recv_Bchannel_skb(bch, skb); 884#endif 885 886 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1; 887 unit = ch % 4; 888 889 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n", 890 timeslot); 891 /* FILLME */ 892 vpm_out(hc, unit, timeslot, 0x01); 893} 894 895 896/* 897 * Speech Design resync feature 898 * NOTE: This is called sometimes outside interrupt handler. 899 * We must lock irqsave, so no other interrupt (other card) will occurr! 900 * Also multiple interrupts may nest, so must lock each access (lists, card)! 901 */ 902static inline void 903hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) 904{ 905 struct hfc_multi *hc, *next, *pcmmaster = NULL; 906 void __iomem *plx_acc_32; 907 u_int pv; 908 u_long flags; 909 910 spin_lock_irqsave(&HFClock, flags); 911 spin_lock(&plx_lock); /* must be locked inside other locks */ 912 913 if (debug & DEBUG_HFCMULTI_PLXSD) 914 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n", 915 __func__, syncmaster); 916 917 /* select new master */ 918 if (newmaster) { 919 if (debug & DEBUG_HFCMULTI_PLXSD) 920 printk(KERN_DEBUG "using provided controller\n"); 921 } else { 922 list_for_each_entry_safe(hc, next, &HFClist, list) { 923 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 924 if (hc->syncronized) { 925 newmaster = hc; 926 break; 927 } 928 } 929 } 930 } 931 932 /* Disable sync of all cards */ 933 list_for_each_entry_safe(hc, next, &HFClist, list) { 934 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 935 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 936 pv = readl(plx_acc_32); 937 pv &= ~PLX_SYNC_O_EN; 938 writel(pv, plx_acc_32); 939 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { 940 pcmmaster = hc; 941 if (hc->ctype == HFC_TYPE_E1) { 942 if (debug & DEBUG_HFCMULTI_PLXSD) 943 printk(KERN_DEBUG 944 "Schedule SYNC_I\n"); 945 hc->e1_resync |= 1; /* get SYNC_I */ 946 } 947 } 948 } 949 } 950 951 if (newmaster) { 952 hc = newmaster; 953 if (debug & DEBUG_HFCMULTI_PLXSD) 954 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with " 955 "interface.\n", hc->id, hc); 956 /* Enable new sync master */ 957 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 958 pv = readl(plx_acc_32); 959 pv |= PLX_SYNC_O_EN; 960 writel(pv, plx_acc_32); 961 /* switch to jatt PLL, if not disabled by RX_SYNC */ 962 if (hc->ctype == HFC_TYPE_E1 963 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) { 964 if (debug & DEBUG_HFCMULTI_PLXSD) 965 printk(KERN_DEBUG "Schedule jatt PLL\n"); 966 hc->e1_resync |= 2; /* switch to jatt */ 967 } 968 } else { 969 if (pcmmaster) { 970 hc = pcmmaster; 971 if (debug & DEBUG_HFCMULTI_PLXSD) 972 printk(KERN_DEBUG 973 "id=%d (0x%p) = PCM master syncronized " 974 "with QUARTZ\n", hc->id, hc); 975 if (hc->ctype == HFC_TYPE_E1) { 976 /* Use the crystal clock for the PCM 977 master card */ 978 if (debug & DEBUG_HFCMULTI_PLXSD) 979 printk(KERN_DEBUG 980 "Schedule QUARTZ for HFC-E1\n"); 981 hc->e1_resync |= 4; /* switch quartz */ 982 } else { 983 if (debug & DEBUG_HFCMULTI_PLXSD) 984 printk(KERN_DEBUG 985 "QUARTZ is automatically " 986 "enabled by HFC-%dS\n", hc->ctype); 987 } 988 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 989 pv = readl(plx_acc_32); 990 pv |= PLX_SYNC_O_EN; 991 writel(pv, plx_acc_32); 992 } else 993 if (!rm) 994 printk(KERN_ERR "%s no pcm master, this MUST " 995 "not happen!\n", __func__); 996 } 997 syncmaster = newmaster; 998 999 spin_unlock(&plx_lock); 1000 spin_unlock_irqrestore(&HFClock, flags); 1001} 1002 1003/* This must be called AND hc must be locked irqsave!!! */ 1004inline void 1005plxsd_checksync(struct hfc_multi *hc, int rm) 1006{ 1007 if (hc->syncronized) { 1008 if (syncmaster == NULL) { 1009 if (debug & DEBUG_HFCMULTI_PLXSD) 1010 printk(KERN_DEBUG "%s: GOT sync on card %d" 1011 " (id=%d)\n", __func__, hc->id + 1, 1012 hc->id); 1013 hfcmulti_resync(hc, hc, rm); 1014 } 1015 } else { 1016 if (syncmaster == hc) { 1017 if (debug & DEBUG_HFCMULTI_PLXSD) 1018 printk(KERN_DEBUG "%s: LOST sync on card %d" 1019 " (id=%d)\n", __func__, hc->id + 1, 1020 hc->id); 1021 hfcmulti_resync(hc, NULL, rm); 1022 } 1023 } 1024} 1025 1026 1027/* 1028 * free hardware resources used by driver 1029 */ 1030static void 1031release_io_hfcmulti(struct hfc_multi *hc) 1032{ 1033 void __iomem *plx_acc_32; 1034 u_int pv; 1035 u_long plx_flags; 1036 1037 if (debug & DEBUG_HFCMULTI_INIT) 1038 printk(KERN_DEBUG "%s: entered\n", __func__); 1039 1040 /* soft reset also masks all interrupts */ 1041 hc->hw.r_cirm |= V_SRES; 1042 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1043 udelay(1000); 1044 hc->hw.r_cirm &= ~V_SRES; 1045 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1046 udelay(1000); /* instead of 'wait' that may cause locking */ 1047 1048 /* release Speech Design card, if PLX was initialized */ 1049 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) { 1050 if (debug & DEBUG_HFCMULTI_PLXSD) 1051 printk(KERN_DEBUG "%s: release PLXSD card %d\n", 1052 __func__, hc->id + 1); 1053 spin_lock_irqsave(&plx_lock, plx_flags); 1054 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1055 writel(PLX_GPIOC_INIT, plx_acc_32); 1056 pv = readl(plx_acc_32); 1057 /* Termination off */ 1058 pv &= ~PLX_TERM_ON; 1059 /* Disconnect the PCM */ 1060 pv |= PLX_SLAVE_EN_N; 1061 pv &= ~PLX_MASTER_EN; 1062 pv &= ~PLX_SYNC_O_EN; 1063 /* Put the DSP in Reset */ 1064 pv &= ~PLX_DSP_RES_N; 1065 writel(pv, plx_acc_32); 1066 if (debug & DEBUG_HFCMULTI_INIT) 1067 printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n", 1068 __func__, pv); 1069 spin_unlock_irqrestore(&plx_lock, plx_flags); 1070 } 1071 1072 /* disable memory mapped ports / io ports */ 1073 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */ 1074 if (hc->pci_dev) 1075 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0); 1076 if (hc->pci_membase) 1077 iounmap(hc->pci_membase); 1078 if (hc->plx_membase) 1079 iounmap(hc->plx_membase); 1080 if (hc->pci_iobase) 1081 release_region(hc->pci_iobase, 8); 1082 if (hc->xhfc_membase) 1083 iounmap((void *)hc->xhfc_membase); 1084 1085 if (hc->pci_dev) { 1086 pci_disable_device(hc->pci_dev); 1087 pci_set_drvdata(hc->pci_dev, NULL); 1088 } 1089 if (debug & DEBUG_HFCMULTI_INIT) 1090 printk(KERN_DEBUG "%s: done\n", __func__); 1091} 1092 1093/* 1094 * function called to reset the HFC chip. A complete software reset of chip 1095 * and fifos is done. All configuration of the chip is done. 1096 */ 1097 1098static int 1099init_chip(struct hfc_multi *hc) 1100{ 1101 u_long flags, val, val2 = 0, rev; 1102 int i, err = 0; 1103 u_char r_conf_en, rval; 1104 void __iomem *plx_acc_32; 1105 u_int pv; 1106 u_long plx_flags, hfc_flags; 1107 int plx_count; 1108 struct hfc_multi *pos, *next, *plx_last_hc; 1109 1110 spin_lock_irqsave(&hc->lock, flags); 1111 /* reset all registers */ 1112 memset(&hc->hw, 0, sizeof(struct hfcm_hw)); 1113 1114 /* revision check */ 1115 if (debug & DEBUG_HFCMULTI_INIT) 1116 printk(KERN_DEBUG "%s: entered\n", __func__); 1117 val = HFC_inb(hc, R_CHIP_ID); 1118 if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe && 1119 (val >> 1) != 0x31) { 1120 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val); 1121 err = -EIO; 1122 goto out; 1123 } 1124 rev = HFC_inb(hc, R_CHIP_RV); 1125 printk(KERN_INFO 1126 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n", 1127 val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ? 1128 " (old FIFO handling)" : ""); 1129 if (hc->ctype != HFC_TYPE_XHFC && rev == 0) { 1130 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip); 1131 printk(KERN_WARNING 1132 "HFC_multi: NOTE: Your chip is revision 0, " 1133 "ask Cologne Chip for update. Newer chips " 1134 "have a better FIFO handling. Old chips " 1135 "still work but may have slightly lower " 1136 "HDLC transmit performance.\n"); 1137 } 1138 if (rev > 1) { 1139 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't " 1140 "consider chip revision = %ld. The chip / " 1141 "bridge may not work.\n", rev); 1142 } 1143 1144 /* set s-ram size */ 1145 hc->Flen = 0x10; 1146 hc->Zmin = 0x80; 1147 hc->Zlen = 384; 1148 hc->DTMFbase = 0x1000; 1149 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) { 1150 if (debug & DEBUG_HFCMULTI_INIT) 1151 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n", 1152 __func__); 1153 hc->hw.r_ctrl |= V_EXT_RAM; 1154 hc->hw.r_ram_sz = 1; 1155 hc->Flen = 0x20; 1156 hc->Zmin = 0xc0; 1157 hc->Zlen = 1856; 1158 hc->DTMFbase = 0x2000; 1159 } 1160 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) { 1161 if (debug & DEBUG_HFCMULTI_INIT) 1162 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n", 1163 __func__); 1164 hc->hw.r_ctrl |= V_EXT_RAM; 1165 hc->hw.r_ram_sz = 2; 1166 hc->Flen = 0x20; 1167 hc->Zmin = 0xc0; 1168 hc->Zlen = 8000; 1169 hc->DTMFbase = 0x2000; 1170 } 1171 if (hc->ctype == HFC_TYPE_XHFC) { 1172 hc->Flen = 0x8; 1173 hc->Zmin = 0x0; 1174 hc->Zlen = 64; 1175 hc->DTMFbase = 0x0; 1176 } 1177 hc->max_trans = poll << 1; 1178 if (hc->max_trans > hc->Zlen) 1179 hc->max_trans = hc->Zlen; 1180 1181 /* Speech Design PLX bridge */ 1182 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1183 if (debug & DEBUG_HFCMULTI_PLXSD) 1184 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n", 1185 __func__, hc->id + 1); 1186 spin_lock_irqsave(&plx_lock, plx_flags); 1187 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1188 writel(PLX_GPIOC_INIT, plx_acc_32); 1189 pv = readl(plx_acc_32); 1190 /* The first and the last cards are terminating the PCM bus */ 1191 pv |= PLX_TERM_ON; /* hc is currently the last */ 1192 /* Disconnect the PCM */ 1193 pv |= PLX_SLAVE_EN_N; 1194 pv &= ~PLX_MASTER_EN; 1195 pv &= ~PLX_SYNC_O_EN; 1196 /* Put the DSP in Reset */ 1197 pv &= ~PLX_DSP_RES_N; 1198 writel(pv, plx_acc_32); 1199 spin_unlock_irqrestore(&plx_lock, plx_flags); 1200 if (debug & DEBUG_HFCMULTI_INIT) 1201 printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n", 1202 __func__, pv); 1203 /* 1204 * If we are the 3rd PLXSD card or higher, we must turn 1205 * termination of last PLXSD card off. 1206 */ 1207 spin_lock_irqsave(&HFClock, hfc_flags); 1208 plx_count = 0; 1209 plx_last_hc = NULL; 1210 list_for_each_entry_safe(pos, next, &HFClist, list) { 1211 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) { 1212 plx_count++; 1213 if (pos != hc) 1214 plx_last_hc = pos; 1215 } 1216 } 1217 if (plx_count >= 3) { 1218 if (debug & DEBUG_HFCMULTI_PLXSD) 1219 printk(KERN_DEBUG "%s: card %d is between, so " 1220 "we disable termination\n", 1221 __func__, plx_last_hc->id + 1); 1222 spin_lock_irqsave(&plx_lock, plx_flags); 1223 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC; 1224 pv = readl(plx_acc_32); 1225 pv &= ~PLX_TERM_ON; 1226 writel(pv, plx_acc_32); 1227 spin_unlock_irqrestore(&plx_lock, plx_flags); 1228 if (debug & DEBUG_HFCMULTI_INIT) 1229 printk(KERN_DEBUG 1230 "%s: term off: PLX_GPIO=%x\n", 1231 __func__, pv); 1232 } 1233 spin_unlock_irqrestore(&HFClock, hfc_flags); 1234 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ 1235 } 1236 1237 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1238 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ 1239 1240 /* we only want the real Z2 read-pointer for revision > 0 */ 1241 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip)) 1242 hc->hw.r_ram_sz |= V_FZ_MD; 1243 1244 /* select pcm mode */ 1245 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 1246 if (debug & DEBUG_HFCMULTI_INIT) 1247 printk(KERN_DEBUG "%s: setting PCM into slave mode\n", 1248 __func__); 1249 } else 1250 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) { 1251 if (debug & DEBUG_HFCMULTI_INIT) 1252 printk(KERN_DEBUG "%s: setting PCM into master mode\n", 1253 __func__); 1254 hc->hw.r_pcm_md0 |= V_PCM_MD; 1255 } else { 1256 if (debug & DEBUG_HFCMULTI_INIT) 1257 printk(KERN_DEBUG "%s: performing PCM auto detect\n", 1258 __func__); 1259 } 1260 1261 /* soft reset */ 1262 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl); 1263 if (hc->ctype == HFC_TYPE_XHFC) 1264 HFC_outb(hc, 0x0C /* R_FIFO_THRES */, 1265 0x11 /* 16 Bytes TX/RX */); 1266 else 1267 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); 1268 HFC_outb(hc, R_FIFO_MD, 0); 1269 if (hc->ctype == HFC_TYPE_XHFC) 1270 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES; 1271 else 1272 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES 1273 | V_RLD_EPR; 1274 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1275 udelay(100); 1276 hc->hw.r_cirm = 0; 1277 HFC_outb(hc, R_CIRM, hc->hw.r_cirm); 1278 udelay(100); 1279 if (hc->ctype != HFC_TYPE_XHFC) 1280 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); 1281 1282 /* Speech Design PLX bridge pcm and sync mode */ 1283 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1284 spin_lock_irqsave(&plx_lock, plx_flags); 1285 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1286 pv = readl(plx_acc_32); 1287 /* Connect PCM */ 1288 if (hc->hw.r_pcm_md0 & V_PCM_MD) { 1289 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; 1290 pv |= PLX_SYNC_O_EN; 1291 if (debug & DEBUG_HFCMULTI_INIT) 1292 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n", 1293 __func__, pv); 1294 } else { 1295 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N); 1296 pv &= ~PLX_SYNC_O_EN; 1297 if (debug & DEBUG_HFCMULTI_INIT) 1298 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n", 1299 __func__, pv); 1300 } 1301 writel(pv, plx_acc_32); 1302 spin_unlock_irqrestore(&plx_lock, plx_flags); 1303 } 1304 1305 /* PCM setup */ 1306 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90); 1307 if (hc->slots == 32) 1308 HFC_outb(hc, R_PCM_MD1, 0x00); 1309 if (hc->slots == 64) 1310 HFC_outb(hc, R_PCM_MD1, 0x10); 1311 if (hc->slots == 128) 1312 HFC_outb(hc, R_PCM_MD1, 0x20); 1313 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0); 1314 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 1315 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */ 1316 else if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1317 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */ 1318 else 1319 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */ 1320 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); 1321 for (i = 0; i < 256; i++) { 1322 HFC_outb_nodebug(hc, R_SLOT, i); 1323 HFC_outb_nodebug(hc, A_SL_CFG, 0); 1324 if (hc->ctype != HFC_TYPE_XHFC) 1325 HFC_outb_nodebug(hc, A_CONF, 0); 1326 hc->slot_owner[i] = -1; 1327 } 1328 1329 /* set clock speed */ 1330 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) { 1331 if (debug & DEBUG_HFCMULTI_INIT) 1332 printk(KERN_DEBUG 1333 "%s: setting double clock\n", __func__); 1334 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); 1335 } 1336 1337 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) 1338 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */); 1339 1340 /* B410P GPIO */ 1341 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 1342 printk(KERN_NOTICE "Setting GPIOs\n"); 1343 HFC_outb(hc, R_GPIO_SEL, 0x30); 1344 HFC_outb(hc, R_GPIO_EN1, 0x3); 1345 udelay(1000); 1346 printk(KERN_NOTICE "calling vpm_init\n"); 1347 vpm_init(hc); 1348 } 1349 1350 /* check if R_F0_CNT counts (8 kHz frame count) */ 1351 val = HFC_inb(hc, R_F0_CNTL); 1352 val += HFC_inb(hc, R_F0_CNTH) << 8; 1353 if (debug & DEBUG_HFCMULTI_INIT) 1354 printk(KERN_DEBUG 1355 "HFC_multi F0_CNT %ld after reset\n", val); 1356 spin_unlock_irqrestore(&hc->lock, flags); 1357 set_current_state(TASK_UNINTERRUPTIBLE); 1358 schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */ 1359 spin_lock_irqsave(&hc->lock, flags); 1360 val2 = HFC_inb(hc, R_F0_CNTL); 1361 val2 += HFC_inb(hc, R_F0_CNTH) << 8; 1362 if (debug & DEBUG_HFCMULTI_INIT) 1363 printk(KERN_DEBUG 1364 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n", 1365 val2); 1366 if (val2 >= val+8) { /* 1 ms */ 1367 /* it counts, so we keep the pcm mode */ 1368 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) 1369 printk(KERN_INFO "controller is PCM bus MASTER\n"); 1370 else 1371 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) 1372 printk(KERN_INFO "controller is PCM bus SLAVE\n"); 1373 else { 1374 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 1375 printk(KERN_INFO "controller is PCM bus SLAVE " 1376 "(auto detected)\n"); 1377 } 1378 } else { 1379 /* does not count */ 1380 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { 1381controller_fail: 1382 printk(KERN_ERR "HFC_multi ERROR, getting no 125us " 1383 "pulse. Seems that controller fails.\n"); 1384 err = -EIO; 1385 goto out; 1386 } 1387 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 1388 printk(KERN_INFO "controller is PCM bus SLAVE " 1389 "(ignoring missing PCM clock)\n"); 1390 } else { 1391 /* only one pcm master */ 1392 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) 1393 && plxsd_master) { 1394 printk(KERN_ERR "HFC_multi ERROR, no clock " 1395 "on another Speech Design card found. " 1396 "Please be sure to connect PCM cable.\n"); 1397 err = -EIO; 1398 goto out; 1399 } 1400 /* retry with master clock */ 1401 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1402 spin_lock_irqsave(&plx_lock, plx_flags); 1403 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1404 pv = readl(plx_acc_32); 1405 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; 1406 pv |= PLX_SYNC_O_EN; 1407 writel(pv, plx_acc_32); 1408 spin_unlock_irqrestore(&plx_lock, plx_flags); 1409 if (debug & DEBUG_HFCMULTI_INIT) 1410 printk(KERN_DEBUG "%s: master: " 1411 "PLX_GPIO=%x\n", __func__, pv); 1412 } 1413 hc->hw.r_pcm_md0 |= V_PCM_MD; 1414 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); 1415 spin_unlock_irqrestore(&hc->lock, flags); 1416 set_current_state(TASK_UNINTERRUPTIBLE); 1417 schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */ 1418 spin_lock_irqsave(&hc->lock, flags); 1419 val2 = HFC_inb(hc, R_F0_CNTL); 1420 val2 += HFC_inb(hc, R_F0_CNTH) << 8; 1421 if (debug & DEBUG_HFCMULTI_INIT) 1422 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after " 1423 "10 ms (2nd try)\n", val2); 1424 if (val2 >= val+8) { /* 1 ms */ 1425 test_and_set_bit(HFC_CHIP_PCM_MASTER, 1426 &hc->chip); 1427 printk(KERN_INFO "controller is PCM bus MASTER " 1428 "(auto detected)\n"); 1429 } else 1430 goto controller_fail; 1431 } 1432 } 1433 1434 /* Release the DSP Reset */ 1435 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1436 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) 1437 plxsd_master = 1; 1438 spin_lock_irqsave(&plx_lock, plx_flags); 1439 plx_acc_32 = hc->plx_membase + PLX_GPIOC; 1440 pv = readl(plx_acc_32); 1441 pv |= PLX_DSP_RES_N; 1442 writel(pv, plx_acc_32); 1443 spin_unlock_irqrestore(&plx_lock, plx_flags); 1444 if (debug & DEBUG_HFCMULTI_INIT) 1445 printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n", 1446 __func__, pv); 1447 } 1448 1449 /* pcm id */ 1450 if (hc->pcm) 1451 printk(KERN_INFO "controller has given PCM BUS ID %d\n", 1452 hc->pcm); 1453 else { 1454 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) 1455 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 1456 PCM_cnt++; /* SD has proprietary bridging */ 1457 } 1458 hc->pcm = PCM_cnt; 1459 printk(KERN_INFO "controller has PCM BUS ID %d " 1460 "(auto selected)\n", hc->pcm); 1461 } 1462 1463 /* set up timer */ 1464 HFC_outb(hc, R_TI_WD, poll_timer); 1465 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK; 1466 1467 /* set E1 state machine IRQ */ 1468 if (hc->ctype == HFC_TYPE_E1) 1469 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK; 1470 1471 /* set DTMF detection */ 1472 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) { 1473 if (debug & DEBUG_HFCMULTI_INIT) 1474 printk(KERN_DEBUG "%s: enabling DTMF detection " 1475 "for all B-channel\n", __func__); 1476 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP; 1477 if (test_bit(HFC_CHIP_ULAW, &hc->chip)) 1478 hc->hw.r_dtmf |= V_ULAW_SEL; 1479 HFC_outb(hc, R_DTMF_N, 102 - 1); 1480 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK; 1481 } 1482 1483 /* conference engine */ 1484 if (test_bit(HFC_CHIP_ULAW, &hc->chip)) 1485 r_conf_en = V_CONF_EN | V_ULAW; 1486 else 1487 r_conf_en = V_CONF_EN; 1488 if (hc->ctype != HFC_TYPE_XHFC) 1489 HFC_outb(hc, R_CONF_EN, r_conf_en); 1490 1491 /* setting leds */ 1492 switch (hc->leds) { 1493 case 1: /* HFC-E1 OEM */ 1494 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) 1495 HFC_outb(hc, R_GPIO_SEL, 0x32); 1496 else 1497 HFC_outb(hc, R_GPIO_SEL, 0x30); 1498 1499 HFC_outb(hc, R_GPIO_EN1, 0x0f); 1500 HFC_outb(hc, R_GPIO_OUT1, 0x00); 1501 1502 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); 1503 break; 1504 1505 case 2: /* HFC-4S OEM */ 1506 case 3: 1507 HFC_outb(hc, R_GPIO_SEL, 0xf0); 1508 HFC_outb(hc, R_GPIO_EN1, 0xff); 1509 HFC_outb(hc, R_GPIO_OUT1, 0x00); 1510 break; 1511 } 1512 1513 if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) { 1514 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */ 1515 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); 1516 } 1517 1518 /* set master clock */ 1519 if (hc->masterclk >= 0) { 1520 if (debug & DEBUG_HFCMULTI_INIT) 1521 printk(KERN_DEBUG "%s: setting ST master clock " 1522 "to port %d (0..%d)\n", 1523 __func__, hc->masterclk, hc->ports-1); 1524 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC); 1525 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); 1526 } 1527 1528 1529 1530 /* setting misc irq */ 1531 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc); 1532 if (debug & DEBUG_HFCMULTI_INIT) 1533 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n", 1534 hc->hw.r_irqmsk_misc); 1535 1536 /* RAM access test */ 1537 HFC_outb(hc, R_RAM_ADDR0, 0); 1538 HFC_outb(hc, R_RAM_ADDR1, 0); 1539 HFC_outb(hc, R_RAM_ADDR2, 0); 1540 for (i = 0; i < 256; i++) { 1541 HFC_outb_nodebug(hc, R_RAM_ADDR0, i); 1542 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff)); 1543 } 1544 for (i = 0; i < 256; i++) { 1545 HFC_outb_nodebug(hc, R_RAM_ADDR0, i); 1546 HFC_inb_nodebug(hc, R_RAM_DATA); 1547 rval = HFC_inb_nodebug(hc, R_INT_DATA); 1548 if (rval != ((i * 3) & 0xff)) { 1549 printk(KERN_DEBUG 1550 "addr:%x val:%x should:%x\n", i, rval, 1551 (i * 3) & 0xff); 1552 err++; 1553 } 1554 } 1555 if (err) { 1556 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err); 1557 err = -EIO; 1558 goto out; 1559 } 1560 1561 if (debug & DEBUG_HFCMULTI_INIT) 1562 printk(KERN_DEBUG "%s: done\n", __func__); 1563out: 1564 spin_unlock_irqrestore(&hc->lock, flags); 1565 return err; 1566} 1567 1568 1569/* 1570 * control the watchdog 1571 */ 1572static void 1573hfcmulti_watchdog(struct hfc_multi *hc) 1574{ 1575 hc->wdcount++; 1576 1577 if (hc->wdcount > 10) { 1578 hc->wdcount = 0; 1579 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ? 1580 V_GPIO_OUT3 : V_GPIO_OUT2; 1581 1582 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */ 1583 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); 1584 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte); 1585 } 1586} 1587 1588 1589 1590/* 1591 * output leds 1592 */ 1593static void 1594hfcmulti_leds(struct hfc_multi *hc) 1595{ 1596 unsigned long lled; 1597 unsigned long leddw; 1598 int i, state, active, leds; 1599 struct dchannel *dch; 1600 int led[4]; 1601 1602 hc->ledcount += poll; 1603 if (hc->ledcount > 4096) { 1604 hc->ledcount -= 4096; 1605 hc->ledstate = 0xAFFEAFFE; 1606 } 1607 1608 switch (hc->leds) { 1609 case 1: /* HFC-E1 OEM */ 1610 /* 2 red blinking: NT mode deactivate 1611 * 2 red steady: TE mode deactivate 1612 * left green: L1 active 1613 * left red: frame sync, but no L1 1614 * right green: L2 active 1615 */ 1616 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */ 1617 if (hc->chan[hc->dslot].dch->dev.D.protocol 1618 != ISDN_P_NT_E1) { 1619 led[0] = 1; 1620 led[1] = 1; 1621 } else if (hc->ledcount>>11) { 1622 led[0] = 1; 1623 led[1] = 1; 1624 } else { 1625 led[0] = 0; 1626 led[1] = 0; 1627 } 1628 led[2] = 0; 1629 led[3] = 0; 1630 } else { /* with frame sync */ 1631 /* TODO make it work */ 1632 led[0] = 0; 1633 led[1] = 0; 1634 led[2] = 0; 1635 led[3] = 1; 1636 } 1637 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF; 1638 /* leds are inverted */ 1639 if (leds != (int)hc->ledstate) { 1640 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds); 1641 hc->ledstate = leds; 1642 } 1643 break; 1644 1645 case 2: /* HFC-4S OEM */ 1646 /* red blinking = PH_DEACTIVATE NT Mode 1647 * red steady = PH_DEACTIVATE TE Mode 1648 * green steady = PH_ACTIVATE 1649 */ 1650 for (i = 0; i < 4; i++) { 1651 state = 0; 1652 active = -1; 1653 dch = hc->chan[(i << 2) | 2].dch; 1654 if (dch) { 1655 state = dch->state; 1656 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1657 active = 3; 1658 else 1659 active = 7; 1660 } 1661 if (state) { 1662 if (state == active) { 1663 led[i] = 1; /* led green */ 1664 } else 1665 if (dch->dev.D.protocol == ISDN_P_TE_S0) 1666 /* TE mode: led red */ 1667 led[i] = 2; 1668 else 1669 if (hc->ledcount>>11) 1670 /* led red */ 1671 led[i] = 2; 1672 else 1673 /* led off */ 1674 led[i] = 0; 1675 } else 1676 led[i] = 0; /* led off */ 1677 } 1678 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 1679 leds = 0; 1680 for (i = 0; i < 4; i++) { 1681 if (led[i] == 1) { 1682 /*green*/ 1683 leds |= (0x2 << (i * 2)); 1684 } else if (led[i] == 2) { 1685 /*red*/ 1686 leds |= (0x1 << (i * 2)); 1687 } 1688 } 1689 if (leds != (int)hc->ledstate) { 1690 vpm_out(hc, 0, 0x1a8 + 3, leds); 1691 hc->ledstate = leds; 1692 } 1693 } else { 1694 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) | 1695 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) | 1696 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) | 1697 ((led[0] & 1) << 6) | ((led[2] & 1) << 7); 1698 if (leds != (int)hc->ledstate) { 1699 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F); 1700 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4); 1701 hc->ledstate = leds; 1702 } 1703 } 1704 break; 1705 1706 case 3: /* HFC 1S/2S Beronet */ 1707 /* red blinking = PH_DEACTIVATE NT Mode 1708 * red steady = PH_DEACTIVATE TE Mode 1709 * green steady = PH_ACTIVATE 1710 */ 1711 for (i = 0; i < 2; i++) { 1712 state = 0; 1713 active = -1; 1714 dch = hc->chan[(i << 2) | 2].dch; 1715 if (dch) { 1716 state = dch->state; 1717 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1718 active = 3; 1719 else 1720 active = 7; 1721 } 1722 if (state) { 1723 if (state == active) { 1724 led[i] = 1; /* led green */ 1725 } else 1726 if (dch->dev.D.protocol == ISDN_P_TE_S0) 1727 /* TE mode: led red */ 1728 led[i] = 2; 1729 else 1730 if (hc->ledcount >> 11) 1731 /* led red */ 1732 led[i] = 2; 1733 else 1734 /* led off */ 1735 led[i] = 0; 1736 } else 1737 led[i] = 0; /* led off */ 1738 } 1739 1740 1741 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2) 1742 | ((led[1]&1)<<3); 1743 if (leds != (int)hc->ledstate) { 1744 HFC_outb_nodebug(hc, R_GPIO_EN1, 1745 ((led[0] > 0) << 2) | ((led[1] > 0) << 3)); 1746 HFC_outb_nodebug(hc, R_GPIO_OUT1, 1747 ((led[0] & 1) << 2) | ((led[1] & 1) << 3)); 1748 hc->ledstate = leds; 1749 } 1750 break; 1751 case 8: /* HFC 8S+ Beronet */ 1752 lled = 0; 1753 1754 for (i = 0; i < 8; i++) { 1755 state = 0; 1756 active = -1; 1757 dch = hc->chan[(i << 2) | 2].dch; 1758 if (dch) { 1759 state = dch->state; 1760 if (dch->dev.D.protocol == ISDN_P_NT_S0) 1761 active = 3; 1762 else 1763 active = 7; 1764 } 1765 if (state) { 1766 if (state == active) { 1767 lled |= 0 << i; 1768 } else 1769 if (hc->ledcount >> 11) 1770 lled |= 0 << i; 1771 else 1772 lled |= 1 << i; 1773 } else 1774 lled |= 1 << i; 1775 } 1776 leddw = lled << 24 | lled << 16 | lled << 8 | lled; 1777 if (leddw != hc->ledstate) { 1778 /* HFC_outb(hc, R_BRG_PCM_CFG, 1); 1779 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */ 1780 /* was _io before */ 1781 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); 1782 outw(0x4000, hc->pci_iobase + 4); 1783 outl(leddw, hc->pci_iobase); 1784 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK); 1785 hc->ledstate = leddw; 1786 } 1787 break; 1788 } 1789} 1790/* 1791 * read dtmf coefficients 1792 */ 1793 1794static void 1795hfcmulti_dtmf(struct hfc_multi *hc) 1796{ 1797 s32 *coeff; 1798 u_int mantissa; 1799 int co, ch; 1800 struct bchannel *bch = NULL; 1801 u8 exponent; 1802 int dtmf = 0; 1803 int addr; 1804 u16 w_float; 1805 struct sk_buff *skb; 1806 struct mISDNhead *hh; 1807 1808 if (debug & DEBUG_HFCMULTI_DTMF) 1809 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__); 1810 for (ch = 0; ch <= 31; ch++) { 1811 /* only process enabled B-channels */ 1812 bch = hc->chan[ch].bch; 1813 if (!bch) 1814 continue; 1815 if (!hc->created[hc->chan[ch].port]) 1816 continue; 1817 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) 1818 continue; 1819 if (debug & DEBUG_HFCMULTI_DTMF) 1820 printk(KERN_DEBUG "%s: dtmf channel %d:", 1821 __func__, ch); 1822 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]); 1823 dtmf = 1; 1824 for (co = 0; co < 8; co++) { 1825 /* read W(n-1) coefficient */ 1826 addr = hc->DTMFbase + ((co<<7) | (ch<<2)); 1827 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr); 1828 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8); 1829 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16) 1830 | V_ADDR_INC); 1831 w_float = HFC_inb_nodebug(hc, R_RAM_DATA); 1832 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); 1833 if (debug & DEBUG_HFCMULTI_DTMF) 1834 printk(" %04x", w_float); 1835 1836 /* decode float (see chip doc) */ 1837 mantissa = w_float & 0x0fff; 1838 if (w_float & 0x8000) 1839 mantissa |= 0xfffff000; 1840 exponent = (w_float>>12) & 0x7; 1841 if (exponent) { 1842 mantissa ^= 0x1000; 1843 mantissa <<= (exponent-1); 1844 } 1845 1846 /* store coefficient */ 1847 coeff[co<<1] = mantissa; 1848 1849 /* read W(n) coefficient */ 1850 w_float = HFC_inb_nodebug(hc, R_RAM_DATA); 1851 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); 1852 if (debug & DEBUG_HFCMULTI_DTMF) 1853 printk(" %04x", w_float); 1854 1855 /* decode float (see chip doc) */ 1856 mantissa = w_float & 0x0fff; 1857 if (w_float & 0x8000) 1858 mantissa |= 0xfffff000; 1859 exponent = (w_float>>12) & 0x7; 1860 if (exponent) { 1861 mantissa ^= 0x1000; 1862 mantissa <<= (exponent-1); 1863 } 1864 1865 /* store coefficient */ 1866 coeff[(co<<1)|1] = mantissa; 1867 } 1868 if (debug & DEBUG_HFCMULTI_DTMF) 1869 printk(" DTMF ready %08x %08x %08x %08x " 1870 "%08x %08x %08x %08x\n", 1871 coeff[0], coeff[1], coeff[2], coeff[3], 1872 coeff[4], coeff[5], coeff[6], coeff[7]); 1873 hc->chan[ch].coeff_count++; 1874 if (hc->chan[ch].coeff_count == 8) { 1875 hc->chan[ch].coeff_count = 0; 1876 skb = mI_alloc_skb(512, GFP_ATOMIC); 1877 if (!skb) { 1878 printk(KERN_DEBUG "%s: No memory for skb\n", 1879 __func__); 1880 continue; 1881 } 1882 hh = mISDN_HEAD_P(skb); 1883 hh->prim = PH_CONTROL_IND; 1884 hh->id = DTMF_HFC_COEF; 1885 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512); 1886 recv_Bchannel_skb(bch, skb); 1887 } 1888 } 1889 1890 /* restart DTMF processing */ 1891 hc->dtmf = dtmf; 1892 if (dtmf) 1893 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF); 1894} 1895 1896 1897/* 1898 * fill fifo as much as possible 1899 */ 1900 1901static void 1902hfcmulti_tx(struct hfc_multi *hc, int ch) 1903{ 1904 int i, ii, temp, len = 0; 1905 int Zspace, z1, z2; /* must be int for calculation */ 1906 int Fspace, f1, f2; 1907 u_char *d; 1908 int *txpending, slot_tx; 1909 struct bchannel *bch; 1910 struct dchannel *dch; 1911 struct sk_buff **sp = NULL; 1912 int *idxp; 1913 1914 bch = hc->chan[ch].bch; 1915 dch = hc->chan[ch].dch; 1916 if ((!dch) && (!bch)) 1917 return; 1918 1919 txpending = &hc->chan[ch].txpending; 1920 slot_tx = hc->chan[ch].slot_tx; 1921 if (dch) { 1922 if (!test_bit(FLG_ACTIVE, &dch->Flags)) 1923 return; 1924 sp = &dch->tx_skb; 1925 idxp = &dch->tx_idx; 1926 } else { 1927 if (!test_bit(FLG_ACTIVE, &bch->Flags)) 1928 return; 1929 sp = &bch->tx_skb; 1930 idxp = &bch->tx_idx; 1931 } 1932 if (*sp) 1933 len = (*sp)->len; 1934 1935 if ((!len) && *txpending != 1) 1936 return; /* no data */ 1937 1938 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 1939 (hc->chan[ch].protocol == ISDN_P_B_RAW) && 1940 (hc->chan[ch].slot_rx < 0) && 1941 (hc->chan[ch].slot_tx < 0)) 1942 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1)); 1943 else 1944 HFC_outb_nodebug(hc, R_FIFO, ch << 1); 1945 HFC_wait_nodebug(hc); 1946 1947 if (*txpending == 2) { 1948 /* reset fifo */ 1949 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 1950 HFC_wait_nodebug(hc); 1951 HFC_outb(hc, A_SUBCH_CFG, 0); 1952 *txpending = 1; 1953 } 1954next_frame: 1955 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 1956 f1 = HFC_inb_nodebug(hc, A_F1); 1957 f2 = HFC_inb_nodebug(hc, A_F2); 1958 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) { 1959 if (debug & DEBUG_HFCMULTI_FIFO) 1960 printk(KERN_DEBUG 1961 "%s(card %d): reread f2 because %d!=%d\n", 1962 __func__, hc->id + 1, temp, f2); 1963 f2 = temp; /* repeat until F2 is equal */ 1964 } 1965 Fspace = f2 - f1 - 1; 1966 if (Fspace < 0) 1967 Fspace += hc->Flen; 1968 /* 1969 * Old FIFO handling doesn't give us the current Z2 read 1970 * pointer, so we cannot send the next frame before the fifo 1971 * is empty. It makes no difference except for a slightly 1972 * lower performance. 1973 */ 1974 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) { 1975 if (f1 != f2) 1976 Fspace = 0; 1977 else 1978 Fspace = 1; 1979 } 1980 /* one frame only for ST D-channels, to allow resending */ 1981 if (hc->ctype != HFC_TYPE_E1 && dch) { 1982 if (f1 != f2) 1983 Fspace = 0; 1984 } 1985 /* F-counter full condition */ 1986 if (Fspace == 0) 1987 return; 1988 } 1989 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; 1990 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; 1991 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) { 1992 if (debug & DEBUG_HFCMULTI_FIFO) 1993 printk(KERN_DEBUG "%s(card %d): reread z2 because " 1994 "%d!=%d\n", __func__, hc->id + 1, temp, z2); 1995 z2 = temp; /* repeat unti Z2 is equal */ 1996 } 1997 hc->chan[ch].Zfill = z1 - z2; 1998 if (hc->chan[ch].Zfill < 0) 1999 hc->chan[ch].Zfill += hc->Zlen; 2000 Zspace = z2 - z1; 2001 if (Zspace <= 0) 2002 Zspace += hc->Zlen; 2003 Zspace -= 4; /* keep not too full, so pointers will not overrun */ 2004 /* fill transparent data only to maxinum transparent load (minus 4) */ 2005 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2006 Zspace = Zspace - hc->Zlen + hc->max_trans; 2007 if (Zspace <= 0) /* no space of 4 bytes */ 2008 return; 2009 2010 /* if no data */ 2011 if (!len) { 2012 if (z1 == z2) { /* empty */ 2013 /* if done with FIFO audio data during PCM connection */ 2014 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && 2015 *txpending && slot_tx >= 0) { 2016 if (debug & DEBUG_HFCMULTI_MODE) 2017 printk(KERN_DEBUG 2018 "%s: reconnecting PCM due to no " 2019 "more FIFO data: channel %d " 2020 "slot_tx %d\n", 2021 __func__, ch, slot_tx); 2022 /* connect slot */ 2023 if (hc->ctype == HFC_TYPE_XHFC) 2024 HFC_outb(hc, A_CON_HDLC, 0xc0 2025 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2026 /* Enable FIFO, no interrupt */ 2027 else 2028 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | 2029 V_HDLC_TRP | V_IFF); 2030 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1); 2031 HFC_wait_nodebug(hc); 2032 if (hc->ctype == HFC_TYPE_XHFC) 2033 HFC_outb(hc, A_CON_HDLC, 0xc0 2034 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2035 /* Enable FIFO, no interrupt */ 2036 else 2037 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | 2038 V_HDLC_TRP | V_IFF); 2039 HFC_outb_nodebug(hc, R_FIFO, ch<<1); 2040 HFC_wait_nodebug(hc); 2041 } 2042 *txpending = 0; 2043 } 2044 return; /* no data */ 2045 } 2046 2047 /* "fill fifo if empty" feature */ 2048 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags) 2049 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) { 2050 if (debug & DEBUG_HFCMULTI_FILL) 2051 printk(KERN_DEBUG "%s: buffer empty, so we have " 2052 "underrun\n", __func__); 2053 /* fill buffer, to prevent future underrun */ 2054 hc->write_fifo(hc, hc->silence_data, poll >> 1); 2055 Zspace -= (poll >> 1); 2056 } 2057 2058 /* if audio data and connected slot */ 2059 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending) 2060 && slot_tx >= 0) { 2061 if (debug & DEBUG_HFCMULTI_MODE) 2062 printk(KERN_DEBUG "%s: disconnecting PCM due to " 2063 "FIFO data: channel %d slot_tx %d\n", 2064 __func__, ch, slot_tx); 2065 /* disconnect slot */ 2066 if (hc->ctype == HFC_TYPE_XHFC) 2067 HFC_outb(hc, A_CON_HDLC, 0x80 2068 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2069 /* Enable FIFO, no interrupt */ 2070 else 2071 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | 2072 V_HDLC_TRP | V_IFF); 2073 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1); 2074 HFC_wait_nodebug(hc); 2075 if (hc->ctype == HFC_TYPE_XHFC) 2076 HFC_outb(hc, A_CON_HDLC, 0x80 2077 | 0x07 << 2 | V_HDLC_TRP | V_IFF); 2078 /* Enable FIFO, no interrupt */ 2079 else 2080 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | 2081 V_HDLC_TRP | V_IFF); 2082 HFC_outb_nodebug(hc, R_FIFO, ch<<1); 2083 HFC_wait_nodebug(hc); 2084 } 2085 *txpending = 1; 2086 2087 /* show activity */ 2088 hc->activity[hc->chan[ch].port] = 1; 2089 2090 /* fill fifo to what we have left */ 2091 ii = len; 2092 if (dch || test_bit(FLG_HDLC, &bch->Flags)) 2093 temp = 1; 2094 else 2095 temp = 0; 2096 i = *idxp; 2097 d = (*sp)->data + i; 2098 if (ii - i > Zspace) 2099 ii = Zspace + i; 2100 if (debug & DEBUG_HFCMULTI_FIFO) 2101 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space " 2102 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n", 2103 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i, 2104 temp ? "HDLC" : "TRANS"); 2105 2106 /* Have to prep the audio data */ 2107 hc->write_fifo(hc, d, ii - i); 2108 hc->chan[ch].Zfill += ii - i; 2109 *idxp = ii; 2110 2111 /* if not all data has been written */ 2112 if (ii != len) { 2113 /* NOTE: fifo is started by the calling function */ 2114 return; 2115 } 2116 2117 /* if all data has been written, terminate frame */ 2118 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2119 /* increment f-counter */ 2120 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); 2121 HFC_wait_nodebug(hc); 2122 } 2123 2124 /* send confirm, since get_net_bframe will not do it with trans */ 2125 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2126 confirm_Bsend(bch); 2127 2128 /* check for next frame */ 2129 dev_kfree_skb(*sp); 2130 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */ 2131 len = (*sp)->len; 2132 goto next_frame; 2133 } 2134 if (dch && get_next_dframe(dch)) { 2135 len = (*sp)->len; 2136 goto next_frame; 2137 } 2138 2139 /* 2140 * now we have no more data, so in case of transparent, 2141 * we set the last byte in fifo to 'silence' in case we will get 2142 * no more data at all. this prevents sending an undefined value. 2143 */ 2144 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) 2145 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 2146} 2147 2148 2149/* NOTE: only called if E1 card is in active state */ 2150static void 2151hfcmulti_rx(struct hfc_multi *hc, int ch) 2152{ 2153 int temp; 2154 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */ 2155 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */ 2156 int again = 0; 2157 struct bchannel *bch; 2158 struct dchannel *dch; 2159 struct sk_buff *skb, **sp = NULL; 2160 int maxlen; 2161 2162 bch = hc->chan[ch].bch; 2163 dch = hc->chan[ch].dch; 2164 if ((!dch) && (!bch)) 2165 return; 2166 if (dch) { 2167 if (!test_bit(FLG_ACTIVE, &dch->Flags)) 2168 return; 2169 sp = &dch->rx_skb; 2170 maxlen = dch->maxlen; 2171 } else { 2172 if (!test_bit(FLG_ACTIVE, &bch->Flags)) 2173 return; 2174 sp = &bch->rx_skb; 2175 maxlen = bch->maxlen; 2176 } 2177next_frame: 2178 /* on first AND before getting next valid frame, R_FIFO must be written 2179 to. */ 2180 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 2181 (hc->chan[ch].protocol == ISDN_P_B_RAW) && 2182 (hc->chan[ch].slot_rx < 0) && 2183 (hc->chan[ch].slot_tx < 0)) 2184 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1); 2185 else 2186 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1); 2187 HFC_wait_nodebug(hc); 2188 2189 /* ignore if rx is off BUT change fifo (above) to start pending TX */ 2190 if (hc->chan[ch].rx_off) 2191 return; 2192 2193 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2194 f1 = HFC_inb_nodebug(hc, A_F1); 2195 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) { 2196 if (debug & DEBUG_HFCMULTI_FIFO) 2197 printk(KERN_DEBUG 2198 "%s(card %d): reread f1 because %d!=%d\n", 2199 __func__, hc->id + 1, temp, f1); 2200 f1 = temp; /* repeat until F1 is equal */ 2201 } 2202 f2 = HFC_inb_nodebug(hc, A_F2); 2203 } 2204 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; 2205 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) { 2206 if (debug & DEBUG_HFCMULTI_FIFO) 2207 printk(KERN_DEBUG "%s(card %d): reread z2 because " 2208 "%d!=%d\n", __func__, hc->id + 1, temp, z2); 2209 z1 = temp; /* repeat until Z1 is equal */ 2210 } 2211 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; 2212 Zsize = z1 - z2; 2213 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2) 2214 /* complete hdlc frame */ 2215 Zsize++; 2216 if (Zsize < 0) 2217 Zsize += hc->Zlen; 2218 /* if buffer is empty */ 2219 if (Zsize <= 0) 2220 return; 2221 2222 if (*sp == NULL) { 2223 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC); 2224 if (*sp == NULL) { 2225 printk(KERN_DEBUG "%s: No mem for rx_skb\n", 2226 __func__); 2227 return; 2228 } 2229 } 2230 /* show activity */ 2231 hc->activity[hc->chan[ch].port] = 1; 2232 2233 /* empty fifo with what we have */ 2234 if (dch || test_bit(FLG_HDLC, &bch->Flags)) { 2235 if (debug & DEBUG_HFCMULTI_FIFO) 2236 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d " 2237 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) " 2238 "got=%d (again %d)\n", __func__, hc->id + 1, ch, 2239 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE", 2240 f1, f2, Zsize + (*sp)->len, again); 2241 /* HDLC */ 2242 if ((Zsize + (*sp)->len) > (maxlen + 3)) { 2243 if (debug & DEBUG_HFCMULTI_FIFO) 2244 printk(KERN_DEBUG 2245 "%s(card %d): hdlc-frame too large.\n", 2246 __func__, hc->id + 1); 2247 skb_trim(*sp, 0); 2248 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 2249 HFC_wait_nodebug(hc); 2250 return; 2251 } 2252 2253 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); 2254 2255 if (f1 != f2) { 2256 /* increment Z2,F2-counter */ 2257 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); 2258 HFC_wait_nodebug(hc); 2259 /* check size */ 2260 if ((*sp)->len < 4) { 2261 if (debug & DEBUG_HFCMULTI_FIFO) 2262 printk(KERN_DEBUG 2263 "%s(card %d): Frame below minimum " 2264 "size\n", __func__, hc->id + 1); 2265 skb_trim(*sp, 0); 2266 goto next_frame; 2267 } 2268 /* there is at least one complete frame, check crc */ 2269 if ((*sp)->data[(*sp)->len - 1]) { 2270 if (debug & DEBUG_HFCMULTI_CRC) 2271 printk(KERN_DEBUG 2272 "%s: CRC-error\n", __func__); 2273 skb_trim(*sp, 0); 2274 goto next_frame; 2275 } 2276 skb_trim(*sp, (*sp)->len - 3); 2277 if ((*sp)->len < MISDN_COPY_SIZE) { 2278 skb = *sp; 2279 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); 2280 if (*sp) { 2281 memcpy(skb_put(*sp, skb->len), 2282 skb->data, skb->len); 2283 skb_trim(skb, 0); 2284 } else { 2285 printk(KERN_DEBUG "%s: No mem\n", 2286 __func__); 2287 *sp = skb; 2288 skb = NULL; 2289 } 2290 } else { 2291 skb = NULL; 2292 } 2293 if (debug & DEBUG_HFCMULTI_FIFO) { 2294 printk(KERN_DEBUG "%s(card %d):", 2295 __func__, hc->id + 1); 2296 temp = 0; 2297 while (temp < (*sp)->len) 2298 printk(" %02x", (*sp)->data[temp++]); 2299 printk("\n"); 2300 } 2301 if (dch) 2302 recv_Dchannel(dch); 2303 else 2304 recv_Bchannel(bch, MISDN_ID_ANY); 2305 *sp = skb; 2306 again++; 2307 goto next_frame; 2308 } 2309 /* there is an incomplete frame */ 2310 } else { 2311 /* transparent */ 2312 if (Zsize > skb_tailroom(*sp)) 2313 Zsize = skb_tailroom(*sp); 2314 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); 2315 if (((*sp)->len) < MISDN_COPY_SIZE) { 2316 skb = *sp; 2317 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); 2318 if (*sp) { 2319 memcpy(skb_put(*sp, skb->len), 2320 skb->data, skb->len); 2321 skb_trim(skb, 0); 2322 } else { 2323 printk(KERN_DEBUG "%s: No mem\n", __func__); 2324 *sp = skb; 2325 skb = NULL; 2326 } 2327 } else { 2328 skb = NULL; 2329 } 2330 if (debug & DEBUG_HFCMULTI_FIFO) 2331 printk(KERN_DEBUG 2332 "%s(card %d): fifo(%d) reading %d bytes " 2333 "(z1=%04x, z2=%04x) TRANS\n", 2334 __func__, hc->id + 1, ch, Zsize, z1, z2); 2335 /* only bch is transparent */ 2336 recv_Bchannel(bch, hc->chan[ch].Zfill); 2337 *sp = skb; 2338 } 2339} 2340 2341 2342/* 2343 * Interrupt handler 2344 */ 2345static void 2346signal_state_up(struct dchannel *dch, int info, char *msg) 2347{ 2348 struct sk_buff *skb; 2349 int id, data = info; 2350 2351 if (debug & DEBUG_HFCMULTI_STATE) 2352 printk(KERN_DEBUG "%s: %s\n", __func__, msg); 2353 2354 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */ 2355 2356 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data, 2357 GFP_ATOMIC); 2358 if (!skb) 2359 return; 2360 recv_Dchannel_skb(dch, skb); 2361} 2362 2363static inline void 2364handle_timer_irq(struct hfc_multi *hc) 2365{ 2366 int ch, temp; 2367 struct dchannel *dch; 2368 u_long flags; 2369 2370 /* process queued resync jobs */ 2371 if (hc->e1_resync) { 2372 /* lock, so e1_resync gets not changed */ 2373 spin_lock_irqsave(&HFClock, flags); 2374 if (hc->e1_resync & 1) { 2375 if (debug & DEBUG_HFCMULTI_PLXSD) 2376 printk(KERN_DEBUG "Enable SYNC_I\n"); 2377 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC); 2378 /* disable JATT, if RX_SYNC is set */ 2379 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) 2380 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); 2381 } 2382 if (hc->e1_resync & 2) { 2383 if (debug & DEBUG_HFCMULTI_PLXSD) 2384 printk(KERN_DEBUG "Enable jatt PLL\n"); 2385 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); 2386 } 2387 if (hc->e1_resync & 4) { 2388 if (debug & DEBUG_HFCMULTI_PLXSD) 2389 printk(KERN_DEBUG 2390 "Enable QUARTZ for HFC-E1\n"); 2391 /* set jatt to quartz */ 2392 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC 2393 | V_JATT_OFF); 2394 /* switch to JATT, in case it is not already */ 2395 HFC_outb(hc, R_SYNC_OUT, 0); 2396 } 2397 hc->e1_resync = 0; 2398 spin_unlock_irqrestore(&HFClock, flags); 2399 } 2400 2401 if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1) 2402 for (ch = 0; ch <= 31; ch++) { 2403 if (hc->created[hc->chan[ch].port]) { 2404 hfcmulti_tx(hc, ch); 2405 /* fifo is started when switching to rx-fifo */ 2406 hfcmulti_rx(hc, ch); 2407 if (hc->chan[ch].dch && 2408 hc->chan[ch].nt_timer > -1) { 2409 dch = hc->chan[ch].dch; 2410 if (!(--hc->chan[ch].nt_timer)) { 2411 schedule_event(dch, 2412 FLG_PHCHANGE); 2413 if (debug & 2414 DEBUG_HFCMULTI_STATE) 2415 printk(KERN_DEBUG 2416 "%s: nt_timer at " 2417 "state %x\n", 2418 __func__, 2419 dch->state); 2420 } 2421 } 2422 } 2423 } 2424 if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) { 2425 dch = hc->chan[hc->dslot].dch; 2426 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) { 2427 /* LOS */ 2428 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS; 2429 if (!temp && hc->chan[hc->dslot].los) 2430 signal_state_up(dch, L1_SIGNAL_LOS_ON, 2431 "LOS detected"); 2432 if (temp && !hc->chan[hc->dslot].los) 2433 signal_state_up(dch, L1_SIGNAL_LOS_OFF, 2434 "LOS gone"); 2435 hc->chan[hc->dslot].los = temp; 2436 } 2437 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) { 2438 /* AIS */ 2439 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS; 2440 if (!temp && hc->chan[hc->dslot].ais) 2441 signal_state_up(dch, L1_SIGNAL_AIS_ON, 2442 "AIS detected"); 2443 if (temp && !hc->chan[hc->dslot].ais) 2444 signal_state_up(dch, L1_SIGNAL_AIS_OFF, 2445 "AIS gone"); 2446 hc->chan[hc->dslot].ais = temp; 2447 } 2448 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) { 2449 /* SLIP */ 2450 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX; 2451 if (!temp && hc->chan[hc->dslot].slip_rx) 2452 signal_state_up(dch, L1_SIGNAL_SLIP_RX, 2453 " bit SLIP detected RX"); 2454 hc->chan[hc->dslot].slip_rx = temp; 2455 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX; 2456 if (!temp && hc->chan[hc->dslot].slip_tx) 2457 signal_state_up(dch, L1_SIGNAL_SLIP_TX, 2458 " bit SLIP detected TX"); 2459 hc->chan[hc->dslot].slip_tx = temp; 2460 } 2461 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) { 2462 /* RDI */ 2463 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A; 2464 if (!temp && hc->chan[hc->dslot].rdi) 2465 signal_state_up(dch, L1_SIGNAL_RDI_ON, 2466 "RDI detected"); 2467 if (temp && !hc->chan[hc->dslot].rdi) 2468 signal_state_up(dch, L1_SIGNAL_RDI_OFF, 2469 "RDI gone"); 2470 hc->chan[hc->dslot].rdi = temp; 2471 } 2472 temp = HFC_inb_nodebug(hc, R_JATT_DIR); 2473 switch (hc->chan[hc->dslot].sync) { 2474 case 0: 2475 if ((temp & 0x60) == 0x60) { 2476 if (debug & DEBUG_HFCMULTI_SYNC) 2477 printk(KERN_DEBUG 2478 "%s: (id=%d) E1 now " 2479 "in clock sync\n", 2480 __func__, hc->id); 2481 HFC_outb(hc, R_RX_OFF, 2482 hc->chan[hc->dslot].jitter | V_RX_INIT); 2483 HFC_outb(hc, R_TX_OFF, 2484 hc->chan[hc->dslot].jitter | V_RX_INIT); 2485 hc->chan[hc->dslot].sync = 1; 2486 goto check_framesync; 2487 } 2488 break; 2489 case 1: 2490 if ((temp & 0x60) != 0x60) { 2491 if (debug & DEBUG_HFCMULTI_SYNC) 2492 printk(KERN_DEBUG 2493 "%s: (id=%d) E1 " 2494 "lost clock sync\n", 2495 __func__, hc->id); 2496 hc->chan[hc->dslot].sync = 0; 2497 break; 2498 } 2499check_framesync: 2500 temp = HFC_inb_nodebug(hc, R_SYNC_STA); 2501 if (temp == 0x27) { 2502 if (debug & DEBUG_HFCMULTI_SYNC) 2503 printk(KERN_DEBUG 2504 "%s: (id=%d) E1 " 2505 "now in frame sync\n", 2506 __func__, hc->id); 2507 hc->chan[hc->dslot].sync = 2; 2508 } 2509 break; 2510 case 2: 2511 if ((temp & 0x60) != 0x60) { 2512 if (debug & DEBUG_HFCMULTI_SYNC) 2513 printk(KERN_DEBUG 2514 "%s: (id=%d) E1 lost " 2515 "clock & frame sync\n", 2516 __func__, hc->id); 2517 hc->chan[hc->dslot].sync = 0; 2518 break; 2519 } 2520 temp = HFC_inb_nodebug(hc, R_SYNC_STA); 2521 if (temp != 0x27) { 2522 if (debug & DEBUG_HFCMULTI_SYNC) 2523 printk(KERN_DEBUG 2524 "%s: (id=%d) E1 " 2525 "lost frame sync\n", 2526 __func__, hc->id); 2527 hc->chan[hc->dslot].sync = 1; 2528 } 2529 break; 2530 } 2531 } 2532 2533 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) 2534 hfcmulti_watchdog(hc); 2535 2536 if (hc->leds) 2537 hfcmulti_leds(hc); 2538} 2539 2540static void 2541ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech) 2542{ 2543 struct dchannel *dch; 2544 int ch; 2545 int active; 2546 u_char st_status, temp; 2547 2548 /* state machine */ 2549 for (ch = 0; ch <= 31; ch++) { 2550 if (hc->chan[ch].dch) { 2551 dch = hc->chan[ch].dch; 2552 if (r_irq_statech & 1) { 2553 HFC_outb_nodebug(hc, R_ST_SEL, 2554 hc->chan[ch].port); 2555 /* undocumented: delay after R_ST_SEL */ 2556 udelay(1); 2557 /* undocumented: status changes during read */ 2558 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE); 2559 while (st_status != (temp = 2560 HFC_inb_nodebug(hc, A_ST_RD_STATE))) { 2561 if (debug & DEBUG_HFCMULTI_STATE) 2562 printk(KERN_DEBUG "%s: reread " 2563 "STATE because %d!=%d\n", 2564 __func__, temp, 2565 st_status); 2566 st_status = temp; /* repeat */ 2567 } 2568 2569 /* Speech Design TE-sync indication */ 2570 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && 2571 dch->dev.D.protocol == ISDN_P_TE_S0) { 2572 if (st_status & V_FR_SYNC_ST) 2573 hc->syncronized |= 2574 (1 << hc->chan[ch].port); 2575 else 2576 hc->syncronized &= 2577 ~(1 << hc->chan[ch].port); 2578 } 2579 dch->state = st_status & 0x0f; 2580 if (dch->dev.D.protocol == ISDN_P_NT_S0) 2581 active = 3; 2582 else 2583 active = 7; 2584 if (dch->state == active) { 2585 HFC_outb_nodebug(hc, R_FIFO, 2586 (ch << 1) | 1); 2587 HFC_wait_nodebug(hc); 2588 HFC_outb_nodebug(hc, 2589 R_INC_RES_FIFO, V_RES_F); 2590 HFC_wait_nodebug(hc); 2591 dch->tx_idx = 0; 2592 } 2593 schedule_event(dch, FLG_PHCHANGE); 2594 if (debug & DEBUG_HFCMULTI_STATE) 2595 printk(KERN_DEBUG 2596 "%s: S/T newstate %x port %d\n", 2597 __func__, dch->state, 2598 hc->chan[ch].port); 2599 } 2600 r_irq_statech >>= 1; 2601 } 2602 } 2603 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 2604 plxsd_checksync(hc, 0); 2605} 2606 2607static void 2608fifo_irq(struct hfc_multi *hc, int block) 2609{ 2610 int ch, j; 2611 struct dchannel *dch; 2612 struct bchannel *bch; 2613 u_char r_irq_fifo_bl; 2614 2615 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block); 2616 j = 0; 2617 while (j < 8) { 2618 ch = (block << 2) + (j >> 1); 2619 dch = hc->chan[ch].dch; 2620 bch = hc->chan[ch].bch; 2621 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) { 2622 j += 2; 2623 continue; 2624 } 2625 if (dch && (r_irq_fifo_bl & (1 << j)) && 2626 test_bit(FLG_ACTIVE, &dch->Flags)) { 2627 hfcmulti_tx(hc, ch); 2628 /* start fifo */ 2629 HFC_outb_nodebug(hc, R_FIFO, 0); 2630 HFC_wait_nodebug(hc); 2631 } 2632 if (bch && (r_irq_fifo_bl & (1 << j)) && 2633 test_bit(FLG_ACTIVE, &bch->Flags)) { 2634 hfcmulti_tx(hc, ch); 2635 /* start fifo */ 2636 HFC_outb_nodebug(hc, R_FIFO, 0); 2637 HFC_wait_nodebug(hc); 2638 } 2639 j++; 2640 if (dch && (r_irq_fifo_bl & (1 << j)) && 2641 test_bit(FLG_ACTIVE, &dch->Flags)) { 2642 hfcmulti_rx(hc, ch); 2643 } 2644 if (bch && (r_irq_fifo_bl & (1 << j)) && 2645 test_bit(FLG_ACTIVE, &bch->Flags)) { 2646 hfcmulti_rx(hc, ch); 2647 } 2648 j++; 2649 } 2650} 2651 2652#ifdef IRQ_DEBUG 2653int irqsem; 2654#endif 2655static irqreturn_t 2656hfcmulti_interrupt(int intno, void *dev_id) 2657{ 2658#ifdef IRQCOUNT_DEBUG 2659 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0, 2660 iq5 = 0, iq6 = 0, iqcnt = 0; 2661#endif 2662 struct hfc_multi *hc = dev_id; 2663 struct dchannel *dch; 2664 u_char r_irq_statech, status, r_irq_misc, r_irq_oview; 2665 int i; 2666 void __iomem *plx_acc; 2667 u_short wval; 2668 u_char e1_syncsta, temp; 2669 u_long flags; 2670 2671 if (!hc) { 2672 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n"); 2673 return IRQ_NONE; 2674 } 2675 2676 spin_lock(&hc->lock); 2677 2678#ifdef IRQ_DEBUG 2679 if (irqsem) 2680 printk(KERN_ERR "irq for card %d during irq from " 2681 "card %d, this is no bug.\n", hc->id + 1, irqsem); 2682 irqsem = hc->id + 1; 2683#endif 2684#ifdef CONFIG_MISDN_HFCMULTI_8xx 2685 if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk) 2686 goto irq_notforus; 2687#endif 2688 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 2689 spin_lock_irqsave(&plx_lock, flags); 2690 plx_acc = hc->plx_membase + PLX_INTCSR; 2691 wval = readw(plx_acc); 2692 spin_unlock_irqrestore(&plx_lock, flags); 2693 if (!(wval & PLX_INTCSR_LINTI1_STATUS)) 2694 goto irq_notforus; 2695 } 2696 2697 status = HFC_inb_nodebug(hc, R_STATUS); 2698 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH); 2699#ifdef IRQCOUNT_DEBUG 2700 if (r_irq_statech) 2701 iq1++; 2702 if (status & V_DTMF_STA) 2703 iq2++; 2704 if (status & V_LOST_STA) 2705 iq3++; 2706 if (status & V_EXT_IRQSTA) 2707 iq4++; 2708 if (status & V_MISC_IRQSTA) 2709 iq5++; 2710 if (status & V_FR_IRQSTA) 2711 iq6++; 2712 if (iqcnt++ > 5000) { 2713 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n", 2714 iq1, iq2, iq3, iq4, iq5, iq6); 2715 iqcnt = 0; 2716 } 2717#endif 2718 2719 if (!r_irq_statech && 2720 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA | 2721 V_MISC_IRQSTA | V_FR_IRQSTA))) { 2722 /* irq is not for us */ 2723 goto irq_notforus; 2724 } 2725 hc->irqcnt++; 2726 if (r_irq_statech) { 2727 if (hc->ctype != HFC_TYPE_E1) 2728 ph_state_irq(hc, r_irq_statech); 2729 } 2730 if (status & V_EXT_IRQSTA) 2731 ; /* external IRQ */ 2732 if (status & V_LOST_STA) { 2733 /* LOST IRQ */ 2734 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */ 2735 } 2736 if (status & V_MISC_IRQSTA) { 2737 /* misc IRQ */ 2738 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC); 2739 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */ 2740 if (r_irq_misc & V_STA_IRQ) { 2741 if (hc->ctype == HFC_TYPE_E1) { 2742 /* state machine */ 2743 dch = hc->chan[hc->dslot].dch; 2744 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA); 2745 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) 2746 && hc->e1_getclock) { 2747 if (e1_syncsta & V_FR_SYNC_E1) 2748 hc->syncronized = 1; 2749 else 2750 hc->syncronized = 0; 2751 } 2752 /* undocumented: status changes during read */ 2753 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA); 2754 while (dch->state != (temp = 2755 HFC_inb_nodebug(hc, R_E1_RD_STA))) { 2756 if (debug & DEBUG_HFCMULTI_STATE) 2757 printk(KERN_DEBUG "%s: reread " 2758 "STATE because %d!=%d\n", 2759 __func__, temp, 2760 dch->state); 2761 dch->state = temp; /* repeat */ 2762 } 2763 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA) 2764 & 0x7; 2765 schedule_event(dch, FLG_PHCHANGE); 2766 if (debug & DEBUG_HFCMULTI_STATE) 2767 printk(KERN_DEBUG 2768 "%s: E1 (id=%d) newstate %x\n", 2769 __func__, hc->id, dch->state); 2770 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) 2771 plxsd_checksync(hc, 0); 2772 } 2773 } 2774 if (r_irq_misc & V_TI_IRQ) { 2775 if (hc->iclock_on) 2776 mISDN_clock_update(hc->iclock, poll, NULL); 2777 handle_timer_irq(hc); 2778 } 2779 2780 if (r_irq_misc & V_DTMF_IRQ) 2781 hfcmulti_dtmf(hc); 2782 2783 if (r_irq_misc & V_IRQ_PROC) { 2784 static int irq_proc_cnt; 2785 if (!irq_proc_cnt++) 2786 printk(KERN_DEBUG "%s: got V_IRQ_PROC -" 2787 " this should not happen\n", __func__); 2788 } 2789 2790 } 2791 if (status & V_FR_IRQSTA) { 2792 /* FIFO IRQ */ 2793 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW); 2794 for (i = 0; i < 8; i++) { 2795 if (r_irq_oview & (1 << i)) 2796 fifo_irq(hc, i); 2797 } 2798 } 2799 2800#ifdef IRQ_DEBUG 2801 irqsem = 0; 2802#endif 2803 spin_unlock(&hc->lock); 2804 return IRQ_HANDLED; 2805 2806irq_notforus: 2807#ifdef IRQ_DEBUG 2808 irqsem = 0; 2809#endif 2810 spin_unlock(&hc->lock); 2811 return IRQ_NONE; 2812} 2813 2814 2815/* 2816 * timer callback for D-chan busy resolution. Currently no function 2817 */ 2818 2819static void 2820hfcmulti_dbusy_timer(struct hfc_multi *hc) 2821{ 2822} 2823 2824 2825/* 2826 * activate/deactivate hardware for selected channels and mode 2827 * 2828 * configure B-channel with the given protocol 2829 * ch eqals to the HFC-channel (0-31) 2830 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31 2831 * for S/T, 1-31 for E1) 2832 * the hdlc interrupts will be set/unset 2833 */ 2834static int 2835mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx, 2836 int bank_tx, int slot_rx, int bank_rx) 2837{ 2838 int flow_tx = 0, flow_rx = 0, routing = 0; 2839 int oslot_tx, oslot_rx; 2840 int conf; 2841 2842 if (ch < 0 || ch > 31) 2843 return -EINVAL; 2844 oslot_tx = hc->chan[ch].slot_tx; 2845 oslot_rx = hc->chan[ch].slot_rx; 2846 conf = hc->chan[ch].conf; 2847 2848 if (debug & DEBUG_HFCMULTI_MODE) 2849 printk(KERN_DEBUG 2850 "%s: card %d channel %d protocol %x slot old=%d new=%d " 2851 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n", 2852 __func__, hc->id, ch, protocol, oslot_tx, slot_tx, 2853 bank_tx, oslot_rx, slot_rx, bank_rx); 2854 2855 if (oslot_tx >= 0 && slot_tx != oslot_tx) { 2856 /* remove from slot */ 2857 if (debug & DEBUG_HFCMULTI_MODE) 2858 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n", 2859 __func__, oslot_tx); 2860 if (hc->slot_owner[oslot_tx<<1] == ch) { 2861 HFC_outb(hc, R_SLOT, oslot_tx << 1); 2862 HFC_outb(hc, A_SL_CFG, 0); 2863 if (hc->ctype != HFC_TYPE_XHFC) 2864 HFC_outb(hc, A_CONF, 0); 2865 hc->slot_owner[oslot_tx<<1] = -1; 2866 } else { 2867 if (debug & DEBUG_HFCMULTI_MODE) 2868 printk(KERN_DEBUG 2869 "%s: we are not owner of this tx slot " 2870 "anymore, channel %d is.\n", 2871 __func__, hc->slot_owner[oslot_tx<<1]); 2872 } 2873 } 2874 2875 if (oslot_rx >= 0 && slot_rx != oslot_rx) { 2876 /* remove from slot */ 2877 if (debug & DEBUG_HFCMULTI_MODE) 2878 printk(KERN_DEBUG 2879 "%s: remove from slot %d (RX)\n", 2880 __func__, oslot_rx); 2881 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) { 2882 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR); 2883 HFC_outb(hc, A_SL_CFG, 0); 2884 hc->slot_owner[(oslot_rx << 1) | 1] = -1; 2885 } else { 2886 if (debug & DEBUG_HFCMULTI_MODE) 2887 printk(KERN_DEBUG 2888 "%s: we are not owner of this rx slot " 2889 "anymore, channel %d is.\n", 2890 __func__, 2891 hc->slot_owner[(oslot_rx << 1) | 1]); 2892 } 2893 } 2894 2895 if (slot_tx < 0) { 2896 flow_tx = 0x80; /* FIFO->ST */ 2897 /* disable pcm slot */ 2898 hc->chan[ch].slot_tx = -1; 2899 hc->chan[ch].bank_tx = 0; 2900 } else { 2901 /* set pcm slot */ 2902 if (hc->chan[ch].txpending) 2903 flow_tx = 0x80; /* FIFO->ST */ 2904 else 2905 flow_tx = 0xc0; /* PCM->ST */ 2906 /* put on slot */ 2907 routing = bank_tx ? 0xc0 : 0x80; 2908 if (conf >= 0 || bank_tx > 1) 2909 routing = 0x40; /* loop */ 2910 if (debug & DEBUG_HFCMULTI_MODE) 2911 printk(KERN_DEBUG "%s: put channel %d to slot %d bank" 2912 " %d flow %02x routing %02x conf %d (TX)\n", 2913 __func__, ch, slot_tx, bank_tx, 2914 flow_tx, routing, conf); 2915 HFC_outb(hc, R_SLOT, slot_tx << 1); 2916 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing); 2917 if (hc->ctype != HFC_TYPE_XHFC) 2918 HFC_outb(hc, A_CONF, 2919 (conf < 0) ? 0 : (conf | V_CONF_SL)); 2920 hc->slot_owner[slot_tx << 1] = ch; 2921 hc->chan[ch].slot_tx = slot_tx; 2922 hc->chan[ch].bank_tx = bank_tx; 2923 } 2924 if (slot_rx < 0) { 2925 /* disable pcm slot */ 2926 flow_rx = 0x80; /* ST->FIFO */ 2927 hc->chan[ch].slot_rx = -1; 2928 hc->chan[ch].bank_rx = 0; 2929 } else { 2930 /* set pcm slot */ 2931 if (hc->chan[ch].txpending) 2932 flow_rx = 0x80; /* ST->FIFO */ 2933 else 2934 flow_rx = 0xc0; /* ST->(FIFO,PCM) */ 2935 /* put on slot */ 2936 routing = bank_rx ? 0x80 : 0xc0; /* reversed */ 2937 if (conf >= 0 || bank_rx > 1) 2938 routing = 0x40; /* loop */ 2939 if (debug & DEBUG_HFCMULTI_MODE) 2940 printk(KERN_DEBUG "%s: put channel %d to slot %d bank" 2941 " %d flow %02x routing %02x conf %d (RX)\n", 2942 __func__, ch, slot_rx, bank_rx, 2943 flow_rx, routing, conf); 2944 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR); 2945 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing); 2946 hc->slot_owner[(slot_rx<<1)|1] = ch; 2947 hc->chan[ch].slot_rx = slot_rx; 2948 hc->chan[ch].bank_rx = bank_rx; 2949 } 2950 2951 switch (protocol) { 2952 case (ISDN_P_NONE): 2953 /* disable TX fifo */ 2954 HFC_outb(hc, R_FIFO, ch << 1); 2955 HFC_wait(hc); 2956 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF); 2957 HFC_outb(hc, A_SUBCH_CFG, 0); 2958 HFC_outb(hc, A_IRQ_MSK, 0); 2959 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 2960 HFC_wait(hc); 2961 /* disable RX fifo */ 2962 HFC_outb(hc, R_FIFO, (ch<<1)|1); 2963 HFC_wait(hc); 2964 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00); 2965 HFC_outb(hc, A_SUBCH_CFG, 0); 2966 HFC_outb(hc, A_IRQ_MSK, 0); 2967 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 2968 HFC_wait(hc); 2969 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) { 2970 hc->hw.a_st_ctrl0[hc->chan[ch].port] &= 2971 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN; 2972 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 2973 /* undocumented: delay after R_ST_SEL */ 2974 udelay(1); 2975 HFC_outb(hc, A_ST_CTRL0, 2976 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 2977 } 2978 if (hc->chan[ch].bch) { 2979 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); 2980 test_and_clear_bit(FLG_TRANSPARENT, 2981 &hc->chan[ch].bch->Flags); 2982 } 2983 break; 2984 case (ISDN_P_B_RAW): /* B-channel */ 2985 2986 if (test_bit(HFC_CHIP_B410P, &hc->chip) && 2987 (hc->chan[ch].slot_rx < 0) && 2988 (hc->chan[ch].slot_tx < 0)) { 2989 2990 printk(KERN_DEBUG 2991 "Setting B-channel %d to echo cancelable " 2992 "state on PCM slot %d\n", ch, 2993 ((ch / 4) * 8) + ((ch % 4) * 4) + 1); 2994 printk(KERN_DEBUG 2995 "Enabling pass through for channel\n"); 2996 vpm_out(hc, ch, ((ch / 4) * 8) + 2997 ((ch % 4) * 4) + 1, 0x01); 2998 /* rx path */ 2999 /* S/T -> PCM */ 3000 HFC_outb(hc, R_FIFO, (ch << 1)); 3001 HFC_wait(hc); 3002 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); 3003 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + 3004 ((ch % 4) * 4) + 1) << 1); 3005 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1)); 3006 3007 /* PCM -> FIFO */ 3008 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1); 3009 HFC_wait(hc); 3010 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); 3011 HFC_outb(hc, A_SUBCH_CFG, 0); 3012 HFC_outb(hc, A_IRQ_MSK, 0); 3013 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3014 HFC_wait(hc); 3015 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + 3016 ((ch % 4) * 4) + 1) << 1) | 1); 3017 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1); 3018 3019 /* tx path */ 3020 /* PCM -> S/T */ 3021 HFC_outb(hc, R_FIFO, (ch << 1) | 1); 3022 HFC_wait(hc); 3023 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); 3024 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + 3025 ((ch % 4) * 4)) << 1) | 1); 3026 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1); 3027 3028 /* FIFO -> PCM */ 3029 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1)); 3030 HFC_wait(hc); 3031 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); 3032 HFC_outb(hc, A_SUBCH_CFG, 0); 3033 HFC_outb(hc, A_IRQ_MSK, 0); 3034 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3035 HFC_wait(hc); 3036 /* tx silence */ 3037 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 3038 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + 3039 ((ch % 4) * 4)) << 1); 3040 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1)); 3041 } else { 3042 /* enable TX fifo */ 3043 HFC_outb(hc, R_FIFO, ch << 1); 3044 HFC_wait(hc); 3045 if (hc->ctype == HFC_TYPE_XHFC) 3046 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 | 3047 V_HDLC_TRP | V_IFF); 3048 /* Enable FIFO, no interrupt */ 3049 else 3050 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | 3051 V_HDLC_TRP | V_IFF); 3052 HFC_outb(hc, A_SUBCH_CFG, 0); 3053 HFC_outb(hc, A_IRQ_MSK, 0); 3054 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3055 HFC_wait(hc); 3056 /* tx silence */ 3057 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); 3058 /* enable RX fifo */ 3059 HFC_outb(hc, R_FIFO, (ch<<1)|1); 3060 HFC_wait(hc); 3061 if (hc->ctype == HFC_TYPE_XHFC) 3062 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 | 3063 V_HDLC_TRP); 3064 /* Enable FIFO, no interrupt*/ 3065 else 3066 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | 3067 V_HDLC_TRP); 3068 HFC_outb(hc, A_SUBCH_CFG, 0); 3069 HFC_outb(hc, A_IRQ_MSK, 0); 3070 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3071 HFC_wait(hc); 3072 } 3073 if (hc->ctype != HFC_TYPE_E1) { 3074 hc->hw.a_st_ctrl0[hc->chan[ch].port] |= 3075 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN; 3076 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3077 /* undocumented: delay after R_ST_SEL */ 3078 udelay(1); 3079 HFC_outb(hc, A_ST_CTRL0, 3080 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3081 } 3082 if (hc->chan[ch].bch) 3083 test_and_set_bit(FLG_TRANSPARENT, 3084 &hc->chan[ch].bch->Flags); 3085 break; 3086 case (ISDN_P_B_HDLC): /* B-channel */ 3087 case (ISDN_P_TE_S0): /* D-channel */ 3088 case (ISDN_P_NT_S0): 3089 case (ISDN_P_TE_E1): 3090 case (ISDN_P_NT_E1): 3091 /* enable TX fifo */ 3092 HFC_outb(hc, R_FIFO, ch<<1); 3093 HFC_wait(hc); 3094 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) { 3095 /* E1 or B-channel */ 3096 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04); 3097 HFC_outb(hc, A_SUBCH_CFG, 0); 3098 } else { 3099 /* D-Channel without HDLC fill flags */ 3100 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF); 3101 HFC_outb(hc, A_SUBCH_CFG, 2); 3102 } 3103 HFC_outb(hc, A_IRQ_MSK, V_IRQ); 3104 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3105 HFC_wait(hc); 3106 /* enable RX fifo */ 3107 HFC_outb(hc, R_FIFO, (ch<<1)|1); 3108 HFC_wait(hc); 3109 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04); 3110 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) 3111 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */ 3112 else 3113 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */ 3114 HFC_outb(hc, A_IRQ_MSK, V_IRQ); 3115 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); 3116 HFC_wait(hc); 3117 if (hc->chan[ch].bch) { 3118 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); 3119 if (hc->ctype != HFC_TYPE_E1) { 3120 hc->hw.a_st_ctrl0[hc->chan[ch].port] |= 3121 ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN; 3122 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); 3123 /* undocumented: delay after R_ST_SEL */ 3124 udelay(1); 3125 HFC_outb(hc, A_ST_CTRL0, 3126 hc->hw.a_st_ctrl0[hc->chan[ch].port]); 3127 } 3128 } 3129 break; 3130 default: 3131 printk(KERN_DEBUG "%s: protocol not known %x\n", 3132 __func__, protocol); 3133 hc->chan[ch].protocol = ISDN_P_NONE; 3134 return -ENOPROTOOPT; 3135 } 3136 hc->chan[ch].protocol = protocol; 3137 return 0; 3138} 3139 3140 3141/* 3142 * connect/disconnect PCM 3143 */ 3144 3145static void 3146hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx, 3147 int slot_rx, int bank_rx) 3148{ 3149 if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) { 3150 /* disable PCM */ 3151 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0); 3152 return; 3153 } 3154 3155 /* enable pcm */ 3156 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx, 3157 slot_rx, bank_rx); 3158} 3159 3160/* 3161 * set/disable conference 3162 */ 3163 3164static void 3165hfcmulti_conf(struct hfc_multi *hc, int ch, int num) 3166{ 3167 if (num >= 0 && num <= 7) 3168 hc->chan[ch].conf = num; 3169 else 3170 hc->chan[ch].conf = -1; 3171 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx, 3172 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx, 3173 hc->chan[ch].bank_rx); 3174} 3175 3176 3177/* 3178 * set/disable sample loop 3179 */ 3180 3181/* NOTE: this function is experimental and therefore disabled */ 3182 3183/* 3184 * Layer 1 callback function 3185 */ 3186static int 3187hfcm_l1callback(struct dchannel *dch, u_int cmd) 3188{ 3189 struct hfc_multi *hc = dch->hw; 3190 u_long flags; 3191 3192 switch (cmd) { 3193 case INFO3_P8: 3194 case INFO3_P10: 3195 break; 3196 case HW_RESET_REQ: 3197 /* start activation */ 3198 spin_lock_irqsave(&hc->lock, flags); 3199 if (hc->ctype == HFC_TYPE_E1) { 3200 if (debug & DEBUG_HFCMULTI_MSG) 3201 printk(KERN_DEBUG 3202 "%s: HW_RESET_REQ no BRI\n", 3203 __func__); 3204 } else { 3205 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3206 /* undocumented: delay after R_ST_SEL */ 3207 udelay(1); 3208 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */ 3209 udelay(6); /* wait at least 5,21us */ 3210 HFC_outb(hc, A_ST_WR_STATE, 3); 3211 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3)); 3212 /* activate */ 3213 } 3214 spin_unlock_irqrestore(&hc->lock, flags); 3215 l1_event(dch->l1, HW_POWERUP_IND); 3216 break; 3217 case HW_DEACT_REQ: 3218 /* start deactivation */ 3219 spin_lock_irqsave(&hc->lock, flags); 3220 if (hc->ctype == HFC_TYPE_E1) { 3221 if (debug & DEBUG_HFCMULTI_MSG) 3222 printk(KERN_DEBUG 3223 "%s: HW_DEACT_REQ no BRI\n", 3224 __func__); 3225 } else { 3226 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3227 /* undocumented: delay after R_ST_SEL */ 3228 udelay(1); 3229 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2); 3230 /* deactivate */ 3231 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 3232 hc->syncronized &= 3233 ~(1 << hc->chan[dch->slot].port); 3234 plxsd_checksync(hc, 0); 3235 } 3236 } 3237 skb_queue_purge(&dch->squeue); 3238 if (dch->tx_skb) { 3239 dev_kfree_skb(dch->tx_skb); 3240 dch->tx_skb = NULL; 3241 } 3242 dch->tx_idx = 0; 3243 if (dch->rx_skb) { 3244 dev_kfree_skb(dch->rx_skb); 3245 dch->rx_skb = NULL; 3246 } 3247 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 3248 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 3249 del_timer(&dch->timer); 3250 spin_unlock_irqrestore(&hc->lock, flags); 3251 break; 3252 case HW_POWERUP_REQ: 3253 spin_lock_irqsave(&hc->lock, flags); 3254 if (hc->ctype == HFC_TYPE_E1) { 3255 if (debug & DEBUG_HFCMULTI_MSG) 3256 printk(KERN_DEBUG 3257 "%s: HW_POWERUP_REQ no BRI\n", 3258 __func__); 3259 } else { 3260 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); 3261 /* undocumented: delay after R_ST_SEL */ 3262 udelay(1); 3263 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */ 3264 udelay(6); /* wait at least 5,21us */ 3265 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */ 3266 } 3267 spin_unlock_irqrestore(&hc->lock, flags); 3268 break; 3269 case PH_ACTIVATE_IND: 3270 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3271 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 3272 GFP_ATOMIC); 3273 break; 3274 case PH_DEACTIVATE_IND: 3275 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3276 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 3277 GFP_ATOMIC); 3278 break; 3279 default: 3280 if (dch->debug & DEBUG_HW) 3281 printk(KERN_DEBUG "%s: unknown command %x\n", 3282 __func__, cmd); 3283 return -1; 3284 } 3285 return 0; 3286} 3287 3288/* 3289 * Layer2 -> Layer 1 Transfer 3290 */ 3291 3292static int 3293handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb) 3294{ 3295 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 3296 struct dchannel *dch = container_of(dev, struct dchannel, dev); 3297 struct hfc_multi *hc = dch->hw; 3298 struct mISDNhead *hh = mISDN_HEAD_P(skb); 3299 int ret = -EINVAL; 3300 unsigned int id; 3301 u_long flags; 3302 3303 switch (hh->prim) { 3304 case PH_DATA_REQ: 3305 if (skb->len < 1) 3306 break; 3307 spin_lock_irqsave(&hc->lock, flags); 3308 ret = dchannel_senddata(dch, skb); 3309 if (ret > 0) { /* direct TX */ 3310 id = hh->id; /* skb can be freed */ 3311 hfcmulti_tx(hc, dch->slot); 3312 ret = 0; 3313 /* start fifo */ 3314 HFC_outb(hc, R_FIFO, 0); 3315 HFC_wait(hc); 3316 spin_unlock_irqrestore(&hc->lock, flags); 3317 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 3318 } else 3319 spin_unlock_irqrestore(&hc->lock, flags); 3320 return ret; 3321 case PH_ACTIVATE_REQ: 3322 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 3323 spin_lock_irqsave(&hc->lock, flags); 3324 ret = 0; 3325 if (debug & DEBUG_HFCMULTI_MSG) 3326 printk(KERN_DEBUG 3327 "%s: PH_ACTIVATE port %d (0..%d)\n", 3328 __func__, hc->chan[dch->slot].port, 3329 hc->ports-1); 3330 /* start activation */ 3331 if (hc->ctype == HFC_TYPE_E1) { 3332 ph_state_change(dch); 3333 if (debug & DEBUG_HFCMULTI_STATE) 3334 printk(KERN_DEBUG 3335 "%s: E1 report state %x \n", 3336 __func__, dch->state); 3337 } else { 3338 HFC_outb(hc, R_ST_SEL, 3339 hc->chan[dch->slot].port); 3340 /* undocumented: delay after R_ST_SEL */ 3341 udelay(1); 3342 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1); 3343 /* G1 */ 3344 udelay(6); /* wait at least 5,21us */ 3345 HFC_outb(hc, A_ST_WR_STATE, 1); 3346 HFC_outb(hc, A_ST_WR_STATE, 1 | 3347 (V_ST_ACT*3)); /* activate */ 3348 dch->state = 1; 3349 } 3350 spin_unlock_irqrestore(&hc->lock, flags); 3351 } else 3352 ret = l1_event(dch->l1, hh->prim); 3353 break; 3354 case PH_DEACTIVATE_REQ: 3355 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); 3356 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 3357 spin_lock_irqsave(&hc->lock, flags); 3358 if (debug & DEBUG_HFCMULTI_MSG) 3359 printk(KERN_DEBUG 3360 "%s: PH_DEACTIVATE port %d (0..%d)\n", 3361 __func__, hc->chan[dch->slot].port, 3362 hc->ports-1); 3363 /* start deactivation */ 3364 if (hc->ctype == HFC_TYPE_E1) { 3365 if (debug & DEBUG_HFCMULTI_MSG) 3366 printk(KERN_DEBUG 3367 "%s: PH_DEACTIVATE no BRI\n", 3368 __func__); 3369 } else { 3370 HFC_outb(hc, R_ST_SEL, 3371 hc->chan[dch->slot].port); 3372 /* undocumented: delay after R_ST_SEL */ 3373 udelay(1); 3374 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2); 3375 /* deactivate */ 3376 dch->state = 1; 3377 } 3378 skb_queue_purge(&dch->squeue); 3379 if (dch->tx_skb) { 3380 dev_kfree_skb(dch->tx_skb); 3381 dch->tx_skb = NULL; 3382 } 3383 dch->tx_idx = 0; 3384 if (dch->rx_skb) { 3385 dev_kfree_skb(dch->rx_skb); 3386 dch->rx_skb = NULL; 3387 } 3388 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 3389 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 3390 del_timer(&dch->timer); 3391#ifdef FIXME 3392 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags)) 3393 dchannel_sched_event(&hc->dch, D_CLEARBUSY); 3394#endif 3395 ret = 0; 3396 spin_unlock_irqrestore(&hc->lock, flags); 3397 } else 3398 ret = l1_event(dch->l1, hh->prim); 3399 break; 3400 } 3401 if (!ret) 3402 dev_kfree_skb(skb); 3403 return ret; 3404} 3405 3406static void 3407deactivate_bchannel(struct bchannel *bch) 3408{ 3409 struct hfc_multi *hc = bch->hw; 3410 u_long flags; 3411 3412 spin_lock_irqsave(&hc->lock, flags); 3413 mISDN_clear_bchannel(bch); 3414 hc->chan[bch->slot].coeff_count = 0; 3415 hc->chan[bch->slot].rx_off = 0; 3416 hc->chan[bch->slot].conf = -1; 3417 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0); 3418 spin_unlock_irqrestore(&hc->lock, flags); 3419} 3420 3421static int 3422handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb) 3423{ 3424 struct bchannel *bch = container_of(ch, struct bchannel, ch); 3425 struct hfc_multi *hc = bch->hw; 3426 int ret = -EINVAL; 3427 struct mISDNhead *hh = mISDN_HEAD_P(skb); 3428 unsigned int id; 3429 u_long flags; 3430 3431 switch (hh->prim) { 3432 case PH_DATA_REQ: 3433 if (!skb->len) 3434 break; 3435 spin_lock_irqsave(&hc->lock, flags); 3436 ret = bchannel_senddata(bch, skb); 3437 if (ret > 0) { /* direct TX */ 3438 id = hh->id; /* skb can be freed */ 3439 hfcmulti_tx(hc, bch->slot); 3440 ret = 0; 3441 /* start fifo */ 3442 HFC_outb_nodebug(hc, R_FIFO, 0); 3443 HFC_wait_nodebug(hc); 3444 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) { 3445 spin_unlock_irqrestore(&hc->lock, flags); 3446 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 3447 } else 3448 spin_unlock_irqrestore(&hc->lock, flags); 3449 } else 3450 spin_unlock_irqrestore(&hc->lock, flags); 3451 return ret; 3452 case PH_ACTIVATE_REQ: 3453 if (debug & DEBUG_HFCMULTI_MSG) 3454 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n", 3455 __func__, bch->slot); 3456 spin_lock_irqsave(&hc->lock, flags); 3457 /* activate B-channel if not already activated */ 3458 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { 3459 hc->chan[bch->slot].txpending = 0; 3460 ret = mode_hfcmulti(hc, bch->slot, 3461 ch->protocol, 3462 hc->chan[bch->slot].slot_tx, 3463 hc->chan[bch->slot].bank_tx, 3464 hc->chan[bch->slot].slot_rx, 3465 hc->chan[bch->slot].bank_rx); 3466 if (!ret) { 3467 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf 3468 && test_bit(HFC_CHIP_DTMF, &hc->chip)) { 3469 /* start decoder */ 3470 hc->dtmf = 1; 3471 if (debug & DEBUG_HFCMULTI_DTMF) 3472 printk(KERN_DEBUG 3473 "%s: start dtmf decoder\n", 3474 __func__); 3475 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf | 3476 V_RST_DTMF); 3477 } 3478 } 3479 } else 3480 ret = 0; 3481 spin_unlock_irqrestore(&hc->lock, flags); 3482 if (!ret) 3483 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL, 3484 GFP_KERNEL); 3485 break; 3486 case PH_CONTROL_REQ: 3487 spin_lock_irqsave(&hc->lock, flags); 3488 switch (hh->id) { 3489 case HFC_SPL_LOOP_ON: /* set sample loop */ 3490 if (debug & DEBUG_HFCMULTI_MSG) 3491 printk(KERN_DEBUG 3492 "%s: HFC_SPL_LOOP_ON (len = %d)\n", 3493 __func__, skb->len); 3494 ret = 0; 3495 break; 3496 case HFC_SPL_LOOP_OFF: /* set silence */ 3497 if (debug & DEBUG_HFCMULTI_MSG) 3498 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n", 3499 __func__); 3500 ret = 0; 3501 break; 3502 default: 3503 printk(KERN_ERR 3504 "%s: unknown PH_CONTROL_REQ info %x\n", 3505 __func__, hh->id); 3506 ret = -EINVAL; 3507 } 3508 spin_unlock_irqrestore(&hc->lock, flags); 3509 break; 3510 case PH_DEACTIVATE_REQ: 3511 deactivate_bchannel(bch); /* locked there */ 3512 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL, 3513 GFP_KERNEL); 3514 ret = 0; 3515 break; 3516 } 3517 if (!ret) 3518 dev_kfree_skb(skb); 3519 return ret; 3520} 3521 3522/* 3523 * bchannel control function 3524 */ 3525static int 3526channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) 3527{ 3528 int ret = 0; 3529 struct dsp_features *features = 3530 (struct dsp_features *)(*((u_long *)&cq->p1)); 3531 struct hfc_multi *hc = bch->hw; 3532 int slot_tx; 3533 int bank_tx; 3534 int slot_rx; 3535 int bank_rx; 3536 int num; 3537 3538 switch (cq->op) { 3539 case MISDN_CTRL_GETOP: 3540 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP 3541 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY; 3542 break; 3543 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */ 3544 hc->chan[bch->slot].rx_off = !!cq->p1; 3545 if (!hc->chan[bch->slot].rx_off) { 3546 /* reset fifo on rx on */ 3547 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1); 3548 HFC_wait_nodebug(hc); 3549 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); 3550 HFC_wait_nodebug(hc); 3551 } 3552 if (debug & DEBUG_HFCMULTI_MSG) 3553 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n", 3554 __func__, bch->nr, hc->chan[bch->slot].rx_off); 3555 break; 3556 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */ 3557 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags); 3558 if (debug & DEBUG_HFCMULTI_MSG) 3559 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d " 3560 "off=%d)\n", __func__, bch->nr, !!cq->p1); 3561 break; 3562 case MISDN_CTRL_HW_FEATURES: /* fill features structure */ 3563 if (debug & DEBUG_HFCMULTI_MSG) 3564 printk(KERN_DEBUG "%s: HW_FEATURE request\n", 3565 __func__); 3566 /* create confirm */ 3567 features->hfc_id = hc->id; 3568 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) 3569 features->hfc_dtmf = 1; 3570 if (test_bit(HFC_CHIP_CONF, &hc->chip)) 3571 features->hfc_conf = 1; 3572 features->hfc_loops = 0; 3573 if (test_bit(HFC_CHIP_B410P, &hc->chip)) { 3574 features->hfc_echocanhw = 1; 3575 } else { 3576 features->pcm_id = hc->pcm; 3577 features->pcm_slots = hc->slots; 3578 features->pcm_banks = 2; 3579 } 3580 break; 3581 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */ 3582 slot_tx = cq->p1 & 0xff; 3583 bank_tx = cq->p1 >> 8; 3584 slot_rx = cq->p2 & 0xff; 3585 bank_rx = cq->p2 >> 8; 3586 if (debug & DEBUG_HFCMULTI_MSG) 3587 printk(KERN_DEBUG 3588 "%s: HFC_PCM_CONN slot %d bank %d (TX) " 3589 "slot %d bank %d (RX)\n", 3590 __func__, slot_tx, bank_tx, 3591 slot_rx, bank_rx); 3592 if (slot_tx < hc->slots && bank_tx <= 2 && 3593 slot_rx < hc->slots && bank_rx <= 2) 3594 hfcmulti_pcm(hc, bch->slot, 3595 slot_tx, bank_tx, slot_rx, bank_rx); 3596 else { 3597 printk(KERN_WARNING 3598 "%s: HFC_PCM_CONN slot %d bank %d (TX) " 3599 "slot %d bank %d (RX) out of range\n", 3600 __func__, slot_tx, bank_tx, 3601 slot_rx, bank_rx); 3602 ret = -EINVAL; 3603 } 3604 break; 3605 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */ 3606 if (debug & DEBUG_HFCMULTI_MSG) 3607 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n", 3608 __func__); 3609 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0); 3610 break; 3611 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */ 3612 num = cq->p1 & 0xff; 3613 if (debug & DEBUG_HFCMULTI_MSG) 3614 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n", 3615 __func__, num); 3616 if (num <= 7) 3617 hfcmulti_conf(hc, bch->slot, num); 3618 else { 3619 printk(KERN_WARNING 3620 "%s: HW_CONF_JOIN conf %d out of range\n", 3621 __func__, num); 3622 ret = -EINVAL; 3623 } 3624 break; 3625 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */ 3626 if (debug & DEBUG_HFCMULTI_MSG) 3627 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__); 3628 hfcmulti_conf(hc, bch->slot, -1); 3629 break; 3630 case MISDN_CTRL_HFC_ECHOCAN_ON: 3631 if (debug & DEBUG_HFCMULTI_MSG) 3632 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__); 3633 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 3634 vpm_echocan_on(hc, bch->slot, cq->p1); 3635 else 3636 ret = -EINVAL; 3637 break; 3638 3639 case MISDN_CTRL_HFC_ECHOCAN_OFF: 3640 if (debug & DEBUG_HFCMULTI_MSG) 3641 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n", 3642 __func__); 3643 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 3644 vpm_echocan_off(hc, bch->slot); 3645 else 3646 ret = -EINVAL; 3647 break; 3648 default: 3649 printk(KERN_WARNING "%s: unknown Op %x\n", 3650 __func__, cq->op); 3651 ret = -EINVAL; 3652 break; 3653 } 3654 return ret; 3655} 3656 3657static int 3658hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) 3659{ 3660 struct bchannel *bch = container_of(ch, struct bchannel, ch); 3661 struct hfc_multi *hc = bch->hw; 3662 int err = -EINVAL; 3663 u_long flags; 3664 3665 if (bch->debug & DEBUG_HW) 3666 printk(KERN_DEBUG "%s: cmd:%x %p\n", 3667 __func__, cmd, arg); 3668 switch (cmd) { 3669 case CLOSE_CHANNEL: 3670 test_and_clear_bit(FLG_OPEN, &bch->Flags); 3671 if (test_bit(FLG_ACTIVE, &bch->Flags)) 3672 deactivate_bchannel(bch); /* locked there */ 3673 ch->protocol = ISDN_P_NONE; 3674 ch->peer = NULL; 3675 module_put(THIS_MODULE); 3676 err = 0; 3677 break; 3678 case CONTROL_CHANNEL: 3679 spin_lock_irqsave(&hc->lock, flags); 3680 err = channel_bctrl(bch, arg); 3681 spin_unlock_irqrestore(&hc->lock, flags); 3682 break; 3683 default: 3684 printk(KERN_WARNING "%s: unknown prim(%x)\n", 3685 __func__, cmd); 3686 } 3687 return err; 3688} 3689 3690/* 3691 * handle D-channel events 3692 * 3693 * handle state change event 3694 */ 3695static void 3696ph_state_change(struct dchannel *dch) 3697{ 3698 struct hfc_multi *hc; 3699 int ch, i; 3700 3701 if (!dch) { 3702 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__); 3703 return; 3704 } 3705 hc = dch->hw; 3706 ch = dch->slot; 3707 3708 if (hc->ctype == HFC_TYPE_E1) { 3709 if (dch->dev.D.protocol == ISDN_P_TE_E1) { 3710 if (debug & DEBUG_HFCMULTI_STATE) 3711 printk(KERN_DEBUG 3712 "%s: E1 TE (id=%d) newstate %x\n", 3713 __func__, hc->id, dch->state); 3714 } else { 3715 if (debug & DEBUG_HFCMULTI_STATE) 3716 printk(KERN_DEBUG 3717 "%s: E1 NT (id=%d) newstate %x\n", 3718 __func__, hc->id, dch->state); 3719 } 3720 switch (dch->state) { 3721 case (1): 3722 if (hc->e1_state != 1) { 3723 for (i = 1; i <= 31; i++) { 3724 /* reset fifos on e1 activation */ 3725 HFC_outb_nodebug(hc, R_FIFO, 3726 (i << 1) | 1); 3727 HFC_wait_nodebug(hc); 3728 HFC_outb_nodebug(hc, R_INC_RES_FIFO, 3729 V_RES_F); 3730 HFC_wait_nodebug(hc); 3731 } 3732 } 3733 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3734 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, 3735 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3736 break; 3737 3738 default: 3739 if (hc->e1_state != 1) 3740 return; 3741 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3742 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, 3743 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3744 } 3745 hc->e1_state = dch->state; 3746 } else { 3747 if (dch->dev.D.protocol == ISDN_P_TE_S0) { 3748 if (debug & DEBUG_HFCMULTI_STATE) 3749 printk(KERN_DEBUG 3750 "%s: S/T TE newstate %x\n", 3751 __func__, dch->state); 3752 switch (dch->state) { 3753 case (0): 3754 l1_event(dch->l1, HW_RESET_IND); 3755 break; 3756 case (3): 3757 l1_event(dch->l1, HW_DEACT_IND); 3758 break; 3759 case (5): 3760 case (8): 3761 l1_event(dch->l1, ANYSIGNAL); 3762 break; 3763 case (6): 3764 l1_event(dch->l1, INFO2); 3765 break; 3766 case (7): 3767 l1_event(dch->l1, INFO4_P8); 3768 break; 3769 } 3770 } else { 3771 if (debug & DEBUG_HFCMULTI_STATE) 3772 printk(KERN_DEBUG "%s: S/T NT newstate %x\n", 3773 __func__, dch->state); 3774 switch (dch->state) { 3775 case (2): 3776 if (hc->chan[ch].nt_timer == 0) { 3777 hc->chan[ch].nt_timer = -1; 3778 HFC_outb(hc, R_ST_SEL, 3779 hc->chan[ch].port); 3780 /* undocumented: delay after R_ST_SEL */ 3781 udelay(1); 3782 HFC_outb(hc, A_ST_WR_STATE, 4 | 3783 V_ST_LD_STA); /* G4 */ 3784 udelay(6); /* wait at least 5,21us */ 3785 HFC_outb(hc, A_ST_WR_STATE, 4); 3786 dch->state = 4; 3787 } else { 3788 /* one extra count for the next event */ 3789 hc->chan[ch].nt_timer = 3790 nt_t1_count[poll_timer] + 1; 3791 HFC_outb(hc, R_ST_SEL, 3792 hc->chan[ch].port); 3793 /* undocumented: delay after R_ST_SEL */ 3794 udelay(1); 3795 /* allow G2 -> G3 transition */ 3796 HFC_outb(hc, A_ST_WR_STATE, 2 | 3797 V_SET_G2_G3); 3798 } 3799 break; 3800 case (1): 3801 hc->chan[ch].nt_timer = -1; 3802 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 3803 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, 3804 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3805 break; 3806 case (4): 3807 hc->chan[ch].nt_timer = -1; 3808 break; 3809 case (3): 3810 hc->chan[ch].nt_timer = -1; 3811 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 3812 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, 3813 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); 3814 break; 3815 } 3816 } 3817 } 3818} 3819 3820/* 3821 * called for card mode init message 3822 */ 3823 3824static void 3825hfcmulti_initmode(struct dchannel *dch) 3826{ 3827 struct hfc_multi *hc = dch->hw; 3828 u_char a_st_wr_state, r_e1_wr_sta; 3829 int i, pt; 3830 3831 if (debug & DEBUG_HFCMULTI_INIT) 3832 printk(KERN_DEBUG "%s: entered\n", __func__); 3833 3834 if (hc->ctype == HFC_TYPE_E1) { 3835 hc->chan[hc->dslot].slot_tx = -1; 3836 hc->chan[hc->dslot].slot_rx = -1; 3837 hc->chan[hc->dslot].conf = -1; 3838 if (hc->dslot) { 3839 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol, 3840 -1, 0, -1, 0); 3841 dch->timer.function = (void *) hfcmulti_dbusy_timer; 3842 dch->timer.data = (long) dch; 3843 init_timer(&dch->timer); 3844 } 3845 for (i = 1; i <= 31; i++) { 3846 if (i == hc->dslot) 3847 continue; 3848 hc->chan[i].slot_tx = -1; 3849 hc->chan[i].slot_rx = -1; 3850 hc->chan[i].conf = -1; 3851 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0); 3852 } 3853 /* E1 */ 3854 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) { 3855 HFC_outb(hc, R_LOS0, 255); /* 2 ms */ 3856 HFC_outb(hc, R_LOS1, 255); /* 512 ms */ 3857 } 3858 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) { 3859 HFC_outb(hc, R_RX0, 0); 3860 hc->hw.r_tx0 = 0 | V_OUT_EN; 3861 } else { 3862 HFC_outb(hc, R_RX0, 1); 3863 hc->hw.r_tx0 = 1 | V_OUT_EN; 3864 } 3865 hc->hw.r_tx1 = V_ATX | V_NTRI; 3866 HFC_outb(hc, R_TX0, hc->hw.r_tx0); 3867 HFC_outb(hc, R_TX1, hc->hw.r_tx1); 3868 HFC_outb(hc, R_TX_FR0, 0x00); 3869 HFC_outb(hc, R_TX_FR1, 0xf8); 3870 3871 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg)) 3872 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E); 3873 3874 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0); 3875 3876 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg)) 3877 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC); 3878 3879 if (dch->dev.D.protocol == ISDN_P_NT_E1) { 3880 if (debug & DEBUG_HFCMULTI_INIT) 3881 printk(KERN_DEBUG "%s: E1 port is NT-mode\n", 3882 __func__); 3883 r_e1_wr_sta = 0; /* G0 */ 3884 hc->e1_getclock = 0; 3885 } else { 3886 if (debug & DEBUG_HFCMULTI_INIT) 3887 printk(KERN_DEBUG "%s: E1 port is TE-mode\n", 3888 __func__); 3889 r_e1_wr_sta = 0; /* F0 */ 3890 hc->e1_getclock = 1; 3891 } 3892 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) 3893 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); 3894 else 3895 HFC_outb(hc, R_SYNC_OUT, 0); 3896 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip)) 3897 hc->e1_getclock = 1; 3898 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip)) 3899 hc->e1_getclock = 0; 3900 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 3901 /* SLAVE (clock master) */ 3902 if (debug & DEBUG_HFCMULTI_INIT) 3903 printk(KERN_DEBUG 3904 "%s: E1 port is clock master " 3905 "(clock from PCM)\n", __func__); 3906 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC); 3907 } else { 3908 if (hc->e1_getclock) { 3909 /* MASTER (clock slave) */ 3910 if (debug & DEBUG_HFCMULTI_INIT) 3911 printk(KERN_DEBUG 3912 "%s: E1 port is clock slave " 3913 "(clock to PCM)\n", __func__); 3914 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); 3915 } else { 3916 /* MASTER (clock master) */ 3917 if (debug & DEBUG_HFCMULTI_INIT) 3918 printk(KERN_DEBUG "%s: E1 port is " 3919 "clock master " 3920 "(clock from QUARTZ)\n", 3921 __func__); 3922 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | 3923 V_PCM_SYNC | V_JATT_OFF); 3924 HFC_outb(hc, R_SYNC_OUT, 0); 3925 } 3926 } 3927 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */ 3928 HFC_outb(hc, R_PWM_MD, V_PWM0_MD); 3929 HFC_outb(hc, R_PWM0, 0x50); 3930 HFC_outb(hc, R_PWM1, 0xff); 3931 /* state machine setup */ 3932 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA); 3933 udelay(6); /* wait at least 5,21us */ 3934 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta); 3935 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 3936 hc->syncronized = 0; 3937 plxsd_checksync(hc, 0); 3938 } 3939 } else { 3940 i = dch->slot; 3941 hc->chan[i].slot_tx = -1; 3942 hc->chan[i].slot_rx = -1; 3943 hc->chan[i].conf = -1; 3944 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0); 3945 dch->timer.function = (void *)hfcmulti_dbusy_timer; 3946 dch->timer.data = (long) dch; 3947 init_timer(&dch->timer); 3948 hc->chan[i - 2].slot_tx = -1; 3949 hc->chan[i - 2].slot_rx = -1; 3950 hc->chan[i - 2].conf = -1; 3951 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0); 3952 hc->chan[i - 1].slot_tx = -1; 3953 hc->chan[i - 1].slot_rx = -1; 3954 hc->chan[i - 1].conf = -1; 3955 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0); 3956 /* ST */ 3957 pt = hc->chan[i].port; 3958 /* select interface */ 3959 HFC_outb(hc, R_ST_SEL, pt); 3960 /* undocumented: delay after R_ST_SEL */ 3961 udelay(1); 3962 if (dch->dev.D.protocol == ISDN_P_NT_S0) { 3963 if (debug & DEBUG_HFCMULTI_INIT) 3964 printk(KERN_DEBUG 3965 "%s: ST port %d is NT-mode\n", 3966 __func__, pt); 3967 /* clock delay */ 3968 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt); 3969 a_st_wr_state = 1; /* G1 */ 3970 hc->hw.a_st_ctrl0[pt] = V_ST_MD; 3971 } else { 3972 if (debug & DEBUG_HFCMULTI_INIT) 3973 printk(KERN_DEBUG 3974 "%s: ST port %d is TE-mode\n", 3975 __func__, pt); 3976 /* clock delay */ 3977 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te); 3978 a_st_wr_state = 2; /* F2 */ 3979 hc->hw.a_st_ctrl0[pt] = 0; 3980 } 3981 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg)) 3982 hc->hw.a_st_ctrl0[pt] |= V_TX_LI; 3983 if (hc->ctype == HFC_TYPE_XHFC) { 3984 hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */; 3985 HFC_outb(hc, 0x35 /* A_ST_CTRL3 */, 3986 0x7c << 1 /* V_ST_PULSE */); 3987 } 3988 /* line setup */ 3989 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]); 3990 /* disable E-channel */ 3991 if ((dch->dev.D.protocol == ISDN_P_NT_S0) || 3992 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg)) 3993 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO); 3994 else 3995 HFC_outb(hc, A_ST_CTRL1, 0); 3996 /* enable B-channel receive */ 3997 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN); 3998 /* state machine setup */ 3999 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA); 4000 udelay(6); /* wait at least 5,21us */ 4001 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state); 4002 hc->hw.r_sci_msk |= 1 << pt; 4003 /* state machine interrupts */ 4004 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk); 4005 /* unset sync on port */ 4006 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4007 hc->syncronized &= 4008 ~(1 << hc->chan[dch->slot].port); 4009 plxsd_checksync(hc, 0); 4010 } 4011 } 4012 if (debug & DEBUG_HFCMULTI_INIT) 4013 printk("%s: done\n", __func__); 4014} 4015 4016 4017static int 4018open_dchannel(struct hfc_multi *hc, struct dchannel *dch, 4019 struct channel_req *rq) 4020{ 4021 int err = 0; 4022 u_long flags; 4023 4024 if (debug & DEBUG_HW_OPEN) 4025 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__, 4026 dch->dev.id, __builtin_return_address(0)); 4027 if (rq->protocol == ISDN_P_NONE) 4028 return -EINVAL; 4029 if ((dch->dev.D.protocol != ISDN_P_NONE) && 4030 (dch->dev.D.protocol != rq->protocol)) { 4031 if (debug & DEBUG_HFCMULTI_MODE) 4032 printk(KERN_DEBUG "%s: change protocol %x to %x\n", 4033 __func__, dch->dev.D.protocol, rq->protocol); 4034 } 4035 if ((dch->dev.D.protocol == ISDN_P_TE_S0) && 4036 (rq->protocol != ISDN_P_TE_S0)) 4037 l1_event(dch->l1, CLOSE_CHANNEL); 4038 if (dch->dev.D.protocol != rq->protocol) { 4039 if (rq->protocol == ISDN_P_TE_S0) { 4040 err = create_l1(dch, hfcm_l1callback); 4041 if (err) 4042 return err; 4043 } 4044 dch->dev.D.protocol = rq->protocol; 4045 spin_lock_irqsave(&hc->lock, flags); 4046 hfcmulti_initmode(dch); 4047 spin_unlock_irqrestore(&hc->lock, flags); 4048 } 4049 4050 if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) || 4051 ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) || 4052 ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) || 4053 ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) { 4054 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY, 4055 0, NULL, GFP_KERNEL); 4056 } 4057 rq->ch = &dch->dev.D; 4058 if (!try_module_get(THIS_MODULE)) 4059 printk(KERN_WARNING "%s:cannot get module\n", __func__); 4060 return 0; 4061} 4062 4063static int 4064open_bchannel(struct hfc_multi *hc, struct dchannel *dch, 4065 struct channel_req *rq) 4066{ 4067 struct bchannel *bch; 4068 int ch; 4069 4070 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap)) 4071 return -EINVAL; 4072 if (rq->protocol == ISDN_P_NONE) 4073 return -EINVAL; 4074 if (hc->ctype == HFC_TYPE_E1) 4075 ch = rq->adr.channel; 4076 else 4077 ch = (rq->adr.channel - 1) + (dch->slot - 2); 4078 bch = hc->chan[ch].bch; 4079 if (!bch) { 4080 printk(KERN_ERR "%s:internal error ch %d has no bch\n", 4081 __func__, ch); 4082 return -EINVAL; 4083 } 4084 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 4085 return -EBUSY; /* b-channel can be only open once */ 4086 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); 4087 bch->ch.protocol = rq->protocol; 4088 hc->chan[ch].rx_off = 0; 4089 rq->ch = &bch->ch; 4090 if (!try_module_get(THIS_MODULE)) 4091 printk(KERN_WARNING "%s:cannot get module\n", __func__); 4092 return 0; 4093} 4094 4095/* 4096 * device control function 4097 */ 4098static int 4099channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq) 4100{ 4101 struct hfc_multi *hc = dch->hw; 4102 int ret = 0; 4103 int wd_mode, wd_cnt; 4104 4105 switch (cq->op) { 4106 case MISDN_CTRL_GETOP: 4107 cq->op = MISDN_CTRL_HFC_OP; 4108 break; 4109 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */ 4110 wd_cnt = cq->p1 & 0xf; 4111 wd_mode = !!(cq->p1 >> 4); 4112 if (debug & DEBUG_HFCMULTI_MSG) 4113 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s" 4114 ", counter 0x%x\n", __func__, 4115 wd_mode ? "AUTO" : "MANUAL", wd_cnt); 4116 /* set the watchdog timer */ 4117 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4)); 4118 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0); 4119 if (hc->ctype == HFC_TYPE_XHFC) 4120 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */; 4121 /* init the watchdog register and reset the counter */ 4122 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES); 4123 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4124 /* enable the watchdog output for Speech-Design */ 4125 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7); 4126 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15); 4127 HFC_outb(hc, R_GPIO_OUT1, 0); 4128 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15); 4129 } 4130 break; 4131 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */ 4132 if (debug & DEBUG_HFCMULTI_MSG) 4133 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n", 4134 __func__); 4135 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES); 4136 break; 4137 default: 4138 printk(KERN_WARNING "%s: unknown Op %x\n", 4139 __func__, cq->op); 4140 ret = -EINVAL; 4141 break; 4142 } 4143 return ret; 4144} 4145 4146static int 4147hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg) 4148{ 4149 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 4150 struct dchannel *dch = container_of(dev, struct dchannel, dev); 4151 struct hfc_multi *hc = dch->hw; 4152 struct channel_req *rq; 4153 int err = 0; 4154 u_long flags; 4155 4156 if (dch->debug & DEBUG_HW) 4157 printk(KERN_DEBUG "%s: cmd:%x %p\n", 4158 __func__, cmd, arg); 4159 switch (cmd) { 4160 case OPEN_CHANNEL: 4161 rq = arg; 4162 switch (rq->protocol) { 4163 case ISDN_P_TE_S0: 4164 case ISDN_P_NT_S0: 4165 if (hc->ctype == HFC_TYPE_E1) { 4166 err = -EINVAL; 4167 break; 4168 } 4169 err = open_dchannel(hc, dch, rq); /* locked there */ 4170 break; 4171 case ISDN_P_TE_E1: 4172 case ISDN_P_NT_E1: 4173 if (hc->ctype != HFC_TYPE_E1) { 4174 err = -EINVAL; 4175 break; 4176 } 4177 err = open_dchannel(hc, dch, rq); /* locked there */ 4178 break; 4179 default: 4180 spin_lock_irqsave(&hc->lock, flags); 4181 err = open_bchannel(hc, dch, rq); 4182 spin_unlock_irqrestore(&hc->lock, flags); 4183 } 4184 break; 4185 case CLOSE_CHANNEL: 4186 if (debug & DEBUG_HW_OPEN) 4187 printk(KERN_DEBUG "%s: dev(%d) close from %p\n", 4188 __func__, dch->dev.id, 4189 __builtin_return_address(0)); 4190 module_put(THIS_MODULE); 4191 break; 4192 case CONTROL_CHANNEL: 4193 spin_lock_irqsave(&hc->lock, flags); 4194 err = channel_dctrl(dch, arg); 4195 spin_unlock_irqrestore(&hc->lock, flags); 4196 break; 4197 default: 4198 if (dch->debug & DEBUG_HW) 4199 printk(KERN_DEBUG "%s: unknown command %x\n", 4200 __func__, cmd); 4201 err = -EINVAL; 4202 } 4203 return err; 4204} 4205 4206static int 4207clockctl(void *priv, int enable) 4208{ 4209 struct hfc_multi *hc = priv; 4210 4211 hc->iclock_on = enable; 4212 return 0; 4213} 4214 4215/* 4216 * initialize the card 4217 */ 4218 4219/* 4220 * start timer irq, wait some time and check if we have interrupts. 4221 * if not, reset chip and try again. 4222 */ 4223static int 4224init_card(struct hfc_multi *hc) 4225{ 4226 int err = -EIO; 4227 u_long flags; 4228 void __iomem *plx_acc; 4229 u_long plx_flags; 4230 4231 if (debug & DEBUG_HFCMULTI_INIT) 4232 printk(KERN_DEBUG "%s: entered\n", __func__); 4233 4234 spin_lock_irqsave(&hc->lock, flags); 4235 /* set interrupts but leave global interrupt disabled */ 4236 hc->hw.r_irq_ctrl = V_FIFO_IRQ; 4237 disable_hwirq(hc); 4238 spin_unlock_irqrestore(&hc->lock, flags); 4239 4240 if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED, 4241 "HFC-multi", hc)) { 4242 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n", 4243 hc->irq); 4244 hc->irq = 0; 4245 return -EIO; 4246 } 4247 4248 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4249 spin_lock_irqsave(&plx_lock, plx_flags); 4250 plx_acc = hc->plx_membase + PLX_INTCSR; 4251 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE), 4252 plx_acc); /* enable PCI & LINT1 irq */ 4253 spin_unlock_irqrestore(&plx_lock, plx_flags); 4254 } 4255 4256 if (debug & DEBUG_HFCMULTI_INIT) 4257 printk(KERN_DEBUG "%s: IRQ %d count %d\n", 4258 __func__, hc->irq, hc->irqcnt); 4259 err = init_chip(hc); 4260 if (err) 4261 goto error; 4262 /* 4263 * Finally enable IRQ output 4264 * this is only allowed, if an IRQ routine is already 4265 * established for this HFC, so don't do that earlier 4266 */ 4267 spin_lock_irqsave(&hc->lock, flags); 4268 enable_hwirq(hc); 4269 spin_unlock_irqrestore(&hc->lock, flags); 4270 /* printk(KERN_DEBUG "no master irq set!!!\n"); */ 4271 set_current_state(TASK_UNINTERRUPTIBLE); 4272 schedule_timeout((100*HZ)/1000); /* Timeout 100ms */ 4273 /* turn IRQ off until chip is completely initialized */ 4274 spin_lock_irqsave(&hc->lock, flags); 4275 disable_hwirq(hc); 4276 spin_unlock_irqrestore(&hc->lock, flags); 4277 if (debug & DEBUG_HFCMULTI_INIT) 4278 printk(KERN_DEBUG "%s: IRQ %d count %d\n", 4279 __func__, hc->irq, hc->irqcnt); 4280 if (hc->irqcnt) { 4281 if (debug & DEBUG_HFCMULTI_INIT) 4282 printk(KERN_DEBUG "%s: done\n", __func__); 4283 4284 return 0; 4285 } 4286 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { 4287 printk(KERN_INFO "ignoring missing interrupts\n"); 4288 return 0; 4289 } 4290 4291 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n", 4292 hc->irq); 4293 4294 err = -EIO; 4295 4296error: 4297 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4298 spin_lock_irqsave(&plx_lock, plx_flags); 4299 plx_acc = hc->plx_membase + PLX_INTCSR; 4300 writew(0x00, plx_acc); /*disable IRQs*/ 4301 spin_unlock_irqrestore(&plx_lock, plx_flags); 4302 } 4303 4304 if (debug & DEBUG_HFCMULTI_INIT) 4305 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq); 4306 if (hc->irq) { 4307 free_irq(hc->irq, hc); 4308 hc->irq = 0; 4309 } 4310 4311 if (debug & DEBUG_HFCMULTI_INIT) 4312 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err); 4313 return err; 4314} 4315 4316/* 4317 * find pci device and set it up 4318 */ 4319 4320static int 4321setup_pci(struct hfc_multi *hc, struct pci_dev *pdev, 4322 const struct pci_device_id *ent) 4323{ 4324 struct hm_map *m = (struct hm_map *)ent->driver_data; 4325 4326 printk(KERN_INFO 4327 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n", 4328 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal"); 4329 4330 hc->pci_dev = pdev; 4331 if (m->clock2) 4332 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip); 4333 4334 if (ent->device == 0xB410) { 4335 test_and_set_bit(HFC_CHIP_B410P, &hc->chip); 4336 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); 4337 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 4338 hc->slots = 32; 4339 } 4340 4341 if (hc->pci_dev->irq <= 0) { 4342 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n"); 4343 return -EIO; 4344 } 4345 if (pci_enable_device(hc->pci_dev)) { 4346 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n"); 4347 return -EIO; 4348 } 4349 hc->leds = m->leds; 4350 hc->ledstate = 0xAFFEAFFE; 4351 hc->opticalsupport = m->opticalsupport; 4352 4353 hc->pci_iobase = 0; 4354 hc->pci_membase = NULL; 4355 hc->plx_membase = NULL; 4356 4357 /* set memory access methods */ 4358 if (m->io_mode) /* use mode from card config */ 4359 hc->io_mode = m->io_mode; 4360 switch (hc->io_mode) { 4361 case HFC_IO_MODE_PLXSD: 4362 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip); 4363 hc->slots = 128; /* required */ 4364 hc->HFC_outb = HFC_outb_pcimem; 4365 hc->HFC_inb = HFC_inb_pcimem; 4366 hc->HFC_inw = HFC_inw_pcimem; 4367 hc->HFC_wait = HFC_wait_pcimem; 4368 hc->read_fifo = read_fifo_pcimem; 4369 hc->write_fifo = write_fifo_pcimem; 4370 hc->plx_origmembase = hc->pci_dev->resource[0].start; 4371 /* MEMBASE 1 is PLX PCI Bridge */ 4372 4373 if (!hc->plx_origmembase) { 4374 printk(KERN_WARNING 4375 "HFC-multi: No IO-Memory for PCI PLX bridge found\n"); 4376 pci_disable_device(hc->pci_dev); 4377 return -EIO; 4378 } 4379 4380 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80); 4381 if (!hc->plx_membase) { 4382 printk(KERN_WARNING 4383 "HFC-multi: failed to remap plx address space. " 4384 "(internal error)\n"); 4385 pci_disable_device(hc->pci_dev); 4386 return -EIO; 4387 } 4388 printk(KERN_INFO 4389 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n", 4390 (u_long)hc->plx_membase, hc->plx_origmembase); 4391 4392 hc->pci_origmembase = hc->pci_dev->resource[2].start; 4393 /* MEMBASE 1 is PLX PCI Bridge */ 4394 if (!hc->pci_origmembase) { 4395 printk(KERN_WARNING 4396 "HFC-multi: No IO-Memory for PCI card found\n"); 4397 pci_disable_device(hc->pci_dev); 4398 return -EIO; 4399 } 4400 4401 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400); 4402 if (!hc->pci_membase) { 4403 printk(KERN_WARNING "HFC-multi: failed to remap io " 4404 "address space. (internal error)\n"); 4405 pci_disable_device(hc->pci_dev); 4406 return -EIO; 4407 } 4408 4409 printk(KERN_INFO 4410 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d " 4411 "leds-type %d\n", 4412 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase, 4413 hc->pci_dev->irq, HZ, hc->leds); 4414 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); 4415 break; 4416 case HFC_IO_MODE_PCIMEM: 4417 hc->HFC_outb = HFC_outb_pcimem; 4418 hc->HFC_inb = HFC_inb_pcimem; 4419 hc->HFC_inw = HFC_inw_pcimem; 4420 hc->HFC_wait = HFC_wait_pcimem; 4421 hc->read_fifo = read_fifo_pcimem; 4422 hc->write_fifo = write_fifo_pcimem; 4423 hc->pci_origmembase = hc->pci_dev->resource[1].start; 4424 if (!hc->pci_origmembase) { 4425 printk(KERN_WARNING 4426 "HFC-multi: No IO-Memory for PCI card found\n"); 4427 pci_disable_device(hc->pci_dev); 4428 return -EIO; 4429 } 4430 4431 hc->pci_membase = ioremap(hc->pci_origmembase, 256); 4432 if (!hc->pci_membase) { 4433 printk(KERN_WARNING 4434 "HFC-multi: failed to remap io address space. " 4435 "(internal error)\n"); 4436 pci_disable_device(hc->pci_dev); 4437 return -EIO; 4438 } 4439 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ " 4440 "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase, 4441 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds); 4442 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); 4443 break; 4444 case HFC_IO_MODE_REGIO: 4445 hc->HFC_outb = HFC_outb_regio; 4446 hc->HFC_inb = HFC_inb_regio; 4447 hc->HFC_inw = HFC_inw_regio; 4448 hc->HFC_wait = HFC_wait_regio; 4449 hc->read_fifo = read_fifo_regio; 4450 hc->write_fifo = write_fifo_regio; 4451 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start; 4452 if (!hc->pci_iobase) { 4453 printk(KERN_WARNING 4454 "HFC-multi: No IO for PCI card found\n"); 4455 pci_disable_device(hc->pci_dev); 4456 return -EIO; 4457 } 4458 4459 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) { 4460 printk(KERN_WARNING "HFC-multi: failed to request " 4461 "address space at 0x%08lx (internal error)\n", 4462 hc->pci_iobase); 4463 pci_disable_device(hc->pci_dev); 4464 return -EIO; 4465 } 4466 4467 printk(KERN_INFO 4468 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n", 4469 m->vendor_name, m->card_name, (u_int) hc->pci_iobase, 4470 hc->pci_dev->irq, HZ, hc->leds); 4471 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO); 4472 break; 4473 default: 4474 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n"); 4475 pci_disable_device(hc->pci_dev); 4476 return -EIO; 4477 } 4478 4479 pci_set_drvdata(hc->pci_dev, hc); 4480 4481 /* At this point the needed PCI config is done */ 4482 /* fifos are still not enabled */ 4483 return 0; 4484} 4485 4486 4487/* 4488 * remove port 4489 */ 4490 4491static void 4492release_port(struct hfc_multi *hc, struct dchannel *dch) 4493{ 4494 int pt, ci, i = 0; 4495 u_long flags; 4496 struct bchannel *pb; 4497 4498 ci = dch->slot; 4499 pt = hc->chan[ci].port; 4500 4501 if (debug & DEBUG_HFCMULTI_INIT) 4502 printk(KERN_DEBUG "%s: entered for port %d\n", 4503 __func__, pt + 1); 4504 4505 if (pt >= hc->ports) { 4506 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n", 4507 __func__, pt + 1); 4508 return; 4509 } 4510 4511 if (debug & DEBUG_HFCMULTI_INIT) 4512 printk(KERN_DEBUG "%s: releasing port=%d\n", 4513 __func__, pt + 1); 4514 4515 if (dch->dev.D.protocol == ISDN_P_TE_S0) 4516 l1_event(dch->l1, CLOSE_CHANNEL); 4517 4518 hc->chan[ci].dch = NULL; 4519 4520 if (hc->created[pt]) { 4521 hc->created[pt] = 0; 4522 mISDN_unregister_device(&dch->dev); 4523 } 4524 4525 spin_lock_irqsave(&hc->lock, flags); 4526 4527 if (dch->timer.function) { 4528 del_timer(&dch->timer); 4529 dch->timer.function = NULL; 4530 } 4531 4532 if (hc->ctype == HFC_TYPE_E1) { /* E1 */ 4533 /* remove sync */ 4534 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4535 hc->syncronized = 0; 4536 plxsd_checksync(hc, 1); 4537 } 4538 /* free channels */ 4539 for (i = 0; i <= 31; i++) { 4540 if (hc->chan[i].bch) { 4541 if (debug & DEBUG_HFCMULTI_INIT) 4542 printk(KERN_DEBUG 4543 "%s: free port %d channel %d\n", 4544 __func__, hc->chan[i].port+1, i); 4545 pb = hc->chan[i].bch; 4546 hc->chan[i].bch = NULL; 4547 spin_unlock_irqrestore(&hc->lock, flags); 4548 mISDN_freebchannel(pb); 4549 kfree(pb); 4550 kfree(hc->chan[i].coeff); 4551 spin_lock_irqsave(&hc->lock, flags); 4552 } 4553 } 4554 } else { 4555 /* remove sync */ 4556 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { 4557 hc->syncronized &= 4558 ~(1 << hc->chan[ci].port); 4559 plxsd_checksync(hc, 1); 4560 } 4561 /* free channels */ 4562 if (hc->chan[ci - 2].bch) { 4563 if (debug & DEBUG_HFCMULTI_INIT) 4564 printk(KERN_DEBUG 4565 "%s: free port %d channel %d\n", 4566 __func__, hc->chan[ci - 2].port+1, 4567 ci - 2); 4568 pb = hc->chan[ci - 2].bch; 4569 hc->chan[ci - 2].bch = NULL; 4570 spin_unlock_irqrestore(&hc->lock, flags); 4571 mISDN_freebchannel(pb); 4572 kfree(pb); 4573 kfree(hc->chan[ci - 2].coeff); 4574 spin_lock_irqsave(&hc->lock, flags); 4575 } 4576 if (hc->chan[ci - 1].bch) { 4577 if (debug & DEBUG_HFCMULTI_INIT) 4578 printk(KERN_DEBUG 4579 "%s: free port %d channel %d\n", 4580 __func__, hc->chan[ci - 1].port+1, 4581 ci - 1); 4582 pb = hc->chan[ci - 1].bch; 4583 hc->chan[ci - 1].bch = NULL; 4584 spin_unlock_irqrestore(&hc->lock, flags); 4585 mISDN_freebchannel(pb); 4586 kfree(pb); 4587 kfree(hc->chan[ci - 1].coeff); 4588 spin_lock_irqsave(&hc->lock, flags); 4589 } 4590 } 4591 4592 spin_unlock_irqrestore(&hc->lock, flags); 4593 4594 if (debug & DEBUG_HFCMULTI_INIT) 4595 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt); 4596 mISDN_freedchannel(dch); 4597 kfree(dch); 4598 4599 if (debug & DEBUG_HFCMULTI_INIT) 4600 printk(KERN_DEBUG "%s: done!\n", __func__); 4601} 4602 4603static void 4604release_card(struct hfc_multi *hc) 4605{ 4606 u_long flags; 4607 int ch; 4608 4609 if (debug & DEBUG_HFCMULTI_INIT) 4610 printk(KERN_DEBUG "%s: release card (%d) entered\n", 4611 __func__, hc->id); 4612 4613 /* unregister clock source */ 4614 if (hc->iclock) 4615 mISDN_unregister_clock(hc->iclock); 4616 4617 /* disable irq */ 4618 spin_lock_irqsave(&hc->lock, flags); 4619 disable_hwirq(hc); 4620 spin_unlock_irqrestore(&hc->lock, flags); 4621 udelay(1000); 4622 4623 /* dimm leds */ 4624 if (hc->leds) 4625 hfcmulti_leds(hc); 4626 4627 /* disable D-channels & B-channels */ 4628 if (debug & DEBUG_HFCMULTI_INIT) 4629 printk(KERN_DEBUG "%s: disable all channels (d and b)\n", 4630 __func__); 4631 for (ch = 0; ch <= 31; ch++) { 4632 if (hc->chan[ch].dch) 4633 release_port(hc, hc->chan[ch].dch); 4634 } 4635 4636 /* release hardware & irq */ 4637 if (hc->irq) { 4638 if (debug & DEBUG_HFCMULTI_INIT) 4639 printk(KERN_DEBUG "%s: free irq %d\n", 4640 __func__, hc->irq); 4641 free_irq(hc->irq, hc); 4642 hc->irq = 0; 4643 4644 } 4645 release_io_hfcmulti(hc); 4646 4647 if (debug & DEBUG_HFCMULTI_INIT) 4648 printk(KERN_DEBUG "%s: remove instance from list\n", 4649 __func__); 4650 list_del(&hc->list); 4651 4652 if (debug & DEBUG_HFCMULTI_INIT) 4653 printk(KERN_DEBUG "%s: delete instance\n", __func__); 4654 if (hc == syncmaster) 4655 syncmaster = NULL; 4656 kfree(hc); 4657 if (debug & DEBUG_HFCMULTI_INIT) 4658 printk(KERN_DEBUG "%s: card successfully removed\n", 4659 __func__); 4660} 4661 4662static int 4663init_e1_port(struct hfc_multi *hc, struct hm_map *m) 4664{ 4665 struct dchannel *dch; 4666 struct bchannel *bch; 4667 int ch, ret = 0; 4668 char name[MISDN_MAX_IDLEN]; 4669 4670 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); 4671 if (!dch) 4672 return -ENOMEM; 4673 dch->debug = debug; 4674 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); 4675 dch->hw = hc; 4676 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1); 4677 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 4678 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 4679 dch->dev.D.send = handle_dmsg; 4680 dch->dev.D.ctrl = hfcm_dctrl; 4681 dch->dev.nrbchan = (hc->dslot) ? 30 : 31; 4682 dch->slot = hc->dslot; 4683 hc->chan[hc->dslot].dch = dch; 4684 hc->chan[hc->dslot].port = 0; 4685 hc->chan[hc->dslot].nt_timer = -1; 4686 for (ch = 1; ch <= 31; ch++) { 4687 if (ch == hc->dslot) /* skip dchannel */ 4688 continue; 4689 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); 4690 if (!bch) { 4691 printk(KERN_ERR "%s: no memory for bchannel\n", 4692 __func__); 4693 ret = -ENOMEM; 4694 goto free_chan; 4695 } 4696 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL); 4697 if (!hc->chan[ch].coeff) { 4698 printk(KERN_ERR "%s: no memory for coeffs\n", 4699 __func__); 4700 ret = -ENOMEM; 4701 kfree(bch); 4702 goto free_chan; 4703 } 4704 bch->nr = ch; 4705 bch->slot = ch; 4706 bch->debug = debug; 4707 mISDN_initbchannel(bch, MAX_DATA_MEM); 4708 bch->hw = hc; 4709 bch->ch.send = handle_bmsg; 4710 bch->ch.ctrl = hfcm_bctrl; 4711 bch->ch.nr = ch; 4712 list_add(&bch->ch.list, &dch->dev.bchannels); 4713 hc->chan[ch].bch = bch; 4714 hc->chan[ch].port = 0; 4715 set_channelmap(bch->nr, dch->dev.channelmap); 4716 } 4717 /* set optical line type */ 4718 if (port[Port_cnt] & 0x001) { 4719 if (!m->opticalsupport) { 4720 printk(KERN_INFO 4721 "This board has no optical " 4722 "support\n"); 4723 } else { 4724 if (debug & DEBUG_HFCMULTI_INIT) 4725 printk(KERN_DEBUG 4726 "%s: PORT set optical " 4727 "interfacs: card(%d) " 4728 "port(%d)\n", 4729 __func__, 4730 HFC_cnt + 1, 1); 4731 test_and_set_bit(HFC_CFG_OPTICAL, 4732 &hc->chan[hc->dslot].cfg); 4733 } 4734 } 4735 /* set LOS report */ 4736 if (port[Port_cnt] & 0x004) { 4737 if (debug & DEBUG_HFCMULTI_INIT) 4738 printk(KERN_DEBUG "%s: PORT set " 4739 "LOS report: card(%d) port(%d)\n", 4740 __func__, HFC_cnt + 1, 1); 4741 test_and_set_bit(HFC_CFG_REPORT_LOS, 4742 &hc->chan[hc->dslot].cfg); 4743 } 4744 /* set AIS report */ 4745 if (port[Port_cnt] & 0x008) { 4746 if (debug & DEBUG_HFCMULTI_INIT) 4747 printk(KERN_DEBUG "%s: PORT set " 4748 "AIS report: card(%d) port(%d)\n", 4749 __func__, HFC_cnt + 1, 1); 4750 test_and_set_bit(HFC_CFG_REPORT_AIS, 4751 &hc->chan[hc->dslot].cfg); 4752 } 4753 /* set SLIP report */ 4754 if (port[Port_cnt] & 0x010) { 4755 if (debug & DEBUG_HFCMULTI_INIT) 4756 printk(KERN_DEBUG 4757 "%s: PORT set SLIP report: " 4758 "card(%d) port(%d)\n", 4759 __func__, HFC_cnt + 1, 1); 4760 test_and_set_bit(HFC_CFG_REPORT_SLIP, 4761 &hc->chan[hc->dslot].cfg); 4762 } 4763 /* set RDI report */ 4764 if (port[Port_cnt] & 0x020) { 4765 if (debug & DEBUG_HFCMULTI_INIT) 4766 printk(KERN_DEBUG 4767 "%s: PORT set RDI report: " 4768 "card(%d) port(%d)\n", 4769 __func__, HFC_cnt + 1, 1); 4770 test_and_set_bit(HFC_CFG_REPORT_RDI, 4771 &hc->chan[hc->dslot].cfg); 4772 } 4773 /* set CRC-4 Mode */ 4774 if (!(port[Port_cnt] & 0x100)) { 4775 if (debug & DEBUG_HFCMULTI_INIT) 4776 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:" 4777 " card(%d) port(%d)\n", 4778 __func__, HFC_cnt + 1, 1); 4779 test_and_set_bit(HFC_CFG_CRC4, 4780 &hc->chan[hc->dslot].cfg); 4781 } else { 4782 if (debug & DEBUG_HFCMULTI_INIT) 4783 printk(KERN_DEBUG "%s: PORT turn off CRC4" 4784 " report: card(%d) port(%d)\n", 4785 __func__, HFC_cnt + 1, 1); 4786 } 4787 /* set forced clock */ 4788 if (port[Port_cnt] & 0x0200) { 4789 if (debug & DEBUG_HFCMULTI_INIT) 4790 printk(KERN_DEBUG "%s: PORT force getting clock from " 4791 "E1: card(%d) port(%d)\n", 4792 __func__, HFC_cnt + 1, 1); 4793 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip); 4794 } else 4795 if (port[Port_cnt] & 0x0400) { 4796 if (debug & DEBUG_HFCMULTI_INIT) 4797 printk(KERN_DEBUG "%s: PORT force putting clock to " 4798 "E1: card(%d) port(%d)\n", 4799 __func__, HFC_cnt + 1, 1); 4800 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip); 4801 } 4802 /* set JATT PLL */ 4803 if (port[Port_cnt] & 0x0800) { 4804 if (debug & DEBUG_HFCMULTI_INIT) 4805 printk(KERN_DEBUG "%s: PORT disable JATT PLL on " 4806 "E1: card(%d) port(%d)\n", 4807 __func__, HFC_cnt + 1, 1); 4808 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip); 4809 } 4810 /* set elastic jitter buffer */ 4811 if (port[Port_cnt] & 0x3000) { 4812 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3; 4813 if (debug & DEBUG_HFCMULTI_INIT) 4814 printk(KERN_DEBUG 4815 "%s: PORT set elastic " 4816 "buffer to %d: card(%d) port(%d)\n", 4817 __func__, hc->chan[hc->dslot].jitter, 4818 HFC_cnt + 1, 1); 4819 } else 4820 hc->chan[hc->dslot].jitter = 2; /* default */ 4821 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1); 4822 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); 4823 if (ret) 4824 goto free_chan; 4825 hc->created[0] = 1; 4826 return ret; 4827free_chan: 4828 release_port(hc, dch); 4829 return ret; 4830} 4831 4832static int 4833init_multi_port(struct hfc_multi *hc, int pt) 4834{ 4835 struct dchannel *dch; 4836 struct bchannel *bch; 4837 int ch, i, ret = 0; 4838 char name[MISDN_MAX_IDLEN]; 4839 4840 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); 4841 if (!dch) 4842 return -ENOMEM; 4843 dch->debug = debug; 4844 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); 4845 dch->hw = hc; 4846 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0); 4847 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 4848 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 4849 dch->dev.D.send = handle_dmsg; 4850 dch->dev.D.ctrl = hfcm_dctrl; 4851 dch->dev.nrbchan = 2; 4852 i = pt << 2; 4853 dch->slot = i + 2; 4854 hc->chan[i + 2].dch = dch; 4855 hc->chan[i + 2].port = pt; 4856 hc->chan[i + 2].nt_timer = -1; 4857 for (ch = 0; ch < dch->dev.nrbchan; ch++) { 4858 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); 4859 if (!bch) { 4860 printk(KERN_ERR "%s: no memory for bchannel\n", 4861 __func__); 4862 ret = -ENOMEM; 4863 goto free_chan; 4864 } 4865 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL); 4866 if (!hc->chan[i + ch].coeff) { 4867 printk(KERN_ERR "%s: no memory for coeffs\n", 4868 __func__); 4869 ret = -ENOMEM; 4870 kfree(bch); 4871 goto free_chan; 4872 } 4873 bch->nr = ch + 1; 4874 bch->slot = i + ch; 4875 bch->debug = debug; 4876 mISDN_initbchannel(bch, MAX_DATA_MEM); 4877 bch->hw = hc; 4878 bch->ch.send = handle_bmsg; 4879 bch->ch.ctrl = hfcm_bctrl; 4880 bch->ch.nr = ch + 1; 4881 list_add(&bch->ch.list, &dch->dev.bchannels); 4882 hc->chan[i + ch].bch = bch; 4883 hc->chan[i + ch].port = pt; 4884 set_channelmap(bch->nr, dch->dev.channelmap); 4885 } 4886 /* set master clock */ 4887 if (port[Port_cnt] & 0x001) { 4888 if (debug & DEBUG_HFCMULTI_INIT) 4889 printk(KERN_DEBUG 4890 "%s: PROTOCOL set master clock: " 4891 "card(%d) port(%d)\n", 4892 __func__, HFC_cnt + 1, pt + 1); 4893 if (dch->dev.D.protocol != ISDN_P_TE_S0) { 4894 printk(KERN_ERR "Error: Master clock " 4895 "for port(%d) of card(%d) is only" 4896 " possible with TE-mode\n", 4897 pt + 1, HFC_cnt + 1); 4898 ret = -EINVAL; 4899 goto free_chan; 4900 } 4901 if (hc->masterclk >= 0) { 4902 printk(KERN_ERR "Error: Master clock " 4903 "for port(%d) of card(%d) already " 4904 "defined for port(%d)\n", 4905 pt + 1, HFC_cnt + 1, hc->masterclk+1); 4906 ret = -EINVAL; 4907 goto free_chan; 4908 } 4909 hc->masterclk = pt; 4910 } 4911 /* set transmitter line to non capacitive */ 4912 if (port[Port_cnt] & 0x002) { 4913 if (debug & DEBUG_HFCMULTI_INIT) 4914 printk(KERN_DEBUG 4915 "%s: PROTOCOL set non capacitive " 4916 "transmitter: card(%d) port(%d)\n", 4917 __func__, HFC_cnt + 1, pt + 1); 4918 test_and_set_bit(HFC_CFG_NONCAP_TX, 4919 &hc->chan[i + 2].cfg); 4920 } 4921 /* disable E-channel */ 4922 if (port[Port_cnt] & 0x004) { 4923 if (debug & DEBUG_HFCMULTI_INIT) 4924 printk(KERN_DEBUG 4925 "%s: PROTOCOL disable E-channel: " 4926 "card(%d) port(%d)\n", 4927 __func__, HFC_cnt + 1, pt + 1); 4928 test_and_set_bit(HFC_CFG_DIS_ECHANNEL, 4929 &hc->chan[i + 2].cfg); 4930 } 4931 if (hc->ctype == HFC_TYPE_XHFC) { 4932 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d", 4933 HFC_cnt + 1, pt + 1); 4934 ret = mISDN_register_device(&dch->dev, NULL, name); 4935 } else { 4936 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d", 4937 hc->ctype, HFC_cnt + 1, pt + 1); 4938 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); 4939 } 4940 if (ret) 4941 goto free_chan; 4942 hc->created[pt] = 1; 4943 return ret; 4944free_chan: 4945 release_port(hc, dch); 4946 return ret; 4947} 4948 4949static int 4950hfcmulti_init(struct hm_map *m, struct pci_dev *pdev, 4951 const struct pci_device_id *ent) 4952{ 4953 int ret_err = 0; 4954 int pt; 4955 struct hfc_multi *hc; 4956 u_long flags; 4957 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */ 4958 int i; 4959 4960 if (HFC_cnt >= MAX_CARDS) { 4961 printk(KERN_ERR "too many cards (max=%d).\n", 4962 MAX_CARDS); 4963 return -EINVAL; 4964 } 4965 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) { 4966 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but " 4967 "type[%d] %d was supplied as module parameter\n", 4968 m->vendor_name, m->card_name, m->type, HFC_cnt, 4969 type[HFC_cnt] & 0xff); 4970 printk(KERN_WARNING "HFC-MULTI: Load module without parameters " 4971 "first, to see cards and their types."); 4972 return -EINVAL; 4973 } 4974 if (debug & DEBUG_HFCMULTI_INIT) 4975 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n", 4976 __func__, m->vendor_name, m->card_name, m->type, 4977 type[HFC_cnt]); 4978 4979 /* allocate card+fifo structure */ 4980 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL); 4981 if (!hc) { 4982 printk(KERN_ERR "No kmem for HFC-Multi card\n"); 4983 return -ENOMEM; 4984 } 4985 spin_lock_init(&hc->lock); 4986 hc->mtyp = m; 4987 hc->ctype = m->type; 4988 hc->ports = m->ports; 4989 hc->id = HFC_cnt; 4990 hc->pcm = pcm[HFC_cnt]; 4991 hc->io_mode = iomode[HFC_cnt]; 4992 if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) { 4993 hc->dslot = 0; 4994 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but " 4995 "31 B-channels\n"); 4996 } 4997 if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 4998 && hc->ctype == HFC_TYPE_E1) { 4999 hc->dslot = dslot[HFC_cnt]; 5000 printk(KERN_INFO "HFC-E1 card has alternating D-channel on " 5001 "time slot %d\n", dslot[HFC_cnt]); 5002 } else 5003 hc->dslot = 16; 5004 5005 /* set chip specific features */ 5006 hc->masterclk = -1; 5007 if (type[HFC_cnt] & 0x100) { 5008 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip); 5009 hc->silence = 0xff; /* ulaw silence */ 5010 } else 5011 hc->silence = 0x2a; /* alaw silence */ 5012 if ((poll >> 1) > sizeof(hc->silence_data)) { 5013 printk(KERN_ERR "HFCMULTI error: silence_data too small, " 5014 "please fix\n"); 5015 return -EINVAL; 5016 } 5017 for (i = 0; i < (poll >> 1); i++) 5018 hc->silence_data[i] = hc->silence; 5019 5020 if (hc->ctype != HFC_TYPE_XHFC) { 5021 if (!(type[HFC_cnt] & 0x200)) 5022 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip); 5023 test_and_set_bit(HFC_CHIP_CONF, &hc->chip); 5024 } 5025 5026 if (type[HFC_cnt] & 0x800) 5027 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 5028 if (type[HFC_cnt] & 0x1000) { 5029 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); 5030 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); 5031 } 5032 if (type[HFC_cnt] & 0x4000) 5033 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip); 5034 if (type[HFC_cnt] & 0x8000) 5035 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip); 5036 hc->slots = 32; 5037 if (type[HFC_cnt] & 0x10000) 5038 hc->slots = 64; 5039 if (type[HFC_cnt] & 0x20000) 5040 hc->slots = 128; 5041 if (type[HFC_cnt] & 0x80000) { 5042 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip); 5043 hc->wdcount = 0; 5044 hc->wdbyte = V_GPIO_OUT2; 5045 printk(KERN_NOTICE "Watchdog enabled\n"); 5046 } 5047 5048 if (pdev && ent) 5049 /* setup pci, hc->slots may change due to PLXSD */ 5050 ret_err = setup_pci(hc, pdev, ent); 5051 else 5052#ifdef CONFIG_MISDN_HFCMULTI_8xx 5053 ret_err = setup_embedded(hc, m); 5054#else 5055 { 5056 printk(KERN_WARNING "Embedded IO Mode not selected\n"); 5057 ret_err = -EIO; 5058 } 5059#endif 5060 if (ret_err) { 5061 if (hc == syncmaster) 5062 syncmaster = NULL; 5063 kfree(hc); 5064 return ret_err; 5065 } 5066 5067 hc->HFC_outb_nodebug = hc->HFC_outb; 5068 hc->HFC_inb_nodebug = hc->HFC_inb; 5069 hc->HFC_inw_nodebug = hc->HFC_inw; 5070 hc->HFC_wait_nodebug = hc->HFC_wait; 5071#ifdef HFC_REGISTER_DEBUG 5072 hc->HFC_outb = HFC_outb_debug; 5073 hc->HFC_inb = HFC_inb_debug; 5074 hc->HFC_inw = HFC_inw_debug; 5075 hc->HFC_wait = HFC_wait_debug; 5076#endif 5077 /* create channels */ 5078 for (pt = 0; pt < hc->ports; pt++) { 5079 if (Port_cnt >= MAX_PORTS) { 5080 printk(KERN_ERR "too many ports (max=%d).\n", 5081 MAX_PORTS); 5082 ret_err = -EINVAL; 5083 goto free_card; 5084 } 5085 if (hc->ctype == HFC_TYPE_E1) 5086 ret_err = init_e1_port(hc, m); 5087 else 5088 ret_err = init_multi_port(hc, pt); 5089 if (debug & DEBUG_HFCMULTI_INIT) 5090 printk(KERN_DEBUG 5091 "%s: Registering D-channel, card(%d) port(%d)" 5092 "result %d\n", 5093 __func__, HFC_cnt + 1, pt, ret_err); 5094 5095 if (ret_err) { 5096 while (pt) { /* release already registered ports */ 5097 pt--; 5098 release_port(hc, hc->chan[(pt << 2) + 2].dch); 5099 } 5100 goto free_card; 5101 } 5102 Port_cnt++; 5103 } 5104 5105 /* disp switches */ 5106 switch (m->dip_type) { 5107 case DIP_4S: 5108 /* 5109 * Get DIP setting for beroNet 1S/2S/4S cards 5110 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) + 5111 * GPI 19/23 (R_GPI_IN2)) 5112 */ 5113 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) | 5114 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) | 5115 (~HFC_inb(hc, R_GPI_IN2) & 0x08); 5116 5117 /* Port mode (TE/NT) jumpers */ 5118 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf); 5119 5120 if (test_bit(HFC_CHIP_B410P, &hc->chip)) 5121 pmj = ~pmj & 0xf; 5122 5123 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n", 5124 m->vendor_name, m->card_name, dips, pmj); 5125 break; 5126 case DIP_8S: 5127 /* 5128 * Get DIP Setting for beroNet 8S0+ cards 5129 * Enable PCI auxbridge function 5130 */ 5131 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); 5132 /* prepare access to auxport */ 5133 outw(0x4000, hc->pci_iobase + 4); 5134 /* 5135 * some dummy reads are required to 5136 * read valid DIP switch data 5137 */ 5138 dips = inb(hc->pci_iobase); 5139 dips = inb(hc->pci_iobase); 5140 dips = inb(hc->pci_iobase); 5141 dips = ~inb(hc->pci_iobase) & 0x3F; 5142 outw(0x0, hc->pci_iobase + 4); 5143 /* disable PCI auxbridge function */ 5144 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); 5145 printk(KERN_INFO "%s: %s DIPs(0x%x)\n", 5146 m->vendor_name, m->card_name, dips); 5147 break; 5148 case DIP_E1: 5149 /* 5150 * get DIP Setting for beroNet E1 cards 5151 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0) 5152 */ 5153 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4; 5154 printk(KERN_INFO "%s: %s DIPs(0x%x)\n", 5155 m->vendor_name, m->card_name, dips); 5156 break; 5157 } 5158 5159 /* add to list */ 5160 spin_lock_irqsave(&HFClock, flags); 5161 list_add_tail(&hc->list, &HFClist); 5162 spin_unlock_irqrestore(&HFClock, flags); 5163 5164 /* use as clock source */ 5165 if (clock == HFC_cnt + 1) 5166 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc); 5167 5168 /* initialize hardware */ 5169 hc->irq = (m->irq) ? : hc->pci_dev->irq; 5170 ret_err = init_card(hc); 5171 if (ret_err) { 5172 printk(KERN_ERR "init card returns %d\n", ret_err); 5173 release_card(hc); 5174 return ret_err; 5175 } 5176 5177 /* start IRQ and return */ 5178 spin_lock_irqsave(&hc->lock, flags); 5179 enable_hwirq(hc); 5180 spin_unlock_irqrestore(&hc->lock, flags); 5181 return 0; 5182 5183free_card: 5184 release_io_hfcmulti(hc); 5185 if (hc == syncmaster) 5186 syncmaster = NULL; 5187 kfree(hc); 5188 return ret_err; 5189} 5190 5191static void __devexit hfc_remove_pci(struct pci_dev *pdev) 5192{ 5193 struct hfc_multi *card = pci_get_drvdata(pdev); 5194 u_long flags; 5195 5196 if (debug) 5197 printk(KERN_INFO "removing hfc_multi card vendor:%x " 5198 "device:%x subvendor:%x subdevice:%x\n", 5199 pdev->vendor, pdev->device, 5200 pdev->subsystem_vendor, pdev->subsystem_device); 5201 5202 if (card) { 5203 spin_lock_irqsave(&HFClock, flags); 5204 release_card(card); 5205 spin_unlock_irqrestore(&HFClock, flags); 5206 } else { 5207 if (debug) 5208 printk(KERN_DEBUG "%s: drvdata already removed\n", 5209 __func__); 5210 } 5211} 5212 5213#define VENDOR_CCD "Cologne Chip AG" 5214#define VENDOR_BN "beroNet GmbH" 5215#define VENDOR_DIG "Digium Inc." 5216#define VENDOR_JH "Junghanns.NET GmbH" 5217#define VENDOR_PRIM "PrimuX" 5218 5219static const struct hm_map hfcm_map[] = { 5220/*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0}, 5221/*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5222/*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5223/*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5224/*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0}, 5225/*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0}, 5226/*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5227/*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0}, 5228/*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0}, 5229/*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0}, 5230/*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0}, 5231/*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0}, 5232 5233/*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0}, 5234/*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S, 5235 HFC_IO_MODE_REGIO, 0}, 5236/*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0}, 5237/*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0}, 5238 5239/*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0}, 5240/*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0}, 5241/*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0}, 5242 5243/*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5244/*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0}, 5245/*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5246/*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0}, 5247 5248/*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0}, 5249/*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0}, 5250/*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0}, 5251 5252/*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0, 5253 HFC_IO_MODE_PLXSD, 0}, 5254/*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0, 5255 HFC_IO_MODE_PLXSD, 0}, 5256/*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0}, 5257/*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0}, 5258/*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0}, 5259/*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0, 5260 HFC_IO_MODE_EMBSD, XHFC_IRQ}, 5261/*32*/ {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0}, 5262/*33*/ {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0}, 5263/*34*/ {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0}, 5264}; 5265 5266#undef H 5267#define H(x) ((unsigned long)&hfcm_map[x]) 5268static struct pci_device_id hfmultipci_ids[] __devinitdata = { 5269 5270 /* Cards with HFC-4S Chip */ 5271 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5272 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */ 5273 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5274 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */ 5275 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5276 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */ 5277 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5278 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */ 5279 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5280 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */ 5281 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5282 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */ 5283 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5284 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */ 5285 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5286 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */ 5287 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 5288 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)}, 5289 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5290 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */ 5291 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5292 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)}, 5293 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5294 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */ 5295 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5296 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */ 5297 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5298 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */ 5299 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5300 0xb761, 0, 0, H(33)}, /* BN2S PCIe */ 5301 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, 5302 0xb762, 0, 0, H(34)}, /* BN4S PCIe */ 5303 5304 /* Cards with HFC-8S Chip */ 5305 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5306 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */ 5307 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5308 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */ 5309 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5310 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */ 5311 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5312 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */ 5313 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5314 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */ 5315 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5316 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */ 5317 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5318 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */ 5319 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5320 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */ 5321 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, 5322 PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S */ 5323 5324 5325 /* Cards with HFC-E1 Chip */ 5326 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5327 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */ 5328 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5329 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */ 5330 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5331 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */ 5332 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5333 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */ 5334 5335 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5336 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */ 5337 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5338 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */ 5339 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5340 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */ 5341 5342 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, 5343 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */ 5344 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, 5345 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */ 5346 5347 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, 5348 PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */ 5349 5350 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 }, 5351 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 }, 5352 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 }, 5353 {0, } 5354}; 5355#undef H 5356 5357MODULE_DEVICE_TABLE(pci, hfmultipci_ids); 5358 5359static int 5360hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 5361{ 5362 struct hm_map *m = (struct hm_map *)ent->driver_data; 5363 int ret; 5364 5365 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && ( 5366 ent->device == PCI_DEVICE_ID_CCD_HFC4S || 5367 ent->device == PCI_DEVICE_ID_CCD_HFC8S || 5368 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) { 5369 printk(KERN_ERR 5370 "Unknown HFC multiport controller (vendor:%04x device:%04x " 5371 "subvendor:%04x subdevice:%04x)\n", pdev->vendor, 5372 pdev->device, pdev->subsystem_vendor, 5373 pdev->subsystem_device); 5374 printk(KERN_ERR 5375 "Please contact the driver maintainer for support.\n"); 5376 return -ENODEV; 5377 } 5378 ret = hfcmulti_init(m, pdev, ent); 5379 if (ret) 5380 return ret; 5381 HFC_cnt++; 5382 printk(KERN_INFO "%d devices registered\n", HFC_cnt); 5383 return 0; 5384} 5385 5386static struct pci_driver hfcmultipci_driver = { 5387 .name = "hfc_multi", 5388 .probe = hfcmulti_probe, 5389 .remove = __devexit_p(hfc_remove_pci), 5390 .id_table = hfmultipci_ids, 5391}; 5392 5393static void __exit 5394HFCmulti_cleanup(void) 5395{ 5396 struct hfc_multi *card, *next; 5397 5398 /* get rid of all devices of this driver */ 5399 list_for_each_entry_safe(card, next, &HFClist, list) 5400 release_card(card); 5401 pci_unregister_driver(&hfcmultipci_driver); 5402} 5403 5404static int __init 5405HFCmulti_init(void) 5406{ 5407 int err; 5408 int i, xhfc = 0; 5409 struct hm_map m; 5410 5411 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION); 5412 5413#ifdef IRQ_DEBUG 5414 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__); 5415#endif 5416 5417 spin_lock_init(&HFClock); 5418 spin_lock_init(&plx_lock); 5419 5420 if (debug & DEBUG_HFCMULTI_INIT) 5421 printk(KERN_DEBUG "%s: init entered\n", __func__); 5422 5423 switch (poll) { 5424 case 0: 5425 poll_timer = 6; 5426 poll = 128; 5427 break; 5428 case 8: 5429 poll_timer = 2; 5430 break; 5431 case 16: 5432 poll_timer = 3; 5433 break; 5434 case 32: 5435 poll_timer = 4; 5436 break; 5437 case 64: 5438 poll_timer = 5; 5439 break; 5440 case 128: 5441 poll_timer = 6; 5442 break; 5443 case 256: 5444 poll_timer = 7; 5445 break; 5446 default: 5447 printk(KERN_ERR 5448 "%s: Wrong poll value (%d).\n", __func__, poll); 5449 err = -EINVAL; 5450 return err; 5451 5452 } 5453 5454 if (!clock) 5455 clock = 1; 5456 5457 /* Register the embedded devices. 5458 * This should be done before the PCI cards registration */ 5459 switch (hwid) { 5460 case HWID_MINIP4: 5461 xhfc = 1; 5462 m = hfcm_map[31]; 5463 break; 5464 case HWID_MINIP8: 5465 xhfc = 2; 5466 m = hfcm_map[31]; 5467 break; 5468 case HWID_MINIP16: 5469 xhfc = 4; 5470 m = hfcm_map[31]; 5471 break; 5472 default: 5473 xhfc = 0; 5474 } 5475 5476 for (i = 0; i < xhfc; ++i) { 5477 err = hfcmulti_init(&m, NULL, NULL); 5478 if (err) { 5479 printk(KERN_ERR "error registering embedded driver: " 5480 "%x\n", err); 5481 return err; 5482 } 5483 HFC_cnt++; 5484 printk(KERN_INFO "%d devices registered\n", HFC_cnt); 5485 } 5486 5487 /* Register the PCI cards */ 5488 err = pci_register_driver(&hfcmultipci_driver); 5489 if (err < 0) { 5490 printk(KERN_ERR "error registering pci driver: %x\n", err); 5491 return err; 5492 } 5493 5494 return 0; 5495} 5496 5497 5498module_init(HFCmulti_init); 5499module_exit(HFCmulti_cleanup); 5500