1/* 2 * ohci1394.h - driver for OHCI 1394 boards 3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au> 4 * Gord Peters <GordPeters@smarttech.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21#ifndef _OHCI1394_H 22#define _OHCI1394_H 23 24#include "ieee1394_types.h" 25#include <asm/io.h> 26 27#define OHCI1394_DRIVER_NAME "ohci1394" 28 29#define OHCI1394_MAX_AT_REQ_RETRIES 0xf 30#define OHCI1394_MAX_AT_RESP_RETRIES 0x2 31#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 32#define OHCI1394_MAX_SELF_ID_ERRORS 16 33 34#define AR_REQ_NUM_DESC 4 /* number of AR req descriptors */ 35#define AR_REQ_BUF_SIZE PAGE_SIZE /* size of AR req buffers */ 36#define AR_REQ_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */ 37 38#define AR_RESP_NUM_DESC 4 /* number of AR resp descriptors */ 39#define AR_RESP_BUF_SIZE PAGE_SIZE /* size of AR resp buffers */ 40#define AR_RESP_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */ 41 42#define IR_NUM_DESC 16 /* number of IR descriptors */ 43#define IR_BUF_SIZE PAGE_SIZE /* 4096 bytes/buffer */ 44#define IR_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */ 45 46#define IT_NUM_DESC 16 /* number of IT descriptors */ 47 48#define AT_REQ_NUM_DESC 32 /* number of AT req descriptors */ 49#define AT_RESP_NUM_DESC 32 /* number of AT resp descriptors */ 50 51#define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */ 52 53#define OHCI_CONFIG_ROM_LEN 1024 /* Length of the mapped configrom space */ 54 55#define OHCI1394_SI_DMA_BUF_SIZE 8192 /* length of the selfid buffer */ 56 57/* PCI configuration space addresses */ 58#define OHCI1394_PCI_HCI_Control 0x40 59 60struct dma_cmd { 61 u32 control; 62 u32 address; 63 u32 branchAddress; 64 u32 status; 65}; 66 67struct at_dma_prg { 68 struct dma_cmd begin; 69 quadlet_t data[4]; 70 struct dma_cmd end; 71 quadlet_t pad[4]; 72}; 73 74/* identify whether a DMA context is asynchronous or isochronous */ 75enum context_type { DMA_CTX_ASYNC_REQ, DMA_CTX_ASYNC_RESP, DMA_CTX_ISO }; 76 77/* DMA receive context */ 78struct dma_rcv_ctx { 79 struct ti_ohci *ohci; 80 enum context_type type; 81 int ctx; 82 unsigned int num_desc; 83 84 unsigned int buf_size; 85 unsigned int split_buf_size; 86 87 /* dma block descriptors */ 88 struct dma_cmd **prg_cpu; 89 dma_addr_t *prg_bus; 90 struct pci_pool *prg_pool; 91 92 /* dma buffers */ 93 quadlet_t **buf_cpu; 94 dma_addr_t *buf_bus; 95 96 unsigned int buf_ind; 97 unsigned int buf_offset; 98 quadlet_t *spb; 99 spinlock_t lock; 100 struct tasklet_struct task; 101 int ctrlClear; 102 int ctrlSet; 103 int cmdPtr; 104 int ctxtMatch; 105}; 106 107/* DMA transmit context */ 108struct dma_trm_ctx { 109 struct ti_ohci *ohci; 110 enum context_type type; 111 int ctx; 112 unsigned int num_desc; 113 114 /* dma block descriptors */ 115 struct at_dma_prg **prg_cpu; 116 dma_addr_t *prg_bus; 117 struct pci_pool *prg_pool; 118 119 unsigned int prg_ind; 120 unsigned int sent_ind; 121 int free_prgs; 122 quadlet_t *branchAddrPtr; 123 124 /* list of packets inserted in the AT FIFO */ 125 struct list_head fifo_list; 126 127 /* list of pending packets to be inserted in the AT FIFO */ 128 struct list_head pending_list; 129 130 spinlock_t lock; 131 struct tasklet_struct task; 132 int ctrlClear; 133 int ctrlSet; 134 int cmdPtr; 135}; 136 137struct ohci1394_iso_tasklet { 138 struct tasklet_struct tasklet; 139 struct list_head link; 140 int context; 141 enum { OHCI_ISO_TRANSMIT, OHCI_ISO_RECEIVE, 142 OHCI_ISO_MULTICHANNEL_RECEIVE } type; 143}; 144 145struct ti_ohci { 146 struct pci_dev *dev; 147 148 enum { 149 OHCI_INIT_ALLOC_HOST, 150 OHCI_INIT_HAVE_MEM_REGION, 151 OHCI_INIT_HAVE_IOMAPPING, 152 OHCI_INIT_HAVE_CONFIG_ROM_BUFFER, 153 OHCI_INIT_HAVE_SELFID_BUFFER, 154 OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE, 155 OHCI_INIT_HAVE_IRQ, 156 OHCI_INIT_DONE, 157 } init_state; 158 159 /* remapped memory spaces */ 160 void __iomem *registers; 161 162 /* dma buffer for self-id packets */ 163 quadlet_t *selfid_buf_cpu; 164 dma_addr_t selfid_buf_bus; 165 166 /* buffer for csr config rom */ 167 quadlet_t *csr_config_rom_cpu; 168 dma_addr_t csr_config_rom_bus; 169 int csr_config_rom_length; 170 171 unsigned int max_packet_size; 172 173 /* async receive */ 174 struct dma_rcv_ctx ar_resp_context; 175 struct dma_rcv_ctx ar_req_context; 176 177 /* async transmit */ 178 struct dma_trm_ctx at_resp_context; 179 struct dma_trm_ctx at_req_context; 180 181 /* iso receive */ 182 int nb_iso_rcv_ctx; 183 unsigned long ir_ctx_usage; /* use test_and_set_bit() for atomicity */ 184 unsigned long ir_multichannel_used; /* ditto */ 185 spinlock_t IR_channel_lock; 186 187 /* iso transmit */ 188 int nb_iso_xmit_ctx; 189 unsigned long it_ctx_usage; /* use test_and_set_bit() for atomicity */ 190 191 u64 ISO_channel_usage; 192 193 /* IEEE-1394 part follows */ 194 struct hpsb_host *host; 195 196 int phyid, isroot; 197 198 spinlock_t phy_reg_lock; 199 spinlock_t event_lock; 200 201 int self_id_errors; 202 203 /* Tasklets for iso receive and transmit, used by video1394 204 * and dv1394 */ 205 struct list_head iso_tasklet_list; 206 spinlock_t iso_tasklet_list_lock; 207 208 /* Swap the selfid buffer? */ 209 unsigned int selfid_swap:1; 210 /* Some Apple chipset seem to swap incoming headers for us */ 211 unsigned int no_swap_incoming:1; 212 213 /* Force extra paranoia checking on bus-reset handling */ 214 unsigned int check_busreset:1; 215}; 216 217static inline int cross_bound(unsigned long addr, unsigned int size) 218{ 219 if (size == 0) 220 return 0; 221 222 if (size > PAGE_SIZE) 223 return 1; 224 225 if (addr >> PAGE_SHIFT != (addr + size - 1) >> PAGE_SHIFT) 226 return 1; 227 228 return 0; 229} 230 231/* 232 * Register read and write helper functions. 233 */ 234static inline void reg_write(const struct ti_ohci *ohci, int offset, u32 data) 235{ 236 writel(data, ohci->registers + offset); 237} 238 239static inline u32 reg_read(const struct ti_ohci *ohci, int offset) 240{ 241 return readl(ohci->registers + offset); 242} 243 244 245/* 2 KiloBytes of register space */ 246#define OHCI1394_REGISTER_SIZE 0x800 247 248/* Offsets relative to context bases defined below */ 249 250#define OHCI1394_ContextControlSet 0x000 251#define OHCI1394_ContextControlClear 0x004 252#define OHCI1394_ContextCommandPtr 0x00C 253 254/* register map */ 255#define OHCI1394_Version 0x000 256#define OHCI1394_GUID_ROM 0x004 257#define OHCI1394_ATRetries 0x008 258#define OHCI1394_CSRData 0x00C 259#define OHCI1394_CSRCompareData 0x010 260#define OHCI1394_CSRControl 0x014 261#define OHCI1394_ConfigROMhdr 0x018 262#define OHCI1394_BusID 0x01C 263#define OHCI1394_BusOptions 0x020 264#define OHCI1394_GUIDHi 0x024 265#define OHCI1394_GUIDLo 0x028 266#define OHCI1394_ConfigROMmap 0x034 267#define OHCI1394_PostedWriteAddressLo 0x038 268#define OHCI1394_PostedWriteAddressHi 0x03C 269#define OHCI1394_VendorID 0x040 270#define OHCI1394_HCControlSet 0x050 271#define OHCI1394_HCControlClear 0x054 272#define OHCI1394_HCControl_noByteSwap 0x40000000 273#define OHCI1394_HCControl_programPhyEnable 0x00800000 274#define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000 275#define OHCI1394_HCControl_LPS 0x00080000 276#define OHCI1394_HCControl_postedWriteEnable 0x00040000 277#define OHCI1394_HCControl_linkEnable 0x00020000 278#define OHCI1394_HCControl_softReset 0x00010000 279#define OHCI1394_SelfIDBuffer 0x064 280#define OHCI1394_SelfIDCount 0x068 281#define OHCI1394_IRMultiChanMaskHiSet 0x070 282#define OHCI1394_IRMultiChanMaskHiClear 0x074 283#define OHCI1394_IRMultiChanMaskLoSet 0x078 284#define OHCI1394_IRMultiChanMaskLoClear 0x07C 285#define OHCI1394_IntEventSet 0x080 286#define OHCI1394_IntEventClear 0x084 287#define OHCI1394_IntMaskSet 0x088 288#define OHCI1394_IntMaskClear 0x08C 289#define OHCI1394_IsoXmitIntEventSet 0x090 290#define OHCI1394_IsoXmitIntEventClear 0x094 291#define OHCI1394_IsoXmitIntMaskSet 0x098 292#define OHCI1394_IsoXmitIntMaskClear 0x09C 293#define OHCI1394_IsoRecvIntEventSet 0x0A0 294#define OHCI1394_IsoRecvIntEventClear 0x0A4 295#define OHCI1394_IsoRecvIntMaskSet 0x0A8 296#define OHCI1394_IsoRecvIntMaskClear 0x0AC 297#define OHCI1394_InitialBandwidthAvailable 0x0B0 298#define OHCI1394_InitialChannelsAvailableHi 0x0B4 299#define OHCI1394_InitialChannelsAvailableLo 0x0B8 300#define OHCI1394_FairnessControl 0x0DC 301#define OHCI1394_LinkControlSet 0x0E0 302#define OHCI1394_LinkControlClear 0x0E4 303#define OHCI1394_LinkControl_RcvSelfID 0x00000200 304#define OHCI1394_LinkControl_RcvPhyPkt 0x00000400 305#define OHCI1394_LinkControl_CycleTimerEnable 0x00100000 306#define OHCI1394_LinkControl_CycleMaster 0x00200000 307#define OHCI1394_LinkControl_CycleSource 0x00400000 308#define OHCI1394_NodeID 0x0E8 309#define OHCI1394_PhyControl 0x0EC 310#define OHCI1394_IsochronousCycleTimer 0x0F0 311#define OHCI1394_AsReqFilterHiSet 0x100 312#define OHCI1394_AsReqFilterHiClear 0x104 313#define OHCI1394_AsReqFilterLoSet 0x108 314#define OHCI1394_AsReqFilterLoClear 0x10C 315#define OHCI1394_PhyReqFilterHiSet 0x110 316#define OHCI1394_PhyReqFilterHiClear 0x114 317#define OHCI1394_PhyReqFilterLoSet 0x118 318#define OHCI1394_PhyReqFilterLoClear 0x11C 319#define OHCI1394_PhyUpperBound 0x120 320 321#define OHCI1394_AsReqTrContextBase 0x180 322#define OHCI1394_AsReqTrContextControlSet 0x180 323#define OHCI1394_AsReqTrContextControlClear 0x184 324#define OHCI1394_AsReqTrCommandPtr 0x18C 325 326#define OHCI1394_AsRspTrContextBase 0x1A0 327#define OHCI1394_AsRspTrContextControlSet 0x1A0 328#define OHCI1394_AsRspTrContextControlClear 0x1A4 329#define OHCI1394_AsRspTrCommandPtr 0x1AC 330 331#define OHCI1394_AsReqRcvContextBase 0x1C0 332#define OHCI1394_AsReqRcvContextControlSet 0x1C0 333#define OHCI1394_AsReqRcvContextControlClear 0x1C4 334#define OHCI1394_AsReqRcvCommandPtr 0x1CC 335 336#define OHCI1394_AsRspRcvContextBase 0x1E0 337#define OHCI1394_AsRspRcvContextControlSet 0x1E0 338#define OHCI1394_AsRspRcvContextControlClear 0x1E4 339#define OHCI1394_AsRspRcvCommandPtr 0x1EC 340 341/* Isochronous transmit registers */ 342/* Add (16 * n) for context n */ 343#define OHCI1394_IsoXmitContextBase 0x200 344#define OHCI1394_IsoXmitContextControlSet 0x200 345#define OHCI1394_IsoXmitContextControlClear 0x204 346#define OHCI1394_IsoXmitCommandPtr 0x20C 347 348/* Isochronous receive registers */ 349/* Add (32 * n) for context n */ 350#define OHCI1394_IsoRcvContextBase 0x400 351#define OHCI1394_IsoRcvContextControlSet 0x400 352#define OHCI1394_IsoRcvContextControlClear 0x404 353#define OHCI1394_IsoRcvCommandPtr 0x40C 354#define OHCI1394_IsoRcvContextMatch 0x410 355 356/* Interrupts Mask/Events */ 357 358#define OHCI1394_reqTxComplete 0x00000001 359#define OHCI1394_respTxComplete 0x00000002 360#define OHCI1394_ARRQ 0x00000004 361#define OHCI1394_ARRS 0x00000008 362#define OHCI1394_RQPkt 0x00000010 363#define OHCI1394_RSPkt 0x00000020 364#define OHCI1394_isochTx 0x00000040 365#define OHCI1394_isochRx 0x00000080 366#define OHCI1394_postedWriteErr 0x00000100 367#define OHCI1394_lockRespErr 0x00000200 368#define OHCI1394_selfIDComplete 0x00010000 369#define OHCI1394_busReset 0x00020000 370#define OHCI1394_phy 0x00080000 371#define OHCI1394_cycleSynch 0x00100000 372#define OHCI1394_cycle64Seconds 0x00200000 373#define OHCI1394_cycleLost 0x00400000 374#define OHCI1394_cycleInconsistent 0x00800000 375#define OHCI1394_unrecoverableError 0x01000000 376#define OHCI1394_cycleTooLong 0x02000000 377#define OHCI1394_phyRegRcvd 0x04000000 378#define OHCI1394_masterIntEnable 0x80000000 379 380/* DMA Control flags */ 381#define DMA_CTL_OUTPUT_MORE 0x00000000 382#define DMA_CTL_OUTPUT_LAST 0x10000000 383#define DMA_CTL_INPUT_MORE 0x20000000 384#define DMA_CTL_INPUT_LAST 0x30000000 385#define DMA_CTL_UPDATE 0x08000000 386#define DMA_CTL_IMMEDIATE 0x02000000 387#define DMA_CTL_IRQ 0x00300000 388#define DMA_CTL_BRANCH 0x000c0000 389#define DMA_CTL_WAIT 0x00030000 390 391/* OHCI evt_* error types, table 3-2 of the OHCI 1.1 spec. */ 392#define EVT_NO_STATUS 0x0 /* No event status */ 393#define EVT_RESERVED_A 0x1 /* Reserved, not used !!! */ 394#define EVT_LONG_PACKET 0x2 /* The revc data was longer than the buf */ 395#define EVT_MISSING_ACK 0x3 /* A subaction gap was detected before an ack 396 arrived, or recv'd ack had a parity error */ 397#define EVT_UNDERRUN 0x4 /* Underrun on corresponding FIFO, packet 398 truncated */ 399#define EVT_OVERRUN 0x5 /* A recv FIFO overflowed on reception of ISO 400 packet */ 401#define EVT_DESCRIPTOR_READ 0x6 /* An unrecoverable error occurred while host was 402 reading a descriptor block */ 403#define EVT_DATA_READ 0x7 /* An error occurred while host controller was 404 attempting to read from host memory in the data 405 stage of descriptor processing */ 406#define EVT_DATA_WRITE 0x8 /* An error occurred while host controller was 407 attempting to write either during the data stage 408 of descriptor processing, or when processing a single 409 16-bit host memory write */ 410#define EVT_BUS_RESET 0x9 /* Identifies a PHY packet in the recv buffer as 411 being a synthesized bus reset packet */ 412#define EVT_TIMEOUT 0xa /* Indicates that the asynchronous transmit response 413 packet expired and was not transmitted, or that an 414 IT DMA context experienced a skip processing overflow */ 415#define EVT_TCODE_ERR 0xb /* A bad tCode is associated with this packet. 416 The packet was flushed */ 417#define EVT_RESERVED_B 0xc /* Reserved, not used !!! */ 418#define EVT_RESERVED_C 0xd /* Reserved, not used !!! */ 419#define EVT_UNKNOWN 0xe /* An error condition has occurred that cannot be 420 represented by any other event codes defined herein. */ 421#define EVT_FLUSHED 0xf /* Send by the link side of output FIFO when asynchronous 422 packets are being flushed due to a bus reset. */ 423 424#define OHCI1394_TCODE_PHY 0xE 425 426/* Node offset map (phys DMA area, posted write area). 427 * The value of OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED may be modified but must 428 * be lower than OHCI1394_MIDDLE_ADDRESS_SPACE. 429 * OHCI1394_PHYS_UPPER_BOUND_FIXED and OHCI1394_MIDDLE_ADDRESS_SPACE are 430 * constants given by the OHCI spec. 431 */ 432#define OHCI1394_PHYS_UPPER_BOUND_FIXED 0x000100000000ULL /* 4 GB */ 433#define OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED 0x010000000000ULL /* 1 TB */ 434#define OHCI1394_MIDDLE_ADDRESS_SPACE 0xffff00000000ULL 435 436void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, 437 int type, 438 void (*func)(unsigned long), 439 unsigned long data); 440int ohci1394_register_iso_tasklet(struct ti_ohci *ohci, 441 struct ohci1394_iso_tasklet *tasklet); 442void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci, 443 struct ohci1394_iso_tasklet *tasklet); 444int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg); 445struct ti_ohci *ohci1394_get_struct(int card_num); 446 447#endif 448