1 2 3#include <linux/types.h> 4#include <linux/module.h> 5#include <linux/kernel.h> 6#include <linux/delay.h> 7#include <linux/blkdev.h> 8#include <linux/interrupt.h> 9#include <linux/pci.h> 10#include <linux/init.h> 11#include <linux/ide.h> 12#include <linux/slab.h> 13 14#include <asm/uaccess.h> 15#include <asm/io.h> 16 17#define DRV_NAME "hpt366" 18 19/* various tuning parameters */ 20#undef HPT_RESET_STATE_ENGINE 21#undef HPT_DELAY_INTERRUPT 22 23static const char *bad_ata100_5[] = { 24 "IBM-DTLA-307075", 25 "IBM-DTLA-307060", 26 "IBM-DTLA-307045", 27 "IBM-DTLA-307030", 28 "IBM-DTLA-307020", 29 "IBM-DTLA-307015", 30 "IBM-DTLA-305040", 31 "IBM-DTLA-305030", 32 "IBM-DTLA-305020", 33 "IC35L010AVER07-0", 34 "IC35L020AVER07-0", 35 "IC35L030AVER07-0", 36 "IC35L040AVER07-0", 37 "IC35L060AVER07-0", 38 "WDC AC310200R", 39 NULL 40}; 41 42static const char *bad_ata66_4[] = { 43 "IBM-DTLA-307075", 44 "IBM-DTLA-307060", 45 "IBM-DTLA-307045", 46 "IBM-DTLA-307030", 47 "IBM-DTLA-307020", 48 "IBM-DTLA-307015", 49 "IBM-DTLA-305040", 50 "IBM-DTLA-305030", 51 "IBM-DTLA-305020", 52 "IC35L010AVER07-0", 53 "IC35L020AVER07-0", 54 "IC35L030AVER07-0", 55 "IC35L040AVER07-0", 56 "IC35L060AVER07-0", 57 "WDC AC310200R", 58 "MAXTOR STM3320620A", 59 NULL 60}; 61 62static const char *bad_ata66_3[] = { 63 "WDC AC310200R", 64 NULL 65}; 66 67static const char *bad_ata33[] = { 68 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 69 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 70 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 71 "Maxtor 90510D4", 72 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 73 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 74 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 75 NULL 76}; 77 78static u8 xfer_speeds[] = { 79 XFER_UDMA_6, 80 XFER_UDMA_5, 81 XFER_UDMA_4, 82 XFER_UDMA_3, 83 XFER_UDMA_2, 84 XFER_UDMA_1, 85 XFER_UDMA_0, 86 87 XFER_MW_DMA_2, 88 XFER_MW_DMA_1, 89 XFER_MW_DMA_0, 90 91 XFER_PIO_4, 92 XFER_PIO_3, 93 XFER_PIO_2, 94 XFER_PIO_1, 95 XFER_PIO_0 96}; 97 98/* Key for bus clock timings 99 * 36x 37x 100 * bits bits 101 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 102 * cycles = value + 1 103 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 104 * cycles = value + 1 105 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 106 * register access. 107 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 108 * register access. 109 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 110 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. 111 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and 112 * MW DMA xfer. 113 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for 114 * task file register access. 115 * 28 28 UDMA enable. 116 * 29 29 DMA enable. 117 * 30 30 PIO MST enable. If set, the chip is in bus master mode during 118 * PIO xfer. 119 * 31 31 FIFO enable. 120 */ 121 122static u32 forty_base_hpt36x[] = { 123 /* XFER_UDMA_6 */ 0x900fd943, 124 /* XFER_UDMA_5 */ 0x900fd943, 125 /* XFER_UDMA_4 */ 0x900fd943, 126 /* XFER_UDMA_3 */ 0x900ad943, 127 /* XFER_UDMA_2 */ 0x900bd943, 128 /* XFER_UDMA_1 */ 0x9008d943, 129 /* XFER_UDMA_0 */ 0x9008d943, 130 131 /* XFER_MW_DMA_2 */ 0xa008d943, 132 /* XFER_MW_DMA_1 */ 0xa010d955, 133 /* XFER_MW_DMA_0 */ 0xa010d9fc, 134 135 /* XFER_PIO_4 */ 0xc008d963, 136 /* XFER_PIO_3 */ 0xc010d974, 137 /* XFER_PIO_2 */ 0xc010d997, 138 /* XFER_PIO_1 */ 0xc010d9c7, 139 /* XFER_PIO_0 */ 0xc018d9d9 140}; 141 142static u32 thirty_three_base_hpt36x[] = { 143 /* XFER_UDMA_6 */ 0x90c9a731, 144 /* XFER_UDMA_5 */ 0x90c9a731, 145 /* XFER_UDMA_4 */ 0x90c9a731, 146 /* XFER_UDMA_3 */ 0x90cfa731, 147 /* XFER_UDMA_2 */ 0x90caa731, 148 /* XFER_UDMA_1 */ 0x90cba731, 149 /* XFER_UDMA_0 */ 0x90c8a731, 150 151 /* XFER_MW_DMA_2 */ 0xa0c8a731, 152 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ 153 /* XFER_MW_DMA_0 */ 0xa0c8a797, 154 155 /* XFER_PIO_4 */ 0xc0c8a731, 156 /* XFER_PIO_3 */ 0xc0c8a742, 157 /* XFER_PIO_2 */ 0xc0d0a753, 158 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ 159 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ 160}; 161 162static u32 twenty_five_base_hpt36x[] = { 163 /* XFER_UDMA_6 */ 0x90c98521, 164 /* XFER_UDMA_5 */ 0x90c98521, 165 /* XFER_UDMA_4 */ 0x90c98521, 166 /* XFER_UDMA_3 */ 0x90cf8521, 167 /* XFER_UDMA_2 */ 0x90cf8521, 168 /* XFER_UDMA_1 */ 0x90cb8521, 169 /* XFER_UDMA_0 */ 0x90cb8521, 170 171 /* XFER_MW_DMA_2 */ 0xa0ca8521, 172 /* XFER_MW_DMA_1 */ 0xa0ca8532, 173 /* XFER_MW_DMA_0 */ 0xa0ca8575, 174 175 /* XFER_PIO_4 */ 0xc0ca8521, 176 /* XFER_PIO_3 */ 0xc0ca8532, 177 /* XFER_PIO_2 */ 0xc0ca8542, 178 /* XFER_PIO_1 */ 0xc0d08572, 179 /* XFER_PIO_0 */ 0xc0d08585 180}; 181 182/* 183 * The following are the new timing tables with PIO mode data/taskfile transfer 184 * overclocking fixed... 185 */ 186 187/* This table is taken from the HPT370 data manual rev. 1.02 */ 188static u32 thirty_three_base_hpt37x[] = { 189 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */ 190 /* XFER_UDMA_5 */ 0x16455031, 191 /* XFER_UDMA_4 */ 0x16455031, 192 /* XFER_UDMA_3 */ 0x166d5031, 193 /* XFER_UDMA_2 */ 0x16495031, 194 /* XFER_UDMA_1 */ 0x164d5033, 195 /* XFER_UDMA_0 */ 0x16515097, 196 197 /* XFER_MW_DMA_2 */ 0x26515031, 198 /* XFER_MW_DMA_1 */ 0x26515033, 199 /* XFER_MW_DMA_0 */ 0x26515097, 200 201 /* XFER_PIO_4 */ 0x06515021, 202 /* XFER_PIO_3 */ 0x06515022, 203 /* XFER_PIO_2 */ 0x06515033, 204 /* XFER_PIO_1 */ 0x06915065, 205 /* XFER_PIO_0 */ 0x06d1508a 206}; 207 208static u32 fifty_base_hpt37x[] = { 209 /* XFER_UDMA_6 */ 0x1a861842, 210 /* XFER_UDMA_5 */ 0x1a861842, 211 /* XFER_UDMA_4 */ 0x1aae1842, 212 /* XFER_UDMA_3 */ 0x1a8e1842, 213 /* XFER_UDMA_2 */ 0x1a0e1842, 214 /* XFER_UDMA_1 */ 0x1a161854, 215 /* XFER_UDMA_0 */ 0x1a1a18ea, 216 217 /* XFER_MW_DMA_2 */ 0x2a821842, 218 /* XFER_MW_DMA_1 */ 0x2a821854, 219 /* XFER_MW_DMA_0 */ 0x2a8218ea, 220 221 /* XFER_PIO_4 */ 0x0a821842, 222 /* XFER_PIO_3 */ 0x0a821843, 223 /* XFER_PIO_2 */ 0x0a821855, 224 /* XFER_PIO_1 */ 0x0ac218a8, 225 /* XFER_PIO_0 */ 0x0b02190c 226}; 227 228static u32 sixty_six_base_hpt37x[] = { 229 /* XFER_UDMA_6 */ 0x1c86fe62, 230 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */ 231 /* XFER_UDMA_4 */ 0x1c8afe62, 232 /* XFER_UDMA_3 */ 0x1c8efe62, 233 /* XFER_UDMA_2 */ 0x1c92fe62, 234 /* XFER_UDMA_1 */ 0x1c9afe62, 235 /* XFER_UDMA_0 */ 0x1c82fe62, 236 237 /* XFER_MW_DMA_2 */ 0x2c82fe62, 238 /* XFER_MW_DMA_1 */ 0x2c82fe66, 239 /* XFER_MW_DMA_0 */ 0x2c82ff2e, 240 241 /* XFER_PIO_4 */ 0x0c82fe62, 242 /* XFER_PIO_3 */ 0x0c82fe84, 243 /* XFER_PIO_2 */ 0x0c82fea6, 244 /* XFER_PIO_1 */ 0x0d02ff26, 245 /* XFER_PIO_0 */ 0x0d42ff7f 246}; 247 248#define HPT371_ALLOW_ATA133_6 1 249#define HPT302_ALLOW_ATA133_6 1 250#define HPT372_ALLOW_ATA133_6 1 251#define HPT370_ALLOW_ATA100_5 0 252#define HPT366_ALLOW_ATA66_4 1 253#define HPT366_ALLOW_ATA66_3 1 254 255/* Supported ATA clock frequencies */ 256enum ata_clock { 257 ATA_CLOCK_25MHZ, 258 ATA_CLOCK_33MHZ, 259 ATA_CLOCK_40MHZ, 260 ATA_CLOCK_50MHZ, 261 ATA_CLOCK_66MHZ, 262 NUM_ATA_CLOCKS 263}; 264 265struct hpt_timings { 266 u32 pio_mask; 267 u32 dma_mask; 268 u32 ultra_mask; 269 u32 *clock_table[NUM_ATA_CLOCKS]; 270}; 271 272/* 273 * Hold all the HighPoint chip information in one place. 274 */ 275 276struct hpt_info { 277 char *chip_name; /* Chip name */ 278 u8 chip_type; /* Chip type */ 279 u8 udma_mask; /* Allowed UltraDMA modes mask. */ 280 u8 dpll_clk; /* DPLL clock in MHz */ 281 u8 pci_clk; /* PCI clock in MHz */ 282 struct hpt_timings *timings; /* Chipset timing data */ 283 u8 clock; /* ATA clock selected */ 284}; 285 286/* Supported HighPoint chips */ 287enum { 288 HPT36x, 289 HPT370, 290 HPT370A, 291 HPT374, 292 HPT372, 293 HPT372A, 294 HPT302, 295 HPT371, 296 HPT372N, 297 HPT302N, 298 HPT371N 299}; 300 301static struct hpt_timings hpt36x_timings = { 302 .pio_mask = 0xc1f8ffff, 303 .dma_mask = 0x303800ff, 304 .ultra_mask = 0x30070000, 305 .clock_table = { 306 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x, 307 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x, 308 [ATA_CLOCK_40MHZ] = forty_base_hpt36x, 309 [ATA_CLOCK_50MHZ] = NULL, 310 [ATA_CLOCK_66MHZ] = NULL 311 } 312}; 313 314static struct hpt_timings hpt37x_timings = { 315 .pio_mask = 0xcfc3ffff, 316 .dma_mask = 0x31c001ff, 317 .ultra_mask = 0x303c0000, 318 .clock_table = { 319 [ATA_CLOCK_25MHZ] = NULL, 320 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x, 321 [ATA_CLOCK_40MHZ] = NULL, 322 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x, 323 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x 324 } 325}; 326 327static const struct hpt_info hpt36x __devinitdata = { 328 .chip_name = "HPT36x", 329 .chip_type = HPT36x, 330 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2, 331 .dpll_clk = 0, /* no DPLL */ 332 .timings = &hpt36x_timings 333}; 334 335static const struct hpt_info hpt370 __devinitdata = { 336 .chip_name = "HPT370", 337 .chip_type = HPT370, 338 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 339 .dpll_clk = 48, 340 .timings = &hpt37x_timings 341}; 342 343static const struct hpt_info hpt370a __devinitdata = { 344 .chip_name = "HPT370A", 345 .chip_type = HPT370A, 346 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 347 .dpll_clk = 48, 348 .timings = &hpt37x_timings 349}; 350 351static const struct hpt_info hpt374 __devinitdata = { 352 .chip_name = "HPT374", 353 .chip_type = HPT374, 354 .udma_mask = ATA_UDMA5, 355 .dpll_clk = 48, 356 .timings = &hpt37x_timings 357}; 358 359static const struct hpt_info hpt372 __devinitdata = { 360 .chip_name = "HPT372", 361 .chip_type = HPT372, 362 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 363 .dpll_clk = 55, 364 .timings = &hpt37x_timings 365}; 366 367static const struct hpt_info hpt372a __devinitdata = { 368 .chip_name = "HPT372A", 369 .chip_type = HPT372A, 370 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 371 .dpll_clk = 66, 372 .timings = &hpt37x_timings 373}; 374 375static const struct hpt_info hpt302 __devinitdata = { 376 .chip_name = "HPT302", 377 .chip_type = HPT302, 378 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 379 .dpll_clk = 66, 380 .timings = &hpt37x_timings 381}; 382 383static const struct hpt_info hpt371 __devinitdata = { 384 .chip_name = "HPT371", 385 .chip_type = HPT371, 386 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 387 .dpll_clk = 66, 388 .timings = &hpt37x_timings 389}; 390 391static const struct hpt_info hpt372n __devinitdata = { 392 .chip_name = "HPT372N", 393 .chip_type = HPT372N, 394 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 395 .dpll_clk = 77, 396 .timings = &hpt37x_timings 397}; 398 399static const struct hpt_info hpt302n __devinitdata = { 400 .chip_name = "HPT302N", 401 .chip_type = HPT302N, 402 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 403 .dpll_clk = 77, 404 .timings = &hpt37x_timings 405}; 406 407static const struct hpt_info hpt371n __devinitdata = { 408 .chip_name = "HPT371N", 409 .chip_type = HPT371N, 410 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 411 .dpll_clk = 77, 412 .timings = &hpt37x_timings 413}; 414 415static int check_in_drive_list(ide_drive_t *drive, const char **list) 416{ 417 char *m = (char *)&drive->id[ATA_ID_PROD]; 418 419 while (*list) 420 if (!strcmp(*list++, m)) 421 return 1; 422 return 0; 423} 424 425static struct hpt_info *hpt3xx_get_info(struct device *dev) 426{ 427 struct ide_host *host = dev_get_drvdata(dev); 428 struct hpt_info *info = (struct hpt_info *)host->host_priv; 429 430 return dev == host->dev[1] ? info + 1 : info; 431} 432 433/* 434 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 435 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 436 */ 437 438static u8 hpt3xx_udma_filter(ide_drive_t *drive) 439{ 440 ide_hwif_t *hwif = drive->hwif; 441 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 442 u8 mask = hwif->ultra_mask; 443 444 switch (info->chip_type) { 445 case HPT36x: 446 if (!HPT366_ALLOW_ATA66_4 || 447 check_in_drive_list(drive, bad_ata66_4)) 448 mask = ATA_UDMA3; 449 450 if (!HPT366_ALLOW_ATA66_3 || 451 check_in_drive_list(drive, bad_ata66_3)) 452 mask = ATA_UDMA2; 453 break; 454 case HPT370: 455 if (!HPT370_ALLOW_ATA100_5 || 456 check_in_drive_list(drive, bad_ata100_5)) 457 mask = ATA_UDMA4; 458 break; 459 case HPT370A: 460 if (!HPT370_ALLOW_ATA100_5 || 461 check_in_drive_list(drive, bad_ata100_5)) 462 return ATA_UDMA4; 463 case HPT372 : 464 case HPT372A: 465 case HPT372N: 466 case HPT374 : 467 if (ata_id_is_sata(drive->id)) 468 mask &= ~0x0e; 469 /* Fall thru */ 470 default: 471 return mask; 472 } 473 474 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; 475} 476 477static u8 hpt3xx_mdma_filter(ide_drive_t *drive) 478{ 479 ide_hwif_t *hwif = drive->hwif; 480 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 481 482 switch (info->chip_type) { 483 case HPT372 : 484 case HPT372A: 485 case HPT372N: 486 case HPT374 : 487 if (ata_id_is_sata(drive->id)) 488 return 0x00; 489 /* Fall thru */ 490 default: 491 return 0x07; 492 } 493} 494 495static u32 get_speed_setting(u8 speed, struct hpt_info *info) 496{ 497 int i; 498 499 /* 500 * Lookup the transfer mode table to get the index into 501 * the timing table. 502 * 503 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. 504 */ 505 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) 506 if (xfer_speeds[i] == speed) 507 break; 508 509 return info->timings->clock_table[info->clock][i]; 510} 511 512static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) 513{ 514 struct pci_dev *dev = to_pci_dev(hwif->dev); 515 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 516 struct hpt_timings *t = info->timings; 517 u8 itr_addr = 0x40 + (drive->dn * 4); 518 u32 old_itr = 0; 519 const u8 speed = drive->dma_mode; 520 u32 new_itr = get_speed_setting(speed, info); 521 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : 522 (speed < XFER_UDMA_0 ? t->dma_mask : 523 t->ultra_mask); 524 525 pci_read_config_dword(dev, itr_addr, &old_itr); 526 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask); 527 /* 528 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) 529 * to avoid problems handling I/O errors later 530 */ 531 new_itr &= ~0xc0000000; 532 533 pci_write_config_dword(dev, itr_addr, new_itr); 534} 535 536static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 537{ 538 drive->dma_mode = drive->pio_mode; 539 hpt3xx_set_mode(hwif, drive); 540} 541 542static void hpt3xx_maskproc(ide_drive_t *drive, int mask) 543{ 544 ide_hwif_t *hwif = drive->hwif; 545 struct pci_dev *dev = to_pci_dev(hwif->dev); 546 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 547 548 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0) 549 return; 550 551 if (info->chip_type >= HPT370) { 552 u8 scr1 = 0; 553 554 pci_read_config_byte(dev, 0x5a, &scr1); 555 if (((scr1 & 0x10) >> 4) != mask) { 556 if (mask) 557 scr1 |= 0x10; 558 else 559 scr1 &= ~0x10; 560 pci_write_config_byte(dev, 0x5a, scr1); 561 } 562 } else if (mask) 563 disable_irq(hwif->irq); 564 else 565 enable_irq(hwif->irq); 566} 567 568/* 569 * This is specific to the HPT366 UDMA chipset 570 * by HighPoint|Triones Technologies, Inc. 571 */ 572static void hpt366_dma_lost_irq(ide_drive_t *drive) 573{ 574 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 575 u8 mcr1 = 0, mcr3 = 0, scr1 = 0; 576 577 pci_read_config_byte(dev, 0x50, &mcr1); 578 pci_read_config_byte(dev, 0x52, &mcr3); 579 pci_read_config_byte(dev, 0x5a, &scr1); 580 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", 581 drive->name, __func__, mcr1, mcr3, scr1); 582 if (scr1 & 0x10) 583 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 584 ide_dma_lost_irq(drive); 585} 586 587static void hpt370_clear_engine(ide_drive_t *drive) 588{ 589 ide_hwif_t *hwif = drive->hwif; 590 struct pci_dev *dev = to_pci_dev(hwif->dev); 591 592 pci_write_config_byte(dev, hwif->select_data, 0x37); 593 udelay(10); 594} 595 596static void hpt370_irq_timeout(ide_drive_t *drive) 597{ 598 ide_hwif_t *hwif = drive->hwif; 599 struct pci_dev *dev = to_pci_dev(hwif->dev); 600 u16 bfifo = 0; 601 u8 dma_cmd; 602 603 pci_read_config_word(dev, hwif->select_data + 2, &bfifo); 604 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); 605 606 /* get DMA command mode */ 607 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 608 /* stop DMA */ 609 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD); 610 hpt370_clear_engine(drive); 611} 612 613static void hpt370_dma_start(ide_drive_t *drive) 614{ 615#ifdef HPT_RESET_STATE_ENGINE 616 hpt370_clear_engine(drive); 617#endif 618 ide_dma_start(drive); 619} 620 621static int hpt370_dma_end(ide_drive_t *drive) 622{ 623 ide_hwif_t *hwif = drive->hwif; 624 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 625 626 if (dma_stat & ATA_DMA_ACTIVE) { 627 /* wait a little */ 628 udelay(20); 629 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 630 if (dma_stat & ATA_DMA_ACTIVE) 631 hpt370_irq_timeout(drive); 632 } 633 return ide_dma_end(drive); 634} 635 636/* returns 1 if DMA IRQ issued, 0 otherwise */ 637static int hpt374_dma_test_irq(ide_drive_t *drive) 638{ 639 ide_hwif_t *hwif = drive->hwif; 640 struct pci_dev *dev = to_pci_dev(hwif->dev); 641 u16 bfifo = 0; 642 u8 dma_stat; 643 644 pci_read_config_word(dev, hwif->select_data + 2, &bfifo); 645 if (bfifo & 0x1FF) { 646// printk("%s: %d bytes in FIFO\n", drive->name, bfifo); 647 return 0; 648 } 649 650 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); 651 /* return 1 if INTR asserted */ 652 if (dma_stat & ATA_DMA_INTR) 653 return 1; 654 655 return 0; 656} 657 658static int hpt374_dma_end(ide_drive_t *drive) 659{ 660 ide_hwif_t *hwif = drive->hwif; 661 struct pci_dev *dev = to_pci_dev(hwif->dev); 662 u8 mcr = 0, mcr_addr = hwif->select_data; 663 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; 664 665 pci_read_config_byte(dev, 0x6a, &bwsr); 666 pci_read_config_byte(dev, mcr_addr, &mcr); 667 if (bwsr & mask) 668 pci_write_config_byte(dev, mcr_addr, mcr | 0x30); 669 return ide_dma_end(drive); 670} 671 672/** 673 * hpt3xxn_set_clock - perform clock switching dance 674 * @hwif: hwif to switch 675 * @mode: clocking mode (0x21 for write, 0x23 otherwise) 676 * 677 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. 678 */ 679 680static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) 681{ 682 unsigned long base = hwif->extra_base; 683 u8 scr2 = inb(base + 0x6b); 684 685 if ((scr2 & 0x7f) == mode) 686 return; 687 688 /* Tristate the bus */ 689 outb(0x80, base + 0x63); 690 outb(0x80, base + 0x67); 691 692 /* Switch clock and reset channels */ 693 outb(mode, base + 0x6b); 694 outb(0xc0, base + 0x69); 695 696 /* 697 * Reset the state machines. 698 * NOTE: avoid accidentally enabling the disabled channels. 699 */ 700 outb(inb(base + 0x60) | 0x32, base + 0x60); 701 outb(inb(base + 0x64) | 0x32, base + 0x64); 702 703 /* Complete reset */ 704 outb(0x00, base + 0x69); 705 706 /* Reconnect channels to bus */ 707 outb(0x00, base + 0x63); 708 outb(0x00, base + 0x67); 709} 710 711/** 712 * hpt3xxn_rw_disk - prepare for I/O 713 * @drive: drive for command 714 * @rq: block request structure 715 * 716 * This is called when a disk I/O is issued to HPT3xxN. 717 * We need it because of the clock switching. 718 */ 719 720static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) 721{ 722 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21); 723} 724 725/** 726 * hpt37x_calibrate_dpll - calibrate the DPLL 727 * @dev: PCI device 728 * 729 * Perform a calibration cycle on the DPLL. 730 * Returns 1 if this succeeds 731 */ 732static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) 733{ 734 u32 dpll = (f_high << 16) | f_low | 0x100; 735 u8 scr2; 736 int i; 737 738 pci_write_config_dword(dev, 0x5c, dpll); 739 740 /* Wait for oscillator ready */ 741 for(i = 0; i < 0x5000; ++i) { 742 udelay(50); 743 pci_read_config_byte(dev, 0x5b, &scr2); 744 if (scr2 & 0x80) 745 break; 746 } 747 /* See if it stays ready (we'll just bail out if it's not yet) */ 748 for(i = 0; i < 0x1000; ++i) { 749 pci_read_config_byte(dev, 0x5b, &scr2); 750 /* DPLL destabilized? */ 751 if(!(scr2 & 0x80)) 752 return 0; 753 } 754 /* Turn off tuning, we have the DPLL set */ 755 pci_read_config_dword (dev, 0x5c, &dpll); 756 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); 757 return 1; 758} 759 760static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr) 761{ 762 struct ide_host *host = pci_get_drvdata(dev); 763 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]); 764 u8 chip_type = info->chip_type; 765 u8 new_mcr, old_mcr = 0; 766 767 /* 768 * Disable the "fast interrupt" prediction. Don't hold off 769 * on interrupts. (== 0x01 despite what the docs say) 770 */ 771 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr); 772 773 if (chip_type >= HPT374) 774 new_mcr = old_mcr & ~0x07; 775 else if (chip_type >= HPT370) { 776 new_mcr = old_mcr; 777 new_mcr &= ~0x02; 778#ifdef HPT_DELAY_INTERRUPT 779 new_mcr &= ~0x01; 780#else 781 new_mcr |= 0x01; 782#endif 783 } else /* HPT366 and HPT368 */ 784 new_mcr = old_mcr & ~0x80; 785 786 if (new_mcr != old_mcr) 787 pci_write_config_byte(dev, mcr_addr + 1, new_mcr); 788} 789 790static int init_chipset_hpt366(struct pci_dev *dev) 791{ 792 unsigned long io_base = pci_resource_start(dev, 4); 793 struct hpt_info *info = hpt3xx_get_info(&dev->dev); 794 const char *name = DRV_NAME; 795 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ 796 u8 chip_type; 797 enum ata_clock clock; 798 799 chip_type = info->chip_type; 800 801 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 802 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 803 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 804 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 805 806 /* 807 * First, try to estimate the PCI clock frequency... 808 */ 809 if (chip_type >= HPT370) { 810 u8 scr1 = 0; 811 u16 f_cnt = 0; 812 u32 temp = 0; 813 814 /* Interrupt force enable. */ 815 pci_read_config_byte(dev, 0x5a, &scr1); 816 if (scr1 & 0x10) 817 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 818 819 /* 820 * HighPoint does this for HPT372A. 821 * NOTE: This register is only writeable via I/O space. 822 */ 823 if (chip_type == HPT372A) 824 outb(0x0e, io_base + 0x9c); 825 826 /* 827 * Default to PCI clock. Make sure MA15/16 are set to output 828 * to prevent drives having problems with 40-pin cables. 829 */ 830 pci_write_config_byte(dev, 0x5b, 0x23); 831 832 /* 833 * We'll have to read f_CNT value in order to determine 834 * the PCI clock frequency according to the following ratio: 835 * 836 * f_CNT = Fpci * 192 / Fdpll 837 * 838 * First try reading the register in which the HighPoint BIOS 839 * saves f_CNT value before reprogramming the DPLL from its 840 * default setting (which differs for the various chips). 841 * 842 * NOTE: This register is only accessible via I/O space; 843 * HPT374 BIOS only saves it for the function 0, so we have to 844 * always read it from there -- no need to check the result of 845 * pci_get_slot() for the function 0 as the whole device has 846 * been already "pinned" (via function 1) in init_setup_hpt374() 847 */ 848 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 849 struct pci_dev *dev1 = pci_get_slot(dev->bus, 850 dev->devfn - 1); 851 unsigned long io_base = pci_resource_start(dev1, 4); 852 853 temp = inl(io_base + 0x90); 854 pci_dev_put(dev1); 855 } else 856 temp = inl(io_base + 0x90); 857 858 /* 859 * In case the signature check fails, we'll have to 860 * resort to reading the f_CNT register itself in hopes 861 * that nobody has touched the DPLL yet... 862 */ 863 if ((temp & 0xFFFFF000) != 0xABCDE000) { 864 int i; 865 866 printk(KERN_WARNING "%s %s: no clock data saved by " 867 "BIOS\n", name, pci_name(dev)); 868 869 /* Calculate the average value of f_CNT. */ 870 for (temp = i = 0; i < 128; i++) { 871 pci_read_config_word(dev, 0x78, &f_cnt); 872 temp += f_cnt & 0x1ff; 873 mdelay(1); 874 } 875 f_cnt = temp / 128; 876 } else 877 f_cnt = temp & 0x1ff; 878 879 dpll_clk = info->dpll_clk; 880 pci_clk = (f_cnt * dpll_clk) / 192; 881 882 /* Clamp PCI clock to bands. */ 883 if (pci_clk < 40) 884 pci_clk = 33; 885 else if(pci_clk < 45) 886 pci_clk = 40; 887 else if(pci_clk < 55) 888 pci_clk = 50; 889 else 890 pci_clk = 66; 891 892 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, " 893 "assuming %d MHz PCI\n", name, pci_name(dev), 894 dpll_clk, f_cnt, pci_clk); 895 } else { 896 u32 itr1 = 0; 897 898 pci_read_config_dword(dev, 0x40, &itr1); 899 900 /* Detect PCI clock by looking at cmd_high_time. */ 901 switch((itr1 >> 8) & 0x07) { 902 case 0x09: 903 pci_clk = 40; 904 break; 905 case 0x05: 906 pci_clk = 25; 907 break; 908 case 0x07: 909 default: 910 pci_clk = 33; 911 break; 912 } 913 } 914 915 /* Let's assume we'll use PCI clock for the ATA clock... */ 916 switch (pci_clk) { 917 case 25: 918 clock = ATA_CLOCK_25MHZ; 919 break; 920 case 33: 921 default: 922 clock = ATA_CLOCK_33MHZ; 923 break; 924 case 40: 925 clock = ATA_CLOCK_40MHZ; 926 break; 927 case 50: 928 clock = ATA_CLOCK_50MHZ; 929 break; 930 case 66: 931 clock = ATA_CLOCK_66MHZ; 932 break; 933 } 934 935 /* 936 * Only try the DPLL if we don't have a table for the PCI clock that 937 * we are running at for HPT370/A, always use it for anything newer... 938 * 939 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. 940 * We also don't like using the DPLL because this causes glitches 941 * on PRST-/SRST- when the state engine gets reset... 942 */ 943 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) { 944 u16 f_low, delta = pci_clk < 50 ? 2 : 4; 945 int adjust; 946 947 /* 948 * Select 66 MHz DPLL clock only if UltraATA/133 mode is 949 * supported/enabled, use 50 MHz DPLL clock otherwise... 950 */ 951 if (info->udma_mask == ATA_UDMA6) { 952 dpll_clk = 66; 953 clock = ATA_CLOCK_66MHZ; 954 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ 955 dpll_clk = 50; 956 clock = ATA_CLOCK_50MHZ; 957 } 958 959 if (info->timings->clock_table[clock] == NULL) { 960 printk(KERN_ERR "%s %s: unknown bus timing!\n", 961 name, pci_name(dev)); 962 return -EIO; 963 } 964 965 /* Select the DPLL clock. */ 966 pci_write_config_byte(dev, 0x5b, 0x21); 967 968 /* 969 * Adjust the DPLL based upon PCI clock, enable it, 970 * and wait for stabilization... 971 */ 972 f_low = (pci_clk * 48) / dpll_clk; 973 974 for (adjust = 0; adjust < 8; adjust++) { 975 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) 976 break; 977 978 /* 979 * See if it'll settle at a fractionally different clock 980 */ 981 if (adjust & 1) 982 f_low -= adjust >> 1; 983 else 984 f_low += adjust >> 1; 985 } 986 if (adjust == 8) { 987 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n", 988 name, pci_name(dev)); 989 return -EIO; 990 } 991 992 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n", 993 name, pci_name(dev), dpll_clk); 994 } else { 995 /* Mark the fact that we're not using the DPLL. */ 996 dpll_clk = 0; 997 998 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n", 999 name, pci_name(dev), pci_clk); 1000 } 1001 1002 /* Store the clock frequencies. */ 1003 info->dpll_clk = dpll_clk; 1004 info->pci_clk = pci_clk; 1005 info->clock = clock; 1006 1007 if (chip_type >= HPT370) { 1008 u8 mcr1, mcr4; 1009 1010 /* 1011 * Reset the state engines. 1012 * NOTE: Avoid accidentally enabling the disabled channels. 1013 */ 1014 pci_read_config_byte (dev, 0x50, &mcr1); 1015 pci_read_config_byte (dev, 0x54, &mcr4); 1016 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); 1017 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); 1018 udelay(100); 1019 } 1020 1021 /* 1022 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 1023 * the MISC. register to stretch the UltraDMA Tss timing. 1024 * NOTE: This register is only writeable via I/O space. 1025 */ 1026 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) 1027 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); 1028 1029 hpt3xx_disable_fast_irq(dev, 0x50); 1030 hpt3xx_disable_fast_irq(dev, 0x54); 1031 1032 return 0; 1033} 1034 1035static u8 hpt3xx_cable_detect(ide_hwif_t *hwif) 1036{ 1037 struct pci_dev *dev = to_pci_dev(hwif->dev); 1038 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 1039 u8 chip_type = info->chip_type; 1040 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; 1041 1042 /* 1043 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1044 * address lines to access an external EEPROM. To read valid 1045 * cable detect state the pins must be enabled as inputs. 1046 */ 1047 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 1048 /* 1049 * HPT374 PCI function 1 1050 * - set bit 15 of reg 0x52 to enable TCBLID as input 1051 * - set bit 15 of reg 0x56 to enable FCBLID as input 1052 */ 1053 u8 mcr_addr = hwif->select_data + 2; 1054 u16 mcr; 1055 1056 pci_read_config_word(dev, mcr_addr, &mcr); 1057 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); 1058 /* now read cable id register */ 1059 pci_read_config_byte(dev, 0x5a, &scr1); 1060 pci_write_config_word(dev, mcr_addr, mcr); 1061 } else if (chip_type >= HPT370) { 1062 /* 1063 * HPT370/372 and 374 pcifn 0 1064 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs 1065 */ 1066 u8 scr2 = 0; 1067 1068 pci_read_config_byte(dev, 0x5b, &scr2); 1069 pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); 1070 /* now read cable id register */ 1071 pci_read_config_byte(dev, 0x5a, &scr1); 1072 pci_write_config_byte(dev, 0x5b, scr2); 1073 } else 1074 pci_read_config_byte(dev, 0x5a, &scr1); 1075 1076 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; 1077} 1078 1079static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) 1080{ 1081 struct hpt_info *info = hpt3xx_get_info(hwif->dev); 1082 u8 chip_type = info->chip_type; 1083 1084 /* Cache the channel's MISC. control registers' offset */ 1085 hwif->select_data = hwif->channel ? 0x54 : 0x50; 1086 1087 /* 1088 * HPT3xxN chips have some complications: 1089 * 1090 * - on 33 MHz PCI we must clock switch 1091 * - on 66 MHz PCI we must NOT use the PCI clock 1092 */ 1093 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { 1094 /* 1095 * Clock is shared between the channels, 1096 * so we'll have to serialize them... :-( 1097 */ 1098 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE; 1099 hwif->rw_disk = &hpt3xxn_rw_disk; 1100 } 1101} 1102 1103static int __devinit init_dma_hpt366(ide_hwif_t *hwif, 1104 const struct ide_port_info *d) 1105{ 1106 struct pci_dev *dev = to_pci_dev(hwif->dev); 1107 unsigned long flags, base = ide_pci_dma_base(hwif, d); 1108 u8 dma_old, dma_new, masterdma = 0, slavedma = 0; 1109 1110 if (base == 0) 1111 return -1; 1112 1113 hwif->dma_base = base; 1114 1115 if (ide_pci_check_simplex(hwif, d) < 0) 1116 return -1; 1117 1118 if (ide_pci_set_master(dev, d->name) < 0) 1119 return -1; 1120 1121 dma_old = inb(base + 2); 1122 1123 local_irq_save(flags); 1124 1125 dma_new = dma_old; 1126 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); 1127 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); 1128 1129 if (masterdma & 0x30) dma_new |= 0x20; 1130 if ( slavedma & 0x30) dma_new |= 0x40; 1131 if (dma_new != dma_old) 1132 outb(dma_new, base + 2); 1133 1134 local_irq_restore(flags); 1135 1136 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", 1137 hwif->name, base, base + 7); 1138 1139 hwif->extra_base = base + (hwif->channel ? 8 : 16); 1140 1141 if (ide_allocate_dma_engine(hwif)) 1142 return -1; 1143 1144 return 0; 1145} 1146 1147static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2) 1148{ 1149 if (dev2->irq != dev->irq) { 1150 dev2->irq = dev->irq; 1151 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt " 1152 "fixed\n", pci_name(dev2)); 1153 } 1154} 1155 1156static void __devinit hpt371_init(struct pci_dev *dev) 1157{ 1158 u8 mcr1 = 0; 1159 1160 /* 1161 * HPT371 chips physically have only one channel, the secondary one, 1162 * but the primary channel registers do exist! Go figure... 1163 * So, we manually disable the non-existing channel here 1164 * (if the BIOS hasn't done this already). 1165 */ 1166 pci_read_config_byte(dev, 0x50, &mcr1); 1167 if (mcr1 & 0x04) 1168 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); 1169} 1170 1171static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2) 1172{ 1173 u8 mcr1 = 0, pin1 = 0, pin2 = 0; 1174 1175 /* 1176 * Now we'll have to force both channels enabled if 1177 * at least one of them has been enabled by BIOS... 1178 */ 1179 pci_read_config_byte(dev, 0x50, &mcr1); 1180 if (mcr1 & 0x30) 1181 pci_write_config_byte(dev, 0x50, mcr1 | 0x30); 1182 1183 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); 1184 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); 1185 1186 if (pin1 != pin2 && dev->irq == dev2->irq) { 1187 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, " 1188 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2); 1189 return 1; 1190 } 1191 1192 return 0; 1193} 1194 1195#define IDE_HFLAGS_HPT3XX \ 1196 (IDE_HFLAG_NO_ATAPI_DMA | \ 1197 IDE_HFLAG_OFF_BOARD) 1198 1199static const struct ide_port_ops hpt3xx_port_ops = { 1200 .set_pio_mode = hpt3xx_set_pio_mode, 1201 .set_dma_mode = hpt3xx_set_mode, 1202 .maskproc = hpt3xx_maskproc, 1203 .mdma_filter = hpt3xx_mdma_filter, 1204 .udma_filter = hpt3xx_udma_filter, 1205 .cable_detect = hpt3xx_cable_detect, 1206}; 1207 1208static const struct ide_dma_ops hpt37x_dma_ops = { 1209 .dma_host_set = ide_dma_host_set, 1210 .dma_setup = ide_dma_setup, 1211 .dma_start = ide_dma_start, 1212 .dma_end = hpt374_dma_end, 1213 .dma_test_irq = hpt374_dma_test_irq, 1214 .dma_lost_irq = ide_dma_lost_irq, 1215 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1216 .dma_sff_read_status = ide_dma_sff_read_status, 1217}; 1218 1219static const struct ide_dma_ops hpt370_dma_ops = { 1220 .dma_host_set = ide_dma_host_set, 1221 .dma_setup = ide_dma_setup, 1222 .dma_start = hpt370_dma_start, 1223 .dma_end = hpt370_dma_end, 1224 .dma_test_irq = ide_dma_test_irq, 1225 .dma_lost_irq = ide_dma_lost_irq, 1226 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1227 .dma_clear = hpt370_irq_timeout, 1228 .dma_sff_read_status = ide_dma_sff_read_status, 1229}; 1230 1231static const struct ide_dma_ops hpt36x_dma_ops = { 1232 .dma_host_set = ide_dma_host_set, 1233 .dma_setup = ide_dma_setup, 1234 .dma_start = ide_dma_start, 1235 .dma_end = ide_dma_end, 1236 .dma_test_irq = ide_dma_test_irq, 1237 .dma_lost_irq = hpt366_dma_lost_irq, 1238 .dma_timer_expiry = ide_dma_sff_timer_expiry, 1239 .dma_sff_read_status = ide_dma_sff_read_status, 1240}; 1241 1242static const struct ide_port_info hpt366_chipsets[] __devinitdata = { 1243 { /* 0: HPT36x */ 1244 .name = DRV_NAME, 1245 .init_chipset = init_chipset_hpt366, 1246 .init_hwif = init_hwif_hpt366, 1247 .init_dma = init_dma_hpt366, 1248 /* 1249 * HPT36x chips have one channel per function and have 1250 * both channel enable bits located differently and visible 1251 * to both functions -- really stupid design decision... :-( 1252 * Bit 4 is for the primary channel, bit 5 for the secondary. 1253 */ 1254 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, 1255 .port_ops = &hpt3xx_port_ops, 1256 .dma_ops = &hpt36x_dma_ops, 1257 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE, 1258 .pio_mask = ATA_PIO4, 1259 .mwdma_mask = ATA_MWDMA2, 1260 }, 1261 { /* 1: HPT3xx */ 1262 .name = DRV_NAME, 1263 .init_chipset = init_chipset_hpt366, 1264 .init_hwif = init_hwif_hpt366, 1265 .init_dma = init_dma_hpt366, 1266 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1267 .port_ops = &hpt3xx_port_ops, 1268 .dma_ops = &hpt37x_dma_ops, 1269 .host_flags = IDE_HFLAGS_HPT3XX, 1270 .pio_mask = ATA_PIO4, 1271 .mwdma_mask = ATA_MWDMA2, 1272 } 1273}; 1274 1275/** 1276 * hpt366_init_one - called when an HPT366 is found 1277 * @dev: the hpt366 device 1278 * @id: the matching pci id 1279 * 1280 * Called when the PCI registration layer (or the IDE initialization) 1281 * finds a device matching our IDE device tables. 1282 */ 1283static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) 1284{ 1285 const struct hpt_info *info = NULL; 1286 struct hpt_info *dyn_info; 1287 struct pci_dev *dev2 = NULL; 1288 struct ide_port_info d; 1289 u8 idx = id->driver_data; 1290 u8 rev = dev->revision; 1291 int ret; 1292 1293 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1)) 1294 return -ENODEV; 1295 1296 switch (idx) { 1297 case 0: 1298 if (rev < 3) 1299 info = &hpt36x; 1300 else { 1301 switch (min_t(u8, rev, 6)) { 1302 case 3: info = &hpt370; break; 1303 case 4: info = &hpt370a; break; 1304 case 5: info = &hpt372; break; 1305 case 6: info = &hpt372n; break; 1306 } 1307 idx++; 1308 } 1309 break; 1310 case 1: 1311 info = (rev > 1) ? &hpt372n : &hpt372a; 1312 break; 1313 case 2: 1314 info = (rev > 1) ? &hpt302n : &hpt302; 1315 break; 1316 case 3: 1317 hpt371_init(dev); 1318 info = (rev > 1) ? &hpt371n : &hpt371; 1319 break; 1320 case 4: 1321 info = &hpt374; 1322 break; 1323 case 5: 1324 info = &hpt372n; 1325 break; 1326 } 1327 1328 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name); 1329 1330 d = hpt366_chipsets[min_t(u8, idx, 1)]; 1331 1332 d.udma_mask = info->udma_mask; 1333 1334 /* fixup ->dma_ops for HPT370/HPT370A */ 1335 if (info == &hpt370 || info == &hpt370a) 1336 d.dma_ops = &hpt370_dma_ops; 1337 1338 if (info == &hpt36x || info == &hpt374) 1339 dev2 = pci_get_slot(dev->bus, dev->devfn + 1); 1340 1341 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL); 1342 if (dyn_info == NULL) { 1343 printk(KERN_ERR "%s %s: out of memory!\n", 1344 d.name, pci_name(dev)); 1345 pci_dev_put(dev2); 1346 return -ENOMEM; 1347 } 1348 1349 /* 1350 * Copy everything from a static "template" structure 1351 * to just allocated per-chip hpt_info structure. 1352 */ 1353 memcpy(dyn_info, info, sizeof(*dyn_info)); 1354 1355 if (dev2) { 1356 memcpy(dyn_info + 1, info, sizeof(*dyn_info)); 1357 1358 if (info == &hpt374) 1359 hpt374_init(dev, dev2); 1360 else { 1361 if (hpt36x_init(dev, dev2)) 1362 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE; 1363 } 1364 1365 ret = ide_pci_init_two(dev, dev2, &d, dyn_info); 1366 if (ret < 0) { 1367 pci_dev_put(dev2); 1368 kfree(dyn_info); 1369 } 1370 return ret; 1371 } 1372 1373 ret = ide_pci_init_one(dev, &d, dyn_info); 1374 if (ret < 0) 1375 kfree(dyn_info); 1376 1377 return ret; 1378} 1379 1380static void __devexit hpt366_remove(struct pci_dev *dev) 1381{ 1382 struct ide_host *host = pci_get_drvdata(dev); 1383 struct ide_info *info = host->host_priv; 1384 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL; 1385 1386 ide_pci_remove(dev); 1387 pci_dev_put(dev2); 1388 kfree(info); 1389} 1390 1391static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = { 1392 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 }, 1393 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 }, 1394 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 }, 1395 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 }, 1396 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 }, 1397 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 }, 1398 { 0, }, 1399}; 1400MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); 1401 1402static struct pci_driver hpt366_pci_driver = { 1403 .name = "HPT366_IDE", 1404 .id_table = hpt366_pci_tbl, 1405 .probe = hpt366_init_one, 1406 .remove = __devexit_p(hpt366_remove), 1407 .suspend = ide_pci_suspend, 1408 .resume = ide_pci_resume, 1409}; 1410 1411static int __init hpt366_ide_init(void) 1412{ 1413 return ide_pci_register_driver(&hpt366_pci_driver); 1414} 1415 1416static void __exit hpt366_ide_exit(void) 1417{ 1418 pci_unregister_driver(&hpt366_pci_driver); 1419} 1420 1421module_init(hpt366_ide_init); 1422module_exit(hpt366_ide_exit); 1423 1424MODULE_AUTHOR("Andre Hedrick"); 1425MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); 1426MODULE_LICENSE("GPL"); 1427