1/* 2 * Copyright (C) 2002 Motorola GSG-China 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, 17 * USA. 18 * 19 * Author: 20 * Darius Augulis, Teltonika Inc. 21 * 22 * Desc.: 23 * Implementation of I2C Adapter/Algorithm Driver 24 * for I2C Bus integrated in Freescale i.MX/MXC processors 25 * 26 * Derived from Motorola GSG China I2C example driver 27 * 28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 30 * Copyright (C) 2007 RightHand Technologies, Inc. 31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 32 * 33 */ 34 35/** Includes ******************************************************************* 36*******************************************************************************/ 37 38#include <linux/init.h> 39#include <linux/kernel.h> 40#include <linux/module.h> 41#include <linux/errno.h> 42#include <linux/err.h> 43#include <linux/interrupt.h> 44#include <linux/delay.h> 45#include <linux/i2c.h> 46#include <linux/io.h> 47#include <linux/sched.h> 48#include <linux/platform_device.h> 49#include <linux/clk.h> 50#include <linux/slab.h> 51 52#include <mach/irqs.h> 53#include <mach/hardware.h> 54#include <mach/i2c.h> 55 56/** Defines ******************************************************************** 57*******************************************************************************/ 58 59/* This will be the driver name the kernel reports */ 60#define DRIVER_NAME "imx-i2c" 61 62/* Default value */ 63#define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 64 65/* IMX I2C registers */ 66#define IMX_I2C_IADR 0x00 /* i2c slave address */ 67#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ 68#define IMX_I2C_I2CR 0x08 /* i2c control */ 69#define IMX_I2C_I2SR 0x0C /* i2c status */ 70#define IMX_I2C_I2DR 0x10 /* i2c transfer data */ 71 72/* Bits of IMX I2C registers */ 73#define I2SR_RXAK 0x01 74#define I2SR_IIF 0x02 75#define I2SR_SRW 0x04 76#define I2SR_IAL 0x10 77#define I2SR_IBB 0x20 78#define I2SR_IAAS 0x40 79#define I2SR_ICF 0x80 80#define I2CR_RSTA 0x04 81#define I2CR_TXAK 0x08 82#define I2CR_MTX 0x10 83#define I2CR_MSTA 0x20 84#define I2CR_IIEN 0x40 85#define I2CR_IEN 0x80 86 87/** Variables ****************************************************************** 88*******************************************************************************/ 89 90/* 91 * sorted list of clock divider, register value pairs 92 * taken from table 26-5, p.26-9, Freescale i.MX 93 * Integrated Portable System Processor Reference Manual 94 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 95 * 96 * Duplicated divider values removed from list 97 */ 98 99static u16 __initdata i2c_clk_div[50][2] = { 100 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 101 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 102 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 103 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 104 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 105 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 106 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 107 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 108 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 109 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 110 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 111 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 112 { 3072, 0x1E }, { 3840, 0x1F } 113}; 114 115struct imx_i2c_struct { 116 struct i2c_adapter adapter; 117 struct resource *res; 118 struct clk *clk; 119 void __iomem *base; 120 int irq; 121 wait_queue_head_t queue; 122 unsigned long i2csr; 123 unsigned int disable_delay; 124 int stopped; 125 unsigned int ifdr; /* IMX_I2C_IFDR */ 126}; 127 128/** Functions for IMX I2C adapter driver *************************************** 129*******************************************************************************/ 130 131static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) 132{ 133 unsigned long orig_jiffies = jiffies; 134 unsigned int temp; 135 136 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 137 138 while (1) { 139 temp = readb(i2c_imx->base + IMX_I2C_I2SR); 140 if (for_busy && (temp & I2SR_IBB)) 141 break; 142 if (!for_busy && !(temp & I2SR_IBB)) 143 break; 144 if (signal_pending(current)) { 145 dev_dbg(&i2c_imx->adapter.dev, 146 "<%s> I2C Interrupted\n", __func__); 147 return -EINTR; 148 } 149 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 150 dev_dbg(&i2c_imx->adapter.dev, 151 "<%s> I2C bus is busy\n", __func__); 152 return -ETIMEDOUT; 153 } 154 schedule(); 155 } 156 157 return 0; 158} 159 160static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) 161{ 162 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 163 164 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 165 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 166 return -ETIMEDOUT; 167 } 168 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 169 i2c_imx->i2csr = 0; 170 return 0; 171} 172 173static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 174{ 175 if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) { 176 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 177 return -EIO; /* No ACK */ 178 } 179 180 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 181 return 0; 182} 183 184static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) 185{ 186 unsigned int temp = 0; 187 int result; 188 189 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 190 191 clk_enable(i2c_imx->clk); 192 writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR); 193 /* Enable I2C controller */ 194 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 195 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR); 196 197 /* Wait controller to be stable */ 198 udelay(50); 199 200 /* Start I2C transaction */ 201 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 202 temp |= I2CR_MSTA; 203 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 204 result = i2c_imx_bus_busy(i2c_imx, 1); 205 if (result) 206 return result; 207 i2c_imx->stopped = 0; 208 209 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 210 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 211 return result; 212} 213 214static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 215{ 216 unsigned int temp = 0; 217 218 if (!i2c_imx->stopped) { 219 /* Stop I2C transaction */ 220 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 221 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 222 temp &= ~(I2CR_MSTA | I2CR_MTX); 223 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 224 } 225 if (cpu_is_mx1()) { 226 /* 227 * This delay caused by an i.MXL hardware bug. 228 * If no (or too short) delay, no "STOP" bit will be generated. 229 */ 230 udelay(i2c_imx->disable_delay); 231 } 232 233 if (!i2c_imx->stopped) { 234 i2c_imx_bus_busy(i2c_imx, 0); 235 i2c_imx->stopped = 1; 236 } 237 238 /* Disable I2C controller */ 239 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 240 clk_disable(i2c_imx->clk); 241} 242 243static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 244 unsigned int rate) 245{ 246 unsigned int i2c_clk_rate; 247 unsigned int div; 248 int i; 249 250 /* Divider value calculation */ 251 i2c_clk_rate = clk_get_rate(i2c_imx->clk); 252 div = (i2c_clk_rate + rate - 1) / rate; 253 if (div < i2c_clk_div[0][0]) 254 i = 0; 255 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 256 i = ARRAY_SIZE(i2c_clk_div) - 1; 257 else 258 for (i = 0; i2c_clk_div[i][0] < div; i++); 259 260 /* Store divider value */ 261 i2c_imx->ifdr = i2c_clk_div[i][1]; 262 263 /* 264 * There dummy delay is calculated. 265 * It should be about one I2C clock period long. 266 * This delay is used in I2C bus disable function 267 * to fix chip hardware bug. 268 */ 269 i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0] 270 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 271 272 /* dev_dbg() can't be used, because adapter is not yet registered */ 273#ifdef CONFIG_I2C_DEBUG_BUS 274 printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n", 275 __func__, i2c_clk_rate, div); 276 printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n", 277 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]); 278#endif 279} 280 281static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 282{ 283 struct imx_i2c_struct *i2c_imx = dev_id; 284 unsigned int temp; 285 286 temp = readb(i2c_imx->base + IMX_I2C_I2SR); 287 if (temp & I2SR_IIF) { 288 /* save status register */ 289 i2c_imx->i2csr = temp; 290 temp &= ~I2SR_IIF; 291 writeb(temp, i2c_imx->base + IMX_I2C_I2SR); 292 wake_up(&i2c_imx->queue); 293 return IRQ_HANDLED; 294 } 295 296 return IRQ_NONE; 297} 298 299static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 300{ 301 int i, result; 302 303 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 304 __func__, msgs->addr << 1); 305 306 /* write slave address */ 307 writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR); 308 result = i2c_imx_trx_complete(i2c_imx); 309 if (result) 310 return result; 311 result = i2c_imx_acked(i2c_imx); 312 if (result) 313 return result; 314 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 315 316 /* write data */ 317 for (i = 0; i < msgs->len; i++) { 318 dev_dbg(&i2c_imx->adapter.dev, 319 "<%s> write byte: B%d=0x%X\n", 320 __func__, i, msgs->buf[i]); 321 writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR); 322 result = i2c_imx_trx_complete(i2c_imx); 323 if (result) 324 return result; 325 result = i2c_imx_acked(i2c_imx); 326 if (result) 327 return result; 328 } 329 return 0; 330} 331 332static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 333{ 334 int i, result; 335 unsigned int temp; 336 337 dev_dbg(&i2c_imx->adapter.dev, 338 "<%s> write slave address: addr=0x%x\n", 339 __func__, (msgs->addr << 1) | 0x01); 340 341 /* write slave address */ 342 writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR); 343 result = i2c_imx_trx_complete(i2c_imx); 344 if (result) 345 return result; 346 result = i2c_imx_acked(i2c_imx); 347 if (result) 348 return result; 349 350 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 351 352 /* setup bus to read data */ 353 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 354 temp &= ~I2CR_MTX; 355 if (msgs->len - 1) 356 temp &= ~I2CR_TXAK; 357 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 358 readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */ 359 360 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 361 362 /* read data */ 363 for (i = 0; i < msgs->len; i++) { 364 result = i2c_imx_trx_complete(i2c_imx); 365 if (result) 366 return result; 367 if (i == (msgs->len - 1)) { 368 /* It must generate STOP before read I2DR to prevent 369 controller from generating another clock cycle */ 370 dev_dbg(&i2c_imx->adapter.dev, 371 "<%s> clear MSTA\n", __func__); 372 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 373 temp &= ~(I2CR_MSTA | I2CR_MTX); 374 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 375 i2c_imx_bus_busy(i2c_imx, 0); 376 i2c_imx->stopped = 1; 377 } else if (i == (msgs->len - 2)) { 378 dev_dbg(&i2c_imx->adapter.dev, 379 "<%s> set TXAK\n", __func__); 380 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 381 temp |= I2CR_TXAK; 382 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 383 } 384 msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR); 385 dev_dbg(&i2c_imx->adapter.dev, 386 "<%s> read byte: B%d=0x%X\n", 387 __func__, i, msgs->buf[i]); 388 } 389 return 0; 390} 391 392static int i2c_imx_xfer(struct i2c_adapter *adapter, 393 struct i2c_msg *msgs, int num) 394{ 395 unsigned int i, temp; 396 int result; 397 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 398 399 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 400 401 /* Start I2C transfer */ 402 result = i2c_imx_start(i2c_imx); 403 if (result) 404 goto fail0; 405 406 /* read/write data */ 407 for (i = 0; i < num; i++) { 408 if (i) { 409 dev_dbg(&i2c_imx->adapter.dev, 410 "<%s> repeated start\n", __func__); 411 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 412 temp |= I2CR_RSTA; 413 writeb(temp, i2c_imx->base + IMX_I2C_I2CR); 414 result = i2c_imx_bus_busy(i2c_imx, 1); 415 if (result) 416 goto fail0; 417 } 418 dev_dbg(&i2c_imx->adapter.dev, 419 "<%s> transfer message: %d\n", __func__, i); 420 /* write/read data */ 421#ifdef CONFIG_I2C_DEBUG_BUS 422 temp = readb(i2c_imx->base + IMX_I2C_I2CR); 423 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " 424 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, 425 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 426 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 427 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 428 temp = readb(i2c_imx->base + IMX_I2C_I2SR); 429 dev_dbg(&i2c_imx->adapter.dev, 430 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " 431 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, 432 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 433 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 434 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 435 (temp & I2SR_RXAK ? 1 : 0)); 436#endif 437 if (msgs[i].flags & I2C_M_RD) 438 result = i2c_imx_read(i2c_imx, &msgs[i]); 439 else 440 result = i2c_imx_write(i2c_imx, &msgs[i]); 441 if (result) 442 goto fail0; 443 } 444 445fail0: 446 /* Stop I2C transfer */ 447 i2c_imx_stop(i2c_imx); 448 449 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 450 (result < 0) ? "error" : "success msg", 451 (result < 0) ? result : num); 452 return (result < 0) ? result : num; 453} 454 455static u32 i2c_imx_func(struct i2c_adapter *adapter) 456{ 457 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 458} 459 460static struct i2c_algorithm i2c_imx_algo = { 461 .master_xfer = i2c_imx_xfer, 462 .functionality = i2c_imx_func, 463}; 464 465static int __init i2c_imx_probe(struct platform_device *pdev) 466{ 467 struct imx_i2c_struct *i2c_imx; 468 struct resource *res; 469 struct imxi2c_platform_data *pdata; 470 void __iomem *base; 471 resource_size_t res_size; 472 int irq; 473 int ret; 474 475 dev_dbg(&pdev->dev, "<%s>\n", __func__); 476 477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 478 if (!res) { 479 dev_err(&pdev->dev, "can't get device resources\n"); 480 return -ENOENT; 481 } 482 irq = platform_get_irq(pdev, 0); 483 if (irq < 0) { 484 dev_err(&pdev->dev, "can't get irq number\n"); 485 return -ENOENT; 486 } 487 488 pdata = pdev->dev.platform_data; 489 490 if (pdata && pdata->init) { 491 ret = pdata->init(&pdev->dev); 492 if (ret) 493 return ret; 494 } 495 496 res_size = resource_size(res); 497 498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) { 499 ret = -EBUSY; 500 goto fail0; 501 } 502 503 base = ioremap(res->start, res_size); 504 if (!base) { 505 dev_err(&pdev->dev, "ioremap failed\n"); 506 ret = -EIO; 507 goto fail1; 508 } 509 510 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL); 511 if (!i2c_imx) { 512 dev_err(&pdev->dev, "can't allocate interface\n"); 513 ret = -ENOMEM; 514 goto fail2; 515 } 516 517 /* Setup i2c_imx driver structure */ 518 strcpy(i2c_imx->adapter.name, pdev->name); 519 i2c_imx->adapter.owner = THIS_MODULE; 520 i2c_imx->adapter.algo = &i2c_imx_algo; 521 i2c_imx->adapter.dev.parent = &pdev->dev; 522 i2c_imx->adapter.nr = pdev->id; 523 i2c_imx->irq = irq; 524 i2c_imx->base = base; 525 i2c_imx->res = res; 526 527 /* Get I2C clock */ 528 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk"); 529 if (IS_ERR(i2c_imx->clk)) { 530 ret = PTR_ERR(i2c_imx->clk); 531 dev_err(&pdev->dev, "can't get I2C clock\n"); 532 goto fail3; 533 } 534 535 /* Request IRQ */ 536 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx); 537 if (ret) { 538 dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq); 539 goto fail4; 540 } 541 542 /* Init queue */ 543 init_waitqueue_head(&i2c_imx->queue); 544 545 /* Set up adapter data */ 546 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 547 548 /* Set up clock divider */ 549 if (pdata && pdata->bitrate) 550 i2c_imx_set_clk(i2c_imx, pdata->bitrate); 551 else 552 i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE); 553 554 /* Set up chip registers to defaults */ 555 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 556 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 557 558 /* Add I2C adapter */ 559 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 560 if (ret < 0) { 561 dev_err(&pdev->dev, "registration failed\n"); 562 goto fail5; 563 } 564 565 /* Set up platform driver data */ 566 platform_set_drvdata(pdev, i2c_imx); 567 568 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq); 569 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n", 570 i2c_imx->res->start, i2c_imx->res->end); 571 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n", 572 res_size, i2c_imx->res->start); 573 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 574 i2c_imx->adapter.name); 575 dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 576 577 return 0; /* Return OK */ 578 579fail5: 580 free_irq(i2c_imx->irq, i2c_imx); 581fail4: 582 clk_put(i2c_imx->clk); 583fail3: 584 kfree(i2c_imx); 585fail2: 586 iounmap(base); 587fail1: 588 release_mem_region(res->start, resource_size(res)); 589fail0: 590 if (pdata && pdata->exit) 591 pdata->exit(&pdev->dev); 592 return ret; /* Return error number */ 593} 594 595static int __exit i2c_imx_remove(struct platform_device *pdev) 596{ 597 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 598 struct imxi2c_platform_data *pdata = pdev->dev.platform_data; 599 600 /* remove adapter */ 601 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 602 i2c_del_adapter(&i2c_imx->adapter); 603 platform_set_drvdata(pdev, NULL); 604 605 /* free interrupt */ 606 free_irq(i2c_imx->irq, i2c_imx); 607 608 /* setup chip registers to defaults */ 609 writeb(0, i2c_imx->base + IMX_I2C_IADR); 610 writeb(0, i2c_imx->base + IMX_I2C_IFDR); 611 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 612 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 613 614 /* Shut down hardware */ 615 if (pdata && pdata->exit) 616 pdata->exit(&pdev->dev); 617 618 clk_put(i2c_imx->clk); 619 620 iounmap(i2c_imx->base); 621 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res)); 622 kfree(i2c_imx); 623 return 0; 624} 625 626static struct platform_driver i2c_imx_driver = { 627 .remove = __exit_p(i2c_imx_remove), 628 .driver = { 629 .name = DRIVER_NAME, 630 .owner = THIS_MODULE, 631 } 632}; 633 634static int __init i2c_adap_imx_init(void) 635{ 636 return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe); 637} 638subsys_initcall(i2c_adap_imx_init); 639 640static void __exit i2c_adap_imx_exit(void) 641{ 642 platform_driver_unregister(&i2c_imx_driver); 643} 644module_exit(i2c_adap_imx_exit); 645 646MODULE_LICENSE("GPL"); 647MODULE_AUTHOR("Darius Augulis"); 648MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 649MODULE_ALIAS("platform:" DRIVER_NAME); 650