1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef __RADEON_H__ 29#define __RADEON_H__ 30 31/* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45/* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63#include <asm/atomic.h> 64#include <linux/wait.h> 65#include <linux/list.h> 66#include <linux/kref.h> 67 68#include <ttm/ttm_bo_api.h> 69#include <ttm/ttm_bo_driver.h> 70#include <ttm/ttm_placement.h> 71#include <ttm/ttm_module.h> 72 73#include "radeon_family.h" 74#include "radeon_mode.h" 75#include "radeon_reg.h" 76 77/* 78 * Modules parameters. 79 */ 80extern int radeon_no_wb; 81extern int radeon_modeset; 82extern int radeon_dynclks; 83extern int radeon_r4xx_atom; 84extern int radeon_agpmode; 85extern int radeon_vram_limit; 86extern int radeon_gart_size; 87extern int radeon_benchmarking; 88extern int radeon_testing; 89extern int radeon_connector_table; 90extern int radeon_tv; 91extern int radeon_new_pll; 92extern int radeon_audio; 93extern int radeon_disp_priority; 94extern int radeon_hw_i2c; 95 96/* 97 * Copy from radeon_drv.h so we don't have to include both and have conflicting 98 * symbol; 99 */ 100#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 101#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 102/* RADEON_IB_POOL_SIZE must be a power of 2 */ 103#define RADEON_IB_POOL_SIZE 16 104#define RADEON_DEBUGFS_MAX_NUM_FILES 32 105#define RADEONFB_CONN_LIMIT 4 106#define RADEON_BIOS_NUM_SCRATCH 8 107 108/* 109 * Errata workarounds. 110 */ 111enum radeon_pll_errata { 112 CHIP_ERRATA_R300_CG = 0x00000001, 113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 114 CHIP_ERRATA_PLL_DELAY = 0x00000004 115}; 116 117 118struct radeon_device; 119 120 121/* 122 * BIOS. 123 */ 124#define ATRM_BIOS_PAGE 4096 125 126#if defined(CONFIG_VGA_SWITCHEROO) 127bool radeon_atrm_supported(struct pci_dev *pdev); 128int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); 129#else 130static inline bool radeon_atrm_supported(struct pci_dev *pdev) 131{ 132 return false; 133} 134 135static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ 136 return -EINVAL; 137} 138#endif 139bool radeon_get_bios(struct radeon_device *rdev); 140 141 142/* 143 * Dummy page 144 */ 145struct radeon_dummy_page { 146 struct page *page; 147 dma_addr_t addr; 148}; 149int radeon_dummy_page_init(struct radeon_device *rdev); 150void radeon_dummy_page_fini(struct radeon_device *rdev); 151 152 153/* 154 * Clocks 155 */ 156struct radeon_clock { 157 struct radeon_pll p1pll; 158 struct radeon_pll p2pll; 159 struct radeon_pll dcpll; 160 struct radeon_pll spll; 161 struct radeon_pll mpll; 162 /* 10 Khz units */ 163 uint32_t default_mclk; 164 uint32_t default_sclk; 165 uint32_t default_dispclk; 166 uint32_t dp_extclk; 167}; 168 169/* 170 * Power management 171 */ 172int radeon_pm_init(struct radeon_device *rdev); 173void radeon_pm_fini(struct radeon_device *rdev); 174void radeon_pm_compute_clocks(struct radeon_device *rdev); 175void radeon_pm_suspend(struct radeon_device *rdev); 176void radeon_pm_resume(struct radeon_device *rdev); 177void radeon_combios_get_power_modes(struct radeon_device *rdev); 178void radeon_atombios_get_power_modes(struct radeon_device *rdev); 179void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level); 180void rs690_pm_info(struct radeon_device *rdev); 181extern u32 rv6xx_get_temp(struct radeon_device *rdev); 182extern u32 rv770_get_temp(struct radeon_device *rdev); 183extern u32 evergreen_get_temp(struct radeon_device *rdev); 184 185/* 186 * Fences. 187 */ 188struct radeon_fence_driver { 189 uint32_t scratch_reg; 190 atomic_t seq; 191 uint32_t last_seq; 192 unsigned long last_jiffies; 193 unsigned long last_timeout; 194 wait_queue_head_t queue; 195 rwlock_t lock; 196 struct list_head created; 197 struct list_head emited; 198 struct list_head signaled; 199 bool initialized; 200}; 201 202struct radeon_fence { 203 struct radeon_device *rdev; 204 struct kref kref; 205 struct list_head list; 206 /* protected by radeon_fence.lock */ 207 uint32_t seq; 208 bool emited; 209 bool signaled; 210}; 211 212int radeon_fence_driver_init(struct radeon_device *rdev); 213void radeon_fence_driver_fini(struct radeon_device *rdev); 214int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); 215int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 216void radeon_fence_process(struct radeon_device *rdev); 217bool radeon_fence_signaled(struct radeon_fence *fence); 218int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 219int radeon_fence_wait_next(struct radeon_device *rdev); 220int radeon_fence_wait_last(struct radeon_device *rdev); 221struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 222void radeon_fence_unref(struct radeon_fence **fence); 223 224/* 225 * Tiling registers 226 */ 227struct radeon_surface_reg { 228 struct radeon_bo *bo; 229}; 230 231#define RADEON_GEM_MAX_SURFACES 8 232 233/* 234 * TTM. 235 */ 236struct radeon_mman { 237 struct ttm_bo_global_ref bo_global_ref; 238 struct drm_global_reference mem_global_ref; 239 struct ttm_bo_device bdev; 240 bool mem_global_referenced; 241 bool initialized; 242}; 243 244struct radeon_bo { 245 /* Protected by gem.mutex */ 246 struct list_head list; 247 /* Protected by tbo.reserved */ 248 u32 placements[3]; 249 struct ttm_placement placement; 250 struct ttm_buffer_object tbo; 251 struct ttm_bo_kmap_obj kmap; 252 unsigned pin_count; 253 void *kptr; 254 u32 tiling_flags; 255 u32 pitch; 256 int surface_reg; 257 /* Constant after initialization */ 258 struct radeon_device *rdev; 259 struct drm_gem_object *gobj; 260}; 261 262struct radeon_bo_list { 263 struct list_head list; 264 struct radeon_bo *bo; 265 uint64_t gpu_offset; 266 unsigned rdomain; 267 unsigned wdomain; 268 u32 tiling_flags; 269 bool reserved; 270}; 271 272/* 273 * GEM objects. 274 */ 275struct radeon_gem { 276 struct mutex mutex; 277 struct list_head objects; 278}; 279 280int radeon_gem_init(struct radeon_device *rdev); 281void radeon_gem_fini(struct radeon_device *rdev); 282int radeon_gem_object_create(struct radeon_device *rdev, int size, 283 int alignment, int initial_domain, 284 bool discardable, bool kernel, 285 struct drm_gem_object **obj); 286int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 287 uint64_t *gpu_addr); 288void radeon_gem_object_unpin(struct drm_gem_object *obj); 289 290 291/* 292 * GART structures, functions & helpers 293 */ 294struct radeon_mc; 295 296struct radeon_gart_table_ram { 297 volatile uint32_t *ptr; 298}; 299 300struct radeon_gart_table_vram { 301 struct radeon_bo *robj; 302 volatile uint32_t *ptr; 303}; 304 305union radeon_gart_table { 306 struct radeon_gart_table_ram ram; 307 struct radeon_gart_table_vram vram; 308}; 309 310#define RADEON_GPU_PAGE_SIZE 4096 311#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 312 313struct radeon_gart { 314 dma_addr_t table_addr; 315 unsigned num_gpu_pages; 316 unsigned num_cpu_pages; 317 unsigned table_size; 318 union radeon_gart_table table; 319 struct page **pages; 320 dma_addr_t *pages_addr; 321 bool ready; 322}; 323 324int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 325void radeon_gart_table_ram_free(struct radeon_device *rdev); 326int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 327void radeon_gart_table_vram_free(struct radeon_device *rdev); 328int radeon_gart_init(struct radeon_device *rdev); 329void radeon_gart_fini(struct radeon_device *rdev); 330void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 331 int pages); 332int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 333 int pages, struct page **pagelist); 334 335 336/* 337 * GPU MC structures, functions & helpers 338 */ 339struct radeon_mc { 340 resource_size_t aper_size; 341 resource_size_t aper_base; 342 resource_size_t agp_base; 343 /* for some chips with <= 32MB we need to lie 344 * about vram size near mc fb location */ 345 u64 mc_vram_size; 346 u64 visible_vram_size; 347 u64 active_vram_size; 348 u64 gtt_size; 349 u64 gtt_start; 350 u64 gtt_end; 351 u64 vram_start; 352 u64 vram_end; 353 unsigned vram_width; 354 u64 real_vram_size; 355 int vram_mtrr; 356 bool vram_is_ddr; 357 bool igp_sideport_enabled; 358 u64 gtt_base_align; 359}; 360 361bool radeon_combios_sideport_present(struct radeon_device *rdev); 362bool radeon_atombios_sideport_present(struct radeon_device *rdev); 363 364/* 365 * GPU scratch registers structures, functions & helpers 366 */ 367struct radeon_scratch { 368 unsigned num_reg; 369 bool free[32]; 370 uint32_t reg[32]; 371}; 372 373int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 374void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 375 376 377/* 378 * IRQS. 379 */ 380struct radeon_irq { 381 bool installed; 382 bool sw_int; 383 bool crtc_vblank_int[6]; 384 wait_queue_head_t vblank_queue; 385 bool hpd[6]; 386 bool gui_idle; 387 bool gui_idle_acked; 388 wait_queue_head_t idle_queue; 389 bool hdmi[2]; 390 spinlock_t sw_lock; 391 int sw_refcount; 392}; 393 394int radeon_irq_kms_init(struct radeon_device *rdev); 395void radeon_irq_kms_fini(struct radeon_device *rdev); 396void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); 397void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); 398 399/* 400 * CP & ring. 401 */ 402struct radeon_ib { 403 struct list_head list; 404 unsigned idx; 405 uint64_t gpu_addr; 406 struct radeon_fence *fence; 407 uint32_t *ptr; 408 uint32_t length_dw; 409 bool free; 410}; 411 412/* 413 * locking - 414 * mutex protects scheduled_ibs, ready, alloc_bm 415 */ 416struct radeon_ib_pool { 417 struct mutex mutex; 418 struct radeon_bo *robj; 419 struct list_head bogus_ib; 420 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 421 bool ready; 422 unsigned head_id; 423}; 424 425struct radeon_cp { 426 struct radeon_bo *ring_obj; 427 volatile uint32_t *ring; 428 unsigned rptr; 429 unsigned wptr; 430 unsigned wptr_old; 431 unsigned ring_size; 432 unsigned ring_free_dw; 433 int count_dw; 434 uint64_t gpu_addr; 435 uint32_t align_mask; 436 uint32_t ptr_mask; 437 struct mutex mutex; 438 bool ready; 439}; 440 441/* 442 * R6xx+ IH ring 443 */ 444struct r600_ih { 445 struct radeon_bo *ring_obj; 446 volatile uint32_t *ring; 447 unsigned rptr; 448 unsigned wptr; 449 unsigned wptr_old; 450 unsigned ring_size; 451 uint64_t gpu_addr; 452 uint32_t ptr_mask; 453 spinlock_t lock; 454 bool enabled; 455}; 456 457struct r600_blit { 458 struct mutex mutex; 459 struct radeon_bo *shader_obj; 460 u64 shader_gpu_addr; 461 u32 vs_offset, ps_offset; 462 u32 state_offset; 463 u32 state_len; 464 u32 vb_used, vb_total; 465 struct radeon_ib *vb_ib; 466}; 467 468int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 469void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 470int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 471int radeon_ib_pool_init(struct radeon_device *rdev); 472void radeon_ib_pool_fini(struct radeon_device *rdev); 473int radeon_ib_test(struct radeon_device *rdev); 474extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); 475/* Ring access between begin & end cannot sleep */ 476void radeon_ring_free_size(struct radeon_device *rdev); 477int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); 478int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 479void radeon_ring_commit(struct radeon_device *rdev); 480void radeon_ring_unlock_commit(struct radeon_device *rdev); 481void radeon_ring_unlock_undo(struct radeon_device *rdev); 482int radeon_ring_test(struct radeon_device *rdev); 483int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 484void radeon_ring_fini(struct radeon_device *rdev); 485 486 487/* 488 * CS. 489 */ 490struct radeon_cs_reloc { 491 struct drm_gem_object *gobj; 492 struct radeon_bo *robj; 493 struct radeon_bo_list lobj; 494 uint32_t handle; 495 uint32_t flags; 496}; 497 498struct radeon_cs_chunk { 499 uint32_t chunk_id; 500 uint32_t length_dw; 501 int kpage_idx[2]; 502 uint32_t *kpage[2]; 503 uint32_t *kdata; 504 void __user *user_ptr; 505 int last_copied_page; 506 int last_page_index; 507}; 508 509struct radeon_cs_parser { 510 struct device *dev; 511 struct radeon_device *rdev; 512 struct drm_file *filp; 513 /* chunks */ 514 unsigned nchunks; 515 struct radeon_cs_chunk *chunks; 516 uint64_t *chunks_array; 517 /* IB */ 518 unsigned idx; 519 /* relocations */ 520 unsigned nrelocs; 521 struct radeon_cs_reloc *relocs; 522 struct radeon_cs_reloc **relocs_ptr; 523 struct list_head validated; 524 /* indices of various chunks */ 525 int chunk_ib_idx; 526 int chunk_relocs_idx; 527 struct radeon_ib *ib; 528 void *track; 529 unsigned family; 530 int parser_error; 531}; 532 533extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); 534extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 535 536 537static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 538{ 539 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 540 u32 pg_idx, pg_offset; 541 u32 idx_value = 0; 542 int new_page; 543 544 pg_idx = (idx * 4) / PAGE_SIZE; 545 pg_offset = (idx * 4) % PAGE_SIZE; 546 547 if (ibc->kpage_idx[0] == pg_idx) 548 return ibc->kpage[0][pg_offset/4]; 549 if (ibc->kpage_idx[1] == pg_idx) 550 return ibc->kpage[1][pg_offset/4]; 551 552 new_page = radeon_cs_update_pages(p, pg_idx); 553 if (new_page < 0) { 554 p->parser_error = new_page; 555 return 0; 556 } 557 558 idx_value = ibc->kpage[new_page][pg_offset/4]; 559 return idx_value; 560} 561 562struct radeon_cs_packet { 563 unsigned idx; 564 unsigned type; 565 unsigned reg; 566 unsigned opcode; 567 int count; 568 unsigned one_reg_wr; 569}; 570 571typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 572 struct radeon_cs_packet *pkt, 573 unsigned idx, unsigned reg); 574typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 575 struct radeon_cs_packet *pkt); 576 577 578/* 579 * AGP 580 */ 581int radeon_agp_init(struct radeon_device *rdev); 582void radeon_agp_resume(struct radeon_device *rdev); 583void radeon_agp_suspend(struct radeon_device *rdev); 584void radeon_agp_fini(struct radeon_device *rdev); 585 586 587/* 588 * Writeback 589 */ 590struct radeon_wb { 591 struct radeon_bo *wb_obj; 592 volatile uint32_t *wb; 593 uint64_t gpu_addr; 594}; 595 596/** 597 * struct radeon_pm - power management datas 598 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 599 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 600 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 601 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 602 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 603 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 604 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 605 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 606 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 607 * @sclk: GPU clock Mhz (core bandwith depends of this clock) 608 * @needed_bandwidth: current bandwidth needs 609 * 610 * It keeps track of various data needed to take powermanagement decision. 611 * Bandwith need is used to determine minimun clock of the GPU and memory. 612 * Equation between gpu/memory clock and available bandwidth is hw dependent 613 * (type of memory, bus size, efficiency, ...) 614 */ 615 616enum radeon_pm_method { 617 PM_METHOD_PROFILE, 618 PM_METHOD_DYNPM, 619}; 620 621enum radeon_dynpm_state { 622 DYNPM_STATE_DISABLED, 623 DYNPM_STATE_MINIMUM, 624 DYNPM_STATE_PAUSED, 625 DYNPM_STATE_ACTIVE, 626 DYNPM_STATE_SUSPENDED, 627}; 628enum radeon_dynpm_action { 629 DYNPM_ACTION_NONE, 630 DYNPM_ACTION_MINIMUM, 631 DYNPM_ACTION_DOWNCLOCK, 632 DYNPM_ACTION_UPCLOCK, 633 DYNPM_ACTION_DEFAULT 634}; 635 636enum radeon_voltage_type { 637 VOLTAGE_NONE = 0, 638 VOLTAGE_GPIO, 639 VOLTAGE_VDDC, 640 VOLTAGE_SW 641}; 642 643enum radeon_pm_state_type { 644 POWER_STATE_TYPE_DEFAULT, 645 POWER_STATE_TYPE_POWERSAVE, 646 POWER_STATE_TYPE_BATTERY, 647 POWER_STATE_TYPE_BALANCED, 648 POWER_STATE_TYPE_PERFORMANCE, 649}; 650 651enum radeon_pm_profile_type { 652 PM_PROFILE_DEFAULT, 653 PM_PROFILE_AUTO, 654 PM_PROFILE_LOW, 655 PM_PROFILE_MID, 656 PM_PROFILE_HIGH, 657}; 658 659#define PM_PROFILE_DEFAULT_IDX 0 660#define PM_PROFILE_LOW_SH_IDX 1 661#define PM_PROFILE_MID_SH_IDX 2 662#define PM_PROFILE_HIGH_SH_IDX 3 663#define PM_PROFILE_LOW_MH_IDX 4 664#define PM_PROFILE_MID_MH_IDX 5 665#define PM_PROFILE_HIGH_MH_IDX 6 666#define PM_PROFILE_MAX 7 667 668struct radeon_pm_profile { 669 int dpms_off_ps_idx; 670 int dpms_on_ps_idx; 671 int dpms_off_cm_idx; 672 int dpms_on_cm_idx; 673}; 674 675enum radeon_int_thermal_type { 676 THERMAL_TYPE_NONE, 677 THERMAL_TYPE_RV6XX, 678 THERMAL_TYPE_RV770, 679 THERMAL_TYPE_EVERGREEN, 680}; 681 682struct radeon_voltage { 683 enum radeon_voltage_type type; 684 /* gpio voltage */ 685 struct radeon_gpio_rec gpio; 686 u32 delay; /* delay in usec from voltage drop to sclk change */ 687 bool active_high; /* voltage drop is active when bit is high */ 688 /* VDDC voltage */ 689 u8 vddc_id; /* index into vddc voltage table */ 690 u8 vddci_id; /* index into vddci voltage table */ 691 bool vddci_enabled; 692 /* r6xx+ sw */ 693 u32 voltage; 694}; 695 696/* clock mode flags */ 697#define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 698 699struct radeon_pm_clock_info { 700 /* memory clock */ 701 u32 mclk; 702 /* engine clock */ 703 u32 sclk; 704 /* voltage info */ 705 struct radeon_voltage voltage; 706 /* standardized clock flags */ 707 u32 flags; 708}; 709 710/* state flags */ 711#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 712 713struct radeon_power_state { 714 enum radeon_pm_state_type type; 715 struct radeon_pm_clock_info clock_info[8]; 716 /* number of valid clock modes in this power state */ 717 int num_clock_modes; 718 struct radeon_pm_clock_info *default_clock_mode; 719 /* standardized state flags */ 720 u32 flags; 721 u32 misc; /* vbios specific flags */ 722 u32 misc2; /* vbios specific flags */ 723 int pcie_lanes; /* pcie lanes */ 724}; 725 726/* 727 * Some modes are overclocked by very low value, accept them 728 */ 729#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 730 731struct radeon_pm { 732 struct mutex mutex; 733 u32 active_crtcs; 734 int active_crtc_count; 735 int req_vblank; 736 bool vblank_sync; 737 bool gui_idle; 738 fixed20_12 max_bandwidth; 739 fixed20_12 igp_sideport_mclk; 740 fixed20_12 igp_system_mclk; 741 fixed20_12 igp_ht_link_clk; 742 fixed20_12 igp_ht_link_width; 743 fixed20_12 k8_bandwidth; 744 fixed20_12 sideport_bandwidth; 745 fixed20_12 ht_bandwidth; 746 fixed20_12 core_bandwidth; 747 fixed20_12 sclk; 748 fixed20_12 mclk; 749 fixed20_12 needed_bandwidth; 750 struct radeon_power_state power_state[8]; 751 /* number of valid power states */ 752 int num_power_states; 753 int current_power_state_index; 754 int current_clock_mode_index; 755 int requested_power_state_index; 756 int requested_clock_mode_index; 757 int default_power_state_index; 758 u32 current_sclk; 759 u32 current_mclk; 760 u32 current_vddc; 761 struct radeon_i2c_chan *i2c_bus; 762 /* selected pm method */ 763 enum radeon_pm_method pm_method; 764 /* dynpm power management */ 765 struct delayed_work dynpm_idle_work; 766 enum radeon_dynpm_state dynpm_state; 767 enum radeon_dynpm_action dynpm_planned_action; 768 unsigned long dynpm_action_timeout; 769 bool dynpm_can_upclock; 770 bool dynpm_can_downclock; 771 /* profile-based power management */ 772 enum radeon_pm_profile_type profile; 773 int profile_index; 774 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 775 /* internal thermal controller on rv6xx+ */ 776 enum radeon_int_thermal_type int_thermal_type; 777 struct device *int_hwmon_dev; 778}; 779 780 781/* 782 * Benchmarking 783 */ 784void radeon_benchmark(struct radeon_device *rdev); 785 786 787/* 788 * Testing 789 */ 790void radeon_test_moves(struct radeon_device *rdev); 791 792 793/* 794 * Debugfs 795 */ 796int radeon_debugfs_add_files(struct radeon_device *rdev, 797 struct drm_info_list *files, 798 unsigned nfiles); 799int radeon_debugfs_fence_init(struct radeon_device *rdev); 800 801 802/* 803 * ASIC specific functions. 804 */ 805struct radeon_asic { 806 int (*init)(struct radeon_device *rdev); 807 void (*fini)(struct radeon_device *rdev); 808 int (*resume)(struct radeon_device *rdev); 809 int (*suspend)(struct radeon_device *rdev); 810 void (*vga_set_state)(struct radeon_device *rdev, bool state); 811 bool (*gpu_is_lockup)(struct radeon_device *rdev); 812 int (*asic_reset)(struct radeon_device *rdev); 813 void (*gart_tlb_flush)(struct radeon_device *rdev); 814 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 815 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 816 void (*cp_fini)(struct radeon_device *rdev); 817 void (*cp_disable)(struct radeon_device *rdev); 818 void (*cp_commit)(struct radeon_device *rdev); 819 void (*ring_start)(struct radeon_device *rdev); 820 int (*ring_test)(struct radeon_device *rdev); 821 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 822 int (*irq_set)(struct radeon_device *rdev); 823 int (*irq_process)(struct radeon_device *rdev); 824 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 825 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 826 int (*cs_parse)(struct radeon_cs_parser *p); 827 int (*copy_blit)(struct radeon_device *rdev, 828 uint64_t src_offset, 829 uint64_t dst_offset, 830 unsigned num_pages, 831 struct radeon_fence *fence); 832 int (*copy_dma)(struct radeon_device *rdev, 833 uint64_t src_offset, 834 uint64_t dst_offset, 835 unsigned num_pages, 836 struct radeon_fence *fence); 837 int (*copy)(struct radeon_device *rdev, 838 uint64_t src_offset, 839 uint64_t dst_offset, 840 unsigned num_pages, 841 struct radeon_fence *fence); 842 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 843 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 844 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 845 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 846 int (*get_pcie_lanes)(struct radeon_device *rdev); 847 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 848 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 849 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 850 uint32_t tiling_flags, uint32_t pitch, 851 uint32_t offset, uint32_t obj_size); 852 void (*clear_surface_reg)(struct radeon_device *rdev, int reg); 853 void (*bandwidth_update)(struct radeon_device *rdev); 854 void (*hpd_init)(struct radeon_device *rdev); 855 void (*hpd_fini)(struct radeon_device *rdev); 856 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 857 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 858 /* ioctl hw specific callback. Some hw might want to perform special 859 * operation on specific ioctl. For instance on wait idle some hw 860 * might want to perform and HDP flush through MMIO as it seems that 861 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 862 * through ring. 863 */ 864 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 865 bool (*gui_idle)(struct radeon_device *rdev); 866 /* power management */ 867 void (*pm_misc)(struct radeon_device *rdev); 868 void (*pm_prepare)(struct radeon_device *rdev); 869 void (*pm_finish)(struct radeon_device *rdev); 870 void (*pm_init_profile)(struct radeon_device *rdev); 871 void (*pm_get_dynpm_state)(struct radeon_device *rdev); 872}; 873 874/* 875 * Asic structures 876 */ 877struct r100_gpu_lockup { 878 unsigned long last_jiffies; 879 u32 last_cp_rptr; 880}; 881 882struct r100_asic { 883 const unsigned *reg_safe_bm; 884 unsigned reg_safe_bm_size; 885 u32 hdp_cntl; 886 struct r100_gpu_lockup lockup; 887}; 888 889struct r300_asic { 890 const unsigned *reg_safe_bm; 891 unsigned reg_safe_bm_size; 892 u32 resync_scratch; 893 u32 hdp_cntl; 894 struct r100_gpu_lockup lockup; 895}; 896 897struct r600_asic { 898 unsigned max_pipes; 899 unsigned max_tile_pipes; 900 unsigned max_simds; 901 unsigned max_backends; 902 unsigned max_gprs; 903 unsigned max_threads; 904 unsigned max_stack_entries; 905 unsigned max_hw_contexts; 906 unsigned max_gs_threads; 907 unsigned sx_max_export_size; 908 unsigned sx_max_export_pos_size; 909 unsigned sx_max_export_smx_size; 910 unsigned sq_num_cf_insts; 911 unsigned tiling_nbanks; 912 unsigned tiling_npipes; 913 unsigned tiling_group_size; 914 unsigned tile_config; 915 struct r100_gpu_lockup lockup; 916}; 917 918struct rv770_asic { 919 unsigned max_pipes; 920 unsigned max_tile_pipes; 921 unsigned max_simds; 922 unsigned max_backends; 923 unsigned max_gprs; 924 unsigned max_threads; 925 unsigned max_stack_entries; 926 unsigned max_hw_contexts; 927 unsigned max_gs_threads; 928 unsigned sx_max_export_size; 929 unsigned sx_max_export_pos_size; 930 unsigned sx_max_export_smx_size; 931 unsigned sq_num_cf_insts; 932 unsigned sx_num_of_sets; 933 unsigned sc_prim_fifo_size; 934 unsigned sc_hiz_tile_fifo_size; 935 unsigned sc_earlyz_tile_fifo_fize; 936 unsigned tiling_nbanks; 937 unsigned tiling_npipes; 938 unsigned tiling_group_size; 939 unsigned tile_config; 940 struct r100_gpu_lockup lockup; 941}; 942 943struct evergreen_asic { 944 unsigned num_ses; 945 unsigned max_pipes; 946 unsigned max_tile_pipes; 947 unsigned max_simds; 948 unsigned max_backends; 949 unsigned max_gprs; 950 unsigned max_threads; 951 unsigned max_stack_entries; 952 unsigned max_hw_contexts; 953 unsigned max_gs_threads; 954 unsigned sx_max_export_size; 955 unsigned sx_max_export_pos_size; 956 unsigned sx_max_export_smx_size; 957 unsigned sq_num_cf_insts; 958 unsigned sx_num_of_sets; 959 unsigned sc_prim_fifo_size; 960 unsigned sc_hiz_tile_fifo_size; 961 unsigned sc_earlyz_tile_fifo_size; 962 unsigned tiling_nbanks; 963 unsigned tiling_npipes; 964 unsigned tiling_group_size; 965 unsigned tile_config; 966}; 967 968union radeon_asic_config { 969 struct r300_asic r300; 970 struct r100_asic r100; 971 struct r600_asic r600; 972 struct rv770_asic rv770; 973 struct evergreen_asic evergreen; 974}; 975 976/* 977 * asic initizalization from radeon_asic.c 978 */ 979void radeon_agp_disable(struct radeon_device *rdev); 980int radeon_asic_init(struct radeon_device *rdev); 981 982 983/* 984 * IOCTL. 985 */ 986int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 987 struct drm_file *filp); 988int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 989 struct drm_file *filp); 990int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 991 struct drm_file *file_priv); 992int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 993 struct drm_file *file_priv); 994int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 995 struct drm_file *file_priv); 996int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 997 struct drm_file *file_priv); 998int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 999 struct drm_file *filp); 1000int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1001 struct drm_file *filp); 1002int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1003 struct drm_file *filp); 1004int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1005 struct drm_file *filp); 1006int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1007int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1008 struct drm_file *filp); 1009int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1010 struct drm_file *filp); 1011 1012/* VRAM scratch page for HDP bug */ 1013struct r700_vram_scratch { 1014 struct radeon_bo *robj; 1015 volatile uint32_t *ptr; 1016}; 1017 1018/* 1019 * Core structure, functions and helpers. 1020 */ 1021typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1022typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1023 1024struct radeon_device { 1025 struct device *dev; 1026 struct drm_device *ddev; 1027 struct pci_dev *pdev; 1028 /* ASIC */ 1029 union radeon_asic_config config; 1030 enum radeon_family family; 1031 unsigned long flags; 1032 int usec_timeout; 1033 enum radeon_pll_errata pll_errata; 1034 int num_gb_pipes; 1035 int num_z_pipes; 1036 int disp_priority; 1037 /* BIOS */ 1038 uint8_t *bios; 1039 bool is_atom_bios; 1040 uint16_t bios_header_start; 1041 struct radeon_bo *stollen_vga_memory; 1042 /* Register mmio */ 1043 resource_size_t rmmio_base; 1044 resource_size_t rmmio_size; 1045 void *rmmio; 1046 radeon_rreg_t mc_rreg; 1047 radeon_wreg_t mc_wreg; 1048 radeon_rreg_t pll_rreg; 1049 radeon_wreg_t pll_wreg; 1050 uint32_t pcie_reg_mask; 1051 radeon_rreg_t pciep_rreg; 1052 radeon_wreg_t pciep_wreg; 1053 /* io port */ 1054 void __iomem *rio_mem; 1055 resource_size_t rio_mem_size; 1056 struct radeon_clock clock; 1057 struct radeon_mc mc; 1058 struct radeon_gart gart; 1059 struct radeon_mode_info mode_info; 1060 struct radeon_scratch scratch; 1061 struct radeon_mman mman; 1062 struct radeon_fence_driver fence_drv; 1063 struct radeon_cp cp; 1064 struct radeon_ib_pool ib_pool; 1065 struct radeon_irq irq; 1066 struct radeon_asic *asic; 1067 struct radeon_gem gem; 1068 struct radeon_pm pm; 1069 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1070 struct mutex cs_mutex; 1071 struct radeon_wb wb; 1072 struct radeon_dummy_page dummy_page; 1073 bool gpu_lockup; 1074 bool shutdown; 1075 bool suspend; 1076 bool need_dma32; 1077 bool accel_working; 1078 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1079 const struct firmware *me_fw; /* all family ME firmware */ 1080 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1081 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1082 struct r600_blit r600_blit; 1083 struct r700_vram_scratch vram_scratch; 1084 int msi_enabled; /* msi enabled */ 1085 struct r600_ih ih; /* r6/700 interrupt ring */ 1086 struct workqueue_struct *wq; 1087 struct work_struct hotplug_work; 1088 int num_crtc; /* number of crtcs */ 1089 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1090 struct mutex vram_mutex; 1091 1092 /* audio stuff */ 1093 bool audio_enabled; 1094 struct timer_list audio_timer; 1095 int audio_channels; 1096 int audio_rate; 1097 int audio_bits_per_sample; 1098 uint8_t audio_status_bits; 1099 uint8_t audio_category_code; 1100 1101 bool powered_down; 1102 struct notifier_block acpi_nb; 1103 /* only one userspace can use Hyperz features at a time */ 1104 struct drm_file *hyperz_filp; 1105 /* i2c buses */ 1106 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1107}; 1108 1109int radeon_device_init(struct radeon_device *rdev, 1110 struct drm_device *ddev, 1111 struct pci_dev *pdev, 1112 uint32_t flags); 1113void radeon_device_fini(struct radeon_device *rdev); 1114int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1115 1116/* r600 blit */ 1117int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); 1118void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); 1119void r600_kms_blit_copy(struct radeon_device *rdev, 1120 u64 src_gpu_addr, u64 dst_gpu_addr, 1121 int size_bytes); 1122 1123static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 1124{ 1125 if (reg < rdev->rmmio_size) 1126 return readl(((void __iomem *)rdev->rmmio) + reg); 1127 else { 1128 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 1129 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 1130 } 1131} 1132 1133static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1134{ 1135 if (reg < rdev->rmmio_size) 1136 writel(v, ((void __iomem *)rdev->rmmio) + reg); 1137 else { 1138 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 1139 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 1140 } 1141} 1142 1143static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 1144{ 1145 if (reg < rdev->rio_mem_size) 1146 return ioread32(rdev->rio_mem + reg); 1147 else { 1148 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 1149 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 1150 } 1151} 1152 1153static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1154{ 1155 if (reg < rdev->rio_mem_size) 1156 iowrite32(v, rdev->rio_mem + reg); 1157 else { 1158 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 1159 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 1160 } 1161} 1162 1163/* 1164 * Cast helper 1165 */ 1166#define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1167 1168/* 1169 * Registers read & write functions. 1170 */ 1171#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 1172#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 1173#define RREG32(reg) r100_mm_rreg(rdev, (reg)) 1174#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1175#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 1176#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1177#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1178#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1179#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1180#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1181#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1182#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1183#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1184#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1185#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1186#define WREG32_P(reg, val, mask) \ 1187 do { \ 1188 uint32_t tmp_ = RREG32(reg); \ 1189 tmp_ &= (mask); \ 1190 tmp_ |= ((val) & ~(mask)); \ 1191 WREG32(reg, tmp_); \ 1192 } while (0) 1193#define WREG32_PLL_P(reg, val, mask) \ 1194 do { \ 1195 uint32_t tmp_ = RREG32_PLL(reg); \ 1196 tmp_ &= (mask); \ 1197 tmp_ |= ((val) & ~(mask)); \ 1198 WREG32_PLL(reg, tmp_); \ 1199 } while (0) 1200#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 1201#define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1202#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1203 1204/* 1205 * Indirect registers accessor 1206 */ 1207static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1208{ 1209 uint32_t r; 1210 1211 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1212 r = RREG32(RADEON_PCIE_DATA); 1213 return r; 1214} 1215 1216static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1217{ 1218 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1219 WREG32(RADEON_PCIE_DATA, (v)); 1220} 1221 1222void r100_pll_errata_after_index(struct radeon_device *rdev); 1223 1224 1225/* 1226 * ASICs helpers. 1227 */ 1228#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 1229 (rdev->pdev->device == 0x5969)) 1230#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1231 (rdev->family == CHIP_RV200) || \ 1232 (rdev->family == CHIP_RS100) || \ 1233 (rdev->family == CHIP_RS200) || \ 1234 (rdev->family == CHIP_RV250) || \ 1235 (rdev->family == CHIP_RV280) || \ 1236 (rdev->family == CHIP_RS300)) 1237#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1238 (rdev->family == CHIP_RV350) || \ 1239 (rdev->family == CHIP_R350) || \ 1240 (rdev->family == CHIP_RV380) || \ 1241 (rdev->family == CHIP_R420) || \ 1242 (rdev->family == CHIP_R423) || \ 1243 (rdev->family == CHIP_RV410) || \ 1244 (rdev->family == CHIP_RS400) || \ 1245 (rdev->family == CHIP_RS480)) 1246#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1247#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1248#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1249#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1250 1251/* 1252 * BIOS helpers. 1253 */ 1254#define RBIOS8(i) (rdev->bios[i]) 1255#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1256#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1257 1258int radeon_combios_init(struct radeon_device *rdev); 1259void radeon_combios_fini(struct radeon_device *rdev); 1260int radeon_atombios_init(struct radeon_device *rdev); 1261void radeon_atombios_fini(struct radeon_device *rdev); 1262 1263 1264/* 1265 * RING helpers. 1266 */ 1267static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 1268{ 1269#if DRM_DEBUG_CODE 1270 if (rdev->cp.count_dw <= 0) { 1271 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 1272 } 1273#endif 1274 rdev->cp.ring[rdev->cp.wptr++] = v; 1275 rdev->cp.wptr &= rdev->cp.ptr_mask; 1276 rdev->cp.count_dw--; 1277 rdev->cp.ring_free_dw--; 1278} 1279 1280 1281/* 1282 * ASICs macro. 1283 */ 1284#define radeon_init(rdev) (rdev)->asic->init((rdev)) 1285#define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1286#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1287#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1288#define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 1289#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1290#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) 1291#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1292#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 1293#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 1294#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 1295#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 1296#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 1297#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 1298#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 1299#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 1300#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 1301#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 1302#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 1303#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 1304#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 1305#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) 1306#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 1307#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) 1308#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) 1309#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) 1310#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 1311#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 1312#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 1313#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 1314#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 1315#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) 1316#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) 1317#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) 1318#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1319#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1320#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) 1321#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) 1322#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) 1323#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) 1324#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) 1325 1326/* Common functions */ 1327/* AGP */ 1328extern int radeon_gpu_reset(struct radeon_device *rdev); 1329extern void radeon_agp_disable(struct radeon_device *rdev); 1330extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1331extern void radeon_gart_restore(struct radeon_device *rdev); 1332extern int radeon_modeset_init(struct radeon_device *rdev); 1333extern void radeon_modeset_fini(struct radeon_device *rdev); 1334extern bool radeon_card_posted(struct radeon_device *rdev); 1335extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1336extern void radeon_update_display_priority(struct radeon_device *rdev); 1337extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1338extern void radeon_scratch_init(struct radeon_device *rdev); 1339extern void radeon_surface_init(struct radeon_device *rdev); 1340extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1341extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1342extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1343extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1344extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1345extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1346extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1347extern int radeon_resume_kms(struct drm_device *dev); 1348extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1349 1350/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1351extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp); 1352extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp); 1353 1354/* rv200,rv250,rv280 */ 1355extern void r200_set_safe_registers(struct radeon_device *rdev); 1356 1357/* r300,r350,rv350,rv370,rv380 */ 1358extern void r300_set_reg_safe(struct radeon_device *rdev); 1359extern void r300_mc_program(struct radeon_device *rdev); 1360extern void r300_mc_init(struct radeon_device *rdev); 1361extern void r300_clock_startup(struct radeon_device *rdev); 1362extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 1363extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1364extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 1365extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 1366extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1367 1368/* r420,r423,rv410 */ 1369extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1370extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1371extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1372extern void r420_pipes_init(struct radeon_device *rdev); 1373 1374/* rv515 */ 1375struct rv515_mc_save { 1376 u32 d1vga_control; 1377 u32 d2vga_control; 1378 u32 vga_render_control; 1379 u32 vga_hdp_control; 1380 u32 d1crtc_control; 1381 u32 d2crtc_control; 1382}; 1383extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1384extern void rv515_vga_render_disable(struct radeon_device *rdev); 1385extern void rv515_set_safe_registers(struct radeon_device *rdev); 1386extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 1387extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 1388extern void rv515_clock_startup(struct radeon_device *rdev); 1389extern void rv515_debugfs(struct radeon_device *rdev); 1390extern int rv515_suspend(struct radeon_device *rdev); 1391 1392/* rs400 */ 1393extern int rs400_gart_init(struct radeon_device *rdev); 1394extern int rs400_gart_enable(struct radeon_device *rdev); 1395extern void rs400_gart_adjust_size(struct radeon_device *rdev); 1396extern void rs400_gart_disable(struct radeon_device *rdev); 1397extern void rs400_gart_fini(struct radeon_device *rdev); 1398 1399/* rs600 */ 1400extern void rs600_set_safe_registers(struct radeon_device *rdev); 1401extern int rs600_irq_set(struct radeon_device *rdev); 1402extern void rs600_irq_disable(struct radeon_device *rdev); 1403 1404/* rs690, rs740 */ 1405extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1406 struct drm_display_mode *mode1, 1407 struct drm_display_mode *mode2); 1408 1409/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1410extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1411extern bool r600_card_posted(struct radeon_device *rdev); 1412extern void r600_cp_stop(struct radeon_device *rdev); 1413extern int r600_cp_start(struct radeon_device *rdev); 1414extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1415extern int r600_cp_resume(struct radeon_device *rdev); 1416extern void r600_cp_fini(struct radeon_device *rdev); 1417extern int r600_count_pipe_bits(uint32_t val); 1418extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1419extern int r600_pcie_gart_init(struct radeon_device *rdev); 1420extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 1421extern int r600_ib_test(struct radeon_device *rdev); 1422extern int r600_ring_test(struct radeon_device *rdev); 1423extern void r600_wb_fini(struct radeon_device *rdev); 1424extern int r600_wb_enable(struct radeon_device *rdev); 1425extern void r600_wb_disable(struct radeon_device *rdev); 1426extern void r600_scratch_init(struct radeon_device *rdev); 1427extern int r600_blit_init(struct radeon_device *rdev); 1428extern void r600_blit_fini(struct radeon_device *rdev); 1429extern int r600_init_microcode(struct radeon_device *rdev); 1430extern int r600_asic_reset(struct radeon_device *rdev); 1431/* r600 irq */ 1432extern int r600_irq_init(struct radeon_device *rdev); 1433extern void r600_irq_fini(struct radeon_device *rdev); 1434extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1435extern int r600_irq_set(struct radeon_device *rdev); 1436extern void r600_irq_suspend(struct radeon_device *rdev); 1437extern void r600_disable_interrupts(struct radeon_device *rdev); 1438extern void r600_rlc_stop(struct radeon_device *rdev); 1439/* r600 audio */ 1440extern int r600_audio_init(struct radeon_device *rdev); 1441extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1442extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1443extern int r600_audio_channels(struct radeon_device *rdev); 1444extern int r600_audio_bits_per_sample(struct radeon_device *rdev); 1445extern int r600_audio_rate(struct radeon_device *rdev); 1446extern uint8_t r600_audio_status_bits(struct radeon_device *rdev); 1447extern uint8_t r600_audio_category_code(struct radeon_device *rdev); 1448extern void r600_audio_schedule_polling(struct radeon_device *rdev); 1449extern void r600_audio_enable_polling(struct drm_encoder *encoder); 1450extern void r600_audio_disable_polling(struct drm_encoder *encoder); 1451extern void r600_audio_fini(struct radeon_device *rdev); 1452extern void r600_hdmi_init(struct drm_encoder *encoder); 1453extern void r600_hdmi_enable(struct drm_encoder *encoder); 1454extern void r600_hdmi_disable(struct drm_encoder *encoder); 1455extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1456extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 1457extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 1458 1459extern void r700_cp_stop(struct radeon_device *rdev); 1460extern void r700_cp_fini(struct radeon_device *rdev); 1461extern void evergreen_disable_interrupt_state(struct radeon_device *rdev); 1462extern int evergreen_irq_set(struct radeon_device *rdev); 1463 1464/* radeon_acpi.c */ 1465#if defined(CONFIG_ACPI) 1466extern int radeon_acpi_init(struct radeon_device *rdev); 1467#else 1468static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 1469#endif 1470 1471/* evergreen */ 1472struct evergreen_mc_save { 1473 u32 vga_control[6]; 1474 u32 vga_render_control; 1475 u32 vga_hdp_control; 1476 u32 crtc_control[6]; 1477}; 1478 1479#include "radeon_object.h" 1480 1481#endif 1482