1/* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27#ifndef R600D_H 28#define R600D_H 29 30#define CP_PACKET2 0x80000000 31#define PACKET2_PAD_SHIFT 0 32#define PACKET2_PAD_MASK (0x3fffffff << 0) 33 34#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 35 36#define R6XX_MAX_SH_GPRS 256 37#define R6XX_MAX_TEMP_GPRS 16 38#define R6XX_MAX_SH_THREADS 256 39#define R6XX_MAX_SH_STACK_ENTRIES 4096 40#define R6XX_MAX_BACKENDS 8 41#define R6XX_MAX_BACKENDS_MASK 0xff 42#define R6XX_MAX_SIMDS 8 43#define R6XX_MAX_SIMDS_MASK 0xff 44#define R6XX_MAX_PIPES 8 45#define R6XX_MAX_PIPES_MASK 0xff 46 47/* PTE flags */ 48#define PTE_VALID (1 << 0) 49#define PTE_SYSTEM (1 << 1) 50#define PTE_SNOOPED (1 << 2) 51#define PTE_READABLE (1 << 5) 52#define PTE_WRITEABLE (1 << 6) 53 54/* Registers */ 55#define ARB_POP 0x2418 56#define ENABLE_TC128 (1 << 30) 57#define ARB_GDEC_RD_CNTL 0x246C 58 59#define CC_GC_SHADER_PIPE_CONFIG 0x8950 60#define CC_RB_BACKEND_DISABLE 0x98F4 61#define BACKEND_DISABLE(x) ((x) << 16) 62 63#define CB_COLOR0_BASE 0x28040 64#define CB_COLOR1_BASE 0x28044 65#define CB_COLOR2_BASE 0x28048 66#define CB_COLOR3_BASE 0x2804C 67#define CB_COLOR4_BASE 0x28050 68#define CB_COLOR5_BASE 0x28054 69#define CB_COLOR6_BASE 0x28058 70#define CB_COLOR7_BASE 0x2805C 71#define CB_COLOR7_FRAG 0x280FC 72 73#define CB_COLOR0_SIZE 0x28060 74#define CB_COLOR0_VIEW 0x28080 75#define CB_COLOR0_INFO 0x280a0 76#define CB_COLOR0_TILE 0x280c0 77#define CB_COLOR0_FRAG 0x280e0 78#define CB_COLOR0_MASK 0x28100 79 80#define SQ_ALU_CONST_CACHE_PS_0 0x28940 81#define SQ_ALU_CONST_CACHE_PS_1 0x28944 82#define SQ_ALU_CONST_CACHE_PS_2 0x28948 83#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 84#define SQ_ALU_CONST_CACHE_PS_4 0x28950 85#define SQ_ALU_CONST_CACHE_PS_5 0x28954 86#define SQ_ALU_CONST_CACHE_PS_6 0x28958 87#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 88#define SQ_ALU_CONST_CACHE_PS_8 0x28960 89#define SQ_ALU_CONST_CACHE_PS_9 0x28964 90#define SQ_ALU_CONST_CACHE_PS_10 0x28968 91#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 92#define SQ_ALU_CONST_CACHE_PS_12 0x28970 93#define SQ_ALU_CONST_CACHE_PS_13 0x28974 94#define SQ_ALU_CONST_CACHE_PS_14 0x28978 95#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 96#define SQ_ALU_CONST_CACHE_VS_0 0x28980 97#define SQ_ALU_CONST_CACHE_VS_1 0x28984 98#define SQ_ALU_CONST_CACHE_VS_2 0x28988 99#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 100#define SQ_ALU_CONST_CACHE_VS_4 0x28990 101#define SQ_ALU_CONST_CACHE_VS_5 0x28994 102#define SQ_ALU_CONST_CACHE_VS_6 0x28998 103#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 104#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 105#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 106#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 107#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 108#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 109#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 110#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 111#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 112#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 113#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 114#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 115#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 116#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 117#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 118#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 119#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 120#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 121#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 122#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 123#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 124#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 125#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 126#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 127#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 128 129#define CONFIG_MEMSIZE 0x5428 130#define CONFIG_CNTL 0x5424 131#define CP_STAT 0x8680 132#define CP_COHER_BASE 0x85F8 133#define CP_DEBUG 0xC1FC 134#define R_0086D8_CP_ME_CNTL 0x86D8 135#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 136#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 137#define CP_ME_RAM_DATA 0xC160 138#define CP_ME_RAM_RADDR 0xC158 139#define CP_ME_RAM_WADDR 0xC15C 140#define CP_MEQ_THRESHOLDS 0x8764 141#define MEQ_END(x) ((x) << 16) 142#define ROQ_END(x) ((x) << 24) 143#define CP_PERFMON_CNTL 0x87FC 144#define CP_PFP_UCODE_ADDR 0xC150 145#define CP_PFP_UCODE_DATA 0xC154 146#define CP_QUEUE_THRESHOLDS 0x8760 147#define ROQ_IB1_START(x) ((x) << 0) 148#define ROQ_IB2_START(x) ((x) << 8) 149#define CP_RB_BASE 0xC100 150#define CP_RB_CNTL 0xC104 151#define RB_BUFSZ(x) ((x)<<0) 152#define RB_BLKSZ(x) ((x)<<8) 153#define RB_NO_UPDATE (1<<27) 154#define RB_RPTR_WR_ENA (1<<31) 155#define BUF_SWAP_32BIT (2 << 16) 156#define CP_RB_RPTR 0x8700 157#define CP_RB_RPTR_ADDR 0xC10C 158#define CP_RB_RPTR_ADDR_HI 0xC110 159#define CP_RB_RPTR_WR 0xC108 160#define CP_RB_WPTR 0xC114 161#define CP_RB_WPTR_ADDR 0xC118 162#define CP_RB_WPTR_ADDR_HI 0xC11C 163#define CP_RB_WPTR_DELAY 0x8704 164#define CP_ROQ_IB1_STAT 0x8784 165#define CP_ROQ_IB2_STAT 0x8788 166#define CP_SEM_WAIT_TIMER 0x85BC 167 168#define DB_DEBUG 0x9830 169#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 170#define DB_DEPTH_BASE 0x2800C 171#define DB_HTILE_DATA_BASE 0x28014 172#define DB_WATERMARKS 0x9838 173#define DEPTH_FREE(x) ((x) << 0) 174#define DEPTH_FLUSH(x) ((x) << 5) 175#define DEPTH_PENDING_FREE(x) ((x) << 15) 176#define DEPTH_CACHELINE_FREE(x) ((x) << 20) 177 178#define DCP_TILING_CONFIG 0x6CA0 179#define PIPE_TILING(x) ((x) << 1) 180#define BANK_TILING(x) ((x) << 4) 181#define GROUP_SIZE(x) ((x) << 6) 182#define ROW_TILING(x) ((x) << 8) 183#define BANK_SWAPS(x) ((x) << 11) 184#define SAMPLE_SPLIT(x) ((x) << 14) 185#define BACKEND_MAP(x) ((x) << 16) 186 187#define GB_TILING_CONFIG 0x98F0 188 189#define GC_USER_SHADER_PIPE_CONFIG 0x8954 190#define INACTIVE_QD_PIPES(x) ((x) << 8) 191#define INACTIVE_QD_PIPES_MASK 0x0000FF00 192#define INACTIVE_SIMDS(x) ((x) << 16) 193#define INACTIVE_SIMDS_MASK 0x00FF0000 194 195#define SQ_CONFIG 0x8c00 196# define VC_ENABLE (1 << 0) 197# define EXPORT_SRC_C (1 << 1) 198# define DX9_CONSTS (1 << 2) 199# define ALU_INST_PREFER_VECTOR (1 << 3) 200# define DX10_CLAMP (1 << 4) 201# define CLAUSE_SEQ_PRIO(x) ((x) << 8) 202# define PS_PRIO(x) ((x) << 24) 203# define VS_PRIO(x) ((x) << 26) 204# define GS_PRIO(x) ((x) << 28) 205# define ES_PRIO(x) ((x) << 30) 206#define SQ_GPR_RESOURCE_MGMT_1 0x8c04 207# define NUM_PS_GPRS(x) ((x) << 0) 208# define NUM_VS_GPRS(x) ((x) << 16) 209# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 210#define SQ_GPR_RESOURCE_MGMT_2 0x8c08 211# define NUM_GS_GPRS(x) ((x) << 0) 212# define NUM_ES_GPRS(x) ((x) << 16) 213#define SQ_THREAD_RESOURCE_MGMT 0x8c0c 214# define NUM_PS_THREADS(x) ((x) << 0) 215# define NUM_VS_THREADS(x) ((x) << 8) 216# define NUM_GS_THREADS(x) ((x) << 16) 217# define NUM_ES_THREADS(x) ((x) << 24) 218#define SQ_STACK_RESOURCE_MGMT_1 0x8c10 219# define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 220# define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 221#define SQ_STACK_RESOURCE_MGMT_2 0x8c14 222# define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 223# define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 224#define SQ_ESGS_RING_BASE 0x8c40 225#define SQ_GSVS_RING_BASE 0x8c48 226#define SQ_ESTMP_RING_BASE 0x8c50 227#define SQ_GSTMP_RING_BASE 0x8c58 228#define SQ_VSTMP_RING_BASE 0x8c60 229#define SQ_PSTMP_RING_BASE 0x8c68 230#define SQ_FBUF_RING_BASE 0x8c70 231#define SQ_REDUC_RING_BASE 0x8c78 232 233#define GRBM_CNTL 0x8000 234# define GRBM_READ_TIMEOUT(x) ((x) << 0) 235#define GRBM_STATUS 0x8010 236#define CMDFIFO_AVAIL_MASK 0x0000001F 237#define GUI_ACTIVE (1<<31) 238#define GRBM_STATUS2 0x8014 239#define GRBM_SOFT_RESET 0x8020 240#define SOFT_RESET_CP (1<<0) 241 242#define CG_THERMAL_STATUS 0x7F4 243#define ASIC_T(x) ((x) << 0) 244#define ASIC_T_MASK 0x1FF 245#define ASIC_T_SHIFT 0 246 247#define HDP_HOST_PATH_CNTL 0x2C00 248#define HDP_NONSURFACE_BASE 0x2C04 249#define HDP_NONSURFACE_INFO 0x2C08 250#define HDP_NONSURFACE_SIZE 0x2C0C 251#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 252#define HDP_TILING_CONFIG 0x2F3C 253#define HDP_DEBUG1 0x2F34 254 255#define MC_VM_AGP_TOP 0x2184 256#define MC_VM_AGP_BOT 0x2188 257#define MC_VM_AGP_BASE 0x218C 258#define MC_VM_FB_LOCATION 0x2180 259#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 260#define ENABLE_L1_TLB (1 << 0) 261#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 262#define ENABLE_L1_STRICT_ORDERING (1 << 2) 263#define SYSTEM_ACCESS_MODE_MASK 0x000000C0 264#define SYSTEM_ACCESS_MODE_SHIFT 6 265#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 266#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 267#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 268#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 269#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 270#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 271#define ENABLE_SEMAPHORE_MODE (1 << 10) 272#define ENABLE_WAIT_L2_QUERY (1 << 11) 273#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 274#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 275#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 276#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 277#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 278#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 279#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 280#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 281#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 282#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 283#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 284#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 285#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 286#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 287#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 288#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 289#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 290#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 291#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 292#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 293#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 294#define LOGICAL_PAGE_NUMBER_SHIFT 0 295#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 296#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 297 298#define PA_CL_ENHANCE 0x8A14 299#define CLIP_VTX_REORDER_ENA (1 << 0) 300#define NUM_CLIP_SEQ(x) ((x) << 1) 301#define PA_SC_AA_CONFIG 0x28C04 302#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 303#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 304#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 305#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 306#define S0_X(x) ((x) << 0) 307#define S0_Y(x) ((x) << 4) 308#define S1_X(x) ((x) << 8) 309#define S1_Y(x) ((x) << 12) 310#define S2_X(x) ((x) << 16) 311#define S2_Y(x) ((x) << 20) 312#define S3_X(x) ((x) << 24) 313#define S3_Y(x) ((x) << 28) 314#define S4_X(x) ((x) << 0) 315#define S4_Y(x) ((x) << 4) 316#define S5_X(x) ((x) << 8) 317#define S5_Y(x) ((x) << 12) 318#define S6_X(x) ((x) << 16) 319#define S6_Y(x) ((x) << 20) 320#define S7_X(x) ((x) << 24) 321#define S7_Y(x) ((x) << 28) 322#define PA_SC_CLIPRECT_RULE 0x2820c 323#define PA_SC_ENHANCE 0x8BF0 324#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 325#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 326#define PA_SC_LINE_STIPPLE 0x28A0C 327#define PA_SC_LINE_STIPPLE_STATE 0x8B10 328#define PA_SC_MODE_CNTL 0x28A4C 329#define PA_SC_MULTI_CHIP_CNTL 0x8B20 330 331#define PA_SC_SCREEN_SCISSOR_TL 0x28030 332#define PA_SC_GENERIC_SCISSOR_TL 0x28240 333#define PA_SC_WINDOW_SCISSOR_TL 0x28204 334 335#define PCIE_PORT_INDEX 0x0038 336#define PCIE_PORT_DATA 0x003C 337 338#define CHMAP 0x2004 339#define NOOFCHAN_SHIFT 12 340#define NOOFCHAN_MASK 0x00003000 341 342#define RAMCFG 0x2408 343#define NOOFBANK_SHIFT 0 344#define NOOFBANK_MASK 0x00000001 345#define NOOFRANK_SHIFT 1 346#define NOOFRANK_MASK 0x00000002 347#define NOOFROWS_SHIFT 2 348#define NOOFROWS_MASK 0x0000001C 349#define NOOFCOLS_SHIFT 5 350#define NOOFCOLS_MASK 0x00000060 351#define CHANSIZE_SHIFT 7 352#define CHANSIZE_MASK 0x00000080 353#define BURSTLENGTH_SHIFT 8 354#define BURSTLENGTH_MASK 0x00000100 355#define CHANSIZE_OVERRIDE (1 << 10) 356 357#define SCRATCH_REG0 0x8500 358#define SCRATCH_REG1 0x8504 359#define SCRATCH_REG2 0x8508 360#define SCRATCH_REG3 0x850C 361#define SCRATCH_REG4 0x8510 362#define SCRATCH_REG5 0x8514 363#define SCRATCH_REG6 0x8518 364#define SCRATCH_REG7 0x851C 365#define SCRATCH_UMSK 0x8540 366#define SCRATCH_ADDR 0x8544 367 368#define SPI_CONFIG_CNTL 0x9100 369#define GPR_WRITE_PRIORITY(x) ((x) << 0) 370#define DISABLE_INTERP_1 (1 << 5) 371#define SPI_CONFIG_CNTL_1 0x913C 372#define VTX_DONE_DELAY(x) ((x) << 0) 373#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 374#define SPI_INPUT_Z 0x286D8 375#define SPI_PS_IN_CONTROL_0 0x286CC 376#define NUM_INTERP(x) ((x)<<0) 377#define POSITION_ENA (1<<8) 378#define POSITION_CENTROID (1<<9) 379#define POSITION_ADDR(x) ((x)<<10) 380#define PARAM_GEN(x) ((x)<<15) 381#define PARAM_GEN_ADDR(x) ((x)<<19) 382#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 383#define PERSP_GRADIENT_ENA (1<<28) 384#define LINEAR_GRADIENT_ENA (1<<29) 385#define POSITION_SAMPLE (1<<30) 386#define BARYC_AT_SAMPLE_ENA (1<<31) 387#define SPI_PS_IN_CONTROL_1 0x286D0 388#define GEN_INDEX_PIX (1<<0) 389#define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 390#define FRONT_FACE_ENA (1<<8) 391#define FRONT_FACE_CHAN(x) ((x)<<9) 392#define FRONT_FACE_ALL_BITS (1<<11) 393#define FRONT_FACE_ADDR(x) ((x)<<12) 394#define FOG_ADDR(x) ((x)<<17) 395#define FIXED_PT_POSITION_ENA (1<<24) 396#define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 397 398#define SQ_MS_FIFO_SIZES 0x8CF0 399#define CACHE_FIFO_SIZE(x) ((x) << 0) 400#define FETCH_FIFO_HIWATER(x) ((x) << 8) 401#define DONE_FIFO_HIWATER(x) ((x) << 16) 402#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 403#define SQ_PGM_START_ES 0x28880 404#define SQ_PGM_START_FS 0x28894 405#define SQ_PGM_START_GS 0x2886C 406#define SQ_PGM_START_PS 0x28840 407#define SQ_PGM_RESOURCES_PS 0x28850 408#define SQ_PGM_EXPORTS_PS 0x28854 409#define SQ_PGM_CF_OFFSET_PS 0x288cc 410#define SQ_PGM_START_VS 0x28858 411#define SQ_PGM_RESOURCES_VS 0x28868 412#define SQ_PGM_CF_OFFSET_VS 0x288d0 413#define SQ_VTX_CONSTANT_WORD6_0 0x38018 414#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 415#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 416#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 417#define SQ_TEX_VTX_INVALID_BUFFER 0x1 418#define SQ_TEX_VTX_VALID_TEXTURE 0x2 419#define SQ_TEX_VTX_VALID_BUFFER 0x3 420 421 422#define SX_MISC 0x28350 423#define SX_MEMORY_EXPORT_BASE 0x9010 424#define SX_DEBUG_1 0x9054 425#define SMX_EVENT_RELEASE (1 << 0) 426#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 427 428#define TA_CNTL_AUX 0x9508 429#define DISABLE_CUBE_WRAP (1 << 0) 430#define DISABLE_CUBE_ANISO (1 << 1) 431#define SYNC_GRADIENT (1 << 24) 432#define SYNC_WALKER (1 << 25) 433#define SYNC_ALIGNER (1 << 26) 434#define BILINEAR_PRECISION_6_BIT (0 << 31) 435#define BILINEAR_PRECISION_8_BIT (1 << 31) 436 437#define TC_CNTL 0x9608 438#define TC_L2_SIZE(x) ((x)<<5) 439#define L2_DISABLE_LATE_HIT (1<<9) 440 441 442#define VGT_CACHE_INVALIDATION 0x88C4 443#define CACHE_INVALIDATION(x) ((x)<<0) 444#define VC_ONLY 0 445#define TC_ONLY 1 446#define VC_AND_TC 2 447#define VGT_DMA_BASE 0x287E8 448#define VGT_DMA_BASE_HI 0x287E4 449#define VGT_ES_PER_GS 0x88CC 450#define VGT_GS_PER_ES 0x88C8 451#define VGT_GS_PER_VS 0x88E8 452#define VGT_GS_VERTEX_REUSE 0x88D4 453#define VGT_PRIMITIVE_TYPE 0x8958 454#define VGT_NUM_INSTANCES 0x8974 455#define VGT_OUT_DEALLOC_CNTL 0x28C5C 456#define DEALLOC_DIST_MASK 0x0000007F 457#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 458#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 459#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 460#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 461#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 462#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 463#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 464#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 465#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 466#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 467#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 468#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 469#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 470#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 471#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 472#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 473#define VGT_STRMOUT_EN 0x28AB0 474#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 475#define VTX_REUSE_DEPTH_MASK 0x000000FF 476#define VGT_EVENT_INITIATOR 0x28a90 477# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 478 479#define VM_CONTEXT0_CNTL 0x1410 480#define ENABLE_CONTEXT (1 << 0) 481#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 482#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 483#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 484#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 485#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 486#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 487#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 488#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 489#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 490#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 491#define RESPONSE_TYPE_MASK 0x000000F0 492#define RESPONSE_TYPE_SHIFT 4 493#define VM_L2_CNTL 0x1400 494#define ENABLE_L2_CACHE (1 << 0) 495#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 496#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 497#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 498#define VM_L2_CNTL2 0x1404 499#define INVALIDATE_ALL_L1_TLBS (1 << 0) 500#define INVALIDATE_L2_CACHE (1 << 1) 501#define VM_L2_CNTL3 0x1408 502#define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 503#define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 504#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 505#define VM_L2_STATUS 0x140C 506#define L2_BUSY (1 << 0) 507 508#define WAIT_UNTIL 0x8040 509#define WAIT_2D_IDLE_bit (1 << 14) 510#define WAIT_3D_IDLE_bit (1 << 15) 511#define WAIT_2D_IDLECLEAN_bit (1 << 16) 512#define WAIT_3D_IDLECLEAN_bit (1 << 17) 513 514#define IH_RB_CNTL 0x3e00 515# define IH_RB_ENABLE (1 << 0) 516# define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 517# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 518# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 519# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 520# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 521# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 522#define IH_RB_BASE 0x3e04 523#define IH_RB_RPTR 0x3e08 524#define IH_RB_WPTR 0x3e0c 525# define RB_OVERFLOW (1 << 0) 526# define WPTR_OFFSET_MASK 0x3fffc 527#define IH_RB_WPTR_ADDR_HI 0x3e10 528#define IH_RB_WPTR_ADDR_LO 0x3e14 529#define IH_CNTL 0x3e18 530# define ENABLE_INTR (1 << 0) 531# define IH_MC_SWAP(x) ((x) << 2) 532# define IH_MC_SWAP_NONE 0 533# define IH_MC_SWAP_16BIT 1 534# define IH_MC_SWAP_32BIT 2 535# define IH_MC_SWAP_64BIT 3 536# define RPTR_REARM (1 << 4) 537# define MC_WRREQ_CREDIT(x) ((x) << 15) 538# define MC_WR_CLEAN_CNT(x) ((x) << 20) 539 540#define RLC_CNTL 0x3f00 541# define RLC_ENABLE (1 << 0) 542#define RLC_HB_BASE 0x3f10 543#define RLC_HB_CNTL 0x3f0c 544#define RLC_HB_RPTR 0x3f20 545#define RLC_HB_WPTR 0x3f1c 546#define RLC_HB_WPTR_LSB_ADDR 0x3f14 547#define RLC_HB_WPTR_MSB_ADDR 0x3f18 548#define RLC_MC_CNTL 0x3f44 549#define RLC_UCODE_CNTL 0x3f48 550#define RLC_UCODE_ADDR 0x3f2c 551#define RLC_UCODE_DATA 0x3f30 552 553#define SRBM_SOFT_RESET 0xe60 554# define SOFT_RESET_RLC (1 << 13) 555 556#define CP_INT_CNTL 0xc124 557# define CNTX_BUSY_INT_ENABLE (1 << 19) 558# define CNTX_EMPTY_INT_ENABLE (1 << 20) 559# define SCRATCH_INT_ENABLE (1 << 25) 560# define TIME_STAMP_INT_ENABLE (1 << 26) 561# define IB2_INT_ENABLE (1 << 29) 562# define IB1_INT_ENABLE (1 << 30) 563# define RB_INT_ENABLE (1 << 31) 564#define CP_INT_STATUS 0xc128 565# define SCRATCH_INT_STAT (1 << 25) 566# define TIME_STAMP_INT_STAT (1 << 26) 567# define IB2_INT_STAT (1 << 29) 568# define IB1_INT_STAT (1 << 30) 569# define RB_INT_STAT (1 << 31) 570 571#define GRBM_INT_CNTL 0x8060 572# define RDERR_INT_ENABLE (1 << 0) 573# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 574# define GUI_IDLE_INT_ENABLE (1 << 19) 575 576#define INTERRUPT_CNTL 0x5468 577# define IH_DUMMY_RD_OVERRIDE (1 << 0) 578# define IH_DUMMY_RD_EN (1 << 1) 579# define IH_REQ_NONSNOOP_EN (1 << 3) 580# define GEN_IH_INT_EN (1 << 8) 581#define INTERRUPT_CNTL2 0x546c 582 583#define D1MODE_VBLANK_STATUS 0x6534 584#define D2MODE_VBLANK_STATUS 0x6d34 585# define DxMODE_VBLANK_OCCURRED (1 << 0) 586# define DxMODE_VBLANK_ACK (1 << 4) 587# define DxMODE_VBLANK_STAT (1 << 12) 588# define DxMODE_VBLANK_INTERRUPT (1 << 16) 589# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 590#define D1MODE_VLINE_STATUS 0x653c 591#define D2MODE_VLINE_STATUS 0x6d3c 592# define DxMODE_VLINE_OCCURRED (1 << 0) 593# define DxMODE_VLINE_ACK (1 << 4) 594# define DxMODE_VLINE_STAT (1 << 12) 595# define DxMODE_VLINE_INTERRUPT (1 << 16) 596# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 597#define DxMODE_INT_MASK 0x6540 598# define D1MODE_VBLANK_INT_MASK (1 << 0) 599# define D1MODE_VLINE_INT_MASK (1 << 4) 600# define D2MODE_VBLANK_INT_MASK (1 << 8) 601# define D2MODE_VLINE_INT_MASK (1 << 12) 602#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 603# define DC_HPD1_INTERRUPT (1 << 18) 604# define DC_HPD2_INTERRUPT (1 << 19) 605#define DISP_INTERRUPT_STATUS 0x7edc 606# define LB_D1_VLINE_INTERRUPT (1 << 2) 607# define LB_D2_VLINE_INTERRUPT (1 << 3) 608# define LB_D1_VBLANK_INTERRUPT (1 << 4) 609# define LB_D2_VBLANK_INTERRUPT (1 << 5) 610# define DACA_AUTODETECT_INTERRUPT (1 << 16) 611# define DACB_AUTODETECT_INTERRUPT (1 << 17) 612# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 613# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 614# define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 615# define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 616#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 617#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 618# define DC_HPD4_INTERRUPT (1 << 14) 619# define DC_HPD4_RX_INTERRUPT (1 << 15) 620# define DC_HPD3_INTERRUPT (1 << 28) 621# define DC_HPD1_RX_INTERRUPT (1 << 29) 622# define DC_HPD2_RX_INTERRUPT (1 << 30) 623#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 624# define DC_HPD3_RX_INTERRUPT (1 << 0) 625# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 626# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 627# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 628# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 629# define AUX1_SW_DONE_INTERRUPT (1 << 5) 630# define AUX1_LS_DONE_INTERRUPT (1 << 6) 631# define AUX2_SW_DONE_INTERRUPT (1 << 7) 632# define AUX2_LS_DONE_INTERRUPT (1 << 8) 633# define AUX3_SW_DONE_INTERRUPT (1 << 9) 634# define AUX3_LS_DONE_INTERRUPT (1 << 10) 635# define AUX4_SW_DONE_INTERRUPT (1 << 11) 636# define AUX4_LS_DONE_INTERRUPT (1 << 12) 637# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 638# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 639/* DCE 3.2 */ 640# define AUX5_SW_DONE_INTERRUPT (1 << 15) 641# define AUX5_LS_DONE_INTERRUPT (1 << 16) 642# define AUX6_SW_DONE_INTERRUPT (1 << 17) 643# define AUX6_LS_DONE_INTERRUPT (1 << 18) 644# define DC_HPD5_INTERRUPT (1 << 19) 645# define DC_HPD5_RX_INTERRUPT (1 << 20) 646# define DC_HPD6_INTERRUPT (1 << 21) 647# define DC_HPD6_RX_INTERRUPT (1 << 22) 648 649#define DACA_AUTO_DETECT_CONTROL 0x7828 650#define DACB_AUTO_DETECT_CONTROL 0x7a28 651#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 652#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 653# define DACx_AUTODETECT_MODE(x) ((x) << 0) 654# define DACx_AUTODETECT_MODE_NONE 0 655# define DACx_AUTODETECT_MODE_CONNECT 1 656# define DACx_AUTODETECT_MODE_DISCONNECT 2 657# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 658/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 659# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 660 661#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 662#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 663#define DACA_AUTODETECT_INT_CONTROL 0x7838 664#define DACB_AUTODETECT_INT_CONTROL 0x7a38 665# define DACx_AUTODETECT_ACK (1 << 0) 666# define DACx_AUTODETECT_INT_ENABLE (1 << 16) 667 668#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 669#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 670#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 671# define DC_HOT_PLUG_DETECTx_EN (1 << 0) 672 673#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 674#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 675#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 676# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 677# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 678 679/* DCE 3.0 */ 680#define DC_HPD1_INT_STATUS 0x7d00 681#define DC_HPD2_INT_STATUS 0x7d0c 682#define DC_HPD3_INT_STATUS 0x7d18 683#define DC_HPD4_INT_STATUS 0x7d24 684/* DCE 3.2 */ 685#define DC_HPD5_INT_STATUS 0x7dc0 686#define DC_HPD6_INT_STATUS 0x7df4 687# define DC_HPDx_INT_STATUS (1 << 0) 688# define DC_HPDx_SENSE (1 << 1) 689# define DC_HPDx_RX_INT_STATUS (1 << 8) 690 691#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 692#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 693#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 694# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 695# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 696# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 697/* DCE 3.0 */ 698#define DC_HPD1_INT_CONTROL 0x7d04 699#define DC_HPD2_INT_CONTROL 0x7d10 700#define DC_HPD3_INT_CONTROL 0x7d1c 701#define DC_HPD4_INT_CONTROL 0x7d28 702/* DCE 3.2 */ 703#define DC_HPD5_INT_CONTROL 0x7dc4 704#define DC_HPD6_INT_CONTROL 0x7df8 705# define DC_HPDx_INT_ACK (1 << 0) 706# define DC_HPDx_INT_POLARITY (1 << 8) 707# define DC_HPDx_INT_EN (1 << 16) 708# define DC_HPDx_RX_INT_ACK (1 << 20) 709# define DC_HPDx_RX_INT_EN (1 << 24) 710 711/* DCE 3.0 */ 712#define DC_HPD1_CONTROL 0x7d08 713#define DC_HPD2_CONTROL 0x7d14 714#define DC_HPD3_CONTROL 0x7d20 715#define DC_HPD4_CONTROL 0x7d2c 716/* DCE 3.2 */ 717#define DC_HPD5_CONTROL 0x7dc8 718#define DC_HPD6_CONTROL 0x7dfc 719# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 720# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 721/* DCE 3.2 */ 722# define DC_HPDx_EN (1 << 28) 723 724/* 725 * PM4 726 */ 727#define PACKET_TYPE0 0 728#define PACKET_TYPE1 1 729#define PACKET_TYPE2 2 730#define PACKET_TYPE3 3 731 732#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 733#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 734#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 735#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 736#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 737 (((reg) >> 2) & 0xFFFF) | \ 738 ((n) & 0x3FFF) << 16) 739#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 740 (((op) & 0xFF) << 8) | \ 741 ((n) & 0x3FFF) << 16) 742 743/* Packet 3 types */ 744#define PACKET3_NOP 0x10 745#define PACKET3_INDIRECT_BUFFER_END 0x17 746#define PACKET3_SET_PREDICATION 0x20 747#define PACKET3_REG_RMW 0x21 748#define PACKET3_COND_EXEC 0x22 749#define PACKET3_PRED_EXEC 0x23 750#define PACKET3_START_3D_CMDBUF 0x24 751#define PACKET3_DRAW_INDEX_2 0x27 752#define PACKET3_CONTEXT_CONTROL 0x28 753#define PACKET3_DRAW_INDEX_IMMD_BE 0x29 754#define PACKET3_INDEX_TYPE 0x2A 755#define PACKET3_DRAW_INDEX 0x2B 756#define PACKET3_DRAW_INDEX_AUTO 0x2D 757#define PACKET3_DRAW_INDEX_IMMD 0x2E 758#define PACKET3_NUM_INSTANCES 0x2F 759#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 760#define PACKET3_INDIRECT_BUFFER_MP 0x38 761#define PACKET3_MEM_SEMAPHORE 0x39 762#define PACKET3_MPEG_INDEX 0x3A 763#define PACKET3_WAIT_REG_MEM 0x3C 764#define PACKET3_MEM_WRITE 0x3D 765#define PACKET3_INDIRECT_BUFFER 0x32 766#define PACKET3_SURFACE_SYNC 0x43 767# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 768# define PACKET3_TC_ACTION_ENA (1 << 23) 769# define PACKET3_VC_ACTION_ENA (1 << 24) 770# define PACKET3_CB_ACTION_ENA (1 << 25) 771# define PACKET3_DB_ACTION_ENA (1 << 26) 772# define PACKET3_SH_ACTION_ENA (1 << 27) 773# define PACKET3_SMX_ACTION_ENA (1 << 28) 774#define PACKET3_ME_INITIALIZE 0x44 775#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 776#define PACKET3_COND_WRITE 0x45 777#define PACKET3_EVENT_WRITE 0x46 778#define PACKET3_EVENT_WRITE_EOP 0x47 779#define PACKET3_ONE_REG_WRITE 0x57 780#define PACKET3_SET_CONFIG_REG 0x68 781#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 782#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 783#define PACKET3_SET_CONTEXT_REG 0x69 784#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 785#define PACKET3_SET_CONTEXT_REG_END 0x00029000 786#define PACKET3_SET_ALU_CONST 0x6A 787#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 788#define PACKET3_SET_ALU_CONST_END 0x00032000 789#define PACKET3_SET_BOOL_CONST 0x6B 790#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 791#define PACKET3_SET_BOOL_CONST_END 0x00040000 792#define PACKET3_SET_LOOP_CONST 0x6C 793#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 794#define PACKET3_SET_LOOP_CONST_END 0x0003e380 795#define PACKET3_SET_RESOURCE 0x6D 796#define PACKET3_SET_RESOURCE_OFFSET 0x00038000 797#define PACKET3_SET_RESOURCE_END 0x0003c000 798#define PACKET3_SET_SAMPLER 0x6E 799#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 800#define PACKET3_SET_SAMPLER_END 0x0003cff0 801#define PACKET3_SET_CTL_CONST 0x6F 802#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 803#define PACKET3_SET_CTL_CONST_END 0x0003e200 804#define PACKET3_SURFACE_BASE_UPDATE 0x73 805 806 807#define R_008020_GRBM_SOFT_RESET 0x8020 808#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 809#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 810#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 811#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 812#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 813#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 814#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 815#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 816#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 817#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 818#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 819#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 820#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 821#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 822#define R_008010_GRBM_STATUS 0x8010 823#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 824#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 825#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 826#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 827#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 828#define S_008010_VC_BUSY(x) (((x) & 1) << 11) 829#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 830#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 831#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 832#define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 833#define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 834#define S_008010_TC_BUSY(x) (((x) & 1) << 19) 835#define S_008010_SX_BUSY(x) (((x) & 1) << 20) 836#define S_008010_SH_BUSY(x) (((x) & 1) << 21) 837#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 838#define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 839#define S_008010_SC_BUSY(x) (((x) & 1) << 24) 840#define S_008010_PA_BUSY(x) (((x) & 1) << 25) 841#define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 842#define S_008010_CR_BUSY(x) (((x) & 1) << 27) 843#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 844#define S_008010_CP_BUSY(x) (((x) & 1) << 29) 845#define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 846#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 847#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 848#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 849#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 850#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 851#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 852#define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 853#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 854#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 855#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 856#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 857#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 858#define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 859#define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 860#define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 861#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 862#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 863#define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 864#define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 865#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 866#define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 867#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 868#define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 869#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 870#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 871#define R_008014_GRBM_STATUS2 0x8014 872#define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 873#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 874#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 875#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 876#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 877#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 878#define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 879#define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 880#define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 881#define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 882#define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 883#define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 884#define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 885#define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 886#define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 887#define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 888#define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 889#define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 890#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 891#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 892#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 893#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 894#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 895#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 896#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 897#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 898#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 899#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 900#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 901#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 902#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 903#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 904#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 905#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 906#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 907#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 908#define R_000E50_SRBM_STATUS 0x0E50 909#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 910#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 911#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 912#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 913#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 914#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 915#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 916#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 917#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 918#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 919#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 920#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 921#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 922#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 923#define R_000E60_SRBM_SOFT_RESET 0x0E60 924#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 925#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 926#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 927#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 928#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 929#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 930#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 931#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 932#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 933#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 934#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 935#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 936#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 937#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 938 939#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 940 941#define R_028C04_PA_SC_AA_CONFIG 0x028C04 942#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 943#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 944#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 945#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 946#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 947#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 948#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 949#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 950#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 951#define R_0280E0_CB_COLOR0_FRAG 0x0280E0 952#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 953#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 954#define C_0280E0_BASE_256B 0x00000000 955#define R_0280E4_CB_COLOR1_FRAG 0x0280E4 956#define R_0280E8_CB_COLOR2_FRAG 0x0280E8 957#define R_0280EC_CB_COLOR3_FRAG 0x0280EC 958#define R_0280F0_CB_COLOR4_FRAG 0x0280F0 959#define R_0280F4_CB_COLOR5_FRAG 0x0280F4 960#define R_0280F8_CB_COLOR6_FRAG 0x0280F8 961#define R_0280FC_CB_COLOR7_FRAG 0x0280FC 962#define R_0280C0_CB_COLOR0_TILE 0x0280C0 963#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 964#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 965#define C_0280C0_BASE_256B 0x00000000 966#define R_0280C4_CB_COLOR1_TILE 0x0280C4 967#define R_0280C8_CB_COLOR2_TILE 0x0280C8 968#define R_0280CC_CB_COLOR3_TILE 0x0280CC 969#define R_0280D0_CB_COLOR4_TILE 0x0280D0 970#define R_0280D4_CB_COLOR5_TILE 0x0280D4 971#define R_0280D8_CB_COLOR6_TILE 0x0280D8 972#define R_0280DC_CB_COLOR7_TILE 0x0280DC 973#define R_0280A0_CB_COLOR0_INFO 0x0280A0 974#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 975#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 976#define C_0280A0_ENDIAN 0xFFFFFFFC 977#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 978#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 979#define C_0280A0_FORMAT 0xFFFFFF03 980#define V_0280A0_COLOR_INVALID 0x00000000 981#define V_0280A0_COLOR_8 0x00000001 982#define V_0280A0_COLOR_4_4 0x00000002 983#define V_0280A0_COLOR_3_3_2 0x00000003 984#define V_0280A0_COLOR_16 0x00000005 985#define V_0280A0_COLOR_16_FLOAT 0x00000006 986#define V_0280A0_COLOR_8_8 0x00000007 987#define V_0280A0_COLOR_5_6_5 0x00000008 988#define V_0280A0_COLOR_6_5_5 0x00000009 989#define V_0280A0_COLOR_1_5_5_5 0x0000000A 990#define V_0280A0_COLOR_4_4_4_4 0x0000000B 991#define V_0280A0_COLOR_5_5_5_1 0x0000000C 992#define V_0280A0_COLOR_32 0x0000000D 993#define V_0280A0_COLOR_32_FLOAT 0x0000000E 994#define V_0280A0_COLOR_16_16 0x0000000F 995#define V_0280A0_COLOR_16_16_FLOAT 0x00000010 996#define V_0280A0_COLOR_8_24 0x00000011 997#define V_0280A0_COLOR_8_24_FLOAT 0x00000012 998#define V_0280A0_COLOR_24_8 0x00000013 999#define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1000#define V_0280A0_COLOR_10_11_11 0x00000015 1001#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1002#define V_0280A0_COLOR_11_11_10 0x00000017 1003#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1004#define V_0280A0_COLOR_2_10_10_10 0x00000019 1005#define V_0280A0_COLOR_8_8_8_8 0x0000001A 1006#define V_0280A0_COLOR_10_10_10_2 0x0000001B 1007#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1008#define V_0280A0_COLOR_32_32 0x0000001D 1009#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1010#define V_0280A0_COLOR_16_16_16_16 0x0000001F 1011#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1012#define V_0280A0_COLOR_32_32_32_32 0x00000022 1013#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1014#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1015#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1016#define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1017#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1018#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1019#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1020#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1021#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1022#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1023#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1024#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1025#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1026#define C_0280A0_READ_SIZE 0xFFFF7FFF 1027#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1028#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1029#define C_0280A0_COMP_SWAP 0xFFFCFFFF 1030#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1031#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1032#define C_0280A0_TILE_MODE 0xFFF3FFFF 1033#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1034#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1035#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1036#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1037#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1038#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1039#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1040#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1041#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1042#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1043#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1044#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1045#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1046#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1047#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1048#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1049#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1050#define C_0280A0_ROUND_MODE 0xFDFFFFFF 1051#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1052#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1053#define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1054#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1055#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1056#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1057#define R_0280A4_CB_COLOR1_INFO 0x0280A4 1058#define R_0280A8_CB_COLOR2_INFO 0x0280A8 1059#define R_0280AC_CB_COLOR3_INFO 0x0280AC 1060#define R_0280B0_CB_COLOR4_INFO 0x0280B0 1061#define R_0280B4_CB_COLOR5_INFO 0x0280B4 1062#define R_0280B8_CB_COLOR6_INFO 0x0280B8 1063#define R_0280BC_CB_COLOR7_INFO 0x0280BC 1064#define R_028060_CB_COLOR0_SIZE 0x028060 1065#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1066#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1067#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1068#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1069#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1070#define C_028060_SLICE_TILE_MAX 0xC00003FF 1071#define R_028064_CB_COLOR1_SIZE 0x028064 1072#define R_028068_CB_COLOR2_SIZE 0x028068 1073#define R_02806C_CB_COLOR3_SIZE 0x02806C 1074#define R_028070_CB_COLOR4_SIZE 0x028070 1075#define R_028074_CB_COLOR5_SIZE 0x028074 1076#define R_028078_CB_COLOR6_SIZE 0x028078 1077#define R_02807C_CB_COLOR7_SIZE 0x02807C 1078#define R_028238_CB_TARGET_MASK 0x028238 1079#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1080#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1081#define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1082#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1083#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1084#define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1085#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1086#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1087#define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1088#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1089#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1090#define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1091#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1092#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1093#define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1094#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1095#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1096#define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1097#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1098#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1099#define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1100#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1101#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1102#define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1103#define R_02823C_CB_SHADER_MASK 0x02823C 1104#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1105#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1106#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1107#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1108#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1109#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1110#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1111#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1112#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1113#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1114#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1115#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1116#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1117#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1118#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1119#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1120#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1121#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1122#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1123#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1124#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1125#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1126#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1127#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1128#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1129#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1130#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1131#define C_028AB0_STREAMOUT 0xFFFFFFFE 1132#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1133#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1134#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1135#define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1136#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1137#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1138#define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1139#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1140#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1141#define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1142#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1143#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1144#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1145#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1146#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1147#define C_028B20_SIZE 0x00000000 1148#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 1149#define S_038000_DIM(x) (((x) & 0x7) << 0) 1150#define G_038000_DIM(x) (((x) >> 0) & 0x7) 1151#define C_038000_DIM 0xFFFFFFF8 1152#define V_038000_SQ_TEX_DIM_1D 0x00000000 1153#define V_038000_SQ_TEX_DIM_2D 0x00000001 1154#define V_038000_SQ_TEX_DIM_3D 0x00000002 1155#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 1156#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1157#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1158#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 1159#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1160#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1161#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1162#define C_038000_TILE_MODE 0xFFFFFF87 1163#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 1164#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 1165#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 1166#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 1167#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1168#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1169#define C_038000_TILE_TYPE 0xFFFFFF7F 1170#define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 1171#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 1172#define C_038000_PITCH 0xFFF800FF 1173#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 1174#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 1175#define C_038000_TEX_WIDTH 0x0007FFFF 1176#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 1177#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 1178#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 1179#define C_038004_TEX_HEIGHT 0xFFFFE000 1180#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 1181#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 1182#define C_038004_TEX_DEPTH 0xFC001FFF 1183#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 1184#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 1185#define C_038004_DATA_FORMAT 0x03FFFFFF 1186#define V_038004_COLOR_INVALID 0x00000000 1187#define V_038004_COLOR_8 0x00000001 1188#define V_038004_COLOR_4_4 0x00000002 1189#define V_038004_COLOR_3_3_2 0x00000003 1190#define V_038004_COLOR_16 0x00000005 1191#define V_038004_COLOR_16_FLOAT 0x00000006 1192#define V_038004_COLOR_8_8 0x00000007 1193#define V_038004_COLOR_5_6_5 0x00000008 1194#define V_038004_COLOR_6_5_5 0x00000009 1195#define V_038004_COLOR_1_5_5_5 0x0000000A 1196#define V_038004_COLOR_4_4_4_4 0x0000000B 1197#define V_038004_COLOR_5_5_5_1 0x0000000C 1198#define V_038004_COLOR_32 0x0000000D 1199#define V_038004_COLOR_32_FLOAT 0x0000000E 1200#define V_038004_COLOR_16_16 0x0000000F 1201#define V_038004_COLOR_16_16_FLOAT 0x00000010 1202#define V_038004_COLOR_8_24 0x00000011 1203#define V_038004_COLOR_8_24_FLOAT 0x00000012 1204#define V_038004_COLOR_24_8 0x00000013 1205#define V_038004_COLOR_24_8_FLOAT 0x00000014 1206#define V_038004_COLOR_10_11_11 0x00000015 1207#define V_038004_COLOR_10_11_11_FLOAT 0x00000016 1208#define V_038004_COLOR_11_11_10 0x00000017 1209#define V_038004_COLOR_11_11_10_FLOAT 0x00000018 1210#define V_038004_COLOR_2_10_10_10 0x00000019 1211#define V_038004_COLOR_8_8_8_8 0x0000001A 1212#define V_038004_COLOR_10_10_10_2 0x0000001B 1213#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 1214#define V_038004_COLOR_32_32 0x0000001D 1215#define V_038004_COLOR_32_32_FLOAT 0x0000001E 1216#define V_038004_COLOR_16_16_16_16 0x0000001F 1217#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 1218#define V_038004_COLOR_32_32_32_32 0x00000022 1219#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 1220#define V_038004_FMT_1 0x00000025 1221#define V_038004_FMT_GB_GR 0x00000027 1222#define V_038004_FMT_BG_RG 0x00000028 1223#define V_038004_FMT_32_AS_8 0x00000029 1224#define V_038004_FMT_32_AS_8_8 0x0000002A 1225#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 1226#define V_038004_FMT_8_8_8 0x0000002C 1227#define V_038004_FMT_16_16_16 0x0000002D 1228#define V_038004_FMT_16_16_16_FLOAT 0x0000002E 1229#define V_038004_FMT_32_32_32 0x0000002F 1230#define V_038004_FMT_32_32_32_FLOAT 0x00000030 1231#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 1232#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1233#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1234#define C_038010_FORMAT_COMP_X 0xFFFFFFFC 1235#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1236#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1237#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 1238#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1239#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1240#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 1241#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1242#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1243#define C_038010_FORMAT_COMP_W 0xFFFFFF3F 1244#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1245#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1246#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 1247#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1248#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1249#define C_038010_SRF_MODE_ALL 0xFFFFFBFF 1250#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1251#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1252#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 1253#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1254#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1255#define C_038010_ENDIAN_SWAP 0xFFFFCFFF 1256#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 1257#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 1258#define C_038010_REQUEST_SIZE 0xFFFF3FFF 1259#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 1260#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1261#define C_038010_DST_SEL_X 0xFFF8FFFF 1262#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1263#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1264#define C_038010_DST_SEL_Y 0xFFC7FFFF 1265#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1266#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1267#define C_038010_DST_SEL_Z 0xFE3FFFFF 1268#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 1269#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1270#define C_038010_DST_SEL_W 0xF1FFFFFF 1271#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1272#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1273#define C_038010_BASE_LEVEL 0x0FFFFFFF 1274#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 1275#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1276#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1277#define C_038014_LAST_LEVEL 0xFFFFFFF0 1278#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1279#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1280#define C_038014_BASE_ARRAY 0xFFFE000F 1281#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1282#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1283#define C_038014_LAST_ARRAY 0xC001FFFF 1284#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 1285#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1286#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1287#define C_0288A8_ITEMSIZE 0xFFFF8000 1288#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 1289#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1290#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1291#define C_008C44_MEM_SIZE 0x00000000 1292#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 1293#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1294#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1295#define C_0288B0_ITEMSIZE 0xFFFF8000 1296#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 1297#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1298#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1299#define C_008C54_MEM_SIZE 0x00000000 1300#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 1301#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1302#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1303#define C_0288C0_ITEMSIZE 0xFFFF8000 1304#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 1305#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1306#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1307#define C_008C74_MEM_SIZE 0x00000000 1308#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 1309#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1310#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1311#define C_0288B4_ITEMSIZE 0xFFFF8000 1312#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 1313#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1314#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1315#define C_008C5C_MEM_SIZE 0x00000000 1316#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 1317#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1318#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1319#define C_0288AC_ITEMSIZE 0xFFFF8000 1320#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 1321#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1322#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1323#define C_008C4C_MEM_SIZE 0x00000000 1324#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 1325#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1326#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1327#define C_0288BC_ITEMSIZE 0xFFFF8000 1328#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 1329#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1330#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1331#define C_008C6C_MEM_SIZE 0x00000000 1332#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 1333#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1334#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1335#define C_0288C4_ITEMSIZE 0xFFFF8000 1336#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 1337#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1338#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1339#define C_008C7C_MEM_SIZE 0x00000000 1340#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 1341#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1342#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1343#define C_0288B8_ITEMSIZE 0xFFFF8000 1344#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 1345#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1346#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1347#define C_008C64_MEM_SIZE 0x00000000 1348#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 1349#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1350#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1351#define C_0288C8_ITEMSIZE 0xFFFF8000 1352#define R_028010_DB_DEPTH_INFO 0x028010 1353#define S_028010_FORMAT(x) (((x) & 0x7) << 0) 1354#define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 1355#define C_028010_FORMAT 0xFFFFFFF8 1356#define V_028010_DEPTH_INVALID 0x00000000 1357#define V_028010_DEPTH_16 0x00000001 1358#define V_028010_DEPTH_X8_24 0x00000002 1359#define V_028010_DEPTH_8_24 0x00000003 1360#define V_028010_DEPTH_X8_24_FLOAT 0x00000004 1361#define V_028010_DEPTH_8_24_FLOAT 0x00000005 1362#define V_028010_DEPTH_32_FLOAT 0x00000006 1363#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 1364#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 1365#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 1366#define C_028010_READ_SIZE 0xFFFFFFF7 1367#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 1368#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 1369#define C_028010_ARRAY_MODE 0xFFF87FFF 1370#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 1371#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 1372#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 1373#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 1374#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 1375#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 1376#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1377#define C_028010_TILE_COMPACT 0xFBFFFFFF 1378#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1379#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1380#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 1381#define R_028000_DB_DEPTH_SIZE 0x028000 1382#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1383#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1384#define C_028000_PITCH_TILE_MAX 0xFFFFFC00 1385#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1386#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1387#define C_028000_SLICE_TILE_MAX 0xC00003FF 1388#define R_028004_DB_DEPTH_VIEW 0x028004 1389#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 1390#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 1391#define C_028004_SLICE_START 0xFFFFF800 1392#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1393#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1394#define C_028004_SLICE_MAX 0xFF001FFF 1395#define R_028800_DB_DEPTH_CONTROL 0x028800 1396#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1397#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1398#define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1399#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1400#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1401#define C_028800_Z_ENABLE 0xFFFFFFFD 1402#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1403#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1404#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1405#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1406#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1407#define C_028800_ZFUNC 0xFFFFFF8F 1408#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1409#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1410#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1411#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1412#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1413#define C_028800_STENCILFUNC 0xFFFFF8FF 1414#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1415#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1416#define C_028800_STENCILFAIL 0xFFFFC7FF 1417#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1418#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1419#define C_028800_STENCILZPASS 0xFFFE3FFF 1420#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1421#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1422#define C_028800_STENCILZFAIL 0xFFF1FFFF 1423#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1424#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1425#define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1426#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1427#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1428#define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1429#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1430#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1431#define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1432#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1433#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1434#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1435 1436#endif 1437