1/* 2 * Copyright 2008-2009 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Dave Airlie <airlied@redhat.com> 26 * Alex Deucher <alexander.deucher@amd.com> 27 */ 28 29#include "drmP.h" 30#include "drm.h" 31#include "radeon_drm.h" 32#include "radeon_drv.h" 33 34#define PFP_UCODE_SIZE 576 35#define PM4_UCODE_SIZE 1792 36#define R700_PFP_UCODE_SIZE 848 37#define R700_PM4_UCODE_SIZE 1360 38 39/* Firmware Names */ 40MODULE_FIRMWARE("radeon/R600_pfp.bin"); 41MODULE_FIRMWARE("radeon/R600_me.bin"); 42MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 43MODULE_FIRMWARE("radeon/RV610_me.bin"); 44MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 45MODULE_FIRMWARE("radeon/RV630_me.bin"); 46MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 47MODULE_FIRMWARE("radeon/RV620_me.bin"); 48MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 49MODULE_FIRMWARE("radeon/RV635_me.bin"); 50MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 51MODULE_FIRMWARE("radeon/RV670_me.bin"); 52MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 53MODULE_FIRMWARE("radeon/RS780_me.bin"); 54MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 55MODULE_FIRMWARE("radeon/RV770_me.bin"); 56MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 57MODULE_FIRMWARE("radeon/RV730_me.bin"); 58MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 59MODULE_FIRMWARE("radeon/RV710_me.bin"); 60 61 62int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, 63 unsigned family, u32 *ib, int *l); 64void r600_cs_legacy_init(void); 65 66 67# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 68# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 69 70#define R600_PTE_VALID (1 << 0) 71#define R600_PTE_SYSTEM (1 << 1) 72#define R600_PTE_SNOOPED (1 << 2) 73#define R600_PTE_READABLE (1 << 5) 74#define R600_PTE_WRITEABLE (1 << 6) 75 76/* MAX values used for gfx init */ 77#define R6XX_MAX_SH_GPRS 256 78#define R6XX_MAX_TEMP_GPRS 16 79#define R6XX_MAX_SH_THREADS 256 80#define R6XX_MAX_SH_STACK_ENTRIES 4096 81#define R6XX_MAX_BACKENDS 8 82#define R6XX_MAX_BACKENDS_MASK 0xff 83#define R6XX_MAX_SIMDS 8 84#define R6XX_MAX_SIMDS_MASK 0xff 85#define R6XX_MAX_PIPES 8 86#define R6XX_MAX_PIPES_MASK 0xff 87 88#define R7XX_MAX_SH_GPRS 256 89#define R7XX_MAX_TEMP_GPRS 16 90#define R7XX_MAX_SH_THREADS 256 91#define R7XX_MAX_SH_STACK_ENTRIES 4096 92#define R7XX_MAX_BACKENDS 8 93#define R7XX_MAX_BACKENDS_MASK 0xff 94#define R7XX_MAX_SIMDS 16 95#define R7XX_MAX_SIMDS_MASK 0xffff 96#define R7XX_MAX_PIPES 8 97#define R7XX_MAX_PIPES_MASK 0xff 98 99static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 100{ 101 int i; 102 103 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 104 105 for (i = 0; i < dev_priv->usec_timeout; i++) { 106 int slots; 107 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 108 slots = (RADEON_READ(R600_GRBM_STATUS) 109 & R700_CMDFIFO_AVAIL_MASK); 110 else 111 slots = (RADEON_READ(R600_GRBM_STATUS) 112 & R600_CMDFIFO_AVAIL_MASK); 113 if (slots >= entries) 114 return 0; 115 DRM_UDELAY(1); 116 } 117 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 118 RADEON_READ(R600_GRBM_STATUS), 119 RADEON_READ(R600_GRBM_STATUS2)); 120 121 return -EBUSY; 122} 123 124static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 125{ 126 int i, ret; 127 128 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 129 130 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 131 ret = r600_do_wait_for_fifo(dev_priv, 8); 132 else 133 ret = r600_do_wait_for_fifo(dev_priv, 16); 134 if (ret) 135 return ret; 136 for (i = 0; i < dev_priv->usec_timeout; i++) { 137 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 138 return 0; 139 DRM_UDELAY(1); 140 } 141 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 142 RADEON_READ(R600_GRBM_STATUS), 143 RADEON_READ(R600_GRBM_STATUS2)); 144 145 return -EBUSY; 146} 147 148void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 149{ 150 struct drm_sg_mem *entry = dev->sg; 151 int max_pages; 152 int pages; 153 int i; 154 155 if (!entry) 156 return; 157 158 if (gart_info->bus_addr) { 159 max_pages = (gart_info->table_size / sizeof(u64)); 160 pages = (entry->pages <= max_pages) 161 ? entry->pages : max_pages; 162 163 for (i = 0; i < pages; i++) { 164 if (!entry->busaddr[i]) 165 break; 166 pci_unmap_page(dev->pdev, entry->busaddr[i], 167 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 168 } 169 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 170 gart_info->bus_addr = 0; 171 } 172} 173 174/* R600 has page table setup */ 175int r600_page_table_init(struct drm_device *dev) 176{ 177 drm_radeon_private_t *dev_priv = dev->dev_private; 178 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 179 struct drm_local_map *map = &gart_info->mapping; 180 struct drm_sg_mem *entry = dev->sg; 181 int ret = 0; 182 int i, j; 183 int pages; 184 u64 page_base; 185 dma_addr_t entry_addr; 186 int max_ati_pages, max_real_pages, gart_idx; 187 188 /* okay page table is available - lets rock */ 189 max_ati_pages = (gart_info->table_size / sizeof(u64)); 190 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); 191 192 pages = (entry->pages <= max_real_pages) ? 193 entry->pages : max_real_pages; 194 195 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); 196 197 gart_idx = 0; 198 for (i = 0; i < pages; i++) { 199 entry->busaddr[i] = pci_map_page(dev->pdev, 200 entry->pagelist[i], 0, 201 PAGE_SIZE, 202 PCI_DMA_BIDIRECTIONAL); 203 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) { 204 DRM_ERROR("unable to map PCIGART pages!\n"); 205 r600_page_table_cleanup(dev, gart_info); 206 goto done; 207 } 208 entry_addr = entry->busaddr[i]; 209 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 210 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 211 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 212 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 213 214 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); 215 216 gart_idx++; 217 218 if ((i % 128) == 0) 219 DRM_DEBUG("page entry %d: 0x%016llx\n", 220 i, (unsigned long long)page_base); 221 entry_addr += ATI_PCIGART_PAGE_SIZE; 222 } 223 } 224 ret = 1; 225done: 226 return ret; 227} 228 229static void r600_vm_flush_gart_range(struct drm_device *dev) 230{ 231 drm_radeon_private_t *dev_priv = dev->dev_private; 232 u32 resp, countdown = 1000; 233 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 234 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 235 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 236 237 do { 238 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 239 countdown--; 240 DRM_UDELAY(1); 241 } while (((resp & 0xf0) == 0) && countdown); 242} 243 244static void r600_vm_init(struct drm_device *dev) 245{ 246 drm_radeon_private_t *dev_priv = dev->dev_private; 247 /* initialise the VM to use the page table we constructed up there */ 248 u32 vm_c0, i; 249 u32 mc_rd_a; 250 u32 vm_l2_cntl, vm_l2_cntl3; 251 /* okay set up the PCIE aperture type thingo */ 252 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 253 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 254 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 255 256 /* setup MC RD a */ 257 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 258 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 259 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 260 261 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 262 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 263 264 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 265 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 266 267 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 268 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 269 270 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 271 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 272 273 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 274 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 275 276 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 277 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 278 279 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 280 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 281 282 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 283 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 284 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 285 286 RADEON_WRITE(R600_VM_L2_CNTL2, 0); 287 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 288 R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 289 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 290 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 291 292 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 293 294 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 295 296 vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 297 298 /* disable all other contexts */ 299 for (i = 1; i < 8; i++) 300 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 301 302 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 303 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 304 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 305 306 r600_vm_flush_gart_range(dev); 307} 308 309static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) 310{ 311 struct platform_device *pdev; 312 const char *chip_name; 313 size_t pfp_req_size, me_req_size; 314 char fw_name[30]; 315 int err; 316 317 pdev = platform_device_register_simple("r600_cp", 0, NULL, 0); 318 err = IS_ERR(pdev); 319 if (err) { 320 printk(KERN_ERR "r600_cp: Failed to register firmware\n"); 321 return -EINVAL; 322 } 323 324 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 325 case CHIP_R600: chip_name = "R600"; break; 326 case CHIP_RV610: chip_name = "RV610"; break; 327 case CHIP_RV630: chip_name = "RV630"; break; 328 case CHIP_RV620: chip_name = "RV620"; break; 329 case CHIP_RV635: chip_name = "RV635"; break; 330 case CHIP_RV670: chip_name = "RV670"; break; 331 case CHIP_RS780: 332 case CHIP_RS880: chip_name = "RS780"; break; 333 case CHIP_RV770: chip_name = "RV770"; break; 334 case CHIP_RV730: 335 case CHIP_RV740: chip_name = "RV730"; break; 336 case CHIP_RV710: chip_name = "RV710"; break; 337 default: BUG(); 338 } 339 340 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 341 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 342 me_req_size = R700_PM4_UCODE_SIZE * 4; 343 } else { 344 pfp_req_size = PFP_UCODE_SIZE * 4; 345 me_req_size = PM4_UCODE_SIZE * 12; 346 } 347 348 DRM_INFO("Loading %s CP Microcode\n", chip_name); 349 350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 351 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); 352 if (err) 353 goto out; 354 if (dev_priv->pfp_fw->size != pfp_req_size) { 355 printk(KERN_ERR 356 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 357 dev_priv->pfp_fw->size, fw_name); 358 err = -EINVAL; 359 goto out; 360 } 361 362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 363 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); 364 if (err) 365 goto out; 366 if (dev_priv->me_fw->size != me_req_size) { 367 printk(KERN_ERR 368 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 369 dev_priv->me_fw->size, fw_name); 370 err = -EINVAL; 371 } 372out: 373 platform_device_unregister(pdev); 374 375 if (err) { 376 if (err != -EINVAL) 377 printk(KERN_ERR 378 "r600_cp: Failed to load firmware \"%s\"\n", 379 fw_name); 380 release_firmware(dev_priv->pfp_fw); 381 dev_priv->pfp_fw = NULL; 382 release_firmware(dev_priv->me_fw); 383 dev_priv->me_fw = NULL; 384 } 385 return err; 386} 387 388static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 389{ 390 const __be32 *fw_data; 391 int i; 392 393 if (!dev_priv->me_fw || !dev_priv->pfp_fw) 394 return; 395 396 r600_do_cp_stop(dev_priv); 397 398 RADEON_WRITE(R600_CP_RB_CNTL, 399 R600_RB_NO_UPDATE | 400 R600_RB_BLKSZ(15) | 401 R600_RB_BUFSZ(3)); 402 403 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 404 RADEON_READ(R600_GRBM_SOFT_RESET); 405 DRM_UDELAY(15000); 406 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 407 408 fw_data = (const __be32 *)dev_priv->me_fw->data; 409 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 410 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 411 RADEON_WRITE(R600_CP_ME_RAM_DATA, 412 be32_to_cpup(fw_data++)); 413 414 fw_data = (const __be32 *)dev_priv->pfp_fw->data; 415 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 416 for (i = 0; i < PFP_UCODE_SIZE; i++) 417 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, 418 be32_to_cpup(fw_data++)); 419 420 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 421 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 422 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 423 424} 425 426static void r700_vm_init(struct drm_device *dev) 427{ 428 drm_radeon_private_t *dev_priv = dev->dev_private; 429 /* initialise the VM to use the page table we constructed up there */ 430 u32 vm_c0, i; 431 u32 mc_vm_md_l1; 432 u32 vm_l2_cntl, vm_l2_cntl3; 433 /* okay set up the PCIE aperture type thingo */ 434 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 435 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 436 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 437 438 mc_vm_md_l1 = R700_ENABLE_L1_TLB | 439 R700_ENABLE_L1_FRAGMENT_PROCESSING | 440 R700_SYSTEM_ACCESS_MODE_IN_SYS | 441 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 442 R700_EFFECTIVE_L1_TLB_SIZE(5) | 443 R700_EFFECTIVE_L1_QUEUE_SIZE(5); 444 445 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 446 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 447 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 448 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 449 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 450 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 451 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 452 453 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 454 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 455 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 456 457 RADEON_WRITE(R600_VM_L2_CNTL2, 0); 458 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 459 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 460 461 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 462 463 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 464 465 vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 466 467 /* disable all other contexts */ 468 for (i = 1; i < 8; i++) 469 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 470 471 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 472 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 473 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 474 475 r600_vm_flush_gart_range(dev); 476} 477 478static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 479{ 480 const __be32 *fw_data; 481 int i; 482 483 if (!dev_priv->me_fw || !dev_priv->pfp_fw) 484 return; 485 486 r600_do_cp_stop(dev_priv); 487 488 RADEON_WRITE(R600_CP_RB_CNTL, 489 R600_RB_NO_UPDATE | 490 (15 << 8) | 491 (3 << 0)); 492 493 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 494 RADEON_READ(R600_GRBM_SOFT_RESET); 495 DRM_UDELAY(15000); 496 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 497 498 fw_data = (const __be32 *)dev_priv->pfp_fw->data; 499 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 500 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 501 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 502 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 503 504 fw_data = (const __be32 *)dev_priv->me_fw->data; 505 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 506 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 507 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 508 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 509 510 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 511 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 512 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 513 514} 515 516static void r600_test_writeback(drm_radeon_private_t *dev_priv) 517{ 518 u32 tmp; 519 520 /* Start with assuming that writeback doesn't work */ 521 dev_priv->writeback_works = 0; 522 523 /* Writeback doesn't seem to work everywhere, test it here and possibly 524 * enable it if it appears to work 525 */ 526 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 527 528 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 529 530 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 531 u32 val; 532 533 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 534 if (val == 0xdeadbeef) 535 break; 536 DRM_UDELAY(1); 537 } 538 539 if (tmp < dev_priv->usec_timeout) { 540 dev_priv->writeback_works = 1; 541 DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 542 } else { 543 dev_priv->writeback_works = 0; 544 DRM_INFO("writeback test failed\n"); 545 } 546 if (radeon_no_wb == 1) { 547 dev_priv->writeback_works = 0; 548 DRM_INFO("writeback forced off\n"); 549 } 550 551 if (!dev_priv->writeback_works) { 552 /* Disable writeback to avoid unnecessary bus master transfer */ 553 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | 554 RADEON_RB_NO_UPDATE); 555 RADEON_WRITE(R600_SCRATCH_UMSK, 0); 556 } 557} 558 559int r600_do_engine_reset(struct drm_device *dev) 560{ 561 drm_radeon_private_t *dev_priv = dev->dev_private; 562 u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 563 564 DRM_INFO("Resetting GPU\n"); 565 566 cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 567 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 568 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 569 570 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 571 RADEON_READ(R600_GRBM_SOFT_RESET); 572 DRM_UDELAY(50); 573 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 574 RADEON_READ(R600_GRBM_SOFT_RESET); 575 576 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 577 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 578 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); 579 580 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 581 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 582 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 583 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 584 585 /* Reset the CP ring */ 586 r600_do_cp_reset(dev_priv); 587 588 /* The CP is no longer running after an engine reset */ 589 dev_priv->cp_running = 0; 590 591 /* Reset any pending vertex, indirect buffers */ 592 radeon_freelist_reset(dev); 593 594 return 0; 595 596} 597 598static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 599 u32 num_backends, 600 u32 backend_disable_mask) 601{ 602 u32 backend_map = 0; 603 u32 enabled_backends_mask; 604 u32 enabled_backends_count; 605 u32 cur_pipe; 606 u32 swizzle_pipe[R6XX_MAX_PIPES]; 607 u32 cur_backend; 608 u32 i; 609 610 if (num_tile_pipes > R6XX_MAX_PIPES) 611 num_tile_pipes = R6XX_MAX_PIPES; 612 if (num_tile_pipes < 1) 613 num_tile_pipes = 1; 614 if (num_backends > R6XX_MAX_BACKENDS) 615 num_backends = R6XX_MAX_BACKENDS; 616 if (num_backends < 1) 617 num_backends = 1; 618 619 enabled_backends_mask = 0; 620 enabled_backends_count = 0; 621 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 622 if (((backend_disable_mask >> i) & 1) == 0) { 623 enabled_backends_mask |= (1 << i); 624 ++enabled_backends_count; 625 } 626 if (enabled_backends_count == num_backends) 627 break; 628 } 629 630 if (enabled_backends_count == 0) { 631 enabled_backends_mask = 1; 632 enabled_backends_count = 1; 633 } 634 635 if (enabled_backends_count != num_backends) 636 num_backends = enabled_backends_count; 637 638 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 639 switch (num_tile_pipes) { 640 case 1: 641 swizzle_pipe[0] = 0; 642 break; 643 case 2: 644 swizzle_pipe[0] = 0; 645 swizzle_pipe[1] = 1; 646 break; 647 case 3: 648 swizzle_pipe[0] = 0; 649 swizzle_pipe[1] = 1; 650 swizzle_pipe[2] = 2; 651 break; 652 case 4: 653 swizzle_pipe[0] = 0; 654 swizzle_pipe[1] = 1; 655 swizzle_pipe[2] = 2; 656 swizzle_pipe[3] = 3; 657 break; 658 case 5: 659 swizzle_pipe[0] = 0; 660 swizzle_pipe[1] = 1; 661 swizzle_pipe[2] = 2; 662 swizzle_pipe[3] = 3; 663 swizzle_pipe[4] = 4; 664 break; 665 case 6: 666 swizzle_pipe[0] = 0; 667 swizzle_pipe[1] = 2; 668 swizzle_pipe[2] = 4; 669 swizzle_pipe[3] = 5; 670 swizzle_pipe[4] = 1; 671 swizzle_pipe[5] = 3; 672 break; 673 case 7: 674 swizzle_pipe[0] = 0; 675 swizzle_pipe[1] = 2; 676 swizzle_pipe[2] = 4; 677 swizzle_pipe[3] = 6; 678 swizzle_pipe[4] = 1; 679 swizzle_pipe[5] = 3; 680 swizzle_pipe[6] = 5; 681 break; 682 case 8: 683 swizzle_pipe[0] = 0; 684 swizzle_pipe[1] = 2; 685 swizzle_pipe[2] = 4; 686 swizzle_pipe[3] = 6; 687 swizzle_pipe[4] = 1; 688 swizzle_pipe[5] = 3; 689 swizzle_pipe[6] = 5; 690 swizzle_pipe[7] = 7; 691 break; 692 } 693 694 cur_backend = 0; 695 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 696 while (((1 << cur_backend) & enabled_backends_mask) == 0) 697 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 698 699 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 700 701 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 702 } 703 704 return backend_map; 705} 706 707static int r600_count_pipe_bits(uint32_t val) 708{ 709 int i, ret = 0; 710 for (i = 0; i < 32; i++) { 711 ret += val & 1; 712 val >>= 1; 713 } 714 return ret; 715} 716 717static void r600_gfx_init(struct drm_device *dev, 718 drm_radeon_private_t *dev_priv) 719{ 720 int i, j, num_qd_pipes; 721 u32 sx_debug_1; 722 u32 tc_cntl; 723 u32 arb_pop; 724 u32 num_gs_verts_per_thread; 725 u32 vgt_gs_per_es; 726 u32 gs_prim_buffer_depth = 0; 727 u32 sq_ms_fifo_sizes; 728 u32 sq_config; 729 u32 sq_gpr_resource_mgmt_1 = 0; 730 u32 sq_gpr_resource_mgmt_2 = 0; 731 u32 sq_thread_resource_mgmt = 0; 732 u32 sq_stack_resource_mgmt_1 = 0; 733 u32 sq_stack_resource_mgmt_2 = 0; 734 u32 hdp_host_path_cntl; 735 u32 backend_map; 736 u32 gb_tiling_config = 0; 737 u32 cc_rb_backend_disable; 738 u32 cc_gc_shader_pipe_config; 739 u32 ramcfg; 740 741 /* setup chip specs */ 742 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 743 case CHIP_R600: 744 dev_priv->r600_max_pipes = 4; 745 dev_priv->r600_max_tile_pipes = 8; 746 dev_priv->r600_max_simds = 4; 747 dev_priv->r600_max_backends = 4; 748 dev_priv->r600_max_gprs = 256; 749 dev_priv->r600_max_threads = 192; 750 dev_priv->r600_max_stack_entries = 256; 751 dev_priv->r600_max_hw_contexts = 8; 752 dev_priv->r600_max_gs_threads = 16; 753 dev_priv->r600_sx_max_export_size = 128; 754 dev_priv->r600_sx_max_export_pos_size = 16; 755 dev_priv->r600_sx_max_export_smx_size = 128; 756 dev_priv->r600_sq_num_cf_insts = 2; 757 break; 758 case CHIP_RV630: 759 case CHIP_RV635: 760 dev_priv->r600_max_pipes = 2; 761 dev_priv->r600_max_tile_pipes = 2; 762 dev_priv->r600_max_simds = 3; 763 dev_priv->r600_max_backends = 1; 764 dev_priv->r600_max_gprs = 128; 765 dev_priv->r600_max_threads = 192; 766 dev_priv->r600_max_stack_entries = 128; 767 dev_priv->r600_max_hw_contexts = 8; 768 dev_priv->r600_max_gs_threads = 4; 769 dev_priv->r600_sx_max_export_size = 128; 770 dev_priv->r600_sx_max_export_pos_size = 16; 771 dev_priv->r600_sx_max_export_smx_size = 128; 772 dev_priv->r600_sq_num_cf_insts = 2; 773 break; 774 case CHIP_RV610: 775 case CHIP_RS780: 776 case CHIP_RS880: 777 case CHIP_RV620: 778 dev_priv->r600_max_pipes = 1; 779 dev_priv->r600_max_tile_pipes = 1; 780 dev_priv->r600_max_simds = 2; 781 dev_priv->r600_max_backends = 1; 782 dev_priv->r600_max_gprs = 128; 783 dev_priv->r600_max_threads = 192; 784 dev_priv->r600_max_stack_entries = 128; 785 dev_priv->r600_max_hw_contexts = 4; 786 dev_priv->r600_max_gs_threads = 4; 787 dev_priv->r600_sx_max_export_size = 128; 788 dev_priv->r600_sx_max_export_pos_size = 16; 789 dev_priv->r600_sx_max_export_smx_size = 128; 790 dev_priv->r600_sq_num_cf_insts = 1; 791 break; 792 case CHIP_RV670: 793 dev_priv->r600_max_pipes = 4; 794 dev_priv->r600_max_tile_pipes = 4; 795 dev_priv->r600_max_simds = 4; 796 dev_priv->r600_max_backends = 4; 797 dev_priv->r600_max_gprs = 192; 798 dev_priv->r600_max_threads = 192; 799 dev_priv->r600_max_stack_entries = 256; 800 dev_priv->r600_max_hw_contexts = 8; 801 dev_priv->r600_max_gs_threads = 16; 802 dev_priv->r600_sx_max_export_size = 128; 803 dev_priv->r600_sx_max_export_pos_size = 16; 804 dev_priv->r600_sx_max_export_smx_size = 128; 805 dev_priv->r600_sq_num_cf_insts = 2; 806 break; 807 default: 808 break; 809 } 810 811 /* Initialize HDP */ 812 j = 0; 813 for (i = 0; i < 32; i++) { 814 RADEON_WRITE((0x2c14 + j), 0x00000000); 815 RADEON_WRITE((0x2c18 + j), 0x00000000); 816 RADEON_WRITE((0x2c1c + j), 0x00000000); 817 RADEON_WRITE((0x2c20 + j), 0x00000000); 818 RADEON_WRITE((0x2c24 + j), 0x00000000); 819 j += 0x18; 820 } 821 822 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 823 824 /* setup tiling, simd, pipe config */ 825 ramcfg = RADEON_READ(R600_RAMCFG); 826 827 switch (dev_priv->r600_max_tile_pipes) { 828 case 1: 829 gb_tiling_config |= R600_PIPE_TILING(0); 830 break; 831 case 2: 832 gb_tiling_config |= R600_PIPE_TILING(1); 833 break; 834 case 4: 835 gb_tiling_config |= R600_PIPE_TILING(2); 836 break; 837 case 8: 838 gb_tiling_config |= R600_PIPE_TILING(3); 839 break; 840 default: 841 break; 842 } 843 844 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 845 846 gb_tiling_config |= R600_GROUP_SIZE(0); 847 848 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 849 gb_tiling_config |= R600_ROW_TILING(3); 850 gb_tiling_config |= R600_SAMPLE_SPLIT(3); 851 } else { 852 gb_tiling_config |= 853 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 854 gb_tiling_config |= 855 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 856 } 857 858 gb_tiling_config |= R600_BANK_SWAPS(1); 859 860 cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 861 cc_rb_backend_disable |= 862 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 863 864 cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 865 cc_gc_shader_pipe_config |= 866 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 867 cc_gc_shader_pipe_config |= 868 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 869 870 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 871 (R6XX_MAX_BACKENDS - 872 r600_count_pipe_bits((cc_rb_backend_disable & 873 R6XX_MAX_BACKENDS_MASK) >> 16)), 874 (cc_rb_backend_disable >> 16)); 875 gb_tiling_config |= R600_BACKEND_MAP(backend_map); 876 877 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 878 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 879 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 880 if (gb_tiling_config & 0xc0) { 881 dev_priv->r600_group_size = 512; 882 } else { 883 dev_priv->r600_group_size = 256; 884 } 885 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 886 if (gb_tiling_config & 0x30) { 887 dev_priv->r600_nbanks = 8; 888 } else { 889 dev_priv->r600_nbanks = 4; 890 } 891 892 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 893 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 894 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 895 896 num_qd_pipes = 897 R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 898 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 899 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 900 901 /* set HW defaults for 3D engine */ 902 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 903 R600_ROQ_IB2_START(0x2b))); 904 905 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 906 R600_ROQ_END(0x40))); 907 908 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 909 R600_SYNC_GRADIENT | 910 R600_SYNC_WALKER | 911 R600_SYNC_ALIGNER)); 912 913 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 914 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 915 916 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 917 sx_debug_1 |= R600_SMX_EVENT_RELEASE; 918 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 919 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 920 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 921 922 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 924 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 925 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 926 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 927 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 928 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 929 else 930 RADEON_WRITE(R600_DB_DEBUG, 0); 931 932 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 933 R600_DEPTH_FLUSH(16) | 934 R600_DEPTH_PENDING_FREE(4) | 935 R600_DEPTH_CACHELINE_FREE(16))); 936 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 937 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 938 939 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 940 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 941 942 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 943 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 944 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 945 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 946 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 947 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 948 R600_FETCH_FIFO_HIWATER(0xa) | 949 R600_DONE_FIFO_HIWATER(0xe0) | 950 R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 951 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 952 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 953 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 954 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 955 } 956 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 957 958 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 959 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 960 */ 961 sq_config = RADEON_READ(R600_SQ_CONFIG); 962 sq_config &= ~(R600_PS_PRIO(3) | 963 R600_VS_PRIO(3) | 964 R600_GS_PRIO(3) | 965 R600_ES_PRIO(3)); 966 sq_config |= (R600_DX9_CONSTS | 967 R600_VC_ENABLE | 968 R600_PS_PRIO(0) | 969 R600_VS_PRIO(1) | 970 R600_GS_PRIO(2) | 971 R600_ES_PRIO(3)); 972 973 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 974 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 975 R600_NUM_VS_GPRS(124) | 976 R600_NUM_CLAUSE_TEMP_GPRS(4)); 977 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 978 R600_NUM_ES_GPRS(0)); 979 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 980 R600_NUM_VS_THREADS(48) | 981 R600_NUM_GS_THREADS(4) | 982 R600_NUM_ES_THREADS(4)); 983 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 984 R600_NUM_VS_STACK_ENTRIES(128)); 985 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 986 R600_NUM_ES_STACK_ENTRIES(0)); 987 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 988 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 989 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 990 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 991 /* no vertex cache */ 992 sq_config &= ~R600_VC_ENABLE; 993 994 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 995 R600_NUM_VS_GPRS(44) | 996 R600_NUM_CLAUSE_TEMP_GPRS(2)); 997 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 998 R600_NUM_ES_GPRS(17)); 999 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1000 R600_NUM_VS_THREADS(78) | 1001 R600_NUM_GS_THREADS(4) | 1002 R600_NUM_ES_THREADS(31)); 1003 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1004 R600_NUM_VS_STACK_ENTRIES(40)); 1005 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1006 R600_NUM_ES_STACK_ENTRIES(16)); 1007 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 1008 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 1009 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1010 R600_NUM_VS_GPRS(44) | 1011 R600_NUM_CLAUSE_TEMP_GPRS(2)); 1012 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 1013 R600_NUM_ES_GPRS(18)); 1014 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1015 R600_NUM_VS_THREADS(78) | 1016 R600_NUM_GS_THREADS(4) | 1017 R600_NUM_ES_THREADS(31)); 1018 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1019 R600_NUM_VS_STACK_ENTRIES(40)); 1020 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1021 R600_NUM_ES_STACK_ENTRIES(16)); 1022 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1023 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1024 R600_NUM_VS_GPRS(44) | 1025 R600_NUM_CLAUSE_TEMP_GPRS(2)); 1026 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1027 R600_NUM_ES_GPRS(17)); 1028 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1029 R600_NUM_VS_THREADS(78) | 1030 R600_NUM_GS_THREADS(4) | 1031 R600_NUM_ES_THREADS(31)); 1032 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1033 R600_NUM_VS_STACK_ENTRIES(64)); 1034 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1035 R600_NUM_ES_STACK_ENTRIES(64)); 1036 } 1037 1038 RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1039 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1040 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1041 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1042 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1043 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1044 1045 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1046 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1047 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 1048 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 1049 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1050 else 1051 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1052 1053 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1054 R600_S0_Y(0x4) | 1055 R600_S1_X(0x4) | 1056 R600_S1_Y(0xc))); 1057 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1058 R600_S0_Y(0xe) | 1059 R600_S1_X(0x2) | 1060 R600_S1_Y(0x2) | 1061 R600_S2_X(0xa) | 1062 R600_S2_Y(0x6) | 1063 R600_S3_X(0x6) | 1064 R600_S3_Y(0xa))); 1065 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1066 R600_S0_Y(0xb) | 1067 R600_S1_X(0x4) | 1068 R600_S1_Y(0xc) | 1069 R600_S2_X(0x1) | 1070 R600_S2_Y(0x6) | 1071 R600_S3_X(0xa) | 1072 R600_S3_Y(0xe))); 1073 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1074 R600_S4_Y(0x1) | 1075 R600_S5_X(0x0) | 1076 R600_S5_Y(0x0) | 1077 R600_S6_X(0xb) | 1078 R600_S6_Y(0x4) | 1079 R600_S7_X(0x7) | 1080 R600_S7_Y(0x8))); 1081 1082 1083 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1084 case CHIP_R600: 1085 case CHIP_RV630: 1086 case CHIP_RV635: 1087 gs_prim_buffer_depth = 0; 1088 break; 1089 case CHIP_RV610: 1090 case CHIP_RS780: 1091 case CHIP_RS880: 1092 case CHIP_RV620: 1093 gs_prim_buffer_depth = 32; 1094 break; 1095 case CHIP_RV670: 1096 gs_prim_buffer_depth = 128; 1097 break; 1098 default: 1099 break; 1100 } 1101 1102 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1103 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1104 /* Max value for this is 256 */ 1105 if (vgt_gs_per_es > 256) 1106 vgt_gs_per_es = 256; 1107 1108 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1109 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1110 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1111 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1112 1113 /* more default values. 2D/3D driver should adjust as needed */ 1114 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1115 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1116 RADEON_WRITE(R600_SX_MISC, 0); 1117 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1118 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1119 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1120 RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1121 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1122 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1123 1124 /* clear render buffer base addresses */ 1125 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1126 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1127 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1128 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1129 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1130 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1131 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1132 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1133 1134 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1135 case CHIP_RV610: 1136 case CHIP_RS780: 1137 case CHIP_RS880: 1138 case CHIP_RV620: 1139 tc_cntl = R600_TC_L2_SIZE(8); 1140 break; 1141 case CHIP_RV630: 1142 case CHIP_RV635: 1143 tc_cntl = R600_TC_L2_SIZE(4); 1144 break; 1145 case CHIP_R600: 1146 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1147 break; 1148 default: 1149 tc_cntl = R600_TC_L2_SIZE(0); 1150 break; 1151 } 1152 1153 RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1154 1155 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1156 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1157 1158 arb_pop = RADEON_READ(R600_ARB_POP); 1159 arb_pop |= R600_ENABLE_TC128; 1160 RADEON_WRITE(R600_ARB_POP, arb_pop); 1161 1162 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1163 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1164 R600_NUM_CLIP_SEQ(3))); 1165 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1166 1167} 1168 1169static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv, 1170 u32 num_tile_pipes, 1171 u32 num_backends, 1172 u32 backend_disable_mask) 1173{ 1174 u32 backend_map = 0; 1175 u32 enabled_backends_mask; 1176 u32 enabled_backends_count; 1177 u32 cur_pipe; 1178 u32 swizzle_pipe[R7XX_MAX_PIPES]; 1179 u32 cur_backend; 1180 u32 i; 1181 bool force_no_swizzle; 1182 1183 if (num_tile_pipes > R7XX_MAX_PIPES) 1184 num_tile_pipes = R7XX_MAX_PIPES; 1185 if (num_tile_pipes < 1) 1186 num_tile_pipes = 1; 1187 if (num_backends > R7XX_MAX_BACKENDS) 1188 num_backends = R7XX_MAX_BACKENDS; 1189 if (num_backends < 1) 1190 num_backends = 1; 1191 1192 enabled_backends_mask = 0; 1193 enabled_backends_count = 0; 1194 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1195 if (((backend_disable_mask >> i) & 1) == 0) { 1196 enabled_backends_mask |= (1 << i); 1197 ++enabled_backends_count; 1198 } 1199 if (enabled_backends_count == num_backends) 1200 break; 1201 } 1202 1203 if (enabled_backends_count == 0) { 1204 enabled_backends_mask = 1; 1205 enabled_backends_count = 1; 1206 } 1207 1208 if (enabled_backends_count != num_backends) 1209 num_backends = enabled_backends_count; 1210 1211 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1212 case CHIP_RV770: 1213 case CHIP_RV730: 1214 force_no_swizzle = false; 1215 break; 1216 case CHIP_RV710: 1217 case CHIP_RV740: 1218 default: 1219 force_no_swizzle = true; 1220 break; 1221 } 1222 1223 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1224 switch (num_tile_pipes) { 1225 case 1: 1226 swizzle_pipe[0] = 0; 1227 break; 1228 case 2: 1229 swizzle_pipe[0] = 0; 1230 swizzle_pipe[1] = 1; 1231 break; 1232 case 3: 1233 if (force_no_swizzle) { 1234 swizzle_pipe[0] = 0; 1235 swizzle_pipe[1] = 1; 1236 swizzle_pipe[2] = 2; 1237 } else { 1238 swizzle_pipe[0] = 0; 1239 swizzle_pipe[1] = 2; 1240 swizzle_pipe[2] = 1; 1241 } 1242 break; 1243 case 4: 1244 if (force_no_swizzle) { 1245 swizzle_pipe[0] = 0; 1246 swizzle_pipe[1] = 1; 1247 swizzle_pipe[2] = 2; 1248 swizzle_pipe[3] = 3; 1249 } else { 1250 swizzle_pipe[0] = 0; 1251 swizzle_pipe[1] = 2; 1252 swizzle_pipe[2] = 3; 1253 swizzle_pipe[3] = 1; 1254 } 1255 break; 1256 case 5: 1257 if (force_no_swizzle) { 1258 swizzle_pipe[0] = 0; 1259 swizzle_pipe[1] = 1; 1260 swizzle_pipe[2] = 2; 1261 swizzle_pipe[3] = 3; 1262 swizzle_pipe[4] = 4; 1263 } else { 1264 swizzle_pipe[0] = 0; 1265 swizzle_pipe[1] = 2; 1266 swizzle_pipe[2] = 4; 1267 swizzle_pipe[3] = 1; 1268 swizzle_pipe[4] = 3; 1269 } 1270 break; 1271 case 6: 1272 if (force_no_swizzle) { 1273 swizzle_pipe[0] = 0; 1274 swizzle_pipe[1] = 1; 1275 swizzle_pipe[2] = 2; 1276 swizzle_pipe[3] = 3; 1277 swizzle_pipe[4] = 4; 1278 swizzle_pipe[5] = 5; 1279 } else { 1280 swizzle_pipe[0] = 0; 1281 swizzle_pipe[1] = 2; 1282 swizzle_pipe[2] = 4; 1283 swizzle_pipe[3] = 5; 1284 swizzle_pipe[4] = 3; 1285 swizzle_pipe[5] = 1; 1286 } 1287 break; 1288 case 7: 1289 if (force_no_swizzle) { 1290 swizzle_pipe[0] = 0; 1291 swizzle_pipe[1] = 1; 1292 swizzle_pipe[2] = 2; 1293 swizzle_pipe[3] = 3; 1294 swizzle_pipe[4] = 4; 1295 swizzle_pipe[5] = 5; 1296 swizzle_pipe[6] = 6; 1297 } else { 1298 swizzle_pipe[0] = 0; 1299 swizzle_pipe[1] = 2; 1300 swizzle_pipe[2] = 4; 1301 swizzle_pipe[3] = 6; 1302 swizzle_pipe[4] = 3; 1303 swizzle_pipe[5] = 1; 1304 swizzle_pipe[6] = 5; 1305 } 1306 break; 1307 case 8: 1308 if (force_no_swizzle) { 1309 swizzle_pipe[0] = 0; 1310 swizzle_pipe[1] = 1; 1311 swizzle_pipe[2] = 2; 1312 swizzle_pipe[3] = 3; 1313 swizzle_pipe[4] = 4; 1314 swizzle_pipe[5] = 5; 1315 swizzle_pipe[6] = 6; 1316 swizzle_pipe[7] = 7; 1317 } else { 1318 swizzle_pipe[0] = 0; 1319 swizzle_pipe[1] = 2; 1320 swizzle_pipe[2] = 4; 1321 swizzle_pipe[3] = 6; 1322 swizzle_pipe[4] = 3; 1323 swizzle_pipe[5] = 1; 1324 swizzle_pipe[6] = 7; 1325 swizzle_pipe[7] = 5; 1326 } 1327 break; 1328 } 1329 1330 cur_backend = 0; 1331 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1332 while (((1 << cur_backend) & enabled_backends_mask) == 0) 1333 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1334 1335 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1336 1337 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1338 } 1339 1340 return backend_map; 1341} 1342 1343static void r700_gfx_init(struct drm_device *dev, 1344 drm_radeon_private_t *dev_priv) 1345{ 1346 int i, j, num_qd_pipes; 1347 u32 ta_aux_cntl; 1348 u32 sx_debug_1; 1349 u32 smx_dc_ctl0; 1350 u32 db_debug3; 1351 u32 num_gs_verts_per_thread; 1352 u32 vgt_gs_per_es; 1353 u32 gs_prim_buffer_depth = 0; 1354 u32 sq_ms_fifo_sizes; 1355 u32 sq_config; 1356 u32 sq_thread_resource_mgmt; 1357 u32 hdp_host_path_cntl; 1358 u32 sq_dyn_gpr_size_simd_ab_0; 1359 u32 backend_map; 1360 u32 gb_tiling_config = 0; 1361 u32 cc_rb_backend_disable; 1362 u32 cc_gc_shader_pipe_config; 1363 u32 mc_arb_ramcfg; 1364 u32 db_debug4; 1365 1366 /* setup chip specs */ 1367 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1368 case CHIP_RV770: 1369 dev_priv->r600_max_pipes = 4; 1370 dev_priv->r600_max_tile_pipes = 8; 1371 dev_priv->r600_max_simds = 10; 1372 dev_priv->r600_max_backends = 4; 1373 dev_priv->r600_max_gprs = 256; 1374 dev_priv->r600_max_threads = 248; 1375 dev_priv->r600_max_stack_entries = 512; 1376 dev_priv->r600_max_hw_contexts = 8; 1377 dev_priv->r600_max_gs_threads = 16 * 2; 1378 dev_priv->r600_sx_max_export_size = 128; 1379 dev_priv->r600_sx_max_export_pos_size = 16; 1380 dev_priv->r600_sx_max_export_smx_size = 112; 1381 dev_priv->r600_sq_num_cf_insts = 2; 1382 1383 dev_priv->r700_sx_num_of_sets = 7; 1384 dev_priv->r700_sc_prim_fifo_size = 0xF9; 1385 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1386 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1387 break; 1388 case CHIP_RV730: 1389 dev_priv->r600_max_pipes = 2; 1390 dev_priv->r600_max_tile_pipes = 4; 1391 dev_priv->r600_max_simds = 8; 1392 dev_priv->r600_max_backends = 2; 1393 dev_priv->r600_max_gprs = 128; 1394 dev_priv->r600_max_threads = 248; 1395 dev_priv->r600_max_stack_entries = 256; 1396 dev_priv->r600_max_hw_contexts = 8; 1397 dev_priv->r600_max_gs_threads = 16 * 2; 1398 dev_priv->r600_sx_max_export_size = 256; 1399 dev_priv->r600_sx_max_export_pos_size = 32; 1400 dev_priv->r600_sx_max_export_smx_size = 224; 1401 dev_priv->r600_sq_num_cf_insts = 2; 1402 1403 dev_priv->r700_sx_num_of_sets = 7; 1404 dev_priv->r700_sc_prim_fifo_size = 0xf9; 1405 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1406 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1407 if (dev_priv->r600_sx_max_export_pos_size > 16) { 1408 dev_priv->r600_sx_max_export_pos_size -= 16; 1409 dev_priv->r600_sx_max_export_smx_size += 16; 1410 } 1411 break; 1412 case CHIP_RV710: 1413 dev_priv->r600_max_pipes = 2; 1414 dev_priv->r600_max_tile_pipes = 2; 1415 dev_priv->r600_max_simds = 2; 1416 dev_priv->r600_max_backends = 1; 1417 dev_priv->r600_max_gprs = 256; 1418 dev_priv->r600_max_threads = 192; 1419 dev_priv->r600_max_stack_entries = 256; 1420 dev_priv->r600_max_hw_contexts = 4; 1421 dev_priv->r600_max_gs_threads = 8 * 2; 1422 dev_priv->r600_sx_max_export_size = 128; 1423 dev_priv->r600_sx_max_export_pos_size = 16; 1424 dev_priv->r600_sx_max_export_smx_size = 112; 1425 dev_priv->r600_sq_num_cf_insts = 1; 1426 1427 dev_priv->r700_sx_num_of_sets = 7; 1428 dev_priv->r700_sc_prim_fifo_size = 0x40; 1429 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1430 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1431 break; 1432 case CHIP_RV740: 1433 dev_priv->r600_max_pipes = 4; 1434 dev_priv->r600_max_tile_pipes = 4; 1435 dev_priv->r600_max_simds = 8; 1436 dev_priv->r600_max_backends = 4; 1437 dev_priv->r600_max_gprs = 256; 1438 dev_priv->r600_max_threads = 248; 1439 dev_priv->r600_max_stack_entries = 512; 1440 dev_priv->r600_max_hw_contexts = 8; 1441 dev_priv->r600_max_gs_threads = 16 * 2; 1442 dev_priv->r600_sx_max_export_size = 256; 1443 dev_priv->r600_sx_max_export_pos_size = 32; 1444 dev_priv->r600_sx_max_export_smx_size = 224; 1445 dev_priv->r600_sq_num_cf_insts = 2; 1446 1447 dev_priv->r700_sx_num_of_sets = 7; 1448 dev_priv->r700_sc_prim_fifo_size = 0x100; 1449 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1450 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1451 1452 if (dev_priv->r600_sx_max_export_pos_size > 16) { 1453 dev_priv->r600_sx_max_export_pos_size -= 16; 1454 dev_priv->r600_sx_max_export_smx_size += 16; 1455 } 1456 break; 1457 default: 1458 break; 1459 } 1460 1461 /* Initialize HDP */ 1462 j = 0; 1463 for (i = 0; i < 32; i++) { 1464 RADEON_WRITE((0x2c14 + j), 0x00000000); 1465 RADEON_WRITE((0x2c18 + j), 0x00000000); 1466 RADEON_WRITE((0x2c1c + j), 0x00000000); 1467 RADEON_WRITE((0x2c20 + j), 0x00000000); 1468 RADEON_WRITE((0x2c24 + j), 0x00000000); 1469 j += 0x18; 1470 } 1471 1472 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1473 1474 /* setup tiling, simd, pipe config */ 1475 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1476 1477 switch (dev_priv->r600_max_tile_pipes) { 1478 case 1: 1479 gb_tiling_config |= R600_PIPE_TILING(0); 1480 break; 1481 case 2: 1482 gb_tiling_config |= R600_PIPE_TILING(1); 1483 break; 1484 case 4: 1485 gb_tiling_config |= R600_PIPE_TILING(2); 1486 break; 1487 case 8: 1488 gb_tiling_config |= R600_PIPE_TILING(3); 1489 break; 1490 default: 1491 break; 1492 } 1493 1494 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1495 gb_tiling_config |= R600_BANK_TILING(1); 1496 else 1497 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1498 1499 gb_tiling_config |= R600_GROUP_SIZE(0); 1500 1501 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1502 gb_tiling_config |= R600_ROW_TILING(3); 1503 gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1504 } else { 1505 gb_tiling_config |= 1506 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1507 gb_tiling_config |= 1508 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1509 } 1510 1511 gb_tiling_config |= R600_BANK_SWAPS(1); 1512 1513 cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1514 cc_rb_backend_disable |= 1515 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1516 1517 cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1518 cc_gc_shader_pipe_config |= 1519 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1520 cc_gc_shader_pipe_config |= 1521 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1522 1523 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) 1524 backend_map = 0x28; 1525 else 1526 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv, 1527 dev_priv->r600_max_tile_pipes, 1528 (R7XX_MAX_BACKENDS - 1529 r600_count_pipe_bits((cc_rb_backend_disable & 1530 R7XX_MAX_BACKENDS_MASK) >> 16)), 1531 (cc_rb_backend_disable >> 16)); 1532 gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1533 1534 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1535 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1536 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1537 if (gb_tiling_config & 0xc0) { 1538 dev_priv->r600_group_size = 512; 1539 } else { 1540 dev_priv->r600_group_size = 256; 1541 } 1542 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 1543 if (gb_tiling_config & 0x30) { 1544 dev_priv->r600_nbanks = 8; 1545 } else { 1546 dev_priv->r600_nbanks = 4; 1547 } 1548 1549 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1550 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1551 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1552 1553 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1554 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1555 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1556 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1557 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1558 1559 num_qd_pipes = 1560 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 1561 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1562 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1563 1564 /* set HW defaults for 3D engine */ 1565 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1566 R600_ROQ_IB2_START(0x2b))); 1567 1568 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1569 1570 ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX); 1571 RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO); 1572 1573 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1574 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1575 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1576 1577 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1578 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1579 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1580 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1581 1582 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) 1583 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1584 R700_GS_FLUSH_CTL(4) | 1585 R700_ACK_FLUSH_CTL(3) | 1586 R700_SYNC_FLUSH_CTL)); 1587 1588 db_debug3 = RADEON_READ(R700_DB_DEBUG3); 1589 db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f); 1590 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1591 case CHIP_RV770: 1592 case CHIP_RV740: 1593 db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f); 1594 break; 1595 case CHIP_RV710: 1596 case CHIP_RV730: 1597 default: 1598 db_debug3 |= R700_DB_CLK_OFF_DELAY(2); 1599 break; 1600 } 1601 RADEON_WRITE(R700_DB_DEBUG3, db_debug3); 1602 1603 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { 1604 db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1605 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1606 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1607 } 1608 1609 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1610 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1611 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1612 1613 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1614 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1615 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1616 1617 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1618 1619 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1620 1621 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1622 1623 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1624 1625 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1626 1627 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1628 R600_DONE_FIFO_HIWATER(0xe0) | 1629 R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1630 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1631 case CHIP_RV770: 1632 case CHIP_RV730: 1633 case CHIP_RV710: 1634 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1635 break; 1636 case CHIP_RV740: 1637 default: 1638 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1639 break; 1640 } 1641 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1642 1643 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1644 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1645 */ 1646 sq_config = RADEON_READ(R600_SQ_CONFIG); 1647 sq_config &= ~(R600_PS_PRIO(3) | 1648 R600_VS_PRIO(3) | 1649 R600_GS_PRIO(3) | 1650 R600_ES_PRIO(3)); 1651 sq_config |= (R600_DX9_CONSTS | 1652 R600_VC_ENABLE | 1653 R600_EXPORT_SRC_C | 1654 R600_PS_PRIO(0) | 1655 R600_VS_PRIO(1) | 1656 R600_GS_PRIO(2) | 1657 R600_ES_PRIO(3)); 1658 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1659 /* no vertex cache */ 1660 sq_config &= ~R600_VC_ENABLE; 1661 1662 RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1663 1664 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1665 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1666 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1667 1668 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1669 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1670 1671 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1672 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1673 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1674 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1675 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1676 else 1677 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1678 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1679 1680 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1681 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1682 1683 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1684 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1685 1686 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1687 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1688 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1689 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1690 1691 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1692 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1693 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1694 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1695 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1696 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1697 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1698 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1699 1700 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1701 R700_FORCE_EOV_MAX_REZ_CNT(255))); 1702 1703 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1704 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1705 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1706 else 1707 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1708 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1709 1710 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1711 case CHIP_RV770: 1712 case CHIP_RV730: 1713 case CHIP_RV740: 1714 gs_prim_buffer_depth = 384; 1715 break; 1716 case CHIP_RV710: 1717 gs_prim_buffer_depth = 128; 1718 break; 1719 default: 1720 break; 1721 } 1722 1723 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1724 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1725 /* Max value for this is 256 */ 1726 if (vgt_gs_per_es > 256) 1727 vgt_gs_per_es = 256; 1728 1729 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1730 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1731 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1732 1733 /* more default values. 2D/3D driver should adjust as needed */ 1734 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1735 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1736 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1737 RADEON_WRITE(R600_SX_MISC, 0); 1738 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1739 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1740 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1741 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1742 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1743 RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1744 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1745 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1746 1747 /* clear render buffer base addresses */ 1748 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1749 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1750 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1751 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1752 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1753 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1754 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1755 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1756 1757 RADEON_WRITE(R700_TCP_CNTL, 0); 1758 1759 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1760 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1761 1762 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1763 1764 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1765 R600_NUM_CLIP_SEQ(3))); 1766 1767} 1768 1769static void r600_cp_init_ring_buffer(struct drm_device *dev, 1770 drm_radeon_private_t *dev_priv, 1771 struct drm_file *file_priv) 1772{ 1773 struct drm_radeon_master_private *master_priv; 1774 u32 ring_start; 1775 u64 rptr_addr; 1776 1777 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1778 r700_gfx_init(dev, dev_priv); 1779 else 1780 r600_gfx_init(dev, dev_priv); 1781 1782 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1783 RADEON_READ(R600_GRBM_SOFT_RESET); 1784 DRM_UDELAY(15000); 1785 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1786 1787 1788 /* Set ring buffer size */ 1789#ifdef __BIG_ENDIAN 1790 RADEON_WRITE(R600_CP_RB_CNTL, 1791 RADEON_BUF_SWAP_32BIT | 1792 RADEON_RB_NO_UPDATE | 1793 (dev_priv->ring.rptr_update_l2qw << 8) | 1794 dev_priv->ring.size_l2qw); 1795#else 1796 RADEON_WRITE(R600_CP_RB_CNTL, 1797 RADEON_RB_NO_UPDATE | 1798 (dev_priv->ring.rptr_update_l2qw << 8) | 1799 dev_priv->ring.size_l2qw); 1800#endif 1801 1802 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); 1803 1804 /* Set the write pointer delay */ 1805 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1806 1807#ifdef __BIG_ENDIAN 1808 RADEON_WRITE(R600_CP_RB_CNTL, 1809 RADEON_BUF_SWAP_32BIT | 1810 RADEON_RB_NO_UPDATE | 1811 RADEON_RB_RPTR_WR_ENA | 1812 (dev_priv->ring.rptr_update_l2qw << 8) | 1813 dev_priv->ring.size_l2qw); 1814#else 1815 RADEON_WRITE(R600_CP_RB_CNTL, 1816 RADEON_RB_NO_UPDATE | 1817 RADEON_RB_RPTR_WR_ENA | 1818 (dev_priv->ring.rptr_update_l2qw << 8) | 1819 dev_priv->ring.size_l2qw); 1820#endif 1821 1822 /* Initialize the ring buffer's read and write pointers */ 1823 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1824 RADEON_WRITE(R600_CP_RB_WPTR, 0); 1825 SET_RING_HEAD(dev_priv, 0); 1826 dev_priv->ring.tail = 0; 1827 1828#if __OS_HAS_AGP 1829 if (dev_priv->flags & RADEON_IS_AGP) { 1830 rptr_addr = dev_priv->ring_rptr->offset 1831 - dev->agp->base + 1832 dev_priv->gart_vm_start; 1833 } else 1834#endif 1835 { 1836 rptr_addr = dev_priv->ring_rptr->offset 1837 - ((unsigned long) dev->sg->virtual) 1838 + dev_priv->gart_vm_start; 1839 } 1840 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, 1841 rptr_addr & 0xffffffff); 1842 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 1843 upper_32_bits(rptr_addr)); 1844 1845#ifdef __BIG_ENDIAN 1846 RADEON_WRITE(R600_CP_RB_CNTL, 1847 RADEON_BUF_SWAP_32BIT | 1848 (dev_priv->ring.rptr_update_l2qw << 8) | 1849 dev_priv->ring.size_l2qw); 1850#else 1851 RADEON_WRITE(R600_CP_RB_CNTL, 1852 (dev_priv->ring.rptr_update_l2qw << 8) | 1853 dev_priv->ring.size_l2qw); 1854#endif 1855 1856#if __OS_HAS_AGP 1857 if (dev_priv->flags & RADEON_IS_AGP) { 1858 radeon_write_agp_base(dev_priv, dev->agp->base); 1859 1860 radeon_write_agp_location(dev_priv, 1861 (((dev_priv->gart_vm_start - 1 + 1862 dev_priv->gart_size) & 0xffff0000) | 1863 (dev_priv->gart_vm_start >> 16))); 1864 1865 ring_start = (dev_priv->cp_ring->offset 1866 - dev->agp->base 1867 + dev_priv->gart_vm_start); 1868 } else 1869#endif 1870 ring_start = (dev_priv->cp_ring->offset 1871 - (unsigned long)dev->sg->virtual 1872 + dev_priv->gart_vm_start); 1873 1874 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1875 1876 RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1877 1878 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1879 1880 /* Initialize the scratch register pointer. This will cause 1881 * the scratch register values to be written out to memory 1882 * whenever they are updated. 1883 * 1884 * We simply put this behind the ring read pointer, this works 1885 * with PCI GART as well as (whatever kind of) AGP GART 1886 */ 1887 { 1888 u64 scratch_addr; 1889 1890 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); 1891 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 1892 scratch_addr += R600_SCRATCH_REG_OFFSET; 1893 scratch_addr >>= 8; 1894 scratch_addr &= 0xffffffff; 1895 1896 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 1897 } 1898 1899 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1900 1901 /* Turn on bus mastering */ 1902 radeon_enable_bm(dev_priv); 1903 1904 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1905 RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1906 1907 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1908 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1909 1910 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1911 RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1912 1913 /* reset sarea copies of these */ 1914 master_priv = file_priv->master->driver_priv; 1915 if (master_priv->sarea_priv) { 1916 master_priv->sarea_priv->last_frame = 0; 1917 master_priv->sarea_priv->last_dispatch = 0; 1918 master_priv->sarea_priv->last_clear = 0; 1919 } 1920 1921 r600_do_wait_for_idle(dev_priv); 1922 1923} 1924 1925int r600_do_cleanup_cp(struct drm_device *dev) 1926{ 1927 drm_radeon_private_t *dev_priv = dev->dev_private; 1928 DRM_DEBUG("\n"); 1929 1930 /* Make sure interrupts are disabled here because the uninstall ioctl 1931 * may not have been called from userspace and after dev_private 1932 * is freed, it's too late. 1933 */ 1934 if (dev->irq_enabled) 1935 drm_irq_uninstall(dev); 1936 1937#if __OS_HAS_AGP 1938 if (dev_priv->flags & RADEON_IS_AGP) { 1939 if (dev_priv->cp_ring != NULL) { 1940 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1941 dev_priv->cp_ring = NULL; 1942 } 1943 if (dev_priv->ring_rptr != NULL) { 1944 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1945 dev_priv->ring_rptr = NULL; 1946 } 1947 if (dev->agp_buffer_map != NULL) { 1948 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1949 dev->agp_buffer_map = NULL; 1950 } 1951 } else 1952#endif 1953 { 1954 1955 if (dev_priv->gart_info.bus_addr) 1956 r600_page_table_cleanup(dev, &dev_priv->gart_info); 1957 1958 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1959 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1960 dev_priv->gart_info.addr = NULL; 1961 } 1962 } 1963 /* only clear to the start of flags */ 1964 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1965 1966 return 0; 1967} 1968 1969int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1970 struct drm_file *file_priv) 1971{ 1972 drm_radeon_private_t *dev_priv = dev->dev_private; 1973 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; 1974 1975 DRM_DEBUG("\n"); 1976 1977 mutex_init(&dev_priv->cs_mutex); 1978 r600_cs_legacy_init(); 1979 /* if we require new memory map but we don't have it fail */ 1980 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1981 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1982 r600_do_cleanup_cp(dev); 1983 return -EINVAL; 1984 } 1985 1986 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1987 DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1988 dev_priv->flags &= ~RADEON_IS_AGP; 1989 /* The writeback test succeeds, but when writeback is enabled, 1990 * the ring buffer read ptr update fails after first 128 bytes. 1991 */ 1992 radeon_no_wb = 1; 1993 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1994 && !init->is_pci) { 1995 DRM_DEBUG("Restoring AGP flag\n"); 1996 dev_priv->flags |= RADEON_IS_AGP; 1997 } 1998 1999 dev_priv->usec_timeout = init->usec_timeout; 2000 if (dev_priv->usec_timeout < 1 || 2001 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 2002 DRM_DEBUG("TIMEOUT problem!\n"); 2003 r600_do_cleanup_cp(dev); 2004 return -EINVAL; 2005 } 2006 2007 /* Enable vblank on CRTC1 for older X servers 2008 */ 2009 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 2010 dev_priv->do_boxes = 0; 2011 dev_priv->cp_mode = init->cp_mode; 2012 2013 /* We don't support anything other than bus-mastering ring mode, 2014 * but the ring can be in either AGP or PCI space for the ring 2015 * read pointer. 2016 */ 2017 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 2018 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 2019 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 2020 r600_do_cleanup_cp(dev); 2021 return -EINVAL; 2022 } 2023 2024 switch (init->fb_bpp) { 2025 case 16: 2026 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 2027 break; 2028 case 32: 2029 default: 2030 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 2031 break; 2032 } 2033 dev_priv->front_offset = init->front_offset; 2034 dev_priv->front_pitch = init->front_pitch; 2035 dev_priv->back_offset = init->back_offset; 2036 dev_priv->back_pitch = init->back_pitch; 2037 2038 dev_priv->ring_offset = init->ring_offset; 2039 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 2040 dev_priv->buffers_offset = init->buffers_offset; 2041 dev_priv->gart_textures_offset = init->gart_textures_offset; 2042 2043 master_priv->sarea = drm_getsarea(dev); 2044 if (!master_priv->sarea) { 2045 DRM_ERROR("could not find sarea!\n"); 2046 r600_do_cleanup_cp(dev); 2047 return -EINVAL; 2048 } 2049 2050 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 2051 if (!dev_priv->cp_ring) { 2052 DRM_ERROR("could not find cp ring region!\n"); 2053 r600_do_cleanup_cp(dev); 2054 return -EINVAL; 2055 } 2056 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 2057 if (!dev_priv->ring_rptr) { 2058 DRM_ERROR("could not find ring read pointer!\n"); 2059 r600_do_cleanup_cp(dev); 2060 return -EINVAL; 2061 } 2062 dev->agp_buffer_token = init->buffers_offset; 2063 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 2064 if (!dev->agp_buffer_map) { 2065 DRM_ERROR("could not find dma buffer region!\n"); 2066 r600_do_cleanup_cp(dev); 2067 return -EINVAL; 2068 } 2069 2070 if (init->gart_textures_offset) { 2071 dev_priv->gart_textures = 2072 drm_core_findmap(dev, init->gart_textures_offset); 2073 if (!dev_priv->gart_textures) { 2074 DRM_ERROR("could not find GART texture region!\n"); 2075 r600_do_cleanup_cp(dev); 2076 return -EINVAL; 2077 } 2078 } 2079 2080#if __OS_HAS_AGP 2081 if (dev_priv->flags & RADEON_IS_AGP) { 2082 drm_core_ioremap_wc(dev_priv->cp_ring, dev); 2083 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 2084 drm_core_ioremap_wc(dev->agp_buffer_map, dev); 2085 if (!dev_priv->cp_ring->handle || 2086 !dev_priv->ring_rptr->handle || 2087 !dev->agp_buffer_map->handle) { 2088 DRM_ERROR("could not find ioremap agp regions!\n"); 2089 r600_do_cleanup_cp(dev); 2090 return -EINVAL; 2091 } 2092 } else 2093#endif 2094 { 2095 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; 2096 dev_priv->ring_rptr->handle = 2097 (void *)(unsigned long)dev_priv->ring_rptr->offset; 2098 dev->agp_buffer_map->handle = 2099 (void *)(unsigned long)dev->agp_buffer_map->offset; 2100 2101 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 2102 dev_priv->cp_ring->handle); 2103 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 2104 dev_priv->ring_rptr->handle); 2105 DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 2106 dev->agp_buffer_map->handle); 2107 } 2108 2109 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 2110 dev_priv->fb_size = 2111 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 2112 - dev_priv->fb_location; 2113 2114 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 2115 ((dev_priv->front_offset 2116 + dev_priv->fb_location) >> 10)); 2117 2118 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 2119 ((dev_priv->back_offset 2120 + dev_priv->fb_location) >> 10)); 2121 2122 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 2123 ((dev_priv->depth_offset 2124 + dev_priv->fb_location) >> 10)); 2125 2126 dev_priv->gart_size = init->gart_size; 2127 2128 /* New let's set the memory map ... */ 2129 if (dev_priv->new_memmap) { 2130 u32 base = 0; 2131 2132 DRM_INFO("Setting GART location based on new memory map\n"); 2133 2134 /* If using AGP, try to locate the AGP aperture at the same 2135 * location in the card and on the bus, though we have to 2136 * align it down. 2137 */ 2138#if __OS_HAS_AGP 2139 if (dev_priv->flags & RADEON_IS_AGP) { 2140 base = dev->agp->base; 2141 /* Check if valid */ 2142 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 2143 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 2144 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 2145 dev->agp->base); 2146 base = 0; 2147 } 2148 } 2149#endif 2150 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2151 if (base == 0) { 2152 base = dev_priv->fb_location + dev_priv->fb_size; 2153 if (base < dev_priv->fb_location || 2154 ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2155 base = dev_priv->fb_location 2156 - dev_priv->gart_size; 2157 } 2158 dev_priv->gart_vm_start = base & 0xffc00000u; 2159 if (dev_priv->gart_vm_start != base) 2160 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2161 base, dev_priv->gart_vm_start); 2162 } 2163 2164#if __OS_HAS_AGP 2165 if (dev_priv->flags & RADEON_IS_AGP) 2166 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2167 - dev->agp->base 2168 + dev_priv->gart_vm_start); 2169 else 2170#endif 2171 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2172 - (unsigned long)dev->sg->virtual 2173 + dev_priv->gart_vm_start); 2174 2175 DRM_DEBUG("fb 0x%08x size %d\n", 2176 (unsigned int) dev_priv->fb_location, 2177 (unsigned int) dev_priv->fb_size); 2178 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2179 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2180 (unsigned int) dev_priv->gart_vm_start); 2181 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2182 dev_priv->gart_buffers_offset); 2183 2184 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2185 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2186 + init->ring_size / sizeof(u32)); 2187 dev_priv->ring.size = init->ring_size; 2188 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2189 2190 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2191 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2192 2193 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2194 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2195 2196 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2197 2198 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2199 2200#if __OS_HAS_AGP 2201 if (dev_priv->flags & RADEON_IS_AGP) { 2202 } else 2203#endif 2204 { 2205 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2206 /* if we have an offset set from userspace */ 2207 if (!dev_priv->pcigart_offset_set) { 2208 DRM_ERROR("Need gart offset from userspace\n"); 2209 r600_do_cleanup_cp(dev); 2210 return -EINVAL; 2211 } 2212 2213 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2214 2215 dev_priv->gart_info.bus_addr = 2216 dev_priv->pcigart_offset + dev_priv->fb_location; 2217 dev_priv->gart_info.mapping.offset = 2218 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2219 dev_priv->gart_info.mapping.size = 2220 dev_priv->gart_info.table_size; 2221 2222 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2223 if (!dev_priv->gart_info.mapping.handle) { 2224 DRM_ERROR("ioremap failed.\n"); 2225 r600_do_cleanup_cp(dev); 2226 return -EINVAL; 2227 } 2228 2229 dev_priv->gart_info.addr = 2230 dev_priv->gart_info.mapping.handle; 2231 2232 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2233 dev_priv->gart_info.addr, 2234 dev_priv->pcigart_offset); 2235 2236 if (!r600_page_table_init(dev)) { 2237 DRM_ERROR("Failed to init GART table\n"); 2238 r600_do_cleanup_cp(dev); 2239 return -EINVAL; 2240 } 2241 2242 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2243 r700_vm_init(dev); 2244 else 2245 r600_vm_init(dev); 2246 } 2247 2248 if (!dev_priv->me_fw || !dev_priv->pfp_fw) { 2249 int err = r600_cp_init_microcode(dev_priv); 2250 if (err) { 2251 DRM_ERROR("Failed to load firmware!\n"); 2252 r600_do_cleanup_cp(dev); 2253 return err; 2254 } 2255 } 2256 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2257 r700_cp_load_microcode(dev_priv); 2258 else 2259 r600_cp_load_microcode(dev_priv); 2260 2261 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2262 2263 dev_priv->last_buf = 0; 2264 2265 r600_do_engine_reset(dev); 2266 r600_test_writeback(dev_priv); 2267 2268 return 0; 2269} 2270 2271int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2272{ 2273 drm_radeon_private_t *dev_priv = dev->dev_private; 2274 2275 DRM_DEBUG("\n"); 2276 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2277 r700_vm_init(dev); 2278 r700_cp_load_microcode(dev_priv); 2279 } else { 2280 r600_vm_init(dev); 2281 r600_cp_load_microcode(dev_priv); 2282 } 2283 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2284 r600_do_engine_reset(dev); 2285 2286 return 0; 2287} 2288 2289/* Wait for the CP to go idle. 2290 */ 2291int r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2292{ 2293 RING_LOCALS; 2294 DRM_DEBUG("\n"); 2295 2296 BEGIN_RING(5); 2297 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2298 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2299 /* wait for 3D idle clean */ 2300 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2301 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2302 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2303 2304 ADVANCE_RING(); 2305 COMMIT_RING(); 2306 2307 return r600_do_wait_for_idle(dev_priv); 2308} 2309 2310/* Start the Command Processor. 2311 */ 2312void r600_do_cp_start(drm_radeon_private_t *dev_priv) 2313{ 2314 u32 cp_me; 2315 RING_LOCALS; 2316 DRM_DEBUG("\n"); 2317 2318 BEGIN_RING(7); 2319 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2320 OUT_RING(0x00000001); 2321 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2322 OUT_RING(0x00000003); 2323 else 2324 OUT_RING(0x00000000); 2325 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2326 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2327 OUT_RING(0x00000000); 2328 OUT_RING(0x00000000); 2329 ADVANCE_RING(); 2330 COMMIT_RING(); 2331 2332 /* set the mux and reset the halt bit */ 2333 cp_me = 0xff; 2334 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2335 2336 dev_priv->cp_running = 1; 2337 2338} 2339 2340void r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2341{ 2342 u32 cur_read_ptr; 2343 DRM_DEBUG("\n"); 2344 2345 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2346 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2347 SET_RING_HEAD(dev_priv, cur_read_ptr); 2348 dev_priv->ring.tail = cur_read_ptr; 2349} 2350 2351void r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2352{ 2353 uint32_t cp_me; 2354 2355 DRM_DEBUG("\n"); 2356 2357 cp_me = 0xff | R600_CP_ME_HALT; 2358 2359 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2360 2361 dev_priv->cp_running = 0; 2362} 2363 2364int r600_cp_dispatch_indirect(struct drm_device *dev, 2365 struct drm_buf *buf, int start, int end) 2366{ 2367 drm_radeon_private_t *dev_priv = dev->dev_private; 2368 RING_LOCALS; 2369 2370 if (start != end) { 2371 unsigned long offset = (dev_priv->gart_buffers_offset 2372 + buf->offset + start); 2373 int dwords = (end - start + 3) / sizeof(u32); 2374 2375 DRM_DEBUG("dwords:%d\n", dwords); 2376 DRM_DEBUG("offset 0x%lx\n", offset); 2377 2378 2379 /* Indirect buffer data must be a multiple of 16 dwords. 2380 * pad the data with a Type-2 CP packet. 2381 */ 2382 while (dwords & 0xf) { 2383 u32 *data = (u32 *) 2384 ((char *)dev->agp_buffer_map->handle 2385 + buf->offset + start); 2386 data[dwords++] = RADEON_CP_PACKET2; 2387 } 2388 2389 /* Fire off the indirect buffer */ 2390 BEGIN_RING(4); 2391 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2392 OUT_RING((offset & 0xfffffffc)); 2393 OUT_RING((upper_32_bits(offset) & 0xff)); 2394 OUT_RING(dwords); 2395 ADVANCE_RING(); 2396 } 2397 2398 return 0; 2399} 2400 2401void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) 2402{ 2403 drm_radeon_private_t *dev_priv = dev->dev_private; 2404 struct drm_master *master = file_priv->master; 2405 struct drm_radeon_master_private *master_priv = master->driver_priv; 2406 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; 2407 int nbox = sarea_priv->nbox; 2408 struct drm_clip_rect *pbox = sarea_priv->boxes; 2409 int i, cpp, src_pitch, dst_pitch; 2410 uint64_t src, dst; 2411 RING_LOCALS; 2412 DRM_DEBUG("\n"); 2413 2414 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) 2415 cpp = 4; 2416 else 2417 cpp = 2; 2418 2419 if (sarea_priv->pfCurrentPage == 0) { 2420 src_pitch = dev_priv->back_pitch; 2421 dst_pitch = dev_priv->front_pitch; 2422 src = dev_priv->back_offset + dev_priv->fb_location; 2423 dst = dev_priv->front_offset + dev_priv->fb_location; 2424 } else { 2425 src_pitch = dev_priv->front_pitch; 2426 dst_pitch = dev_priv->back_pitch; 2427 src = dev_priv->front_offset + dev_priv->fb_location; 2428 dst = dev_priv->back_offset + dev_priv->fb_location; 2429 } 2430 2431 if (r600_prepare_blit_copy(dev, file_priv)) { 2432 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 2433 return; 2434 } 2435 for (i = 0; i < nbox; i++) { 2436 int x = pbox[i].x1; 2437 int y = pbox[i].y1; 2438 int w = pbox[i].x2 - x; 2439 int h = pbox[i].y2 - y; 2440 2441 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); 2442 2443 r600_blit_swap(dev, 2444 src, dst, 2445 x, y, x, y, w, h, 2446 src_pitch, dst_pitch, cpp); 2447 } 2448 r600_done_blit_copy(dev); 2449 2450 /* Increment the frame counter. The client-side 3D driver must 2451 * throttle the framerate by waiting for this value before 2452 * performing the swapbuffer ioctl. 2453 */ 2454 sarea_priv->last_frame++; 2455 2456 BEGIN_RING(3); 2457 R600_FRAME_AGE(sarea_priv->last_frame); 2458 ADVANCE_RING(); 2459} 2460 2461int r600_cp_dispatch_texture(struct drm_device *dev, 2462 struct drm_file *file_priv, 2463 drm_radeon_texture_t *tex, 2464 drm_radeon_tex_image_t *image) 2465{ 2466 drm_radeon_private_t *dev_priv = dev->dev_private; 2467 struct drm_buf *buf; 2468 u32 *buffer; 2469 const u8 __user *data; 2470 int size, pass_size; 2471 u64 src_offset, dst_offset; 2472 2473 if (!radeon_check_offset(dev_priv, tex->offset)) { 2474 DRM_ERROR("Invalid destination offset\n"); 2475 return -EINVAL; 2476 } 2477 2478 /* this might fail for zero-sized uploads - are those illegal? */ 2479 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { 2480 DRM_ERROR("Invalid final destination offset\n"); 2481 return -EINVAL; 2482 } 2483 2484 size = tex->height * tex->pitch; 2485 2486 if (size == 0) 2487 return 0; 2488 2489 dst_offset = tex->offset; 2490 2491 if (r600_prepare_blit_copy(dev, file_priv)) { 2492 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 2493 return -EAGAIN; 2494 } 2495 do { 2496 data = (const u8 __user *)image->data; 2497 pass_size = size; 2498 2499 buf = radeon_freelist_get(dev); 2500 if (!buf) { 2501 DRM_DEBUG("EAGAIN\n"); 2502 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) 2503 return -EFAULT; 2504 return -EAGAIN; 2505 } 2506 2507 if (pass_size > buf->total) 2508 pass_size = buf->total; 2509 2510 /* Dispatch the indirect buffer. 2511 */ 2512 buffer = 2513 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); 2514 2515 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { 2516 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); 2517 return -EFAULT; 2518 } 2519 2520 buf->file_priv = file_priv; 2521 buf->used = pass_size; 2522 src_offset = dev_priv->gart_buffers_offset + buf->offset; 2523 2524 r600_blit_copy(dev, src_offset, dst_offset, pass_size); 2525 2526 radeon_cp_discard_buffer(dev, file_priv->master, buf); 2527 2528 /* Update the input parameters for next time */ 2529 image->data = (const u8 __user *)image->data + pass_size; 2530 dst_offset += pass_size; 2531 size -= pass_size; 2532 } while (size > 0); 2533 r600_done_blit_copy(dev); 2534 2535 return 0; 2536} 2537 2538/* 2539 * Legacy cs ioctl 2540 */ 2541static u32 radeon_cs_id_get(struct drm_radeon_private *radeon) 2542{ 2543 radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; 2544 if (!radeon->cs_id_scnt) { 2545 /* increment wrap counter */ 2546 radeon->cs_id_wcnt += 0x01000000; 2547 /* valid sequence counter start at 1 */ 2548 radeon->cs_id_scnt = 1; 2549 } 2550 return (radeon->cs_id_scnt | radeon->cs_id_wcnt); 2551} 2552 2553static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) 2554{ 2555 RING_LOCALS; 2556 2557 *id = radeon_cs_id_get(dev_priv); 2558 2559 /* SCRATCH 2 */ 2560 BEGIN_RING(3); 2561 R600_CLEAR_AGE(*id); 2562 ADVANCE_RING(); 2563 COMMIT_RING(); 2564} 2565 2566static int r600_ib_get(struct drm_device *dev, 2567 struct drm_file *fpriv, 2568 struct drm_buf **buffer) 2569{ 2570 struct drm_buf *buf; 2571 2572 *buffer = NULL; 2573 buf = radeon_freelist_get(dev); 2574 if (!buf) { 2575 return -EBUSY; 2576 } 2577 buf->file_priv = fpriv; 2578 *buffer = buf; 2579 return 0; 2580} 2581 2582static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, 2583 struct drm_file *fpriv, int l, int r) 2584{ 2585 drm_radeon_private_t *dev_priv = dev->dev_private; 2586 2587 if (buf) { 2588 if (!r) 2589 r600_cp_dispatch_indirect(dev, buf, 0, l * 4); 2590 radeon_cp_discard_buffer(dev, fpriv->master, buf); 2591 COMMIT_RING(); 2592 } 2593} 2594 2595int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) 2596{ 2597 struct drm_radeon_private *dev_priv = dev->dev_private; 2598 struct drm_radeon_cs *cs = data; 2599 struct drm_buf *buf; 2600 unsigned family; 2601 int l, r = 0; 2602 u32 *ib, cs_id = 0; 2603 2604 if (dev_priv == NULL) { 2605 DRM_ERROR("called with no initialization\n"); 2606 return -EINVAL; 2607 } 2608 family = dev_priv->flags & RADEON_FAMILY_MASK; 2609 if (family < CHIP_R600) { 2610 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); 2611 return -EINVAL; 2612 } 2613 mutex_lock(&dev_priv->cs_mutex); 2614 /* get ib */ 2615 r = r600_ib_get(dev, fpriv, &buf); 2616 if (r) { 2617 DRM_ERROR("ib_get failed\n"); 2618 goto out; 2619 } 2620 ib = dev->agp_buffer_map->handle + buf->offset; 2621 /* now parse command stream */ 2622 r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); 2623 if (r) { 2624 goto out; 2625 } 2626 2627out: 2628 r600_ib_free(dev, buf, fpriv, l, r); 2629 /* emit cs id sequence */ 2630 r600_cs_id_emit(dev_priv, &cs_id); 2631 cs->cs_id = cs_id; 2632 mutex_unlock(&dev_priv->cs_mutex); 2633 return r; 2634} 2635 2636void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size) 2637{ 2638 struct drm_radeon_private *dev_priv = dev->dev_private; 2639 2640 *npipes = dev_priv->r600_npipes; 2641 *nbanks = dev_priv->r600_nbanks; 2642 *group_size = dev_priv->r600_group_size; 2643} 2644