1/* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Alex Deucher <alexander.deucher@amd.com> 25 */ 26 27#include <linux/types.h> 28#include <linux/kernel.h> 29 30/* 31 * R6xx+ cards need to use the 3D engine to blit data which requires 32 * quite a bit of hw state setup. Rather than pull the whole 3D driver 33 * (which normally generates the 3D state) into the DRM, we opt to use 34 * statically generated state tables. The regsiter state and shaders 35 * were hand generated to support blitting functionality. See the 3D 36 * driver or documentation for descriptions of the registers and 37 * shader instructions. 38 */ 39 40const u32 r6xx_default_state[] = 41{ 42 0xc0002400, /* START_3D_CMDBUF */ 43 0x00000000, 44 45 0xc0012800, /* CONTEXT_CONTROL */ 46 0x80000000, 47 0x80000000, 48 49 0xc0016800, 50 0x00000010, 51 0x00008000, /* WAIT_UNTIL */ 52 53 0xc0016800, 54 0x00000542, 55 0x07000003, /* TA_CNTL_AUX */ 56 57 0xc0016800, 58 0x000005c5, 59 0x00000000, /* VC_ENHANCE */ 60 61 0xc0016800, 62 0x00000363, 63 0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */ 64 65 0xc0016800, 66 0x0000060c, 67 0x82000000, /* DB_DEBUG */ 68 69 0xc0016800, 70 0x0000060e, 71 0x01020204, /* DB_WATERMARKS */ 72 73 0xc0026f00, 74 0x00000000, 75 0x00000000, /* SQ_VTX_BASE_VTX_LOC */ 76 0x00000000, /* SQ_VTX_START_INST_LOC */ 77 78 0xc0096900, 79 0x0000022a, 80 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ 81 0x00000000, 82 0x00000000, 83 0x00000000, 84 0x00000000, 85 0x00000000, 86 0x00000000, 87 0x00000000, 88 0x00000000, 89 90 0xc0016900, 91 0x00000004, 92 0x00000000, /* DB_DEPTH_INFO */ 93 94 0xc0026900, 95 0x0000000a, 96 0x00000000, /* DB_STENCIL_CLEAR */ 97 0x00000000, /* DB_DEPTH_CLEAR */ 98 99 0xc0016900, 100 0x00000200, 101 0x00000000, /* DB_DEPTH_CONTROL */ 102 103 0xc0026900, 104 0x00000343, 105 0x00000060, /* DB_RENDER_CONTROL */ 106 0x00000040, /* DB_RENDER_OVERRIDE */ 107 108 0xc0016900, 109 0x00000351, 110 0x0000aa00, /* DB_ALPHA_TO_MASK */ 111 112 0xc00f6900, 113 0x00000100, 114 0x00000800, /* VGT_MAX_VTX_INDX */ 115 0x00000000, /* VGT_MIN_VTX_INDX */ 116 0x00000000, /* VGT_INDX_OFFSET */ 117 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 118 0x00000000, /* SX_ALPHA_TEST_CONTROL */ 119 0x00000000, /* CB_BLEND_RED */ 120 0x00000000, 121 0x00000000, 122 0x00000000, 123 0x00000000, /* CB_FOG_RED */ 124 0x00000000, 125 0x00000000, 126 0x00000000, /* DB_STENCILREFMASK */ 127 0x00000000, /* DB_STENCILREFMASK_BF */ 128 0x00000000, /* SX_ALPHA_REF */ 129 130 0xc0046900, 131 0x0000030c, 132 0x01000000, /* CB_CLRCMP_CNTL */ 133 0x00000000, 134 0x00000000, 135 0x00000000, 136 137 0xc0046900, 138 0x00000048, 139 0x3f800000, /* CB_CLEAR_RED */ 140 0x00000000, 141 0x3f800000, 142 0x3f800000, 143 144 0xc0016900, 145 0x00000080, 146 0x00000000, /* PA_SC_WINDOW_OFFSET */ 147 148 0xc00a6900, 149 0x00000083, 150 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */ 151 0x00000000, /* PA_SC_CLIPRECT_0_TL */ 152 0x20002000, 153 0x00000000, 154 0x20002000, 155 0x00000000, 156 0x20002000, 157 0x00000000, 158 0x20002000, 159 0x00000000, /* PA_SC_EDGERULE */ 160 161 0xc0406900, 162 0x00000094, 163 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ 164 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ 165 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */ 166 0x20002000, 167 0x80000000, 168 0x20002000, 169 0x80000000, 170 0x20002000, 171 0x80000000, 172 0x20002000, 173 0x80000000, 174 0x20002000, 175 0x80000000, 176 0x20002000, 177 0x80000000, 178 0x20002000, 179 0x80000000, 180 0x20002000, 181 0x80000000, 182 0x20002000, 183 0x80000000, 184 0x20002000, 185 0x80000000, 186 0x20002000, 187 0x80000000, 188 0x20002000, 189 0x80000000, 190 0x20002000, 191 0x80000000, 192 0x20002000, 193 0x80000000, 194 0x20002000, 195 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ 196 0x3f800000, 197 0x00000000, 198 0x3f800000, 199 0x00000000, 200 0x3f800000, 201 0x00000000, 202 0x3f800000, 203 0x00000000, 204 0x3f800000, 205 0x00000000, 206 0x3f800000, 207 0x00000000, 208 0x3f800000, 209 0x00000000, 210 0x3f800000, 211 0x00000000, 212 0x3f800000, 213 0x00000000, 214 0x3f800000, 215 0x00000000, 216 0x3f800000, 217 0x00000000, 218 0x3f800000, 219 0x00000000, 220 0x3f800000, 221 0x00000000, 222 0x3f800000, 223 0x00000000, 224 0x3f800000, 225 0x00000000, 226 0x3f800000, 227 228 0xc0026900, 229 0x00000292, 230 0x00000000, /* PA_SC_MPASS_PS_CNTL */ 231 0x00004010, /* PA_SC_MODE_CNTL */ 232 233 0xc0096900, 234 0x00000300, 235 0x00000000, /* PA_SC_LINE_CNTL */ 236 0x00000000, /* PA_SC_AA_CONFIG */ 237 0x0000002d, /* PA_SU_VTX_CNTL */ 238 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ 239 0x3f800000, 240 0x3f800000, 241 0x3f800000, 242 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ 243 0x00000000, 244 245 0xc0016900, 246 0x00000312, 247 0xffffffff, /* PA_SC_AA_MASK */ 248 249 0xc0066900, 250 0x0000037e, 251 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 252 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ 253 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ 254 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ 255 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ 256 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ 257 258 0xc0046900, 259 0x000001b6, 260 0x00000000, /* SPI_INPUT_Z */ 261 0x00000000, /* SPI_FOG_CNTL */ 262 0x00000000, /* SPI_FOG_FUNC_SCALE */ 263 0x00000000, /* SPI_FOG_FUNC_BIAS */ 264 265 0xc0016900, 266 0x00000225, 267 0x00000000, /* SQ_PGM_START_FS */ 268 269 0xc0016900, 270 0x00000229, 271 0x00000000, /* SQ_PGM_RESOURCES_FS */ 272 273 0xc0016900, 274 0x00000237, 275 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ 276 277 0xc0026900, 278 0x000002a8, 279 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 280 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ 281 282 0xc0116900, 283 0x00000280, 284 0x00000000, /* PA_SU_POINT_SIZE */ 285 0x00000000, /* PA_SU_POINT_MINMAX */ 286 0x00000008, /* PA_SU_LINE_CNTL */ 287 0x00000000, /* PA_SC_LINE_STIPPLE */ 288 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 289 0x00000000, /* VGT_HOS_CNTL */ 290 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */ 291 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */ 292 0x00000000, /* VGT_HOS_REUSE_DEPTH */ 293 0x00000000, /* VGT_GROUP_PRIM_TYPE */ 294 0x00000000, /* VGT_GROUP_FIRST_DECR */ 295 0x00000000, /* VGT_GROUP_DECR */ 296 0x00000000, /* VGT_GROUP_VECT_0_CNTL */ 297 0x00000000, /* VGT_GROUP_VECT_1_CNTL */ 298 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ 299 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ 300 0x00000000, /* VGT_GS_MODE */ 301 302 0xc0016900, 303 0x000002a1, 304 0x00000000, /* VGT_PRIMITIVEID_EN */ 305 306 0xc0016900, 307 0x000002a5, 308 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */ 309 310 0xc0036900, 311 0x000002ac, 312 0x00000000, /* VGT_STRMOUT_EN */ 313 0x00000000, /* VGT_REUSE_OFF */ 314 0x00000000, /* VGT_VTX_CNT_EN */ 315 316 0xc0016900, 317 0x000002c8, 318 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ 319 320 0xc0076900, 321 0x00000202, 322 0x00cc0000, /* CB_COLOR_CONTROL */ 323 0x00000210, /* DB_SHADER_CNTL */ 324 0x00010000, /* PA_CL_CLIP_CNTL */ 325 0x00000244, /* PA_SU_SC_MODE_CNTL */ 326 0x00000100, /* PA_CL_VTE_CNTL */ 327 0x00000000, /* PA_CL_VS_OUT_CNTL */ 328 0x00000000, /* PA_CL_NANINF_CNTL */ 329 330 0xc0026900, 331 0x0000008e, 332 0x0000000f, /* CB_TARGET_MASK */ 333 0x0000000f, /* CB_SHADER_MASK */ 334 335 0xc0016900, 336 0x000001e8, 337 0x00000001, /* CB_SHADER_CONTROL */ 338 339 0xc0016900, 340 0x00000185, 341 0x00000000, /* SPI_VS_OUT_ID_0 */ 342 343 0xc0016900, 344 0x00000191, 345 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ 346 347 0xc0056900, 348 0x000001b1, 349 0x00000000, /* SPI_VS_OUT_CONFIG */ 350 0x00000000, /* SPI_THREAD_GROUPING */ 351 0x00000001, /* SPI_PS_IN_CONTROL_0 */ 352 0x00000000, /* SPI_PS_IN_CONTROL_1 */ 353 0x00000000, /* SPI_INTERP_CONTROL_0 */ 354 355 0xc0036e00, /* SET_SAMPLER */ 356 0x00000000, 357 0x00000012, 358 0x00000000, 359 0x00000000, 360}; 361 362const u32 r7xx_default_state[] = 363{ 364 0xc0012800, /* CONTEXT_CONTROL */ 365 0x80000000, 366 0x80000000, 367 368 0xc0016800, 369 0x00000010, 370 0x00008000, /* WAIT_UNTIL */ 371 372 0xc0016800, 373 0x00000542, 374 0x07000002, /* TA_CNTL_AUX */ 375 376 0xc0016800, 377 0x000005c5, 378 0x00000000, /* VC_ENHANCE */ 379 380 0xc0016800, 381 0x00000363, 382 0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */ 383 384 0xc0016800, 385 0x0000060c, 386 0x00000000, /* DB_DEBUG */ 387 388 0xc0016800, 389 0x0000060e, 390 0x00420204, /* DB_WATERMARKS */ 391 392 0xc0026f00, 393 0x00000000, 394 0x00000000, /* SQ_VTX_BASE_VTX_LOC */ 395 0x00000000, /* SQ_VTX_START_INST_LOC */ 396 397 0xc0096900, 398 0x0000022a, 399 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ 400 0x00000000, 401 0x00000000, 402 0x00000000, 403 0x00000000, 404 0x00000000, 405 0x00000000, 406 0x00000000, 407 0x00000000, 408 409 0xc0016900, 410 0x00000004, 411 0x00000000, /* DB_DEPTH_INFO */ 412 413 0xc0026900, 414 0x0000000a, 415 0x00000000, /* DB_STENCIL_CLEAR */ 416 0x00000000, /* DB_DEPTH_CLEAR */ 417 418 0xc0016900, 419 0x00000200, 420 0x00000000, /* DB_DEPTH_CONTROL */ 421 422 0xc0026900, 423 0x00000343, 424 0x00000060, /* DB_RENDER_CONTROL */ 425 0x00000000, /* DB_RENDER_OVERRIDE */ 426 427 0xc0016900, 428 0x00000351, 429 0x0000aa00, /* DB_ALPHA_TO_MASK */ 430 431 0xc0096900, 432 0x00000100, 433 0x00000800, /* VGT_MAX_VTX_INDX */ 434 0x00000000, /* VGT_MIN_VTX_INDX */ 435 0x00000000, /* VGT_INDX_OFFSET */ 436 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 437 0x00000000, /* SX_ALPHA_TEST_CONTROL */ 438 0x00000000, /* CB_BLEND_RED */ 439 0x00000000, 440 0x00000000, 441 0x00000000, 442 443 0xc0036900, 444 0x0000010c, 445 0x00000000, /* DB_STENCILREFMASK */ 446 0x00000000, /* DB_STENCILREFMASK_BF */ 447 0x00000000, /* SX_ALPHA_REF */ 448 449 0xc0046900, 450 0x0000030c, /* CB_CLRCMP_CNTL */ 451 0x01000000, 452 0x00000000, 453 0x00000000, 454 0x00000000, 455 456 0xc0016900, 457 0x00000080, 458 0x00000000, /* PA_SC_WINDOW_OFFSET */ 459 460 0xc00a6900, 461 0x00000083, 462 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */ 463 0x00000000, /* PA_SC_CLIPRECT_0_TL */ 464 0x20002000, 465 0x00000000, 466 0x20002000, 467 0x00000000, 468 0x20002000, 469 0x00000000, 470 0x20002000, 471 0xaaaaaaaa, /* PA_SC_EDGERULE */ 472 473 0xc0406900, 474 0x00000094, 475 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ 476 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ 477 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */ 478 0x20002000, 479 0x80000000, 480 0x20002000, 481 0x80000000, 482 0x20002000, 483 0x80000000, 484 0x20002000, 485 0x80000000, 486 0x20002000, 487 0x80000000, 488 0x20002000, 489 0x80000000, 490 0x20002000, 491 0x80000000, 492 0x20002000, 493 0x80000000, 494 0x20002000, 495 0x80000000, 496 0x20002000, 497 0x80000000, 498 0x20002000, 499 0x80000000, 500 0x20002000, 501 0x80000000, 502 0x20002000, 503 0x80000000, 504 0x20002000, 505 0x80000000, 506 0x20002000, 507 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ 508 0x3f800000, 509 0x00000000, 510 0x3f800000, 511 0x00000000, 512 0x3f800000, 513 0x00000000, 514 0x3f800000, 515 0x00000000, 516 0x3f800000, 517 0x00000000, 518 0x3f800000, 519 0x00000000, 520 0x3f800000, 521 0x00000000, 522 0x3f800000, 523 0x00000000, 524 0x3f800000, 525 0x00000000, 526 0x3f800000, 527 0x00000000, 528 0x3f800000, 529 0x00000000, 530 0x3f800000, 531 0x00000000, 532 0x3f800000, 533 0x00000000, 534 0x3f800000, 535 0x00000000, 536 0x3f800000, 537 0x00000000, 538 0x3f800000, 539 540 0xc0026900, 541 0x00000292, 542 0x00000000, /* PA_SC_MPASS_PS_CNTL */ 543 0x00514000, /* PA_SC_MODE_CNTL */ 544 545 0xc0096900, 546 0x00000300, 547 0x00000000, /* PA_SC_LINE_CNTL */ 548 0x00000000, /* PA_SC_AA_CONFIG */ 549 0x0000002d, /* PA_SU_VTX_CNTL */ 550 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ 551 0x3f800000, 552 0x3f800000, 553 0x3f800000, 554 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ 555 0x00000000, 556 557 0xc0016900, 558 0x00000312, 559 0xffffffff, /* PA_SC_AA_MASK */ 560 561 0xc0066900, 562 0x0000037e, 563 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 564 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ 565 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ 566 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ 567 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ 568 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ 569 570 0xc0046900, 571 0x000001b6, 572 0x00000000, /* SPI_INPUT_Z */ 573 0x00000000, /* SPI_FOG_CNTL */ 574 0x00000000, /* SPI_FOG_FUNC_SCALE */ 575 0x00000000, /* SPI_FOG_FUNC_BIAS */ 576 577 0xc0016900, 578 0x00000225, 579 0x00000000, /* SQ_PGM_START_FS */ 580 581 0xc0016900, 582 0x00000229, 583 0x00000000, /* SQ_PGM_RESOURCES_FS */ 584 585 0xc0016900, 586 0x00000237, 587 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ 588 589 0xc0026900, 590 0x000002a8, 591 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 592 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ 593 594 0xc0116900, 595 0x00000280, 596 0x00000000, /* PA_SU_POINT_SIZE */ 597 0x00000000, /* PA_SU_POINT_MINMAX */ 598 0x00000008, /* PA_SU_LINE_CNTL */ 599 0x00000000, /* PA_SC_LINE_STIPPLE */ 600 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 601 0x00000000, /* VGT_HOS_CNTL */ 602 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */ 603 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */ 604 0x00000000, /* VGT_HOS_REUSE_DEPTH */ 605 0x00000000, /* VGT_GROUP_PRIM_TYPE */ 606 0x00000000, /* VGT_GROUP_FIRST_DECR */ 607 0x00000000, /* VGT_GROUP_DECR */ 608 0x00000000, /* VGT_GROUP_VECT_0_CNTL */ 609 0x00000000, /* VGT_GROUP_VECT_1_CNTL */ 610 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ 611 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ 612 0x00000000, /* VGT_GS_MODE */ 613 614 0xc0016900, 615 0x000002a1, 616 0x00000000, /* VGT_PRIMITIVEID_EN */ 617 618 0xc0016900, 619 0x000002a5, 620 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */ 621 622 0xc0036900, 623 0x000002ac, 624 0x00000000, /* VGT_STRMOUT_EN */ 625 0x00000000, /* VGT_REUSE_OFF */ 626 0x00000000, /* VGT_VTX_CNT_EN */ 627 628 0xc0016900, 629 0x000002c8, 630 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ 631 632 0xc0076900, 633 0x00000202, 634 0x00cc0000, /* CB_COLOR_CONTROL */ 635 0x00000210, /* DB_SHADER_CNTL */ 636 0x00010000, /* PA_CL_CLIP_CNTL */ 637 0x00000244, /* PA_SU_SC_MODE_CNTL */ 638 0x00000100, /* PA_CL_VTE_CNTL */ 639 0x00000000, /* PA_CL_VS_OUT_CNTL */ 640 0x00000000, /* PA_CL_NANINF_CNTL */ 641 642 0xc0026900, 643 0x0000008e, 644 0x0000000f, /* CB_TARGET_MASK */ 645 0x0000000f, /* CB_SHADER_MASK */ 646 647 0xc0016900, 648 0x000001e8, 649 0x00000001, /* CB_SHADER_CONTROL */ 650 651 0xc0016900, 652 0x00000185, 653 0x00000000, /* SPI_VS_OUT_ID_0 */ 654 655 0xc0016900, 656 0x00000191, 657 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ 658 659 0xc0056900, 660 0x000001b1, 661 0x00000000, /* SPI_VS_OUT_CONFIG */ 662 0x00000001, /* SPI_THREAD_GROUPING */ 663 0x00000001, /* SPI_PS_IN_CONTROL_0 */ 664 0x00000000, /* SPI_PS_IN_CONTROL_1 */ 665 0x00000000, /* SPI_INTERP_CONTROL_0 */ 666 667 0xc0036e00, /* SET_SAMPLER */ 668 0x00000000, 669 0x00000012, 670 0x00000000, 671 0x00000000, 672}; 673 674/* same for r6xx/r7xx */ 675const u32 r6xx_vs[] = 676{ 677 0x00000004, 678 0x81000000, 679 0x0000203c, 680 0x94000b08, 681 0x00004000, 682 0x14200b1a, 683 0x00000000, 684 0x00000000, 685 0x3c000000, 686 0x68cd1000, 687 0x00080000, 688 0x00000000, 689}; 690 691const u32 r6xx_ps[] = 692{ 693 0x00000002, 694 0x80800000, 695 0x00000000, 696 0x94200688, 697 0x00000010, 698 0x000d1000, 699 0xb0800000, 700 0x00000000, 701}; 702 703const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps); 704const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs); 705const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state); 706const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); 707