1/* r128_state.c -- State support for r128 -*- linux-c -*- 2 * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com 3 */ 4/* 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include "drmP.h" 32#include "drm.h" 33#include "r128_drm.h" 34#include "r128_drv.h" 35 36/* ================================================================ 37 * CCE hardware state programming functions 38 */ 39 40static void r128_emit_clip_rects(drm_r128_private_t *dev_priv, 41 struct drm_clip_rect *boxes, int count) 42{ 43 u32 aux_sc_cntl = 0x00000000; 44 RING_LOCALS; 45 DRM_DEBUG("\n"); 46 47 BEGIN_RING((count < 3 ? count : 3) * 5 + 2); 48 49 if (count >= 1) { 50 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); 51 OUT_RING(boxes[0].x1); 52 OUT_RING(boxes[0].x2 - 1); 53 OUT_RING(boxes[0].y1); 54 OUT_RING(boxes[0].y2 - 1); 55 56 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); 57 } 58 if (count >= 2) { 59 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); 60 OUT_RING(boxes[1].x1); 61 OUT_RING(boxes[1].x2 - 1); 62 OUT_RING(boxes[1].y1); 63 OUT_RING(boxes[1].y2 - 1); 64 65 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); 66 } 67 if (count >= 3) { 68 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3)); 69 OUT_RING(boxes[2].x1); 70 OUT_RING(boxes[2].x2 - 1); 71 OUT_RING(boxes[2].y1); 72 OUT_RING(boxes[2].y2 - 1); 73 74 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); 75 } 76 77 OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0)); 78 OUT_RING(aux_sc_cntl); 79 80 ADVANCE_RING(); 81} 82 83static __inline__ void r128_emit_core(drm_r128_private_t *dev_priv) 84{ 85 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 86 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 87 RING_LOCALS; 88 DRM_DEBUG("\n"); 89 90 BEGIN_RING(2); 91 92 OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0)); 93 OUT_RING(ctx->scale_3d_cntl); 94 95 ADVANCE_RING(); 96} 97 98static __inline__ void r128_emit_context(drm_r128_private_t *dev_priv) 99{ 100 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 101 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 102 RING_LOCALS; 103 DRM_DEBUG("\n"); 104 105 BEGIN_RING(13); 106 107 OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11)); 108 OUT_RING(ctx->dst_pitch_offset_c); 109 OUT_RING(ctx->dp_gui_master_cntl_c); 110 OUT_RING(ctx->sc_top_left_c); 111 OUT_RING(ctx->sc_bottom_right_c); 112 OUT_RING(ctx->z_offset_c); 113 OUT_RING(ctx->z_pitch_c); 114 OUT_RING(ctx->z_sten_cntl_c); 115 OUT_RING(ctx->tex_cntl_c); 116 OUT_RING(ctx->misc_3d_state_cntl_reg); 117 OUT_RING(ctx->texture_clr_cmp_clr_c); 118 OUT_RING(ctx->texture_clr_cmp_msk_c); 119 OUT_RING(ctx->fog_color_c); 120 121 ADVANCE_RING(); 122} 123 124static __inline__ void r128_emit_setup(drm_r128_private_t *dev_priv) 125{ 126 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 127 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 128 RING_LOCALS; 129 DRM_DEBUG("\n"); 130 131 BEGIN_RING(3); 132 133 OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP)); 134 OUT_RING(ctx->setup_cntl); 135 OUT_RING(ctx->pm4_vc_fpu_setup); 136 137 ADVANCE_RING(); 138} 139 140static __inline__ void r128_emit_masks(drm_r128_private_t *dev_priv) 141{ 142 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 143 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 144 RING_LOCALS; 145 DRM_DEBUG("\n"); 146 147 BEGIN_RING(5); 148 149 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); 150 OUT_RING(ctx->dp_write_mask); 151 152 OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1)); 153 OUT_RING(ctx->sten_ref_mask_c); 154 OUT_RING(ctx->plane_3d_mask_c); 155 156 ADVANCE_RING(); 157} 158 159static __inline__ void r128_emit_window(drm_r128_private_t *dev_priv) 160{ 161 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 162 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 163 RING_LOCALS; 164 DRM_DEBUG("\n"); 165 166 BEGIN_RING(2); 167 168 OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0)); 169 OUT_RING(ctx->window_xy_offset); 170 171 ADVANCE_RING(); 172} 173 174static __inline__ void r128_emit_tex0(drm_r128_private_t *dev_priv) 175{ 176 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 177 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 178 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; 179 int i; 180 RING_LOCALS; 181 DRM_DEBUG("\n"); 182 183 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS); 184 185 OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C, 186 2 + R128_MAX_TEXTURE_LEVELS)); 187 OUT_RING(tex->tex_cntl); 188 OUT_RING(tex->tex_combine_cntl); 189 OUT_RING(ctx->tex_size_pitch_c); 190 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) 191 OUT_RING(tex->tex_offset[i]); 192 193 OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1)); 194 OUT_RING(ctx->constant_color_c); 195 OUT_RING(tex->tex_border_color); 196 197 ADVANCE_RING(); 198} 199 200static __inline__ void r128_emit_tex1(drm_r128_private_t *dev_priv) 201{ 202 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 203 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; 204 int i; 205 RING_LOCALS; 206 DRM_DEBUG("\n"); 207 208 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS); 209 210 OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS)); 211 OUT_RING(tex->tex_cntl); 212 OUT_RING(tex->tex_combine_cntl); 213 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) 214 OUT_RING(tex->tex_offset[i]); 215 216 OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0)); 217 OUT_RING(tex->tex_border_color); 218 219 ADVANCE_RING(); 220} 221 222static void r128_emit_state(drm_r128_private_t *dev_priv) 223{ 224 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 225 unsigned int dirty = sarea_priv->dirty; 226 227 DRM_DEBUG("dirty=0x%08x\n", dirty); 228 229 if (dirty & R128_UPLOAD_CORE) { 230 r128_emit_core(dev_priv); 231 sarea_priv->dirty &= ~R128_UPLOAD_CORE; 232 } 233 234 if (dirty & R128_UPLOAD_CONTEXT) { 235 r128_emit_context(dev_priv); 236 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; 237 } 238 239 if (dirty & R128_UPLOAD_SETUP) { 240 r128_emit_setup(dev_priv); 241 sarea_priv->dirty &= ~R128_UPLOAD_SETUP; 242 } 243 244 if (dirty & R128_UPLOAD_MASKS) { 245 r128_emit_masks(dev_priv); 246 sarea_priv->dirty &= ~R128_UPLOAD_MASKS; 247 } 248 249 if (dirty & R128_UPLOAD_WINDOW) { 250 r128_emit_window(dev_priv); 251 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; 252 } 253 254 if (dirty & R128_UPLOAD_TEX0) { 255 r128_emit_tex0(dev_priv); 256 sarea_priv->dirty &= ~R128_UPLOAD_TEX0; 257 } 258 259 if (dirty & R128_UPLOAD_TEX1) { 260 r128_emit_tex1(dev_priv); 261 sarea_priv->dirty &= ~R128_UPLOAD_TEX1; 262 } 263 264 /* Turn off the texture cache flushing */ 265 sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; 266 267 sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; 268} 269 270#if R128_PERFORMANCE_BOXES 271/* ================================================================ 272 * Performance monitoring functions 273 */ 274 275static void r128_clear_box(drm_r128_private_t *dev_priv, 276 int x, int y, int w, int h, int r, int g, int b) 277{ 278 u32 pitch, offset; 279 u32 fb_bpp, color; 280 RING_LOCALS; 281 282 switch (dev_priv->fb_bpp) { 283 case 16: 284 fb_bpp = R128_GMC_DST_16BPP; 285 color = (((r & 0xf8) << 8) | 286 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); 287 break; 288 case 24: 289 fb_bpp = R128_GMC_DST_24BPP; 290 color = ((r << 16) | (g << 8) | b); 291 break; 292 case 32: 293 fb_bpp = R128_GMC_DST_32BPP; 294 color = (((0xff) << 24) | (r << 16) | (g << 8) | b); 295 break; 296 default: 297 return; 298 } 299 300 offset = dev_priv->back_offset; 301 pitch = dev_priv->back_pitch >> 3; 302 303 BEGIN_RING(6); 304 305 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); 306 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | 307 R128_GMC_BRUSH_SOLID_COLOR | 308 fb_bpp | 309 R128_GMC_SRC_DATATYPE_COLOR | 310 R128_ROP3_P | 311 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS); 312 313 OUT_RING((pitch << 21) | (offset >> 5)); 314 OUT_RING(color); 315 316 OUT_RING((x << 16) | y); 317 OUT_RING((w << 16) | h); 318 319 ADVANCE_RING(); 320} 321 322static void r128_cce_performance_boxes(drm_r128_private_t *dev_priv) 323{ 324 if (atomic_read(&dev_priv->idle_count) == 0) 325 r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); 326 else 327 atomic_set(&dev_priv->idle_count, 0); 328} 329 330#endif 331 332/* ================================================================ 333 * CCE command dispatch functions 334 */ 335 336static void r128_print_dirty(const char *msg, unsigned int flags) 337{ 338 DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", 339 msg, 340 flags, 341 (flags & R128_UPLOAD_CORE) ? "core, " : "", 342 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", 343 (flags & R128_UPLOAD_SETUP) ? "setup, " : "", 344 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", 345 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", 346 (flags & R128_UPLOAD_MASKS) ? "masks, " : "", 347 (flags & R128_UPLOAD_WINDOW) ? "window, " : "", 348 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", 349 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : ""); 350} 351 352static void r128_cce_dispatch_clear(struct drm_device *dev, 353 drm_r128_clear_t *clear) 354{ 355 drm_r128_private_t *dev_priv = dev->dev_private; 356 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 357 int nbox = sarea_priv->nbox; 358 struct drm_clip_rect *pbox = sarea_priv->boxes; 359 unsigned int flags = clear->flags; 360 int i; 361 RING_LOCALS; 362 DRM_DEBUG("\n"); 363 364 if (dev_priv->page_flipping && dev_priv->current_page == 1) { 365 unsigned int tmp = flags; 366 367 flags &= ~(R128_FRONT | R128_BACK); 368 if (tmp & R128_FRONT) 369 flags |= R128_BACK; 370 if (tmp & R128_BACK) 371 flags |= R128_FRONT; 372 } 373 374 for (i = 0; i < nbox; i++) { 375 int x = pbox[i].x1; 376 int y = pbox[i].y1; 377 int w = pbox[i].x2 - x; 378 int h = pbox[i].y2 - y; 379 380 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", 381 pbox[i].x1, pbox[i].y1, pbox[i].x2, 382 pbox[i].y2, flags); 383 384 if (flags & (R128_FRONT | R128_BACK)) { 385 BEGIN_RING(2); 386 387 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); 388 OUT_RING(clear->color_mask); 389 390 ADVANCE_RING(); 391 } 392 393 if (flags & R128_FRONT) { 394 BEGIN_RING(6); 395 396 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); 397 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | 398 R128_GMC_BRUSH_SOLID_COLOR | 399 (dev_priv->color_fmt << 8) | 400 R128_GMC_SRC_DATATYPE_COLOR | 401 R128_ROP3_P | 402 R128_GMC_CLR_CMP_CNTL_DIS | 403 R128_GMC_AUX_CLIP_DIS); 404 405 OUT_RING(dev_priv->front_pitch_offset_c); 406 OUT_RING(clear->clear_color); 407 408 OUT_RING((x << 16) | y); 409 OUT_RING((w << 16) | h); 410 411 ADVANCE_RING(); 412 } 413 414 if (flags & R128_BACK) { 415 BEGIN_RING(6); 416 417 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); 418 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | 419 R128_GMC_BRUSH_SOLID_COLOR | 420 (dev_priv->color_fmt << 8) | 421 R128_GMC_SRC_DATATYPE_COLOR | 422 R128_ROP3_P | 423 R128_GMC_CLR_CMP_CNTL_DIS | 424 R128_GMC_AUX_CLIP_DIS); 425 426 OUT_RING(dev_priv->back_pitch_offset_c); 427 OUT_RING(clear->clear_color); 428 429 OUT_RING((x << 16) | y); 430 OUT_RING((w << 16) | h); 431 432 ADVANCE_RING(); 433 } 434 435 if (flags & R128_DEPTH) { 436 BEGIN_RING(6); 437 438 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); 439 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | 440 R128_GMC_BRUSH_SOLID_COLOR | 441 (dev_priv->depth_fmt << 8) | 442 R128_GMC_SRC_DATATYPE_COLOR | 443 R128_ROP3_P | 444 R128_GMC_CLR_CMP_CNTL_DIS | 445 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); 446 447 OUT_RING(dev_priv->depth_pitch_offset_c); 448 OUT_RING(clear->clear_depth); 449 450 OUT_RING((x << 16) | y); 451 OUT_RING((w << 16) | h); 452 453 ADVANCE_RING(); 454 } 455 } 456} 457 458static void r128_cce_dispatch_swap(struct drm_device *dev) 459{ 460 drm_r128_private_t *dev_priv = dev->dev_private; 461 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 462 int nbox = sarea_priv->nbox; 463 struct drm_clip_rect *pbox = sarea_priv->boxes; 464 int i; 465 RING_LOCALS; 466 DRM_DEBUG("\n"); 467 468#if R128_PERFORMANCE_BOXES 469 /* Do some trivial performance monitoring... 470 */ 471 r128_cce_performance_boxes(dev_priv); 472#endif 473 474 for (i = 0; i < nbox; i++) { 475 int x = pbox[i].x1; 476 int y = pbox[i].y1; 477 int w = pbox[i].x2 - x; 478 int h = pbox[i].y2 - y; 479 480 BEGIN_RING(7); 481 482 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); 483 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | 484 R128_GMC_DST_PITCH_OFFSET_CNTL | 485 R128_GMC_BRUSH_NONE | 486 (dev_priv->color_fmt << 8) | 487 R128_GMC_SRC_DATATYPE_COLOR | 488 R128_ROP3_S | 489 R128_DP_SRC_SOURCE_MEMORY | 490 R128_GMC_CLR_CMP_CNTL_DIS | 491 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); 492 493 /* Make this work even if front & back are flipped: 494 */ 495 if (dev_priv->current_page == 0) { 496 OUT_RING(dev_priv->back_pitch_offset_c); 497 OUT_RING(dev_priv->front_pitch_offset_c); 498 } else { 499 OUT_RING(dev_priv->front_pitch_offset_c); 500 OUT_RING(dev_priv->back_pitch_offset_c); 501 } 502 503 OUT_RING((x << 16) | y); 504 OUT_RING((x << 16) | y); 505 OUT_RING((w << 16) | h); 506 507 ADVANCE_RING(); 508 } 509 510 /* Increment the frame counter. The client-side 3D driver must 511 * throttle the framerate by waiting for this value before 512 * performing the swapbuffer ioctl. 513 */ 514 dev_priv->sarea_priv->last_frame++; 515 516 BEGIN_RING(2); 517 518 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); 519 OUT_RING(dev_priv->sarea_priv->last_frame); 520 521 ADVANCE_RING(); 522} 523 524static void r128_cce_dispatch_flip(struct drm_device *dev) 525{ 526 drm_r128_private_t *dev_priv = dev->dev_private; 527 RING_LOCALS; 528 DRM_DEBUG("page=%d pfCurrentPage=%d\n", 529 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); 530 531#if R128_PERFORMANCE_BOXES 532 /* Do some trivial performance monitoring... 533 */ 534 r128_cce_performance_boxes(dev_priv); 535#endif 536 537 BEGIN_RING(4); 538 539 R128_WAIT_UNTIL_PAGE_FLIPPED(); 540 OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0)); 541 542 if (dev_priv->current_page == 0) 543 OUT_RING(dev_priv->back_offset); 544 else 545 OUT_RING(dev_priv->front_offset); 546 547 ADVANCE_RING(); 548 549 /* Increment the frame counter. The client-side 3D driver must 550 * throttle the framerate by waiting for this value before 551 * performing the swapbuffer ioctl. 552 */ 553 dev_priv->sarea_priv->last_frame++; 554 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = 555 1 - dev_priv->current_page; 556 557 BEGIN_RING(2); 558 559 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); 560 OUT_RING(dev_priv->sarea_priv->last_frame); 561 562 ADVANCE_RING(); 563} 564 565static void r128_cce_dispatch_vertex(struct drm_device *dev, struct drm_buf *buf) 566{ 567 drm_r128_private_t *dev_priv = dev->dev_private; 568 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 569 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 570 int format = sarea_priv->vc_format; 571 int offset = buf->bus_address; 572 int size = buf->used; 573 int prim = buf_priv->prim; 574 int i = 0; 575 RING_LOCALS; 576 DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox); 577 578 if (0) 579 r128_print_dirty("dispatch_vertex", sarea_priv->dirty); 580 581 if (buf->used) { 582 buf_priv->dispatched = 1; 583 584 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) 585 r128_emit_state(dev_priv); 586 587 do { 588 /* Emit the next set of up to three cliprects */ 589 if (i < sarea_priv->nbox) { 590 r128_emit_clip_rects(dev_priv, 591 &sarea_priv->boxes[i], 592 sarea_priv->nbox - i); 593 } 594 595 /* Emit the vertex buffer rendering commands */ 596 BEGIN_RING(5); 597 598 OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3)); 599 OUT_RING(offset); 600 OUT_RING(size); 601 OUT_RING(format); 602 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | 603 (size << R128_CCE_VC_CNTL_NUM_SHIFT)); 604 605 ADVANCE_RING(); 606 607 i += 3; 608 } while (i < sarea_priv->nbox); 609 } 610 611 if (buf_priv->discard) { 612 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 613 614 /* Emit the vertex buffer age */ 615 BEGIN_RING(2); 616 617 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); 618 OUT_RING(buf_priv->age); 619 620 ADVANCE_RING(); 621 622 buf->pending = 1; 623 buf->used = 0; 624 buf_priv->dispatched = 0; 625 } 626 627 dev_priv->sarea_priv->last_dispatch++; 628 629 sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; 630 sarea_priv->nbox = 0; 631} 632 633static void r128_cce_dispatch_indirect(struct drm_device *dev, 634 struct drm_buf *buf, int start, int end) 635{ 636 drm_r128_private_t *dev_priv = dev->dev_private; 637 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 638 RING_LOCALS; 639 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); 640 641 if (start != end) { 642 int offset = buf->bus_address + start; 643 int dwords = (end - start + 3) / sizeof(u32); 644 645 /* Indirect buffer data must be an even number of 646 * dwords, so if we've been given an odd number we must 647 * pad the data with a Type-2 CCE packet. 648 */ 649 if (dwords & 1) { 650 u32 *data = (u32 *) 651 ((char *)dev->agp_buffer_map->handle 652 + buf->offset + start); 653 data[dwords++] = cpu_to_le32(R128_CCE_PACKET2); 654 } 655 656 buf_priv->dispatched = 1; 657 658 /* Fire off the indirect buffer */ 659 BEGIN_RING(3); 660 661 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1)); 662 OUT_RING(offset); 663 OUT_RING(dwords); 664 665 ADVANCE_RING(); 666 } 667 668 if (buf_priv->discard) { 669 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 670 671 /* Emit the indirect buffer age */ 672 BEGIN_RING(2); 673 674 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); 675 OUT_RING(buf_priv->age); 676 677 ADVANCE_RING(); 678 679 buf->pending = 1; 680 buf->used = 0; 681 buf_priv->dispatched = 0; 682 } 683 684 dev_priv->sarea_priv->last_dispatch++; 685} 686 687static void r128_cce_dispatch_indices(struct drm_device *dev, 688 struct drm_buf *buf, 689 int start, int end, int count) 690{ 691 drm_r128_private_t *dev_priv = dev->dev_private; 692 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 693 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 694 int format = sarea_priv->vc_format; 695 int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset; 696 int prim = buf_priv->prim; 697 u32 *data; 698 int dwords; 699 int i = 0; 700 RING_LOCALS; 701 DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count); 702 703 if (0) 704 r128_print_dirty("dispatch_indices", sarea_priv->dirty); 705 706 if (start != end) { 707 buf_priv->dispatched = 1; 708 709 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) 710 r128_emit_state(dev_priv); 711 712 dwords = (end - start + 3) / sizeof(u32); 713 714 data = (u32 *) ((char *)dev->agp_buffer_map->handle 715 + buf->offset + start); 716 717 data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 718 dwords - 2)); 719 720 data[1] = cpu_to_le32(offset); 721 data[2] = cpu_to_le32(R128_MAX_VB_VERTS); 722 data[3] = cpu_to_le32(format); 723 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | 724 (count << 16))); 725 726 if (count & 0x1) { 727#ifdef __LITTLE_ENDIAN 728 data[dwords - 1] &= 0x0000ffff; 729#else 730 data[dwords - 1] &= 0xffff0000; 731#endif 732 } 733 734 do { 735 /* Emit the next set of up to three cliprects */ 736 if (i < sarea_priv->nbox) { 737 r128_emit_clip_rects(dev_priv, 738 &sarea_priv->boxes[i], 739 sarea_priv->nbox - i); 740 } 741 742 r128_cce_dispatch_indirect(dev, buf, start, end); 743 744 i += 3; 745 } while (i < sarea_priv->nbox); 746 } 747 748 if (buf_priv->discard) { 749 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 750 751 /* Emit the vertex buffer age */ 752 BEGIN_RING(2); 753 754 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); 755 OUT_RING(buf_priv->age); 756 757 ADVANCE_RING(); 758 759 buf->pending = 1; 760 buf_priv->dispatched = 0; 761 } 762 763 dev_priv->sarea_priv->last_dispatch++; 764 765 sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; 766 sarea_priv->nbox = 0; 767} 768 769static int r128_cce_dispatch_blit(struct drm_device *dev, 770 struct drm_file *file_priv, 771 drm_r128_blit_t *blit) 772{ 773 drm_r128_private_t *dev_priv = dev->dev_private; 774 struct drm_device_dma *dma = dev->dma; 775 struct drm_buf *buf; 776 drm_r128_buf_priv_t *buf_priv; 777 u32 *data; 778 int dword_shift, dwords; 779 RING_LOCALS; 780 DRM_DEBUG("\n"); 781 782 /* The compiler won't optimize away a division by a variable, 783 * even if the only legal values are powers of two. Thus, we'll 784 * use a shift instead. 785 */ 786 switch (blit->format) { 787 case R128_DATATYPE_ARGB8888: 788 dword_shift = 0; 789 break; 790 case R128_DATATYPE_ARGB1555: 791 case R128_DATATYPE_RGB565: 792 case R128_DATATYPE_ARGB4444: 793 case R128_DATATYPE_YVYU422: 794 case R128_DATATYPE_VYUY422: 795 dword_shift = 1; 796 break; 797 case R128_DATATYPE_CI8: 798 case R128_DATATYPE_RGB8: 799 dword_shift = 2; 800 break; 801 default: 802 DRM_ERROR("invalid blit format %d\n", blit->format); 803 return -EINVAL; 804 } 805 806 /* Flush the pixel cache, and mark the contents as Read Invalid. 807 * This ensures no pixel data gets mixed up with the texture 808 * data from the host data blit, otherwise part of the texture 809 * image may be corrupted. 810 */ 811 BEGIN_RING(2); 812 813 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); 814 OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI); 815 816 ADVANCE_RING(); 817 818 /* Dispatch the indirect buffer. 819 */ 820 buf = dma->buflist[blit->idx]; 821 buf_priv = buf->dev_private; 822 823 if (buf->file_priv != file_priv) { 824 DRM_ERROR("process %d using buffer owned by %p\n", 825 DRM_CURRENTPID, buf->file_priv); 826 return -EINVAL; 827 } 828 if (buf->pending) { 829 DRM_ERROR("sending pending buffer %d\n", blit->idx); 830 return -EINVAL; 831 } 832 833 buf_priv->discard = 1; 834 835 dwords = (blit->width * blit->height) >> dword_shift; 836 837 data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); 838 839 data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6)); 840 data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL | 841 R128_GMC_BRUSH_NONE | 842 (blit->format << 8) | 843 R128_GMC_SRC_DATATYPE_COLOR | 844 R128_ROP3_S | 845 R128_DP_SRC_SOURCE_HOST_DATA | 846 R128_GMC_CLR_CMP_CNTL_DIS | 847 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS)); 848 849 data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5)); 850 data[3] = cpu_to_le32(0xffffffff); 851 data[4] = cpu_to_le32(0xffffffff); 852 data[5] = cpu_to_le32((blit->y << 16) | blit->x); 853 data[6] = cpu_to_le32((blit->height << 16) | blit->width); 854 data[7] = cpu_to_le32(dwords); 855 856 buf->used = (dwords + 8) * sizeof(u32); 857 858 r128_cce_dispatch_indirect(dev, buf, 0, buf->used); 859 860 /* Flush the pixel cache after the blit completes. This ensures 861 * the texture data is written out to memory before rendering 862 * continues. 863 */ 864 BEGIN_RING(2); 865 866 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); 867 OUT_RING(R128_PC_FLUSH_GUI); 868 869 ADVANCE_RING(); 870 871 return 0; 872} 873 874 875static int r128_cce_dispatch_write_span(struct drm_device *dev, 876 drm_r128_depth_t *depth) 877{ 878 drm_r128_private_t *dev_priv = dev->dev_private; 879 int count, x, y; 880 u32 *buffer; 881 u8 *mask; 882 int i, buffer_size, mask_size; 883 RING_LOCALS; 884 DRM_DEBUG("\n"); 885 886 count = depth->n; 887 if (count > 4096 || count <= 0) 888 return -EMSGSIZE; 889 890 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) 891 return -EFAULT; 892 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) 893 return -EFAULT; 894 895 buffer_size = depth->n * sizeof(u32); 896 buffer = kmalloc(buffer_size, GFP_KERNEL); 897 if (buffer == NULL) 898 return -ENOMEM; 899 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { 900 kfree(buffer); 901 return -EFAULT; 902 } 903 904 mask_size = depth->n * sizeof(u8); 905 if (depth->mask) { 906 mask = kmalloc(mask_size, GFP_KERNEL); 907 if (mask == NULL) { 908 kfree(buffer); 909 return -ENOMEM; 910 } 911 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { 912 kfree(buffer); 913 kfree(mask); 914 return -EFAULT; 915 } 916 917 for (i = 0; i < count; i++, x++) { 918 if (mask[i]) { 919 BEGIN_RING(6); 920 921 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); 922 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | 923 R128_GMC_BRUSH_SOLID_COLOR | 924 (dev_priv->depth_fmt << 8) | 925 R128_GMC_SRC_DATATYPE_COLOR | 926 R128_ROP3_P | 927 R128_GMC_CLR_CMP_CNTL_DIS | 928 R128_GMC_WR_MSK_DIS); 929 930 OUT_RING(dev_priv->depth_pitch_offset_c); 931 OUT_RING(buffer[i]); 932 933 OUT_RING((x << 16) | y); 934 OUT_RING((1 << 16) | 1); 935 936 ADVANCE_RING(); 937 } 938 } 939 940 kfree(mask); 941 } else { 942 for (i = 0; i < count; i++, x++) { 943 BEGIN_RING(6); 944 945 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); 946 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | 947 R128_GMC_BRUSH_SOLID_COLOR | 948 (dev_priv->depth_fmt << 8) | 949 R128_GMC_SRC_DATATYPE_COLOR | 950 R128_ROP3_P | 951 R128_GMC_CLR_CMP_CNTL_DIS | 952 R128_GMC_WR_MSK_DIS); 953 954 OUT_RING(dev_priv->depth_pitch_offset_c); 955 OUT_RING(buffer[i]); 956 957 OUT_RING((x << 16) | y); 958 OUT_RING((1 << 16) | 1); 959 960 ADVANCE_RING(); 961 } 962 } 963 964 kfree(buffer); 965 966 return 0; 967} 968 969static int r128_cce_dispatch_write_pixels(struct drm_device *dev, 970 drm_r128_depth_t *depth) 971{ 972 drm_r128_private_t *dev_priv = dev->dev_private; 973 int count, *x, *y; 974 u32 *buffer; 975 u8 *mask; 976 int i, xbuf_size, ybuf_size, buffer_size, mask_size; 977 RING_LOCALS; 978 DRM_DEBUG("\n"); 979 980 count = depth->n; 981 if (count > 4096 || count <= 0) 982 return -EMSGSIZE; 983 984 xbuf_size = count * sizeof(*x); 985 ybuf_size = count * sizeof(*y); 986 x = kmalloc(xbuf_size, GFP_KERNEL); 987 if (x == NULL) 988 return -ENOMEM; 989 y = kmalloc(ybuf_size, GFP_KERNEL); 990 if (y == NULL) { 991 kfree(x); 992 return -ENOMEM; 993 } 994 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { 995 kfree(x); 996 kfree(y); 997 return -EFAULT; 998 } 999 if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) { 1000 kfree(x); 1001 kfree(y); 1002 return -EFAULT; 1003 } 1004 1005 buffer_size = depth->n * sizeof(u32); 1006 buffer = kmalloc(buffer_size, GFP_KERNEL); 1007 if (buffer == NULL) { 1008 kfree(x); 1009 kfree(y); 1010 return -ENOMEM; 1011 } 1012 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { 1013 kfree(x); 1014 kfree(y); 1015 kfree(buffer); 1016 return -EFAULT; 1017 } 1018 1019 if (depth->mask) { 1020 mask_size = depth->n * sizeof(u8); 1021 mask = kmalloc(mask_size, GFP_KERNEL); 1022 if (mask == NULL) { 1023 kfree(x); 1024 kfree(y); 1025 kfree(buffer); 1026 return -ENOMEM; 1027 } 1028 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { 1029 kfree(x); 1030 kfree(y); 1031 kfree(buffer); 1032 kfree(mask); 1033 return -EFAULT; 1034 } 1035 1036 for (i = 0; i < count; i++) { 1037 if (mask[i]) { 1038 BEGIN_RING(6); 1039 1040 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); 1041 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | 1042 R128_GMC_BRUSH_SOLID_COLOR | 1043 (dev_priv->depth_fmt << 8) | 1044 R128_GMC_SRC_DATATYPE_COLOR | 1045 R128_ROP3_P | 1046 R128_GMC_CLR_CMP_CNTL_DIS | 1047 R128_GMC_WR_MSK_DIS); 1048 1049 OUT_RING(dev_priv->depth_pitch_offset_c); 1050 OUT_RING(buffer[i]); 1051 1052 OUT_RING((x[i] << 16) | y[i]); 1053 OUT_RING((1 << 16) | 1); 1054 1055 ADVANCE_RING(); 1056 } 1057 } 1058 1059 kfree(mask); 1060 } else { 1061 for (i = 0; i < count; i++) { 1062 BEGIN_RING(6); 1063 1064 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); 1065 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | 1066 R128_GMC_BRUSH_SOLID_COLOR | 1067 (dev_priv->depth_fmt << 8) | 1068 R128_GMC_SRC_DATATYPE_COLOR | 1069 R128_ROP3_P | 1070 R128_GMC_CLR_CMP_CNTL_DIS | 1071 R128_GMC_WR_MSK_DIS); 1072 1073 OUT_RING(dev_priv->depth_pitch_offset_c); 1074 OUT_RING(buffer[i]); 1075 1076 OUT_RING((x[i] << 16) | y[i]); 1077 OUT_RING((1 << 16) | 1); 1078 1079 ADVANCE_RING(); 1080 } 1081 } 1082 1083 kfree(x); 1084 kfree(y); 1085 kfree(buffer); 1086 1087 return 0; 1088} 1089 1090static int r128_cce_dispatch_read_span(struct drm_device *dev, 1091 drm_r128_depth_t *depth) 1092{ 1093 drm_r128_private_t *dev_priv = dev->dev_private; 1094 int count, x, y; 1095 RING_LOCALS; 1096 DRM_DEBUG("\n"); 1097 1098 count = depth->n; 1099 if (count > 4096 || count <= 0) 1100 return -EMSGSIZE; 1101 1102 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) 1103 return -EFAULT; 1104 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) 1105 return -EFAULT; 1106 1107 BEGIN_RING(7); 1108 1109 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); 1110 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | 1111 R128_GMC_DST_PITCH_OFFSET_CNTL | 1112 R128_GMC_BRUSH_NONE | 1113 (dev_priv->depth_fmt << 8) | 1114 R128_GMC_SRC_DATATYPE_COLOR | 1115 R128_ROP3_S | 1116 R128_DP_SRC_SOURCE_MEMORY | 1117 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); 1118 1119 OUT_RING(dev_priv->depth_pitch_offset_c); 1120 OUT_RING(dev_priv->span_pitch_offset_c); 1121 1122 OUT_RING((x << 16) | y); 1123 OUT_RING((0 << 16) | 0); 1124 OUT_RING((count << 16) | 1); 1125 1126 ADVANCE_RING(); 1127 1128 return 0; 1129} 1130 1131static int r128_cce_dispatch_read_pixels(struct drm_device *dev, 1132 drm_r128_depth_t *depth) 1133{ 1134 drm_r128_private_t *dev_priv = dev->dev_private; 1135 int count, *x, *y; 1136 int i, xbuf_size, ybuf_size; 1137 RING_LOCALS; 1138 DRM_DEBUG("\n"); 1139 1140 count = depth->n; 1141 if (count > 4096 || count <= 0) 1142 return -EMSGSIZE; 1143 1144 if (count > dev_priv->depth_pitch) 1145 count = dev_priv->depth_pitch; 1146 1147 xbuf_size = count * sizeof(*x); 1148 ybuf_size = count * sizeof(*y); 1149 x = kmalloc(xbuf_size, GFP_KERNEL); 1150 if (x == NULL) 1151 return -ENOMEM; 1152 y = kmalloc(ybuf_size, GFP_KERNEL); 1153 if (y == NULL) { 1154 kfree(x); 1155 return -ENOMEM; 1156 } 1157 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { 1158 kfree(x); 1159 kfree(y); 1160 return -EFAULT; 1161 } 1162 if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) { 1163 kfree(x); 1164 kfree(y); 1165 return -EFAULT; 1166 } 1167 1168 for (i = 0; i < count; i++) { 1169 BEGIN_RING(7); 1170 1171 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); 1172 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | 1173 R128_GMC_DST_PITCH_OFFSET_CNTL | 1174 R128_GMC_BRUSH_NONE | 1175 (dev_priv->depth_fmt << 8) | 1176 R128_GMC_SRC_DATATYPE_COLOR | 1177 R128_ROP3_S | 1178 R128_DP_SRC_SOURCE_MEMORY | 1179 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); 1180 1181 OUT_RING(dev_priv->depth_pitch_offset_c); 1182 OUT_RING(dev_priv->span_pitch_offset_c); 1183 1184 OUT_RING((x[i] << 16) | y[i]); 1185 OUT_RING((i << 16) | 0); 1186 OUT_RING((1 << 16) | 1); 1187 1188 ADVANCE_RING(); 1189 } 1190 1191 kfree(x); 1192 kfree(y); 1193 1194 return 0; 1195} 1196 1197/* ================================================================ 1198 * Polygon stipple 1199 */ 1200 1201static void r128_cce_dispatch_stipple(struct drm_device *dev, u32 *stipple) 1202{ 1203 drm_r128_private_t *dev_priv = dev->dev_private; 1204 int i; 1205 RING_LOCALS; 1206 DRM_DEBUG("\n"); 1207 1208 BEGIN_RING(33); 1209 1210 OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31)); 1211 for (i = 0; i < 32; i++) 1212 OUT_RING(stipple[i]); 1213 1214 ADVANCE_RING(); 1215} 1216 1217/* ================================================================ 1218 * IOCTL functions 1219 */ 1220 1221static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) 1222{ 1223 drm_r128_private_t *dev_priv = dev->dev_private; 1224 drm_r128_sarea_t *sarea_priv; 1225 drm_r128_clear_t *clear = data; 1226 DRM_DEBUG("\n"); 1227 1228 LOCK_TEST_WITH_RETURN(dev, file_priv); 1229 1230 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1231 1232 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1233 1234 sarea_priv = dev_priv->sarea_priv; 1235 1236 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) 1237 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; 1238 1239 r128_cce_dispatch_clear(dev, clear); 1240 COMMIT_RING(); 1241 1242 /* Make sure we restore the 3D state next time. 1243 */ 1244 dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; 1245 1246 return 0; 1247} 1248 1249static int r128_do_init_pageflip(struct drm_device *dev) 1250{ 1251 drm_r128_private_t *dev_priv = dev->dev_private; 1252 DRM_DEBUG("\n"); 1253 1254 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET); 1255 dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL); 1256 1257 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset); 1258 R128_WRITE(R128_CRTC_OFFSET_CNTL, 1259 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL); 1260 1261 dev_priv->page_flipping = 1; 1262 dev_priv->current_page = 0; 1263 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; 1264 1265 return 0; 1266} 1267 1268static int r128_do_cleanup_pageflip(struct drm_device *dev) 1269{ 1270 drm_r128_private_t *dev_priv = dev->dev_private; 1271 DRM_DEBUG("\n"); 1272 1273 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); 1274 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); 1275 1276 if (dev_priv->current_page != 0) { 1277 r128_cce_dispatch_flip(dev); 1278 COMMIT_RING(); 1279 } 1280 1281 dev_priv->page_flipping = 0; 1282 return 0; 1283} 1284 1285/* Swapping and flipping are different operations, need different ioctls. 1286 * They can & should be intermixed to support multiple 3d windows. 1287 */ 1288 1289static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *file_priv) 1290{ 1291 drm_r128_private_t *dev_priv = dev->dev_private; 1292 DRM_DEBUG("\n"); 1293 1294 LOCK_TEST_WITH_RETURN(dev, file_priv); 1295 1296 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1297 1298 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1299 1300 if (!dev_priv->page_flipping) 1301 r128_do_init_pageflip(dev); 1302 1303 r128_cce_dispatch_flip(dev); 1304 1305 COMMIT_RING(); 1306 return 0; 1307} 1308 1309static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) 1310{ 1311 drm_r128_private_t *dev_priv = dev->dev_private; 1312 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 1313 DRM_DEBUG("\n"); 1314 1315 LOCK_TEST_WITH_RETURN(dev, file_priv); 1316 1317 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1318 1319 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1320 1321 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) 1322 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; 1323 1324 r128_cce_dispatch_swap(dev); 1325 dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | 1326 R128_UPLOAD_MASKS); 1327 1328 COMMIT_RING(); 1329 return 0; 1330} 1331 1332static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) 1333{ 1334 drm_r128_private_t *dev_priv = dev->dev_private; 1335 struct drm_device_dma *dma = dev->dma; 1336 struct drm_buf *buf; 1337 drm_r128_buf_priv_t *buf_priv; 1338 drm_r128_vertex_t *vertex = data; 1339 1340 LOCK_TEST_WITH_RETURN(dev, file_priv); 1341 1342 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1343 1344 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", 1345 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); 1346 1347 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { 1348 DRM_ERROR("buffer index %d (of %d max)\n", 1349 vertex->idx, dma->buf_count - 1); 1350 return -EINVAL; 1351 } 1352 if (vertex->prim < 0 || 1353 vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { 1354 DRM_ERROR("buffer prim %d\n", vertex->prim); 1355 return -EINVAL; 1356 } 1357 1358 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1359 VB_AGE_TEST_WITH_RETURN(dev_priv); 1360 1361 buf = dma->buflist[vertex->idx]; 1362 buf_priv = buf->dev_private; 1363 1364 if (buf->file_priv != file_priv) { 1365 DRM_ERROR("process %d using buffer owned by %p\n", 1366 DRM_CURRENTPID, buf->file_priv); 1367 return -EINVAL; 1368 } 1369 if (buf->pending) { 1370 DRM_ERROR("sending pending buffer %d\n", vertex->idx); 1371 return -EINVAL; 1372 } 1373 1374 buf->used = vertex->count; 1375 buf_priv->prim = vertex->prim; 1376 buf_priv->discard = vertex->discard; 1377 1378 r128_cce_dispatch_vertex(dev, buf); 1379 1380 COMMIT_RING(); 1381 return 0; 1382} 1383 1384static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) 1385{ 1386 drm_r128_private_t *dev_priv = dev->dev_private; 1387 struct drm_device_dma *dma = dev->dma; 1388 struct drm_buf *buf; 1389 drm_r128_buf_priv_t *buf_priv; 1390 drm_r128_indices_t *elts = data; 1391 int count; 1392 1393 LOCK_TEST_WITH_RETURN(dev, file_priv); 1394 1395 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1396 1397 DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, 1398 elts->idx, elts->start, elts->end, elts->discard); 1399 1400 if (elts->idx < 0 || elts->idx >= dma->buf_count) { 1401 DRM_ERROR("buffer index %d (of %d max)\n", 1402 elts->idx, dma->buf_count - 1); 1403 return -EINVAL; 1404 } 1405 if (elts->prim < 0 || 1406 elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { 1407 DRM_ERROR("buffer prim %d\n", elts->prim); 1408 return -EINVAL; 1409 } 1410 1411 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1412 VB_AGE_TEST_WITH_RETURN(dev_priv); 1413 1414 buf = dma->buflist[elts->idx]; 1415 buf_priv = buf->dev_private; 1416 1417 if (buf->file_priv != file_priv) { 1418 DRM_ERROR("process %d using buffer owned by %p\n", 1419 DRM_CURRENTPID, buf->file_priv); 1420 return -EINVAL; 1421 } 1422 if (buf->pending) { 1423 DRM_ERROR("sending pending buffer %d\n", elts->idx); 1424 return -EINVAL; 1425 } 1426 1427 count = (elts->end - elts->start) / sizeof(u16); 1428 elts->start -= R128_INDEX_PRIM_OFFSET; 1429 1430 if (elts->start & 0x7) { 1431 DRM_ERROR("misaligned buffer 0x%x\n", elts->start); 1432 return -EINVAL; 1433 } 1434 if (elts->start < buf->used) { 1435 DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used); 1436 return -EINVAL; 1437 } 1438 1439 buf->used = elts->end; 1440 buf_priv->prim = elts->prim; 1441 buf_priv->discard = elts->discard; 1442 1443 r128_cce_dispatch_indices(dev, buf, elts->start, elts->end, count); 1444 1445 COMMIT_RING(); 1446 return 0; 1447} 1448 1449static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *file_priv) 1450{ 1451 struct drm_device_dma *dma = dev->dma; 1452 drm_r128_private_t *dev_priv = dev->dev_private; 1453 drm_r128_blit_t *blit = data; 1454 int ret; 1455 1456 LOCK_TEST_WITH_RETURN(dev, file_priv); 1457 1458 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1459 1460 DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx); 1461 1462 if (blit->idx < 0 || blit->idx >= dma->buf_count) { 1463 DRM_ERROR("buffer index %d (of %d max)\n", 1464 blit->idx, dma->buf_count - 1); 1465 return -EINVAL; 1466 } 1467 1468 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1469 VB_AGE_TEST_WITH_RETURN(dev_priv); 1470 1471 ret = r128_cce_dispatch_blit(dev, file_priv, blit); 1472 1473 COMMIT_RING(); 1474 return ret; 1475} 1476 1477static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv) 1478{ 1479 drm_r128_private_t *dev_priv = dev->dev_private; 1480 drm_r128_depth_t *depth = data; 1481 int ret; 1482 1483 LOCK_TEST_WITH_RETURN(dev, file_priv); 1484 1485 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1486 1487 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1488 1489 ret = -EINVAL; 1490 switch (depth->func) { 1491 case R128_WRITE_SPAN: 1492 ret = r128_cce_dispatch_write_span(dev, depth); 1493 break; 1494 case R128_WRITE_PIXELS: 1495 ret = r128_cce_dispatch_write_pixels(dev, depth); 1496 break; 1497 case R128_READ_SPAN: 1498 ret = r128_cce_dispatch_read_span(dev, depth); 1499 break; 1500 case R128_READ_PIXELS: 1501 ret = r128_cce_dispatch_read_pixels(dev, depth); 1502 break; 1503 } 1504 1505 COMMIT_RING(); 1506 return ret; 1507} 1508 1509static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv) 1510{ 1511 drm_r128_private_t *dev_priv = dev->dev_private; 1512 drm_r128_stipple_t *stipple = data; 1513 u32 mask[32]; 1514 1515 LOCK_TEST_WITH_RETURN(dev, file_priv); 1516 1517 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1518 1519 if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) 1520 return -EFAULT; 1521 1522 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1523 1524 r128_cce_dispatch_stipple(dev, mask); 1525 1526 COMMIT_RING(); 1527 return 0; 1528} 1529 1530static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv) 1531{ 1532 drm_r128_private_t *dev_priv = dev->dev_private; 1533 struct drm_device_dma *dma = dev->dma; 1534 struct drm_buf *buf; 1535 drm_r128_buf_priv_t *buf_priv; 1536 drm_r128_indirect_t *indirect = data; 1537 1538 LOCK_TEST_WITH_RETURN(dev, file_priv); 1539 1540 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1541 1542 DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", 1543 indirect->idx, indirect->start, indirect->end, 1544 indirect->discard); 1545 1546 if (indirect->idx < 0 || indirect->idx >= dma->buf_count) { 1547 DRM_ERROR("buffer index %d (of %d max)\n", 1548 indirect->idx, dma->buf_count - 1); 1549 return -EINVAL; 1550 } 1551 1552 buf = dma->buflist[indirect->idx]; 1553 buf_priv = buf->dev_private; 1554 1555 if (buf->file_priv != file_priv) { 1556 DRM_ERROR("process %d using buffer owned by %p\n", 1557 DRM_CURRENTPID, buf->file_priv); 1558 return -EINVAL; 1559 } 1560 if (buf->pending) { 1561 DRM_ERROR("sending pending buffer %d\n", indirect->idx); 1562 return -EINVAL; 1563 } 1564 1565 if (indirect->start < buf->used) { 1566 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", 1567 indirect->start, buf->used); 1568 return -EINVAL; 1569 } 1570 1571 RING_SPACE_TEST_WITH_RETURN(dev_priv); 1572 VB_AGE_TEST_WITH_RETURN(dev_priv); 1573 1574 buf->used = indirect->end; 1575 buf_priv->discard = indirect->discard; 1576 1577 1578 /* Dispatch the indirect buffer full of commands from the 1579 * X server. This is insecure and is thus only available to 1580 * privileged clients. 1581 */ 1582 r128_cce_dispatch_indirect(dev, buf, indirect->start, indirect->end); 1583 1584 COMMIT_RING(); 1585 return 0; 1586} 1587 1588static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) 1589{ 1590 drm_r128_private_t *dev_priv = dev->dev_private; 1591 drm_r128_getparam_t *param = data; 1592 int value; 1593 1594 DEV_INIT_TEST_WITH_RETURN(dev_priv); 1595 1596 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); 1597 1598 switch (param->param) { 1599 case R128_PARAM_IRQ_NR: 1600 value = drm_dev_to_irq(dev); 1601 break; 1602 default: 1603 return -EINVAL; 1604 } 1605 1606 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { 1607 DRM_ERROR("copy_to_user\n"); 1608 return -EFAULT; 1609 } 1610 1611 return 0; 1612} 1613 1614void r128_driver_preclose(struct drm_device *dev, struct drm_file *file_priv) 1615{ 1616 if (dev->dev_private) { 1617 drm_r128_private_t *dev_priv = dev->dev_private; 1618 if (dev_priv->page_flipping) 1619 r128_do_cleanup_pageflip(dev); 1620 } 1621} 1622void r128_driver_lastclose(struct drm_device *dev) 1623{ 1624 r128_do_cleanup_cce(dev); 1625} 1626 1627struct drm_ioctl_desc r128_ioctls[] = { 1628 DRM_IOCTL_DEF_DRV(R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1629 DRM_IOCTL_DEF_DRV(R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1630 DRM_IOCTL_DEF_DRV(R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1631 DRM_IOCTL_DEF_DRV(R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1632 DRM_IOCTL_DEF_DRV(R128_CCE_IDLE, r128_cce_idle, DRM_AUTH), 1633 DRM_IOCTL_DEF_DRV(R128_RESET, r128_engine_reset, DRM_AUTH), 1634 DRM_IOCTL_DEF_DRV(R128_FULLSCREEN, r128_fullscreen, DRM_AUTH), 1635 DRM_IOCTL_DEF_DRV(R128_SWAP, r128_cce_swap, DRM_AUTH), 1636 DRM_IOCTL_DEF_DRV(R128_FLIP, r128_cce_flip, DRM_AUTH), 1637 DRM_IOCTL_DEF_DRV(R128_CLEAR, r128_cce_clear, DRM_AUTH), 1638 DRM_IOCTL_DEF_DRV(R128_VERTEX, r128_cce_vertex, DRM_AUTH), 1639 DRM_IOCTL_DEF_DRV(R128_INDICES, r128_cce_indices, DRM_AUTH), 1640 DRM_IOCTL_DEF_DRV(R128_BLIT, r128_cce_blit, DRM_AUTH), 1641 DRM_IOCTL_DEF_DRV(R128_DEPTH, r128_cce_depth, DRM_AUTH), 1642 DRM_IOCTL_DEF_DRV(R128_STIPPLE, r128_cce_stipple, DRM_AUTH), 1643 DRM_IOCTL_DEF_DRV(R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1644 DRM_IOCTL_DEF_DRV(R128_GETPARAM, r128_getparam, DRM_AUTH), 1645}; 1646 1647int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); 1648