1/* 2 * Copyright (C) 2007 Ben Skeggs. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#ifndef __NOUVEAU_DMA_H__ 28#define __NOUVEAU_DMA_H__ 29 30#ifndef NOUVEAU_DMA_DEBUG 31#define NOUVEAU_DMA_DEBUG 0 32#endif 33 34void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *, 35 int delta, int length); 36 37/* 38 * There's a hw race condition where you can't jump to your PUT offset, 39 * to avoid this we jump to offset + SKIPS and fill the difference with 40 * NOPs. 41 * 42 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses 43 * a SKIPS value of 8. Lets assume that the race condition is to do 44 * with writing into the fetch area, we configure a fetch size of 128 45 * bytes so we need a larger SKIPS value. 46 */ 47#define NOUVEAU_DMA_SKIPS (128 / 4) 48 49/* Hardcoded object assignments to subchannels (subchannel id). */ 50enum { 51 NvSubM2MF = 0, 52 NvSubSw = 1, 53 NvSub2D = 2, 54 NvSubCtxSurf2D = 2, 55 NvSubGdiRect = 3, 56 NvSubImageBlit = 4 57}; 58 59/* Object handles. */ 60enum { 61 NvM2MF = 0x80000001, 62 NvDmaFB = 0x80000002, 63 NvDmaTT = 0x80000003, 64 NvDmaVRAM = 0x80000004, 65 NvDmaGART = 0x80000005, 66 NvNotify0 = 0x80000006, 67 Nv2D = 0x80000007, 68 NvCtxSurf2D = 0x80000008, 69 NvRop = 0x80000009, 70 NvImagePatt = 0x8000000a, 71 NvClipRect = 0x8000000b, 72 NvGdiRect = 0x8000000c, 73 NvImageBlit = 0x8000000d, 74 NvSw = 0x8000000e, 75 76 /* G80+ display objects */ 77 NvEvoVRAM = 0x01000000, 78 NvEvoFB16 = 0x01000001, 79 NvEvoFB32 = 0x01000002 80}; 81 82#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 83#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 84#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 85#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 86#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 87#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 88#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 89#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 90#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 91#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c 92 93#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 94#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 95#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c 96#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 97#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c 98 99static __must_check inline int 100RING_SPACE(struct nouveau_channel *chan, int size) 101{ 102 int ret; 103 104 ret = nouveau_dma_wait(chan, 1, size); 105 if (ret) 106 return ret; 107 108 chan->dma.free -= size; 109 return 0; 110} 111 112static inline void 113OUT_RING(struct nouveau_channel *chan, int data) 114{ 115 if (NOUVEAU_DMA_DEBUG) { 116 NV_INFO(chan->dev, "Ch%d/0x%08x: 0x%08x\n", 117 chan->id, chan->dma.cur << 2, data); 118 } 119 120 nouveau_bo_wr32(chan->pushbuf_bo, chan->dma.cur++, data); 121} 122 123extern void 124OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords); 125 126static inline void 127BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size) 128{ 129 OUT_RING(chan, (subc << 13) | (size << 18) | mthd); 130} 131 132#define WRITE_PUT(val) do { \ 133 DRM_MEMORYBARRIER(); \ 134 nouveau_bo_rd32(chan->pushbuf_bo, 0); \ 135 nvchan_wr32(chan, chan->user_put, ((val) << 2) + chan->pushbuf_base); \ 136} while (0) 137 138static inline void 139FIRE_RING(struct nouveau_channel *chan) 140{ 141 if (NOUVEAU_DMA_DEBUG) { 142 NV_INFO(chan->dev, "Ch%d/0x%08x: PUSH!\n", 143 chan->id, chan->dma.cur << 2); 144 } 145 146 if (chan->dma.cur == chan->dma.put) 147 return; 148 chan->accel_done = true; 149 150 if (chan->dma.ib_max) { 151 nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2, 152 (chan->dma.cur - chan->dma.put) << 2); 153 } else { 154 WRITE_PUT(chan->dma.cur); 155 } 156 157 chan->dma.put = chan->dma.cur; 158} 159 160static inline void 161WIND_RING(struct nouveau_channel *chan) 162{ 163 chan->dma.cur = chan->dma.put; 164} 165 166#endif 167