1/* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright �� 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/delay.h> 31#include "drmP.h" 32#include "drm.h" 33#include "drm_crtc.h" 34#include "drm_edid.h" 35#include "intel_drv.h" 36#include "i915_drm.h" 37#include "i915_drv.h" 38#include "intel_sdvo_regs.h" 39 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) 44 45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 46 SDVO_TV_MASK) 47 48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 51 52 53static const char *tv_format_names[] = { 54 "NTSC_M" , "NTSC_J" , "NTSC_443", 55 "PAL_B" , "PAL_D" , "PAL_G" , 56 "PAL_H" , "PAL_I" , "PAL_M" , 57 "PAL_N" , "PAL_NC" , "PAL_60" , 58 "SECAM_B" , "SECAM_D" , "SECAM_G" , 59 "SECAM_K" , "SECAM_K1", "SECAM_L" , 60 "SECAM_60" 61}; 62 63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) 64 65struct intel_sdvo { 66 struct intel_encoder base; 67 68 u8 slave_addr; 69 70 /* Register for the SDVO device: SDVOB or SDVOC */ 71 int sdvo_reg; 72 73 /* Active outputs controlled by this SDVO output */ 74 uint16_t controlled_output; 75 76 /* 77 * Capabilities of the SDVO device returned by 78 * i830_sdvo_get_capabilities() 79 */ 80 struct intel_sdvo_caps caps; 81 82 /* Pixel clock limitations reported by the SDVO device, in kHz */ 83 int pixel_clock_min, pixel_clock_max; 84 85 /* 86 * For multiple function SDVO device, 87 * this is for current attached outputs. 88 */ 89 uint16_t attached_output; 90 91 /** 92 * This is set if we're going to treat the device as TV-out. 93 * 94 * While we have these nice friendly flags for output types that ought 95 * to decide this for us, the S-Video output on our HDMI+S-Video card 96 * shows up as RGB1 (VGA). 97 */ 98 bool is_tv; 99 100 /* This is for current tv format name */ 101 int tv_format_index; 102 103 /** 104 * This is set if we treat the device as HDMI, instead of DVI. 105 */ 106 bool is_hdmi; 107 108 /** 109 * This is set if we detect output of sdvo device as LVDS. 110 */ 111 bool is_lvds; 112 113 /** 114 * This is sdvo flags for input timing. 115 */ 116 uint8_t sdvo_flags; 117 118 /** 119 * This is sdvo fixed pannel mode pointer 120 */ 121 struct drm_display_mode *sdvo_lvds_fixed_mode; 122 123 /* 124 * supported encoding mode, used to determine whether HDMI is 125 * supported 126 */ 127 struct intel_sdvo_encode encode; 128 129 /* DDC bus used by this SDVO encoder */ 130 uint8_t ddc_bus; 131 132 /* Mac mini hack -- use the same DDC as the analog connector */ 133 struct i2c_adapter *analog_ddc_bus; 134 135}; 136 137struct intel_sdvo_connector { 138 struct intel_connector base; 139 140 /* Mark the type of connector */ 141 uint16_t output_flag; 142 143 /* This contains all current supported TV format */ 144 u8 tv_format_supported[TV_FORMAT_NUM]; 145 int format_supported_num; 146 struct drm_property *tv_format; 147 148 /* add the property for the SDVO-TV */ 149 struct drm_property *left; 150 struct drm_property *right; 151 struct drm_property *top; 152 struct drm_property *bottom; 153 struct drm_property *hpos; 154 struct drm_property *vpos; 155 struct drm_property *contrast; 156 struct drm_property *saturation; 157 struct drm_property *hue; 158 struct drm_property *sharpness; 159 struct drm_property *flicker_filter; 160 struct drm_property *flicker_filter_adaptive; 161 struct drm_property *flicker_filter_2d; 162 struct drm_property *tv_chroma_filter; 163 struct drm_property *tv_luma_filter; 164 struct drm_property *dot_crawl; 165 166 /* add the property for the SDVO-TV/LVDS */ 167 struct drm_property *brightness; 168 169 /* Add variable to record current setting for the above property */ 170 u32 left_margin, right_margin, top_margin, bottom_margin; 171 172 /* this is to get the range of margin.*/ 173 u32 max_hscan, max_vscan; 174 u32 max_hpos, cur_hpos; 175 u32 max_vpos, cur_vpos; 176 u32 cur_brightness, max_brightness; 177 u32 cur_contrast, max_contrast; 178 u32 cur_saturation, max_saturation; 179 u32 cur_hue, max_hue; 180 u32 cur_sharpness, max_sharpness; 181 u32 cur_flicker_filter, max_flicker_filter; 182 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 183 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 184 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 185 u32 cur_tv_luma_filter, max_tv_luma_filter; 186 u32 cur_dot_crawl, max_dot_crawl; 187}; 188 189static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder) 190{ 191 return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base); 192} 193 194static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 195{ 196 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 197} 198 199static bool 200intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 201static bool 202intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 203 struct intel_sdvo_connector *intel_sdvo_connector, 204 int type); 205static bool 206intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 207 struct intel_sdvo_connector *intel_sdvo_connector); 208 209static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 210{ 211 struct drm_device *dev = intel_sdvo->base.enc.dev; 212 struct drm_i915_private *dev_priv = dev->dev_private; 213 u32 bval = val, cval = val; 214 int i; 215 216 if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 217 I915_WRITE(intel_sdvo->sdvo_reg, val); 218 I915_READ(intel_sdvo->sdvo_reg); 219 return; 220 } 221 222 if (intel_sdvo->sdvo_reg == SDVOB) { 223 cval = I915_READ(SDVOC); 224 } else { 225 bval = I915_READ(SDVOB); 226 } 227 /* 228 * Write the registers twice for luck. Sometimes, 229 * writing them only once doesn't appear to 'stick'. 230 * The BIOS does this too. Yay, magic 231 */ 232 for (i = 0; i < 2; i++) 233 { 234 I915_WRITE(SDVOB, bval); 235 I915_READ(SDVOB); 236 I915_WRITE(SDVOC, cval); 237 I915_READ(SDVOC); 238 } 239} 240 241static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 242{ 243 u8 out_buf[2] = { addr, 0 }; 244 u8 buf[2]; 245 struct i2c_msg msgs[] = { 246 { 247 .addr = intel_sdvo->slave_addr >> 1, 248 .flags = 0, 249 .len = 1, 250 .buf = out_buf, 251 }, 252 { 253 .addr = intel_sdvo->slave_addr >> 1, 254 .flags = I2C_M_RD, 255 .len = 1, 256 .buf = buf, 257 } 258 }; 259 int ret; 260 261 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2) 262 { 263 *ch = buf[0]; 264 return true; 265 } 266 267 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 268 return false; 269} 270 271static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch) 272{ 273 u8 out_buf[2] = { addr, ch }; 274 struct i2c_msg msgs[] = { 275 { 276 .addr = intel_sdvo->slave_addr >> 1, 277 .flags = 0, 278 .len = 2, 279 .buf = out_buf, 280 } 281 }; 282 283 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1; 284} 285 286#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 287/** Mapping of command numbers to names, for debug output */ 288static const struct _sdvo_cmd_name { 289 u8 cmd; 290 const char *name; 291} sdvo_cmd_names[] = { 292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 335 336 /* Add the op code for SDVO enhancements */ 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 381 382 /* HDMI op code */ 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 403}; 404 405#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) 406#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") 407 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 409 const void *args, int args_len) 410{ 411 int i; 412 413 DRM_DEBUG_KMS("%s: W: %02X ", 414 SDVO_NAME(intel_sdvo), cmd); 415 for (i = 0; i < args_len; i++) 416 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); 417 for (; i < 8; i++) 418 DRM_LOG_KMS(" "); 419 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 420 if (cmd == sdvo_cmd_names[i].cmd) { 421 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); 422 break; 423 } 424 } 425 if (i == ARRAY_SIZE(sdvo_cmd_names)) 426 DRM_LOG_KMS("(%02X)", cmd); 427 DRM_LOG_KMS("\n"); 428} 429 430static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 431 const void *args, int args_len) 432{ 433 int i; 434 435 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 436 437 for (i = 0; i < args_len; i++) { 438 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i, 439 ((u8*)args)[i])) 440 return false; 441 } 442 443 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd); 444} 445 446static const char *cmd_status_names[] = { 447 "Power on", 448 "Success", 449 "Not supported", 450 "Invalid arg", 451 "Pending", 452 "Target not specified", 453 "Scaling not supported" 454}; 455 456static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo, 457 void *response, int response_len, 458 u8 status) 459{ 460 int i; 461 462 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); 463 for (i = 0; i < response_len; i++) 464 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); 465 for (; i < 8; i++) 466 DRM_LOG_KMS(" "); 467 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 468 DRM_LOG_KMS("(%s)", cmd_status_names[status]); 469 else 470 DRM_LOG_KMS("(??? %d)", status); 471 DRM_LOG_KMS("\n"); 472} 473 474static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 475 void *response, int response_len) 476{ 477 int i; 478 u8 status; 479 u8 retry = 50; 480 481 while (retry--) { 482 /* Read the command response */ 483 for (i = 0; i < response_len; i++) { 484 if (!intel_sdvo_read_byte(intel_sdvo, 485 SDVO_I2C_RETURN_0 + i, 486 &((u8 *)response)[i])) 487 return false; 488 } 489 490 /* read the return status */ 491 if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS, 492 &status)) 493 return false; 494 495 intel_sdvo_debug_response(intel_sdvo, response, response_len, 496 status); 497 if (status != SDVO_CMD_STATUS_PENDING) 498 break; 499 500 mdelay(50); 501 } 502 503 return status == SDVO_CMD_STATUS_SUCCESS; 504} 505 506static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 507{ 508 if (mode->clock >= 100000) 509 return 1; 510 else if (mode->clock >= 50000) 511 return 2; 512 else 513 return 4; 514} 515 516/** 517 * Try to read the response after issuie the DDC switch command. But it 518 * is noted that we must do the action of reading response and issuing DDC 519 * switch command in one I2C transaction. Otherwise when we try to start 520 * another I2C transaction after issuing the DDC bus switch, it will be 521 * switched to the internal SDVO register. 522 */ 523static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 524 u8 target) 525{ 526 u8 out_buf[2], cmd_buf[2], ret_value[2], ret; 527 struct i2c_msg msgs[] = { 528 { 529 .addr = intel_sdvo->slave_addr >> 1, 530 .flags = 0, 531 .len = 2, 532 .buf = out_buf, 533 }, 534 /* the following two are to read the response */ 535 { 536 .addr = intel_sdvo->slave_addr >> 1, 537 .flags = 0, 538 .len = 1, 539 .buf = cmd_buf, 540 }, 541 { 542 .addr = intel_sdvo->slave_addr >> 1, 543 .flags = I2C_M_RD, 544 .len = 1, 545 .buf = ret_value, 546 }, 547 }; 548 549 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH, 550 &target, 1); 551 /* write the DDC switch command argument */ 552 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target); 553 554 out_buf[0] = SDVO_I2C_OPCODE; 555 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; 556 cmd_buf[0] = SDVO_I2C_CMD_STATUS; 557 cmd_buf[1] = 0; 558 ret_value[0] = 0; 559 ret_value[1] = 0; 560 561 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3); 562 if (ret != 3) { 563 /* failure in I2C transfer */ 564 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 565 return; 566 } 567 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) { 568 DRM_DEBUG_KMS("DDC switch command returns response %d\n", 569 ret_value[0]); 570 return; 571 } 572 return; 573} 574 575static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 576{ 577 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 578 return false; 579 580 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 581} 582 583static bool 584intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 585{ 586 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 587 return false; 588 589 return intel_sdvo_read_response(intel_sdvo, value, len); 590} 591 592static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 593{ 594 struct intel_sdvo_set_target_input_args targets = {0}; 595 return intel_sdvo_set_value(intel_sdvo, 596 SDVO_CMD_SET_TARGET_INPUT, 597 &targets, sizeof(targets)); 598} 599 600/** 601 * Return whether each input is trained. 602 * 603 * This function is making an assumption about the layout of the response, 604 * which should be checked against the docs. 605 */ 606static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 607{ 608 struct intel_sdvo_get_trained_inputs_response response; 609 610 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 611 &response, sizeof(response))) 612 return false; 613 614 *input_1 = response.input0_trained; 615 *input_2 = response.input1_trained; 616 return true; 617} 618 619static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 620 u16 outputs) 621{ 622 return intel_sdvo_set_value(intel_sdvo, 623 SDVO_CMD_SET_ACTIVE_OUTPUTS, 624 &outputs, sizeof(outputs)); 625} 626 627static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 628 int mode) 629{ 630 u8 state = SDVO_ENCODER_STATE_ON; 631 632 switch (mode) { 633 case DRM_MODE_DPMS_ON: 634 state = SDVO_ENCODER_STATE_ON; 635 break; 636 case DRM_MODE_DPMS_STANDBY: 637 state = SDVO_ENCODER_STATE_STANDBY; 638 break; 639 case DRM_MODE_DPMS_SUSPEND: 640 state = SDVO_ENCODER_STATE_SUSPEND; 641 break; 642 case DRM_MODE_DPMS_OFF: 643 state = SDVO_ENCODER_STATE_OFF; 644 break; 645 } 646 647 return intel_sdvo_set_value(intel_sdvo, 648 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 649} 650 651static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 652 int *clock_min, 653 int *clock_max) 654{ 655 struct intel_sdvo_pixel_clock_range clocks; 656 657 if (!intel_sdvo_get_value(intel_sdvo, 658 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 659 &clocks, sizeof(clocks))) 660 return false; 661 662 /* Convert the values from units of 10 kHz to kHz. */ 663 *clock_min = clocks.min * 10; 664 *clock_max = clocks.max * 10; 665 return true; 666} 667 668static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 669 u16 outputs) 670{ 671 return intel_sdvo_set_value(intel_sdvo, 672 SDVO_CMD_SET_TARGET_OUTPUT, 673 &outputs, sizeof(outputs)); 674} 675 676static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 677 struct intel_sdvo_dtd *dtd) 678{ 679 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 680 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 681} 682 683static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 684 struct intel_sdvo_dtd *dtd) 685{ 686 return intel_sdvo_set_timing(intel_sdvo, 687 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 688} 689 690static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 691 struct intel_sdvo_dtd *dtd) 692{ 693 return intel_sdvo_set_timing(intel_sdvo, 694 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 695} 696 697static bool 698intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 699 uint16_t clock, 700 uint16_t width, 701 uint16_t height) 702{ 703 struct intel_sdvo_preferred_input_timing_args args; 704 705 memset(&args, 0, sizeof(args)); 706 args.clock = clock; 707 args.width = width; 708 args.height = height; 709 args.interlace = 0; 710 711 if (intel_sdvo->is_lvds && 712 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 713 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 714 args.scaled = 1; 715 716 return intel_sdvo_set_value(intel_sdvo, 717 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 718 &args, sizeof(args)); 719} 720 721static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 722 struct intel_sdvo_dtd *dtd) 723{ 724 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 725 &dtd->part1, sizeof(dtd->part1)) && 726 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 727 &dtd->part2, sizeof(dtd->part2)); 728} 729 730static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 731{ 732 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 733} 734 735static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 736 const struct drm_display_mode *mode) 737{ 738 uint16_t width, height; 739 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 740 uint16_t h_sync_offset, v_sync_offset; 741 742 width = mode->crtc_hdisplay; 743 height = mode->crtc_vdisplay; 744 745 /* do some mode translations */ 746 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; 747 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 748 749 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; 750 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 751 752 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; 753 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; 754 755 dtd->part1.clock = mode->clock / 10; 756 dtd->part1.h_active = width & 0xff; 757 dtd->part1.h_blank = h_blank_len & 0xff; 758 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 759 ((h_blank_len >> 8) & 0xf); 760 dtd->part1.v_active = height & 0xff; 761 dtd->part1.v_blank = v_blank_len & 0xff; 762 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 763 ((v_blank_len >> 8) & 0xf); 764 765 dtd->part2.h_sync_off = h_sync_offset & 0xff; 766 dtd->part2.h_sync_width = h_sync_len & 0xff; 767 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 768 (v_sync_len & 0xf); 769 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 770 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 771 ((v_sync_len & 0x30) >> 4); 772 773 dtd->part2.dtd_flags = 0x18; 774 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 775 dtd->part2.dtd_flags |= 0x2; 776 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 777 dtd->part2.dtd_flags |= 0x4; 778 779 dtd->part2.sdvo_flags = 0; 780 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 781 dtd->part2.reserved = 0; 782} 783 784static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, 785 const struct intel_sdvo_dtd *dtd) 786{ 787 mode->hdisplay = dtd->part1.h_active; 788 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 789 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; 790 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 791 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; 792 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 793 mode->htotal = mode->hdisplay + dtd->part1.h_blank; 794 mode->htotal += (dtd->part1.h_high & 0xf) << 8; 795 796 mode->vdisplay = dtd->part1.v_active; 797 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 798 mode->vsync_start = mode->vdisplay; 799 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 800 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 801 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; 802 mode->vsync_end = mode->vsync_start + 803 (dtd->part2.v_sync_off_width & 0xf); 804 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 805 mode->vtotal = mode->vdisplay + dtd->part1.v_blank; 806 mode->vtotal += (dtd->part1.v_high & 0xf) << 8; 807 808 mode->clock = dtd->part1.clock * 10; 809 810 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 811 if (dtd->part2.dtd_flags & 0x2) 812 mode->flags |= DRM_MODE_FLAG_PHSYNC; 813 if (dtd->part2.dtd_flags & 0x4) 814 mode->flags |= DRM_MODE_FLAG_PVSYNC; 815} 816 817static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo, 818 struct intel_sdvo_encode *encode) 819{ 820 if (intel_sdvo_get_value(intel_sdvo, 821 SDVO_CMD_GET_SUPP_ENCODE, 822 encode, sizeof(*encode))) 823 return true; 824 825 /* non-support means DVI */ 826 memset(encode, 0, sizeof(*encode)); 827 return false; 828} 829 830static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 831 uint8_t mode) 832{ 833 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 834} 835 836static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 837 uint8_t mode) 838{ 839 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 840} 841 842 843static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo, 844 int index, 845 uint8_t *data, int8_t size, uint8_t tx_rate) 846{ 847 uint8_t set_buf_index[2]; 848 849 set_buf_index[0] = index; 850 set_buf_index[1] = 0; 851 852 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX, 853 set_buf_index, 2)) 854 return false; 855 856 for (; size > 0; size -= 8) { 857 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8)) 858 return false; 859 860 data += 8; 861 } 862 863 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); 864} 865 866static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) 867{ 868 uint8_t csum = 0; 869 int i; 870 871 for (i = 0; i < size; i++) 872 csum += data[i]; 873 874 return 0x100 - csum; 875} 876 877#define DIP_TYPE_AVI 0x82 878#define DIP_VERSION_AVI 0x2 879#define DIP_LEN_AVI 13 880 881struct dip_infoframe { 882 uint8_t type; 883 uint8_t version; 884 uint8_t len; 885 uint8_t checksum; 886 union { 887 struct { 888 /* Packet Byte #1 */ 889 uint8_t S:2; 890 uint8_t B:2; 891 uint8_t A:1; 892 uint8_t Y:2; 893 uint8_t rsvd1:1; 894 /* Packet Byte #2 */ 895 uint8_t R:4; 896 uint8_t M:2; 897 uint8_t C:2; 898 /* Packet Byte #3 */ 899 uint8_t SC:2; 900 uint8_t Q:2; 901 uint8_t EC:3; 902 uint8_t ITC:1; 903 /* Packet Byte #4 */ 904 uint8_t VIC:7; 905 uint8_t rsvd2:1; 906 /* Packet Byte #5 */ 907 uint8_t PR:4; 908 uint8_t rsvd3:4; 909 /* Packet Byte #6~13 */ 910 uint16_t top_bar_end; 911 uint16_t bottom_bar_start; 912 uint16_t left_bar_end; 913 uint16_t right_bar_start; 914 } avi; 915 struct { 916 /* Packet Byte #1 */ 917 uint8_t channel_count:3; 918 uint8_t rsvd1:1; 919 uint8_t coding_type:4; 920 /* Packet Byte #2 */ 921 uint8_t sample_size:2; /* SS0, SS1 */ 922 uint8_t sample_frequency:3; 923 uint8_t rsvd2:3; 924 /* Packet Byte #3 */ 925 uint8_t coding_type_private:5; 926 uint8_t rsvd3:3; 927 /* Packet Byte #4 */ 928 uint8_t channel_allocation; 929 /* Packet Byte #5 */ 930 uint8_t rsvd4:3; 931 uint8_t level_shift:4; 932 uint8_t downmix_inhibit:1; 933 } audio; 934 uint8_t payload[28]; 935 } __attribute__ ((packed)) u; 936} __attribute__((packed)); 937 938static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 939 struct drm_display_mode * mode) 940{ 941 struct dip_infoframe avi_if = { 942 .type = DIP_TYPE_AVI, 943 .version = DIP_VERSION_AVI, 944 .len = DIP_LEN_AVI, 945 }; 946 947 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, 948 4 + avi_if.len); 949 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if, 950 4 + avi_if.len, 951 SDVO_HBUF_TX_VSYNC); 952} 953 954static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 955{ 956 struct intel_sdvo_tv_format format; 957 uint32_t format_map; 958 959 format_map = 1 << intel_sdvo->tv_format_index; 960 memset(&format, 0, sizeof(format)); 961 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 962 963 BUILD_BUG_ON(sizeof(format) != 6); 964 return intel_sdvo_set_value(intel_sdvo, 965 SDVO_CMD_SET_TV_FORMAT, 966 &format, sizeof(format)); 967} 968 969static bool 970intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 971 struct drm_display_mode *mode) 972{ 973 struct intel_sdvo_dtd output_dtd; 974 975 if (!intel_sdvo_set_target_output(intel_sdvo, 976 intel_sdvo->attached_output)) 977 return false; 978 979 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 980 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 981 return false; 982 983 return true; 984} 985 986static bool 987intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, 988 struct drm_display_mode *mode, 989 struct drm_display_mode *adjusted_mode) 990{ 991 struct intel_sdvo_dtd input_dtd; 992 993 /* Reset the input timing to the screen. Assume always input 0. */ 994 if (!intel_sdvo_set_target_input(intel_sdvo)) 995 return false; 996 997 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 998 mode->clock / 10, 999 mode->hdisplay, 1000 mode->vdisplay)) 1001 return false; 1002 1003 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1004 &input_dtd)) 1005 return false; 1006 1007 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1008 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags; 1009 1010 drm_mode_set_crtcinfo(adjusted_mode, 0); 1011 mode->clock = adjusted_mode->clock; 1012 return true; 1013} 1014 1015static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, 1016 struct drm_display_mode *mode, 1017 struct drm_display_mode *adjusted_mode) 1018{ 1019 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1020 1021 /* We need to construct preferred input timings based on our 1022 * output timings. To do that, we have to set the output 1023 * timings, even though this isn't really the right place in 1024 * the sequence to do it. Oh well. 1025 */ 1026 if (intel_sdvo->is_tv) { 1027 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1028 return false; 1029 1030 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, 1031 mode, 1032 adjusted_mode); 1033 } else if (intel_sdvo->is_lvds) { 1034 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0); 1035 1036 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1037 intel_sdvo->sdvo_lvds_fixed_mode)) 1038 return false; 1039 1040 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, 1041 mode, 1042 adjusted_mode); 1043 } 1044 1045 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1046 * SDVO device will be told of the multiplier during mode_set. 1047 */ 1048 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode); 1049 1050 return true; 1051} 1052 1053static void intel_sdvo_mode_set(struct drm_encoder *encoder, 1054 struct drm_display_mode *mode, 1055 struct drm_display_mode *adjusted_mode) 1056{ 1057 struct drm_device *dev = encoder->dev; 1058 struct drm_i915_private *dev_priv = dev->dev_private; 1059 struct drm_crtc *crtc = encoder->crtc; 1060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1061 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1062 u32 sdvox = 0; 1063 int sdvo_pixel_multiply, rate; 1064 struct intel_sdvo_in_out_map in_out; 1065 struct intel_sdvo_dtd input_dtd; 1066 1067 if (!mode) 1068 return; 1069 1070 /* First, set the input mapping for the first input to our controlled 1071 * output. This is only correct if we're a single-input device, in 1072 * which case the first input is the output from the appropriate SDVO 1073 * channel on the motherboard. In a two-input device, the first input 1074 * will be SDVOB and the second SDVOC. 1075 */ 1076 in_out.in0 = intel_sdvo->attached_output; 1077 in_out.in1 = 0; 1078 1079 intel_sdvo_set_value(intel_sdvo, 1080 SDVO_CMD_SET_IN_OUT_MAP, 1081 &in_out, sizeof(in_out)); 1082 1083 if (intel_sdvo->is_hdmi) { 1084 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode)) 1085 return; 1086 1087 sdvox |= SDVO_AUDIO_ENABLE; 1088 } 1089 1090 /* We have tried to get input timing in mode_fixup, and filled into 1091 adjusted_mode */ 1092 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1093 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1094 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags; 1095 1096 /* If it's a TV, we already set the output timing in mode_fixup. 1097 * Otherwise, the output timing is equal to the input timing. 1098 */ 1099 if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) { 1100 /* Set the output timing to the screen */ 1101 if (!intel_sdvo_set_target_output(intel_sdvo, 1102 intel_sdvo->attached_output)) 1103 return; 1104 1105 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd); 1106 } 1107 1108 /* Set the input timing to the screen. Assume always input 0. */ 1109 if (!intel_sdvo_set_target_input(intel_sdvo)) 1110 return; 1111 1112 if (intel_sdvo->is_tv) { 1113 if (!intel_sdvo_set_tv_format(intel_sdvo)) 1114 return; 1115 } 1116 1117 /* We would like to use intel_sdvo_create_preferred_input_timing() to 1118 * provide the device with a timing it can support, if it supports that 1119 * feature. However, presumably we would need to adjust the CRTC to 1120 * output the preferred timing, and we don't support that currently. 1121 */ 1122 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd); 1123 1124 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); 1125 switch (sdvo_pixel_multiply) { 1126 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1127 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1128 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1129 } 1130 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1131 return; 1132 1133 /* Set the SDVO control regs. */ 1134 if (IS_I965G(dev)) { 1135 sdvox |= SDVO_BORDER_ENABLE; 1136 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1137 sdvox |= SDVO_VSYNC_ACTIVE_HIGH; 1138 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1139 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 1140 } else { 1141 sdvox |= I915_READ(intel_sdvo->sdvo_reg); 1142 switch (intel_sdvo->sdvo_reg) { 1143 case SDVOB: 1144 sdvox &= SDVOB_PRESERVE_MASK; 1145 break; 1146 case SDVOC: 1147 sdvox &= SDVOC_PRESERVE_MASK; 1148 break; 1149 } 1150 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1151 } 1152 if (intel_crtc->pipe == 1) 1153 sdvox |= SDVO_PIPE_B_SELECT; 1154 1155 if (IS_I965G(dev)) { 1156 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1157 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1158 /* done in crtc_mode_set as it lives inside the dpll register */ 1159 } else { 1160 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT; 1161 } 1162 1163 if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL) 1164 sdvox |= SDVO_STALL_SELECT; 1165 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1166} 1167 1168static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) 1169{ 1170 struct drm_device *dev = encoder->dev; 1171 struct drm_i915_private *dev_priv = dev->dev_private; 1172 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1173 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 1174 u32 temp; 1175 1176 if (mode != DRM_MODE_DPMS_ON) { 1177 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1178 if (0) 1179 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1180 1181 if (mode == DRM_MODE_DPMS_OFF) { 1182 temp = I915_READ(intel_sdvo->sdvo_reg); 1183 if ((temp & SDVO_ENABLE) != 0) { 1184 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); 1185 } 1186 } 1187 } else { 1188 bool input1, input2; 1189 int i; 1190 u8 status; 1191 1192 temp = I915_READ(intel_sdvo->sdvo_reg); 1193 if ((temp & SDVO_ENABLE) == 0) 1194 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); 1195 for (i = 0; i < 2; i++) 1196 intel_wait_for_vblank(dev, intel_crtc->pipe); 1197 1198 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1199 /* Warn if the device reported failure to sync. 1200 * A lot of SDVO devices fail to notify of sync, but it's 1201 * a given it the status is a success, we succeeded. 1202 */ 1203 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { 1204 DRM_DEBUG_KMS("First %s output reported failure to " 1205 "sync\n", SDVO_NAME(intel_sdvo)); 1206 } 1207 1208 if (0) 1209 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1210 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1211 } 1212 return; 1213} 1214 1215static int intel_sdvo_mode_valid(struct drm_connector *connector, 1216 struct drm_display_mode *mode) 1217{ 1218 struct drm_encoder *encoder = intel_attached_encoder(connector); 1219 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1220 1221 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1222 return MODE_NO_DBLESCAN; 1223 1224 if (intel_sdvo->pixel_clock_min > mode->clock) 1225 return MODE_CLOCK_LOW; 1226 1227 if (intel_sdvo->pixel_clock_max < mode->clock) 1228 return MODE_CLOCK_HIGH; 1229 1230 if (intel_sdvo->is_lvds) { 1231 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1232 return MODE_PANEL; 1233 1234 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1235 return MODE_PANEL; 1236 } 1237 1238 return MODE_OK; 1239} 1240 1241static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1242{ 1243 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps)); 1244} 1245 1246/* No use! */ 1247 1248static bool 1249intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1250{ 1251 int caps = 0; 1252 1253 if (intel_sdvo->caps.output_flags & 1254 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) 1255 caps++; 1256 if (intel_sdvo->caps.output_flags & 1257 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) 1258 caps++; 1259 if (intel_sdvo->caps.output_flags & 1260 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) 1261 caps++; 1262 if (intel_sdvo->caps.output_flags & 1263 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) 1264 caps++; 1265 if (intel_sdvo->caps.output_flags & 1266 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) 1267 caps++; 1268 1269 if (intel_sdvo->caps.output_flags & 1270 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) 1271 caps++; 1272 1273 if (intel_sdvo->caps.output_flags & 1274 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) 1275 caps++; 1276 1277 return (caps > 1); 1278} 1279 1280static struct drm_connector * 1281intel_find_analog_connector(struct drm_device *dev) 1282{ 1283 struct drm_connector *connector; 1284 struct drm_encoder *encoder; 1285 struct intel_sdvo *intel_sdvo; 1286 1287 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1288 intel_sdvo = enc_to_intel_sdvo(encoder); 1289 if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) { 1290 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1291 if (encoder == intel_attached_encoder(connector)) 1292 return connector; 1293 } 1294 } 1295 } 1296 return NULL; 1297} 1298 1299static int 1300intel_analog_is_connected(struct drm_device *dev) 1301{ 1302 struct drm_connector *analog_connector; 1303 1304 analog_connector = intel_find_analog_connector(dev); 1305 if (!analog_connector) 1306 return false; 1307 1308 if (analog_connector->funcs->detect(analog_connector, false) == 1309 connector_status_disconnected) 1310 return false; 1311 1312 return true; 1313} 1314 1315enum drm_connector_status 1316intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) 1317{ 1318 struct drm_encoder *encoder = intel_attached_encoder(connector); 1319 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1320 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1321 enum drm_connector_status status = connector_status_connected; 1322 struct edid *edid = NULL; 1323 1324 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus); 1325 1326 /* This is only applied to SDVO cards with multiple outputs */ 1327 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1328 uint8_t saved_ddc, temp_ddc; 1329 saved_ddc = intel_sdvo->ddc_bus; 1330 temp_ddc = intel_sdvo->ddc_bus >> 1; 1331 /* 1332 * Don't use the 1 as the argument of DDC bus switch to get 1333 * the EDID. It is used for SDVO SPD ROM. 1334 */ 1335 while(temp_ddc > 1) { 1336 intel_sdvo->ddc_bus = temp_ddc; 1337 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus); 1338 if (edid) { 1339 /* 1340 * When we can get the EDID, maybe it is the 1341 * correct DDC bus. Update it. 1342 */ 1343 intel_sdvo->ddc_bus = temp_ddc; 1344 break; 1345 } 1346 temp_ddc >>= 1; 1347 } 1348 if (edid == NULL) 1349 intel_sdvo->ddc_bus = saved_ddc; 1350 } 1351 /* when there is no edid and no monitor is connected with VGA 1352 * port, try to use the CRT ddc to read the EDID for DVI-connector 1353 */ 1354 if (edid == NULL && intel_sdvo->analog_ddc_bus && 1355 !intel_analog_is_connected(connector->dev)) 1356 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus); 1357 1358 if (edid != NULL) { 1359 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1360 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK); 1361 1362 /* DDC bus is shared, match EDID to connector type */ 1363 if (is_digital && need_digital) 1364 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid); 1365 else if (is_digital != need_digital) 1366 status = connector_status_disconnected; 1367 1368 connector->display_info.raw_edid = NULL; 1369 } else 1370 status = connector_status_disconnected; 1371 1372 kfree(edid); 1373 1374 return status; 1375} 1376 1377static enum drm_connector_status 1378intel_sdvo_detect(struct drm_connector *connector, bool force) 1379{ 1380 uint16_t response; 1381 struct drm_encoder *encoder = intel_attached_encoder(connector); 1382 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1383 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1384 enum drm_connector_status ret; 1385 1386 if (!intel_sdvo_write_cmd(intel_sdvo, 1387 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) 1388 return connector_status_unknown; 1389 1390 /* add 30ms delay when the output type might be TV */ 1391 if (intel_sdvo->caps.output_flags & 1392 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0)) 1393 mdelay(30); 1394 1395 if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) 1396 return connector_status_unknown; 1397 1398 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); 1399 1400 if (response == 0) 1401 return connector_status_disconnected; 1402 1403 intel_sdvo->attached_output = response; 1404 1405 if ((intel_sdvo_connector->output_flag & response) == 0) 1406 ret = connector_status_disconnected; 1407 else if (response & SDVO_TMDS_MASK) 1408 ret = intel_sdvo_hdmi_sink_detect(connector); 1409 else 1410 ret = connector_status_connected; 1411 1412 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1413 if (ret == connector_status_connected) { 1414 intel_sdvo->is_tv = false; 1415 intel_sdvo->is_lvds = false; 1416 intel_sdvo->base.needs_tv_clock = false; 1417 1418 if (response & SDVO_TV_MASK) { 1419 intel_sdvo->is_tv = true; 1420 intel_sdvo->base.needs_tv_clock = true; 1421 } 1422 if (response & SDVO_LVDS_MASK) 1423 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1424 } 1425 1426 return ret; 1427} 1428 1429static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1430{ 1431 struct drm_encoder *encoder = intel_attached_encoder(connector); 1432 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1433 int num_modes; 1434 1435 /* set the bus switch and get the modes */ 1436 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus); 1437 1438 /* 1439 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1440 * link between analog and digital outputs. So, if the regular SDVO 1441 * DDC fails, check to see if the analog output is disconnected, in 1442 * which case we'll look there for the digital DDC data. 1443 */ 1444 if (num_modes == 0 && 1445 intel_sdvo->analog_ddc_bus && 1446 !intel_analog_is_connected(connector->dev)) { 1447 /* Switch to the analog ddc bus and try that 1448 */ 1449 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus); 1450 } 1451} 1452 1453struct drm_display_mode sdvo_tv_modes[] = { 1454 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1455 416, 0, 200, 201, 232, 233, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1457 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1458 416, 0, 240, 241, 272, 273, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1460 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1461 496, 0, 300, 301, 332, 333, 0, 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1463 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1464 736, 0, 350, 351, 382, 383, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1466 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1467 736, 0, 400, 401, 432, 433, 0, 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1469 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1470 736, 0, 480, 481, 512, 513, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1472 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1473 800, 0, 480, 481, 512, 513, 0, 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1475 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1476 800, 0, 576, 577, 608, 609, 0, 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1478 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1479 816, 0, 350, 351, 382, 383, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1481 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1482 816, 0, 400, 401, 432, 433, 0, 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1484 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1485 816, 0, 480, 481, 512, 513, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1487 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1488 816, 0, 540, 541, 572, 573, 0, 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1490 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1491 816, 0, 576, 577, 608, 609, 0, 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1493 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1494 864, 0, 576, 577, 608, 609, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1496 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1497 896, 0, 600, 601, 632, 633, 0, 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1499 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1500 928, 0, 624, 625, 656, 657, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1502 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1503 1016, 0, 766, 767, 798, 799, 0, 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1505 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1506 1120, 0, 768, 769, 800, 801, 0, 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1508 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1509 1376, 0, 1024, 1025, 1056, 1057, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1511}; 1512 1513static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1514{ 1515 struct drm_encoder *encoder = intel_attached_encoder(connector); 1516 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1517 struct intel_sdvo_sdtv_resolution_request tv_res; 1518 uint32_t reply = 0, format_map = 0; 1519 int i; 1520 1521 /* Read the list of supported input resolutions for the selected TV 1522 * format. 1523 */ 1524 format_map = 1 << intel_sdvo->tv_format_index; 1525 memcpy(&tv_res, &format_map, 1526 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1527 1528 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1529 return; 1530 1531 BUILD_BUG_ON(sizeof(tv_res) != 3); 1532 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1533 &tv_res, sizeof(tv_res))) 1534 return; 1535 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1536 return; 1537 1538 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1539 if (reply & (1 << i)) { 1540 struct drm_display_mode *nmode; 1541 nmode = drm_mode_duplicate(connector->dev, 1542 &sdvo_tv_modes[i]); 1543 if (nmode) 1544 drm_mode_probed_add(connector, nmode); 1545 } 1546} 1547 1548static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1549{ 1550 struct drm_encoder *encoder = intel_attached_encoder(connector); 1551 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1552 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1553 struct drm_display_mode *newmode; 1554 1555 /* 1556 * Attempt to get the mode list from DDC. 1557 * Assume that the preferred modes are 1558 * arranged in priority order. 1559 */ 1560 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus); 1561 if (list_empty(&connector->probed_modes) == false) 1562 goto end; 1563 1564 /* Fetch modes from VBT */ 1565 if (dev_priv->sdvo_lvds_vbt_mode != NULL) { 1566 newmode = drm_mode_duplicate(connector->dev, 1567 dev_priv->sdvo_lvds_vbt_mode); 1568 if (newmode != NULL) { 1569 /* Guarantee the mode is preferred */ 1570 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1571 DRM_MODE_TYPE_DRIVER); 1572 drm_mode_probed_add(connector, newmode); 1573 } 1574 } 1575 1576end: 1577 list_for_each_entry(newmode, &connector->probed_modes, head) { 1578 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1579 intel_sdvo->sdvo_lvds_fixed_mode = 1580 drm_mode_duplicate(connector->dev, newmode); 1581 intel_sdvo->is_lvds = true; 1582 break; 1583 } 1584 } 1585 1586} 1587 1588static int intel_sdvo_get_modes(struct drm_connector *connector) 1589{ 1590 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1591 1592 if (IS_TV(intel_sdvo_connector)) 1593 intel_sdvo_get_tv_modes(connector); 1594 else if (IS_LVDS(intel_sdvo_connector)) 1595 intel_sdvo_get_lvds_modes(connector); 1596 else 1597 intel_sdvo_get_ddc_modes(connector); 1598 1599 return !list_empty(&connector->probed_modes); 1600} 1601 1602static void 1603intel_sdvo_destroy_enhance_property(struct drm_connector *connector) 1604{ 1605 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1606 struct drm_device *dev = connector->dev; 1607 1608 if (intel_sdvo_connector->left) 1609 drm_property_destroy(dev, intel_sdvo_connector->left); 1610 if (intel_sdvo_connector->right) 1611 drm_property_destroy(dev, intel_sdvo_connector->right); 1612 if (intel_sdvo_connector->top) 1613 drm_property_destroy(dev, intel_sdvo_connector->top); 1614 if (intel_sdvo_connector->bottom) 1615 drm_property_destroy(dev, intel_sdvo_connector->bottom); 1616 if (intel_sdvo_connector->hpos) 1617 drm_property_destroy(dev, intel_sdvo_connector->hpos); 1618 if (intel_sdvo_connector->vpos) 1619 drm_property_destroy(dev, intel_sdvo_connector->vpos); 1620 if (intel_sdvo_connector->saturation) 1621 drm_property_destroy(dev, intel_sdvo_connector->saturation); 1622 if (intel_sdvo_connector->contrast) 1623 drm_property_destroy(dev, intel_sdvo_connector->contrast); 1624 if (intel_sdvo_connector->hue) 1625 drm_property_destroy(dev, intel_sdvo_connector->hue); 1626 if (intel_sdvo_connector->sharpness) 1627 drm_property_destroy(dev, intel_sdvo_connector->sharpness); 1628 if (intel_sdvo_connector->flicker_filter) 1629 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); 1630 if (intel_sdvo_connector->flicker_filter_2d) 1631 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); 1632 if (intel_sdvo_connector->flicker_filter_adaptive) 1633 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); 1634 if (intel_sdvo_connector->tv_luma_filter) 1635 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); 1636 if (intel_sdvo_connector->tv_chroma_filter) 1637 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); 1638 if (intel_sdvo_connector->dot_crawl) 1639 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); 1640 if (intel_sdvo_connector->brightness) 1641 drm_property_destroy(dev, intel_sdvo_connector->brightness); 1642} 1643 1644static void intel_sdvo_destroy(struct drm_connector *connector) 1645{ 1646 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1647 1648 if (intel_sdvo_connector->tv_format) 1649 drm_property_destroy(connector->dev, 1650 intel_sdvo_connector->tv_format); 1651 1652 intel_sdvo_destroy_enhance_property(connector); 1653 drm_sysfs_connector_remove(connector); 1654 drm_connector_cleanup(connector); 1655 kfree(connector); 1656} 1657 1658static int 1659intel_sdvo_set_property(struct drm_connector *connector, 1660 struct drm_property *property, 1661 uint64_t val) 1662{ 1663 struct drm_encoder *encoder = intel_attached_encoder(connector); 1664 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1665 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1666 uint16_t temp_value; 1667 uint8_t cmd; 1668 int ret; 1669 1670 ret = drm_connector_property_set_value(connector, property, val); 1671 if (ret) 1672 return ret; 1673 1674#define CHECK_PROPERTY(name, NAME) \ 1675 if (intel_sdvo_connector->name == property) { \ 1676 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 1677 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 1678 cmd = SDVO_CMD_SET_##NAME; \ 1679 intel_sdvo_connector->cur_##name = temp_value; \ 1680 goto set_value; \ 1681 } 1682 1683 if (property == intel_sdvo_connector->tv_format) { 1684 if (val >= TV_FORMAT_NUM) 1685 return -EINVAL; 1686 1687 if (intel_sdvo->tv_format_index == 1688 intel_sdvo_connector->tv_format_supported[val]) 1689 return 0; 1690 1691 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 1692 goto done; 1693 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 1694 temp_value = val; 1695 if (intel_sdvo_connector->left == property) { 1696 drm_connector_property_set_value(connector, 1697 intel_sdvo_connector->right, val); 1698 if (intel_sdvo_connector->left_margin == temp_value) 1699 return 0; 1700 1701 intel_sdvo_connector->left_margin = temp_value; 1702 intel_sdvo_connector->right_margin = temp_value; 1703 temp_value = intel_sdvo_connector->max_hscan - 1704 intel_sdvo_connector->left_margin; 1705 cmd = SDVO_CMD_SET_OVERSCAN_H; 1706 goto set_value; 1707 } else if (intel_sdvo_connector->right == property) { 1708 drm_connector_property_set_value(connector, 1709 intel_sdvo_connector->left, val); 1710 if (intel_sdvo_connector->right_margin == temp_value) 1711 return 0; 1712 1713 intel_sdvo_connector->left_margin = temp_value; 1714 intel_sdvo_connector->right_margin = temp_value; 1715 temp_value = intel_sdvo_connector->max_hscan - 1716 intel_sdvo_connector->left_margin; 1717 cmd = SDVO_CMD_SET_OVERSCAN_H; 1718 goto set_value; 1719 } else if (intel_sdvo_connector->top == property) { 1720 drm_connector_property_set_value(connector, 1721 intel_sdvo_connector->bottom, val); 1722 if (intel_sdvo_connector->top_margin == temp_value) 1723 return 0; 1724 1725 intel_sdvo_connector->top_margin = temp_value; 1726 intel_sdvo_connector->bottom_margin = temp_value; 1727 temp_value = intel_sdvo_connector->max_vscan - 1728 intel_sdvo_connector->top_margin; 1729 cmd = SDVO_CMD_SET_OVERSCAN_V; 1730 goto set_value; 1731 } else if (intel_sdvo_connector->bottom == property) { 1732 drm_connector_property_set_value(connector, 1733 intel_sdvo_connector->top, val); 1734 if (intel_sdvo_connector->bottom_margin == temp_value) 1735 return 0; 1736 1737 intel_sdvo_connector->top_margin = temp_value; 1738 intel_sdvo_connector->bottom_margin = temp_value; 1739 temp_value = intel_sdvo_connector->max_vscan - 1740 intel_sdvo_connector->top_margin; 1741 cmd = SDVO_CMD_SET_OVERSCAN_V; 1742 goto set_value; 1743 } 1744 CHECK_PROPERTY(hpos, HPOS) 1745 CHECK_PROPERTY(vpos, VPOS) 1746 CHECK_PROPERTY(saturation, SATURATION) 1747 CHECK_PROPERTY(contrast, CONTRAST) 1748 CHECK_PROPERTY(hue, HUE) 1749 CHECK_PROPERTY(brightness, BRIGHTNESS) 1750 CHECK_PROPERTY(sharpness, SHARPNESS) 1751 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 1752 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 1753 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 1754 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 1755 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 1756 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 1757 } 1758 1759 return -EINVAL; /* unknown property */ 1760 1761set_value: 1762 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 1763 return -EIO; 1764 1765 1766done: 1767 if (encoder->crtc) { 1768 struct drm_crtc *crtc = encoder->crtc; 1769 1770 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, 1771 crtc->y, crtc->fb); 1772 } 1773 1774 return 0; 1775#undef CHECK_PROPERTY 1776} 1777 1778static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { 1779 .dpms = intel_sdvo_dpms, 1780 .mode_fixup = intel_sdvo_mode_fixup, 1781 .prepare = intel_encoder_prepare, 1782 .mode_set = intel_sdvo_mode_set, 1783 .commit = intel_encoder_commit, 1784}; 1785 1786static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 1787 .dpms = drm_helper_connector_dpms, 1788 .detect = intel_sdvo_detect, 1789 .fill_modes = drm_helper_probe_single_connector_modes, 1790 .set_property = intel_sdvo_set_property, 1791 .destroy = intel_sdvo_destroy, 1792}; 1793 1794static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 1795 .get_modes = intel_sdvo_get_modes, 1796 .mode_valid = intel_sdvo_mode_valid, 1797 .best_encoder = intel_attached_encoder, 1798}; 1799 1800static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 1801{ 1802 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1803 1804 if (intel_sdvo->analog_ddc_bus) 1805 intel_i2c_destroy(intel_sdvo->analog_ddc_bus); 1806 1807 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 1808 drm_mode_destroy(encoder->dev, 1809 intel_sdvo->sdvo_lvds_fixed_mode); 1810 1811 intel_encoder_destroy(encoder); 1812} 1813 1814static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 1815 .destroy = intel_sdvo_enc_destroy, 1816}; 1817 1818static void 1819intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 1820{ 1821 uint16_t mask = 0; 1822 unsigned int num_bits; 1823 1824 /* Make a mask of outputs less than or equal to our own priority in the 1825 * list. 1826 */ 1827 switch (sdvo->controlled_output) { 1828 case SDVO_OUTPUT_LVDS1: 1829 mask |= SDVO_OUTPUT_LVDS1; 1830 case SDVO_OUTPUT_LVDS0: 1831 mask |= SDVO_OUTPUT_LVDS0; 1832 case SDVO_OUTPUT_TMDS1: 1833 mask |= SDVO_OUTPUT_TMDS1; 1834 case SDVO_OUTPUT_TMDS0: 1835 mask |= SDVO_OUTPUT_TMDS0; 1836 case SDVO_OUTPUT_RGB1: 1837 mask |= SDVO_OUTPUT_RGB1; 1838 case SDVO_OUTPUT_RGB0: 1839 mask |= SDVO_OUTPUT_RGB0; 1840 break; 1841 } 1842 1843 /* Count bits to find what number we are in the priority list. */ 1844 mask &= sdvo->caps.output_flags; 1845 num_bits = hweight16(mask); 1846 /* If more than 3 outputs, default to DDC bus 3 for now. */ 1847 if (num_bits > 3) 1848 num_bits = 3; 1849 1850 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 1851 sdvo->ddc_bus = 1 << num_bits; 1852} 1853 1854/** 1855 * Choose the appropriate DDC bus for control bus switch command for this 1856 * SDVO output based on the controlled output. 1857 * 1858 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 1859 * outputs, then LVDS outputs. 1860 */ 1861static void 1862intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 1863 struct intel_sdvo *sdvo, u32 reg) 1864{ 1865 struct sdvo_device_mapping *mapping; 1866 1867 if (IS_SDVOB(reg)) 1868 mapping = &(dev_priv->sdvo_mappings[0]); 1869 else 1870 mapping = &(dev_priv->sdvo_mappings[1]); 1871 1872 if (mapping->initialized) 1873 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 1874 else 1875 intel_sdvo_guess_ddc_bus(sdvo); 1876} 1877 1878static bool 1879intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device) 1880{ 1881 return intel_sdvo_set_target_output(intel_sdvo, 1882 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) && 1883 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1884 &intel_sdvo->is_hdmi, 1); 1885} 1886 1887static struct intel_sdvo * 1888intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan) 1889{ 1890 struct drm_device *dev = chan->drm_dev; 1891 struct drm_encoder *encoder; 1892 1893 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1894 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); 1895 if (intel_sdvo->base.ddc_bus == &chan->adapter) 1896 return intel_sdvo; 1897 } 1898 1899 return NULL; 1900} 1901 1902static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, 1903 struct i2c_msg msgs[], int num) 1904{ 1905 struct intel_sdvo *intel_sdvo; 1906 struct i2c_algo_bit_data *algo_data; 1907 const struct i2c_algorithm *algo; 1908 1909 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; 1910 intel_sdvo = 1911 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *) 1912 (algo_data->data)); 1913 if (intel_sdvo == NULL) 1914 return -EINVAL; 1915 1916 algo = intel_sdvo->base.i2c_bus->algo; 1917 1918 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus); 1919 return algo->master_xfer(i2c_adap, msgs, num); 1920} 1921 1922static struct i2c_algorithm intel_sdvo_i2c_bit_algo = { 1923 .master_xfer = intel_sdvo_master_xfer, 1924}; 1925 1926static u8 1927intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) 1928{ 1929 struct drm_i915_private *dev_priv = dev->dev_private; 1930 struct sdvo_device_mapping *my_mapping, *other_mapping; 1931 1932 if (IS_SDVOB(sdvo_reg)) { 1933 my_mapping = &dev_priv->sdvo_mappings[0]; 1934 other_mapping = &dev_priv->sdvo_mappings[1]; 1935 } else { 1936 my_mapping = &dev_priv->sdvo_mappings[1]; 1937 other_mapping = &dev_priv->sdvo_mappings[0]; 1938 } 1939 1940 /* If the BIOS described our SDVO device, take advantage of it. */ 1941 if (my_mapping->slave_addr) 1942 return my_mapping->slave_addr; 1943 1944 /* If the BIOS only described a different SDVO device, use the 1945 * address that it isn't using. 1946 */ 1947 if (other_mapping->slave_addr) { 1948 if (other_mapping->slave_addr == 0x70) 1949 return 0x72; 1950 else 1951 return 0x70; 1952 } 1953 1954 /* No SDVO device info is found for another DVO port, 1955 * so use mapping assumption we had before BIOS parsing. 1956 */ 1957 if (IS_SDVOB(sdvo_reg)) 1958 return 0x70; 1959 else 1960 return 0x72; 1961} 1962 1963static void 1964intel_sdvo_connector_init(struct drm_encoder *encoder, 1965 struct drm_connector *connector) 1966{ 1967 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs, 1968 connector->connector_type); 1969 1970 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs); 1971 1972 connector->interlace_allowed = 0; 1973 connector->doublescan_allowed = 0; 1974 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1975 1976 drm_mode_connector_attach_encoder(connector, encoder); 1977 drm_sysfs_connector_add(connector); 1978} 1979 1980static bool 1981intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 1982{ 1983 struct drm_encoder *encoder = &intel_sdvo->base.enc; 1984 struct drm_connector *connector; 1985 struct intel_connector *intel_connector; 1986 struct intel_sdvo_connector *intel_sdvo_connector; 1987 1988 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 1989 if (!intel_sdvo_connector) 1990 return false; 1991 1992 if (device == 0) { 1993 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 1994 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 1995 } else if (device == 1) { 1996 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 1997 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 1998 } 1999 2000 intel_connector = &intel_sdvo_connector->base; 2001 connector = &intel_connector->base; 2002 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2003 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2004 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2005 2006 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode) 2007 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device) 2008 && intel_sdvo->is_hdmi) { 2009 /* enable hdmi encoding mode if supported */ 2010 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 2011 intel_sdvo_set_colorimetry(intel_sdvo, 2012 SDVO_COLORIMETRY_RGB256); 2013 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2014 } 2015 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2016 (1 << INTEL_ANALOG_CLONE_BIT)); 2017 2018 intel_sdvo_connector_init(encoder, connector); 2019 2020 return true; 2021} 2022 2023static bool 2024intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2025{ 2026 struct drm_encoder *encoder = &intel_sdvo->base.enc; 2027 struct drm_connector *connector; 2028 struct intel_connector *intel_connector; 2029 struct intel_sdvo_connector *intel_sdvo_connector; 2030 2031 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2032 if (!intel_sdvo_connector) 2033 return false; 2034 2035 intel_connector = &intel_sdvo_connector->base; 2036 connector = &intel_connector->base; 2037 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2038 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2039 2040 intel_sdvo->controlled_output |= type; 2041 intel_sdvo_connector->output_flag = type; 2042 2043 intel_sdvo->is_tv = true; 2044 intel_sdvo->base.needs_tv_clock = true; 2045 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; 2046 2047 intel_sdvo_connector_init(encoder, connector); 2048 2049 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2050 goto err; 2051 2052 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2053 goto err; 2054 2055 return true; 2056 2057err: 2058 intel_sdvo_destroy(connector); 2059 return false; 2060} 2061 2062static bool 2063intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2064{ 2065 struct drm_encoder *encoder = &intel_sdvo->base.enc; 2066 struct drm_connector *connector; 2067 struct intel_connector *intel_connector; 2068 struct intel_sdvo_connector *intel_sdvo_connector; 2069 2070 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2071 if (!intel_sdvo_connector) 2072 return false; 2073 2074 intel_connector = &intel_sdvo_connector->base; 2075 connector = &intel_connector->base; 2076 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2077 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2078 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2079 2080 if (device == 0) { 2081 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2082 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2083 } else if (device == 1) { 2084 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2085 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2086 } 2087 2088 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2089 (1 << INTEL_ANALOG_CLONE_BIT)); 2090 2091 intel_sdvo_connector_init(encoder, connector); 2092 return true; 2093} 2094 2095static bool 2096intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2097{ 2098 struct drm_encoder *encoder = &intel_sdvo->base.enc; 2099 struct drm_connector *connector; 2100 struct intel_connector *intel_connector; 2101 struct intel_sdvo_connector *intel_sdvo_connector; 2102 2103 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2104 if (!intel_sdvo_connector) 2105 return false; 2106 2107 intel_connector = &intel_sdvo_connector->base; 2108 connector = &intel_connector->base; 2109 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2110 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2111 2112 if (device == 0) { 2113 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2114 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2115 } else if (device == 1) { 2116 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2117 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2118 } 2119 2120 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | 2121 (1 << INTEL_SDVO_LVDS_CLONE_BIT)); 2122 2123 intel_sdvo_connector_init(encoder, connector); 2124 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2125 goto err; 2126 2127 return true; 2128 2129err: 2130 intel_sdvo_destroy(connector); 2131 return false; 2132} 2133 2134static bool 2135intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2136{ 2137 intel_sdvo->is_tv = false; 2138 intel_sdvo->base.needs_tv_clock = false; 2139 intel_sdvo->is_lvds = false; 2140 2141 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2142 2143 if (flags & SDVO_OUTPUT_TMDS0) 2144 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2145 return false; 2146 2147 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2148 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2149 return false; 2150 2151 /* TV has no XXX1 function block */ 2152 if (flags & SDVO_OUTPUT_SVID0) 2153 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2154 return false; 2155 2156 if (flags & SDVO_OUTPUT_CVBS0) 2157 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2158 return false; 2159 2160 if (flags & SDVO_OUTPUT_RGB0) 2161 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2162 return false; 2163 2164 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2165 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2166 return false; 2167 2168 if (flags & SDVO_OUTPUT_LVDS0) 2169 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2170 return false; 2171 2172 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2173 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2174 return false; 2175 2176 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2177 unsigned char bytes[2]; 2178 2179 intel_sdvo->controlled_output = 0; 2180 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2181 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2182 SDVO_NAME(intel_sdvo), 2183 bytes[0], bytes[1]); 2184 return false; 2185 } 2186 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); 2187 2188 return true; 2189} 2190 2191static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2192 struct intel_sdvo_connector *intel_sdvo_connector, 2193 int type) 2194{ 2195 struct drm_device *dev = intel_sdvo->base.enc.dev; 2196 struct intel_sdvo_tv_format format; 2197 uint32_t format_map, i; 2198 2199 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2200 return false; 2201 2202 if (!intel_sdvo_get_value(intel_sdvo, 2203 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2204 &format, sizeof(format))) 2205 return false; 2206 2207 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2208 2209 if (format_map == 0) 2210 return false; 2211 2212 intel_sdvo_connector->format_supported_num = 0; 2213 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2214 if (format_map & (1 << i)) 2215 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2216 2217 2218 intel_sdvo_connector->tv_format = 2219 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2220 "mode", intel_sdvo_connector->format_supported_num); 2221 if (!intel_sdvo_connector->tv_format) 2222 return false; 2223 2224 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2225 drm_property_add_enum( 2226 intel_sdvo_connector->tv_format, i, 2227 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2228 2229 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2230 drm_connector_attach_property(&intel_sdvo_connector->base.base, 2231 intel_sdvo_connector->tv_format, 0); 2232 return true; 2233 2234} 2235 2236#define ENHANCEMENT(name, NAME) do { \ 2237 if (enhancements.name) { \ 2238 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2239 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2240 return false; \ 2241 intel_sdvo_connector->max_##name = data_value[0]; \ 2242 intel_sdvo_connector->cur_##name = response; \ 2243 intel_sdvo_connector->name = \ 2244 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \ 2245 if (!intel_sdvo_connector->name) return false; \ 2246 intel_sdvo_connector->name->values[0] = 0; \ 2247 intel_sdvo_connector->name->values[1] = data_value[0]; \ 2248 drm_connector_attach_property(connector, \ 2249 intel_sdvo_connector->name, \ 2250 intel_sdvo_connector->cur_##name); \ 2251 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2252 data_value[0], data_value[1], response); \ 2253 } \ 2254} while(0) 2255 2256static bool 2257intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2258 struct intel_sdvo_connector *intel_sdvo_connector, 2259 struct intel_sdvo_enhancements_reply enhancements) 2260{ 2261 struct drm_device *dev = intel_sdvo->base.enc.dev; 2262 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2263 uint16_t response, data_value[2]; 2264 2265 /* when horizontal overscan is supported, Add the left/right property */ 2266 if (enhancements.overscan_h) { 2267 if (!intel_sdvo_get_value(intel_sdvo, 2268 SDVO_CMD_GET_MAX_OVERSCAN_H, 2269 &data_value, 4)) 2270 return false; 2271 2272 if (!intel_sdvo_get_value(intel_sdvo, 2273 SDVO_CMD_GET_OVERSCAN_H, 2274 &response, 2)) 2275 return false; 2276 2277 intel_sdvo_connector->max_hscan = data_value[0]; 2278 intel_sdvo_connector->left_margin = data_value[0] - response; 2279 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2280 intel_sdvo_connector->left = 2281 drm_property_create(dev, DRM_MODE_PROP_RANGE, 2282 "left_margin", 2); 2283 if (!intel_sdvo_connector->left) 2284 return false; 2285 2286 intel_sdvo_connector->left->values[0] = 0; 2287 intel_sdvo_connector->left->values[1] = data_value[0]; 2288 drm_connector_attach_property(connector, 2289 intel_sdvo_connector->left, 2290 intel_sdvo_connector->left_margin); 2291 2292 intel_sdvo_connector->right = 2293 drm_property_create(dev, DRM_MODE_PROP_RANGE, 2294 "right_margin", 2); 2295 if (!intel_sdvo_connector->right) 2296 return false; 2297 2298 intel_sdvo_connector->right->values[0] = 0; 2299 intel_sdvo_connector->right->values[1] = data_value[0]; 2300 drm_connector_attach_property(connector, 2301 intel_sdvo_connector->right, 2302 intel_sdvo_connector->right_margin); 2303 DRM_DEBUG_KMS("h_overscan: max %d, " 2304 "default %d, current %d\n", 2305 data_value[0], data_value[1], response); 2306 } 2307 2308 if (enhancements.overscan_v) { 2309 if (!intel_sdvo_get_value(intel_sdvo, 2310 SDVO_CMD_GET_MAX_OVERSCAN_V, 2311 &data_value, 4)) 2312 return false; 2313 2314 if (!intel_sdvo_get_value(intel_sdvo, 2315 SDVO_CMD_GET_OVERSCAN_V, 2316 &response, 2)) 2317 return false; 2318 2319 intel_sdvo_connector->max_vscan = data_value[0]; 2320 intel_sdvo_connector->top_margin = data_value[0] - response; 2321 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2322 intel_sdvo_connector->top = 2323 drm_property_create(dev, DRM_MODE_PROP_RANGE, 2324 "top_margin", 2); 2325 if (!intel_sdvo_connector->top) 2326 return false; 2327 2328 intel_sdvo_connector->top->values[0] = 0; 2329 intel_sdvo_connector->top->values[1] = data_value[0]; 2330 drm_connector_attach_property(connector, 2331 intel_sdvo_connector->top, 2332 intel_sdvo_connector->top_margin); 2333 2334 intel_sdvo_connector->bottom = 2335 drm_property_create(dev, DRM_MODE_PROP_RANGE, 2336 "bottom_margin", 2); 2337 if (!intel_sdvo_connector->bottom) 2338 return false; 2339 2340 intel_sdvo_connector->bottom->values[0] = 0; 2341 intel_sdvo_connector->bottom->values[1] = data_value[0]; 2342 drm_connector_attach_property(connector, 2343 intel_sdvo_connector->bottom, 2344 intel_sdvo_connector->bottom_margin); 2345 DRM_DEBUG_KMS("v_overscan: max %d, " 2346 "default %d, current %d\n", 2347 data_value[0], data_value[1], response); 2348 } 2349 2350 ENHANCEMENT(hpos, HPOS); 2351 ENHANCEMENT(vpos, VPOS); 2352 ENHANCEMENT(saturation, SATURATION); 2353 ENHANCEMENT(contrast, CONTRAST); 2354 ENHANCEMENT(hue, HUE); 2355 ENHANCEMENT(sharpness, SHARPNESS); 2356 ENHANCEMENT(brightness, BRIGHTNESS); 2357 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2358 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2359 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2360 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2361 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2362 2363 if (enhancements.dot_crawl) { 2364 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2365 return false; 2366 2367 intel_sdvo_connector->max_dot_crawl = 1; 2368 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2369 intel_sdvo_connector->dot_crawl = 2370 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2); 2371 if (!intel_sdvo_connector->dot_crawl) 2372 return false; 2373 2374 intel_sdvo_connector->dot_crawl->values[0] = 0; 2375 intel_sdvo_connector->dot_crawl->values[1] = 1; 2376 drm_connector_attach_property(connector, 2377 intel_sdvo_connector->dot_crawl, 2378 intel_sdvo_connector->cur_dot_crawl); 2379 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2380 } 2381 2382 return true; 2383} 2384 2385static bool 2386intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2387 struct intel_sdvo_connector *intel_sdvo_connector, 2388 struct intel_sdvo_enhancements_reply enhancements) 2389{ 2390 struct drm_device *dev = intel_sdvo->base.enc.dev; 2391 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2392 uint16_t response, data_value[2]; 2393 2394 ENHANCEMENT(brightness, BRIGHTNESS); 2395 2396 return true; 2397} 2398#undef ENHANCEMENT 2399 2400static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2401 struct intel_sdvo_connector *intel_sdvo_connector) 2402{ 2403 union { 2404 struct intel_sdvo_enhancements_reply reply; 2405 uint16_t response; 2406 } enhancements; 2407 2408 enhancements.response = 0; 2409 intel_sdvo_get_value(intel_sdvo, 2410 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2411 &enhancements, sizeof(enhancements)); 2412 if (enhancements.response == 0) { 2413 DRM_DEBUG_KMS("No enhancement is supported\n"); 2414 return true; 2415 } 2416 2417 if (IS_TV(intel_sdvo_connector)) 2418 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2419 else if(IS_LVDS(intel_sdvo_connector)) 2420 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2421 else 2422 return true; 2423 2424} 2425 2426bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) 2427{ 2428 struct drm_i915_private *dev_priv = dev->dev_private; 2429 struct intel_encoder *intel_encoder; 2430 struct intel_sdvo *intel_sdvo; 2431 u8 ch[0x40]; 2432 int i; 2433 u32 i2c_reg, ddc_reg, analog_ddc_reg; 2434 2435 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); 2436 if (!intel_sdvo) 2437 return false; 2438 2439 intel_sdvo->sdvo_reg = sdvo_reg; 2440 2441 intel_encoder = &intel_sdvo->base; 2442 intel_encoder->type = INTEL_OUTPUT_SDVO; 2443 2444 if (HAS_PCH_SPLIT(dev)) { 2445 i2c_reg = PCH_GPIOE; 2446 ddc_reg = PCH_GPIOE; 2447 analog_ddc_reg = PCH_GPIOA; 2448 } else { 2449 i2c_reg = GPIOE; 2450 ddc_reg = GPIOE; 2451 analog_ddc_reg = GPIOA; 2452 } 2453 2454 /* setup the DDC bus. */ 2455 if (IS_SDVOB(sdvo_reg)) 2456 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB"); 2457 else 2458 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC"); 2459 2460 if (!intel_encoder->i2c_bus) 2461 goto err_inteloutput; 2462 2463 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); 2464 2465 /* Save the bit-banging i2c functionality for use by the DDC wrapper */ 2466 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality; 2467 2468 /* Read the regs to test if we can talk to the device */ 2469 for (i = 0; i < 0x40; i++) { 2470 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) { 2471 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", 2472 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2473 goto err_i2c; 2474 } 2475 } 2476 2477 /* setup the DDC bus. */ 2478 if (IS_SDVOB(sdvo_reg)) { 2479 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS"); 2480 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, 2481 "SDVOB/VGA DDC BUS"); 2482 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; 2483 } else { 2484 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS"); 2485 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, 2486 "SDVOC/VGA DDC BUS"); 2487 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; 2488 } 2489 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL) 2490 goto err_i2c; 2491 2492 /* Wrap with our custom algo which switches to DDC mode */ 2493 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo; 2494 2495 /* encoder type will be decided later */ 2496 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0); 2497 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs); 2498 2499 /* In default case sdvo lvds is false */ 2500 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 2501 goto err_enc; 2502 2503 if (intel_sdvo_output_setup(intel_sdvo, 2504 intel_sdvo->caps.output_flags) != true) { 2505 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", 2506 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2507 goto err_enc; 2508 } 2509 2510 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 2511 2512 /* Set the input timing to the screen. Assume always input 0. */ 2513 if (!intel_sdvo_set_target_input(intel_sdvo)) 2514 goto err_enc; 2515 2516 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 2517 &intel_sdvo->pixel_clock_min, 2518 &intel_sdvo->pixel_clock_max)) 2519 goto err_enc; 2520 2521 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 2522 "clock range %dMHz - %dMHz, " 2523 "input 1: %c, input 2: %c, " 2524 "output 1: %c, output 2: %c\n", 2525 SDVO_NAME(intel_sdvo), 2526 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 2527 intel_sdvo->caps.device_rev_id, 2528 intel_sdvo->pixel_clock_min / 1000, 2529 intel_sdvo->pixel_clock_max / 1000, 2530 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 2531 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 2532 /* check currently supported outputs */ 2533 intel_sdvo->caps.output_flags & 2534 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 2535 intel_sdvo->caps.output_flags & 2536 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 2537 return true; 2538 2539err_enc: 2540 drm_encoder_cleanup(&intel_encoder->enc); 2541err_i2c: 2542 if (intel_sdvo->analog_ddc_bus != NULL) 2543 intel_i2c_destroy(intel_sdvo->analog_ddc_bus); 2544 if (intel_encoder->ddc_bus != NULL) 2545 intel_i2c_destroy(intel_encoder->ddc_bus); 2546 if (intel_encoder->i2c_bus != NULL) 2547 intel_i2c_destroy(intel_encoder->i2c_bus); 2548err_inteloutput: 2549 kfree(intel_sdvo); 2550 2551 return false; 2552} 2553