1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef _I915_REG_H_ 26#define _I915_REG_H_ 27 28/* 29 * The Bridge device's PCI config space has information about the 30 * fb aperture size and the amount of pre-reserved memory. 31 */ 32#define INTEL_GMCH_CTRL 0x52 33#define INTEL_GMCH_VGA_DISABLE (1 << 1) 34#define INTEL_GMCH_ENABLED 0x4 35#define INTEL_GMCH_MEM_MASK 0x1 36#define INTEL_GMCH_MEM_64M 0x1 37#define INTEL_GMCH_MEM_128M 0 38 39#define INTEL_GMCH_GMS_MASK (0xf << 4) 40#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) 41#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) 42#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) 43#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) 44#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) 45#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) 46 47#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) 48#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) 49#define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4) 50#define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4) 51#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 52#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 53#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 54#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 55 56#define SNB_GMCH_CTRL 0x50 57#define SNB_GMCH_GMS_STOLEN_MASK 0xF8 58#define SNB_GMCH_GMS_STOLEN_32M (1 << 3) 59#define SNB_GMCH_GMS_STOLEN_64M (2 << 3) 60#define SNB_GMCH_GMS_STOLEN_96M (3 << 3) 61#define SNB_GMCH_GMS_STOLEN_128M (4 << 3) 62#define SNB_GMCH_GMS_STOLEN_160M (5 << 3) 63#define SNB_GMCH_GMS_STOLEN_192M (6 << 3) 64#define SNB_GMCH_GMS_STOLEN_224M (7 << 3) 65#define SNB_GMCH_GMS_STOLEN_256M (8 << 3) 66#define SNB_GMCH_GMS_STOLEN_288M (9 << 3) 67#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) 68#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) 69#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) 70#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) 71#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) 72#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) 73#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) 74 75/* PCI config space */ 76 77#define HPLLCC 0xc0 /* 855 only */ 78#define GC_CLOCK_CONTROL_MASK (0xf << 0) 79#define GC_CLOCK_133_200 (0 << 0) 80#define GC_CLOCK_100_200 (1 << 0) 81#define GC_CLOCK_100_133 (2 << 0) 82#define GC_CLOCK_166_250 (3 << 0) 83#define GCFGC2 0xda 84#define GCFGC 0xf0 /* 915+ only */ 85#define GC_LOW_FREQUENCY_ENABLE (1 << 7) 86#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 87#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 88#define GC_DISPLAY_CLOCK_MASK (7 << 4) 89#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 90#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 91#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 92#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 93#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 94#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 95#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 96#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 97#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 98#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 99#define I945_GC_RENDER_CLOCK_MASK (7 << 0) 100#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 101#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 102#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 103#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 104#define I915_GC_RENDER_CLOCK_MASK (7 << 0) 105#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 106#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 107#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 108#define LBB 0xf4 109#define GDRST 0xc0 110#define GDRST_FULL (0<<2) 111#define GDRST_RENDER (1<<2) 112#define GDRST_MEDIA (3<<2) 113 114/* VGA stuff */ 115 116#define VGA_ST01_MDA 0x3ba 117#define VGA_ST01_CGA 0x3da 118 119#define VGA_MSR_WRITE 0x3c2 120#define VGA_MSR_READ 0x3cc 121#define VGA_MSR_MEM_EN (1<<1) 122#define VGA_MSR_CGA_MODE (1<<0) 123 124#define VGA_SR_INDEX 0x3c4 125#define VGA_SR_DATA 0x3c5 126 127#define VGA_AR_INDEX 0x3c0 128#define VGA_AR_VID_EN (1<<5) 129#define VGA_AR_DATA_WRITE 0x3c0 130#define VGA_AR_DATA_READ 0x3c1 131 132#define VGA_GR_INDEX 0x3ce 133#define VGA_GR_DATA 0x3cf 134/* GR05 */ 135#define VGA_GR_MEM_READ_MODE_SHIFT 3 136#define VGA_GR_MEM_READ_MODE_PLANE 1 137/* GR06 */ 138#define VGA_GR_MEM_MODE_MASK 0xc 139#define VGA_GR_MEM_MODE_SHIFT 2 140#define VGA_GR_MEM_A0000_AFFFF 0 141#define VGA_GR_MEM_A0000_BFFFF 1 142#define VGA_GR_MEM_B0000_B7FFF 2 143#define VGA_GR_MEM_B0000_BFFFF 3 144 145#define VGA_DACMASK 0x3c6 146#define VGA_DACRX 0x3c7 147#define VGA_DACWX 0x3c8 148#define VGA_DACDATA 0x3c9 149 150#define VGA_CR_INDEX_MDA 0x3b4 151#define VGA_CR_DATA_MDA 0x3b5 152#define VGA_CR_INDEX_CGA 0x3d4 153#define VGA_CR_DATA_CGA 0x3d5 154 155/* 156 * Memory interface instructions used by the kernel 157 */ 158#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 159 160#define MI_NOOP MI_INSTR(0, 0) 161#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 162#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 163#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 164#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 165#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 166#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 167#define MI_FLUSH MI_INSTR(0x04, 0) 168#define MI_READ_FLUSH (1 << 0) 169#define MI_EXE_FLUSH (1 << 1) 170#define MI_NO_WRITE_FLUSH (1 << 2) 171#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 172#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 173#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 174#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 175#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 176#define MI_OVERLAY_FLIP MI_INSTR(0x11,0) 177#define MI_OVERLAY_CONTINUE (0x0<<21) 178#define MI_OVERLAY_ON (0x1<<21) 179#define MI_OVERLAY_OFF (0x2<<21) 180#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 181#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 182#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 183#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 184#define MI_SET_CONTEXT MI_INSTR(0x18, 0) 185#define MI_MM_SPACE_GTT (1<<8) 186#define MI_MM_SPACE_PHYSICAL (0<<8) 187#define MI_SAVE_EXT_STATE_EN (1<<3) 188#define MI_RESTORE_EXT_STATE_EN (1<<2) 189#define MI_RESTORE_INHIBIT (1<<0) 190#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 191#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 192#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 193#define MI_STORE_DWORD_INDEX_SHIFT 2 194#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) 195#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 196#define MI_BATCH_NON_SECURE (1) 197#define MI_BATCH_NON_SECURE_I965 (1<<8) 198#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 199 200/* 201 * 3D instructions used by the kernel 202 */ 203#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 204 205#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 206#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 207#define SC_UPDATE_SCISSOR (0x1<<1) 208#define SC_ENABLE_MASK (0x1<<0) 209#define SC_ENABLE (0x1<<0) 210#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 211#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 212#define SCI_YMIN_MASK (0xffff<<16) 213#define SCI_XMIN_MASK (0xffff<<0) 214#define SCI_YMAX_MASK (0xffff<<16) 215#define SCI_XMAX_MASK (0xffff<<0) 216#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 217#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 218#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 219#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 220#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 221#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 222#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 223#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 224#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 225#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 226#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 227#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 228#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 229#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 230#define BLT_DEPTH_8 (0<<24) 231#define BLT_DEPTH_16_565 (1<<24) 232#define BLT_DEPTH_16_1555 (2<<24) 233#define BLT_DEPTH_32 (3<<24) 234#define BLT_ROP_GXCOPY (0xcc<<16) 235#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 236#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 237#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 238#define ASYNC_FLIP (1<<22) 239#define DISPLAY_PLANE_A (0<<20) 240#define DISPLAY_PLANE_B (1<<20) 241#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) 242#define PIPE_CONTROL_QW_WRITE (1<<14) 243#define PIPE_CONTROL_DEPTH_STALL (1<<13) 244#define PIPE_CONTROL_WC_FLUSH (1<<12) 245#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */ 246#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */ 247#define PIPE_CONTROL_ISP_DIS (1<<9) 248#define PIPE_CONTROL_NOTIFY (1<<8) 249#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 250#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ 251 252/* 253 * Fence registers 254 */ 255#define FENCE_REG_830_0 0x2000 256#define FENCE_REG_945_8 0x3000 257#define I830_FENCE_START_MASK 0x07f80000 258#define I830_FENCE_TILING_Y_SHIFT 12 259#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 260#define I830_FENCE_PITCH_SHIFT 4 261#define I830_FENCE_REG_VALID (1<<0) 262#define I915_FENCE_MAX_PITCH_VAL 4 263#define I830_FENCE_MAX_PITCH_VAL 6 264#define I830_FENCE_MAX_SIZE_VAL (1<<8) 265 266#define I915_FENCE_START_MASK 0x0ff00000 267#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 268 269#define FENCE_REG_965_0 0x03000 270#define I965_FENCE_PITCH_SHIFT 2 271#define I965_FENCE_TILING_Y_SHIFT 1 272#define I965_FENCE_REG_VALID (1<<0) 273#define I965_FENCE_MAX_PITCH_VAL 0x0400 274 275#define FENCE_REG_SANDYBRIDGE_0 0x100000 276#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 277 278/* 279 * Instruction and interrupt control regs 280 */ 281#define PGTBL_ER 0x02024 282#define PRB0_TAIL 0x02030 283#define PRB0_HEAD 0x02034 284#define PRB0_START 0x02038 285#define PRB0_CTL 0x0203c 286#define TAIL_ADDR 0x001FFFF8 287#define HEAD_WRAP_COUNT 0xFFE00000 288#define HEAD_WRAP_ONE 0x00200000 289#define HEAD_ADDR 0x001FFFFC 290#define RING_NR_PAGES 0x001FF000 291#define RING_REPORT_MASK 0x00000006 292#define RING_REPORT_64K 0x00000002 293#define RING_REPORT_128K 0x00000004 294#define RING_NO_REPORT 0x00000000 295#define RING_VALID_MASK 0x00000001 296#define RING_VALID 0x00000001 297#define RING_INVALID 0x00000000 298#define PRB1_TAIL 0x02040 /* 915+ only */ 299#define PRB1_HEAD 0x02044 /* 915+ only */ 300#define PRB1_START 0x02048 /* 915+ only */ 301#define PRB1_CTL 0x0204c /* 915+ only */ 302#define IPEIR_I965 0x02064 303#define IPEHR_I965 0x02068 304#define INSTDONE_I965 0x0206c 305#define INSTPS 0x02070 /* 965+ only */ 306#define INSTDONE1 0x0207c /* 965+ only */ 307#define ACTHD_I965 0x02074 308#define HWS_PGA 0x02080 309#define HWS_PGA_GEN6 0x04080 310#define HWS_ADDRESS_MASK 0xfffff000 311#define HWS_START_ADDRESS_SHIFT 4 312#define PWRCTXA 0x2088 /* 965GM+ only */ 313#define PWRCTX_EN (1<<0) 314#define IPEIR 0x02088 315#define IPEHR 0x0208c 316#define INSTDONE 0x02090 317#define NOPID 0x02094 318#define HWSTAM 0x02098 319 320#define MI_MODE 0x0209c 321# define VS_TIMER_DISPATCH (1 << 6) 322# define MI_FLUSH_ENABLE (1 << 11) 323 324#define SCPD0 0x0209c /* 915+ only */ 325#define IER 0x020a0 326#define IIR 0x020a4 327#define IMR 0x020a8 328#define ISR 0x020ac 329#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 330#define I915_DISPLAY_PORT_INTERRUPT (1<<17) 331#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 332#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 333#define I915_HWB_OOM_INTERRUPT (1<<13) 334#define I915_SYNC_STATUS_INTERRUPT (1<<12) 335#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 336#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 337#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 338#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 339#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 340#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 341#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 342#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 343#define I915_DEBUG_INTERRUPT (1<<2) 344#define I915_USER_INTERRUPT (1<<1) 345#define I915_ASLE_INTERRUPT (1<<0) 346#define I915_BSD_USER_INTERRUPT (1<<25) 347#define EIR 0x020b0 348#define EMR 0x020b4 349#define ESR 0x020b8 350#define GM45_ERROR_PAGE_TABLE (1<<5) 351#define GM45_ERROR_MEM_PRIV (1<<4) 352#define I915_ERROR_PAGE_TABLE (1<<4) 353#define GM45_ERROR_CP_PRIV (1<<3) 354#define I915_ERROR_MEMORY_REFRESH (1<<1) 355#define I915_ERROR_INSTRUCTION (1<<0) 356#define INSTPM 0x020c0 357#define INSTPM_SELF_EN (1<<12) /* 915GM only */ 358#define ACTHD 0x020c8 359#define FW_BLC 0x020d8 360#define FW_BLC2 0x020dc 361#define FW_BLC_SELF 0x020e0 /* 915+ only */ 362#define FW_BLC_SELF_EN_MASK (1<<31) 363#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 364#define FW_BLC_SELF_EN (1<<15) /* 945 only */ 365#define MM_BURST_LENGTH 0x00700000 366#define MM_FIFO_WATERMARK 0x0001F000 367#define LM_BURST_LENGTH 0x00000700 368#define LM_FIFO_WATERMARK 0x0000001F 369#define MI_ARB_STATE 0x020e4 /* 915+ only */ 370#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ 371 372/* Make render/texture TLB fetches lower priorty than associated data 373 * fetches. This is not turned on by default 374 */ 375#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 376 377/* Isoch request wait on GTT enable (Display A/B/C streams). 378 * Make isoch requests stall on the TLB update. May cause 379 * display underruns (test mode only) 380 */ 381#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 382 383/* Block grant count for isoch requests when block count is 384 * set to a finite value. 385 */ 386#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 387#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 388#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 389#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 390#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 391 392/* Enable render writes to complete in C2/C3/C4 power states. 393 * If this isn't enabled, render writes are prevented in low 394 * power states. That seems bad to me. 395 */ 396#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 397 398/* This acknowledges an async flip immediately instead 399 * of waiting for 2TLB fetches. 400 */ 401#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 402 403/* Enables non-sequential data reads through arbiter 404 */ 405#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 406 407/* Disable FSB snooping of cacheable write cycles from binner/render 408 * command stream 409 */ 410#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 411 412/* Arbiter time slice for non-isoch streams */ 413#define MI_ARB_TIME_SLICE_MASK (7 << 5) 414#define MI_ARB_TIME_SLICE_1 (0 << 5) 415#define MI_ARB_TIME_SLICE_2 (1 << 5) 416#define MI_ARB_TIME_SLICE_4 (2 << 5) 417#define MI_ARB_TIME_SLICE_6 (3 << 5) 418#define MI_ARB_TIME_SLICE_8 (4 << 5) 419#define MI_ARB_TIME_SLICE_10 (5 << 5) 420#define MI_ARB_TIME_SLICE_14 (6 << 5) 421#define MI_ARB_TIME_SLICE_16 (7 << 5) 422 423/* Low priority grace period page size */ 424#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 425#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 426 427/* Disable display A/B trickle feed */ 428#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 429 430/* Set display plane priority */ 431#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 432#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 433 434#define CACHE_MODE_0 0x02120 /* 915+ only */ 435#define CM0_MASK_SHIFT 16 436#define CM0_IZ_OPT_DISABLE (1<<6) 437#define CM0_ZR_OPT_DISABLE (1<<5) 438#define CM0_DEPTH_EVICT_DISABLE (1<<4) 439#define CM0_COLOR_EVICT_DISABLE (1<<3) 440#define CM0_DEPTH_WRITE_DISABLE (1<<1) 441#define CM0_RC_OP_FLUSH_DISABLE (1<<0) 442#define BB_ADDR 0x02140 /* 8 bytes */ 443#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 444#define ECOSKPD 0x021d0 445#define ECO_GATING_CX_ONLY (1<<3) 446#define ECO_FLIP_DONE (1<<0) 447 448/* GEN6 interrupt control */ 449#define GEN6_RENDER_HWSTAM 0x2098 450#define GEN6_RENDER_IMR 0x20a8 451#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) 452#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) 453#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) 454#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) 455#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) 456#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) 457#define GEN6_RENDER_SYNC_STATUS (1 << 2) 458#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) 459#define GEN6_RENDER_USER_INTERRUPT (1 << 0) 460 461#define GEN6_BLITTER_HWSTAM 0x22098 462#define GEN6_BLITTER_IMR 0x220a8 463#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) 464#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 465#define GEN6_BLITTER_SYNC_STATUS (1 << 24) 466#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 467/* 468 * BSD (bit stream decoder instruction and interrupt control register defines 469 * (G4X and Ironlake only) 470 */ 471 472#define BSD_RING_TAIL 0x04030 473#define BSD_RING_HEAD 0x04034 474#define BSD_RING_START 0x04038 475#define BSD_RING_CTL 0x0403c 476#define BSD_RING_ACTHD 0x04074 477#define BSD_HWS_PGA 0x04080 478 479/* 480 * Framebuffer compression (915+ only) 481 */ 482 483#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 484#define FBC_LL_BASE 0x03204 /* 4k page aligned */ 485#define FBC_CONTROL 0x03208 486#define FBC_CTL_EN (1<<31) 487#define FBC_CTL_PERIODIC (1<<30) 488#define FBC_CTL_INTERVAL_SHIFT (16) 489#define FBC_CTL_UNCOMPRESSIBLE (1<<14) 490#define FBC_CTL_C3_IDLE (1<<13) 491#define FBC_CTL_STRIDE_SHIFT (5) 492#define FBC_CTL_FENCENO (1<<0) 493#define FBC_COMMAND 0x0320c 494#define FBC_CMD_COMPRESS (1<<0) 495#define FBC_STATUS 0x03210 496#define FBC_STAT_COMPRESSING (1<<31) 497#define FBC_STAT_COMPRESSED (1<<30) 498#define FBC_STAT_MODIFIED (1<<29) 499#define FBC_STAT_CURRENT_LINE (1<<0) 500#define FBC_CONTROL2 0x03214 501#define FBC_CTL_FENCE_DBL (0<<4) 502#define FBC_CTL_IDLE_IMM (0<<2) 503#define FBC_CTL_IDLE_FULL (1<<2) 504#define FBC_CTL_IDLE_LINE (2<<2) 505#define FBC_CTL_IDLE_DEBUG (3<<2) 506#define FBC_CTL_CPU_FENCE (1<<1) 507#define FBC_CTL_PLANEA (0<<0) 508#define FBC_CTL_PLANEB (1<<0) 509#define FBC_FENCE_OFF 0x0321b 510#define FBC_TAG 0x03300 511 512#define FBC_LL_SIZE (1536) 513 514/* Framebuffer compression for GM45+ */ 515#define DPFC_CB_BASE 0x3200 516#define DPFC_CONTROL 0x3208 517#define DPFC_CTL_EN (1<<31) 518#define DPFC_CTL_PLANEA (0<<30) 519#define DPFC_CTL_PLANEB (1<<30) 520#define DPFC_CTL_FENCE_EN (1<<29) 521#define DPFC_SR_EN (1<<10) 522#define DPFC_CTL_LIMIT_1X (0<<6) 523#define DPFC_CTL_LIMIT_2X (1<<6) 524#define DPFC_CTL_LIMIT_4X (2<<6) 525#define DPFC_RECOMP_CTL 0x320c 526#define DPFC_RECOMP_STALL_EN (1<<27) 527#define DPFC_RECOMP_STALL_WM_SHIFT (16) 528#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 529#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 530#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 531#define DPFC_STATUS 0x3210 532#define DPFC_INVAL_SEG_SHIFT (16) 533#define DPFC_INVAL_SEG_MASK (0x07ff0000) 534#define DPFC_COMP_SEG_SHIFT (0) 535#define DPFC_COMP_SEG_MASK (0x000003ff) 536#define DPFC_STATUS2 0x3214 537#define DPFC_FENCE_YOFF 0x3218 538#define DPFC_CHICKEN 0x3224 539#define DPFC_HT_MODIFY (1<<31) 540 541/* Framebuffer compression for Ironlake */ 542#define ILK_DPFC_CB_BASE 0x43200 543#define ILK_DPFC_CONTROL 0x43208 544/* The bit 28-8 is reserved */ 545#define DPFC_RESERVED (0x1FFFFF00) 546#define ILK_DPFC_RECOMP_CTL 0x4320c 547#define ILK_DPFC_STATUS 0x43210 548#define ILK_DPFC_FENCE_YOFF 0x43218 549#define ILK_DPFC_CHICKEN 0x43224 550#define ILK_FBC_RT_BASE 0x2128 551#define ILK_FBC_RT_VALID (1<<0) 552 553#define ILK_DISPLAY_CHICKEN1 0x42000 554#define ILK_FBCQ_DIS (1<<22) 555 556/* 557 * GPIO regs 558 */ 559#define GPIOA 0x5010 560#define GPIOB 0x5014 561#define GPIOC 0x5018 562#define GPIOD 0x501c 563#define GPIOE 0x5020 564#define GPIOF 0x5024 565#define GPIOG 0x5028 566#define GPIOH 0x502c 567# define GPIO_CLOCK_DIR_MASK (1 << 0) 568# define GPIO_CLOCK_DIR_IN (0 << 1) 569# define GPIO_CLOCK_DIR_OUT (1 << 1) 570# define GPIO_CLOCK_VAL_MASK (1 << 2) 571# define GPIO_CLOCK_VAL_OUT (1 << 3) 572# define GPIO_CLOCK_VAL_IN (1 << 4) 573# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 574# define GPIO_DATA_DIR_MASK (1 << 8) 575# define GPIO_DATA_DIR_IN (0 << 9) 576# define GPIO_DATA_DIR_OUT (1 << 9) 577# define GPIO_DATA_VAL_MASK (1 << 10) 578# define GPIO_DATA_VAL_OUT (1 << 11) 579# define GPIO_DATA_VAL_IN (1 << 12) 580# define GPIO_DATA_PULLUP_DISABLE (1 << 13) 581 582#define GMBUS0 0x5100 583#define GMBUS1 0x5104 584#define GMBUS2 0x5108 585#define GMBUS3 0x510c 586#define GMBUS4 0x5110 587#define GMBUS5 0x5120 588 589/* 590 * Clock control & power management 591 */ 592 593#define VGA0 0x6000 594#define VGA1 0x6004 595#define VGA_PD 0x6010 596#define VGA0_PD_P2_DIV_4 (1 << 7) 597#define VGA0_PD_P1_DIV_2 (1 << 5) 598#define VGA0_PD_P1_SHIFT 0 599#define VGA0_PD_P1_MASK (0x1f << 0) 600#define VGA1_PD_P2_DIV_4 (1 << 15) 601#define VGA1_PD_P1_DIV_2 (1 << 13) 602#define VGA1_PD_P1_SHIFT 8 603#define VGA1_PD_P1_MASK (0x1f << 8) 604#define DPLL_A 0x06014 605#define DPLL_B 0x06018 606#define DPLL_VCO_ENABLE (1 << 31) 607#define DPLL_DVO_HIGH_SPEED (1 << 30) 608#define DPLL_SYNCLOCK_ENABLE (1 << 29) 609#define DPLL_VGA_MODE_DIS (1 << 28) 610#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 611#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 612#define DPLL_MODE_MASK (3 << 26) 613#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 614#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 615#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 616#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 617#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 618#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 619#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 620 621#define SRX_INDEX 0x3c4 622#define SRX_DATA 0x3c5 623#define SR01 1 624#define SR01_SCREEN_OFF (1<<5) 625 626#define PPCR 0x61204 627#define PPCR_ON (1<<0) 628 629#define DVOB 0x61140 630#define DVOB_ON (1<<31) 631#define DVOC 0x61160 632#define DVOC_ON (1<<31) 633#define LVDS 0x61180 634#define LVDS_ON (1<<31) 635 636#define ADPA 0x61100 637#define ADPA_DPMS_MASK (~(3<<10)) 638#define ADPA_DPMS_ON (0<<10) 639#define ADPA_DPMS_SUSPEND (1<<10) 640#define ADPA_DPMS_STANDBY (2<<10) 641#define ADPA_DPMS_OFF (3<<10) 642 643#define RING_TAIL 0x00 644#define TAIL_ADDR 0x001FFFF8 645#define RING_HEAD 0x04 646#define HEAD_WRAP_COUNT 0xFFE00000 647#define HEAD_WRAP_ONE 0x00200000 648#define HEAD_ADDR 0x001FFFFC 649#define RING_START 0x08 650#define START_ADDR 0xFFFFF000 651#define RING_LEN 0x0C 652#define RING_NR_PAGES 0x001FF000 653#define RING_REPORT_MASK 0x00000006 654#define RING_REPORT_64K 0x00000002 655#define RING_REPORT_128K 0x00000004 656#define RING_NO_REPORT 0x00000000 657#define RING_VALID_MASK 0x00000001 658#define RING_VALID 0x00000001 659#define RING_INVALID 0x00000000 660 661/* Scratch pad debug 0 reg: 662 */ 663#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 664/* 665 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 666 * this field (only one bit may be set). 667 */ 668#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 669#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 670#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 671/* i830, required in DVO non-gang */ 672#define PLL_P2_DIVIDE_BY_4 (1 << 23) 673#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 674#define PLL_REF_INPUT_DREFCLK (0 << 13) 675#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 676#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 677#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 678#define PLL_REF_INPUT_MASK (3 << 13) 679#define PLL_LOAD_PULSE_PHASE_SHIFT 9 680/* Ironlake */ 681# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 682# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 683# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 684# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 685# define DPLL_FPA1_P1_POST_DIV_MASK 0xff 686 687/* 688 * Parallel to Serial Load Pulse phase selection. 689 * Selects the phase for the 10X DPLL clock for the PCIe 690 * digital display port. The range is 4 to 13; 10 or more 691 * is just a flip delay. The default is 6 692 */ 693#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 694#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 695/* 696 * SDVO multiplier for 945G/GM. Not used on 965. 697 */ 698#define SDVO_MULTIPLIER_MASK 0x000000ff 699#define SDVO_MULTIPLIER_SHIFT_HIRES 4 700#define SDVO_MULTIPLIER_SHIFT_VGA 0 701#define DPLL_A_MD 0x0601c /* 965+ only */ 702/* 703 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 704 * 705 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 706 */ 707#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 708#define DPLL_MD_UDI_DIVIDER_SHIFT 24 709/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 710#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 711#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 712/* 713 * SDVO/UDI pixel multiplier. 714 * 715 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 716 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 717 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 718 * dummy bytes in the datastream at an increased clock rate, with both sides of 719 * the link knowing how many bytes are fill. 720 * 721 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 722 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 723 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 724 * through an SDVO command. 725 * 726 * This register field has values of multiplication factor minus 1, with 727 * a maximum multiplier of 5 for SDVO. 728 */ 729#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 730#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 731/* 732 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 733 * This best be set to the default value (3) or the CRT won't work. No, 734 * I don't entirely understand what this does... 735 */ 736#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 737#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 738#define DPLL_B_MD 0x06020 /* 965+ only */ 739#define FPA0 0x06040 740#define FPA1 0x06044 741#define FPB0 0x06048 742#define FPB1 0x0604c 743#define FP_N_DIV_MASK 0x003f0000 744#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 745#define FP_N_DIV_SHIFT 16 746#define FP_M1_DIV_MASK 0x00003f00 747#define FP_M1_DIV_SHIFT 8 748#define FP_M2_DIV_MASK 0x0000003f 749#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 750#define FP_M2_DIV_SHIFT 0 751#define DPLL_TEST 0x606c 752#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 753#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 754#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 755#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 756#define DPLLB_TEST_N_BYPASS (1 << 19) 757#define DPLLB_TEST_M_BYPASS (1 << 18) 758#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 759#define DPLLA_TEST_N_BYPASS (1 << 3) 760#define DPLLA_TEST_M_BYPASS (1 << 2) 761#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 762#define D_STATE 0x6104 763#define DSTATE_PLL_D3_OFF (1<<3) 764#define DSTATE_GFX_CLOCK_GATING (1<<1) 765#define DSTATE_DOT_CLOCK_GATING (1<<0) 766#define DSPCLK_GATE_D 0x6200 767# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 768# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 769# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 770# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 771# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 772# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 773# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 774# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 775# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 776# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 777# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 778# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 779# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 780# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 781# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 782# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 783# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 784# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 785# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 786# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 787# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 788# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 789# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 790# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 791# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 792# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 793# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 794# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 795/** 796 * This bit must be set on the 830 to prevent hangs when turning off the 797 * overlay scaler. 798 */ 799# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 800# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 801# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 802# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 803# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 804 805#define RENCLK_GATE_D1 0x6204 806# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 807# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 808# define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 809# define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 810# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 811# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 812# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 813# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 814# define MAG_CLOCK_GATE_DISABLE (1 << 5) 815/** This bit must be unset on 855,865 */ 816# define MECI_CLOCK_GATE_DISABLE (1 << 4) 817# define DCMP_CLOCK_GATE_DISABLE (1 << 3) 818# define MEC_CLOCK_GATE_DISABLE (1 << 2) 819# define MECO_CLOCK_GATE_DISABLE (1 << 1) 820/** This bit must be set on 855,865. */ 821# define SV_CLOCK_GATE_DISABLE (1 << 0) 822# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 823# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 824# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 825# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 826# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 827# define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 828# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 829# define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 830# define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 831# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 832# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 833# define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 834# define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 835# define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 836# define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 837# define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 838# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 839 840# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 841/** This bit must always be set on 965G/965GM */ 842# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 843# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 844# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 845# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 846# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 847# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 848/** This bit must always be set on 965G */ 849# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 850# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 851# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 852# define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 853# define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 854# define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 855# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 856# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 857# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 858# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 859# define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 860# define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 861# define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 862# define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 863# define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 864# define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 865# define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 866# define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 867# define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 868 869#define RENCLK_GATE_D2 0x6208 870#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 871#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 872#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 873#define RAMCLK_GATE_D 0x6210 /* CRL only */ 874#define DEUC 0x6214 /* CRL only */ 875 876/* 877 * Palette regs 878 */ 879 880#define PALETTE_A 0x0a000 881#define PALETTE_B 0x0a800 882 883/* MCH MMIO space */ 884 885/* 886 * MCHBAR mirror. 887 * 888 * This mirrors the MCHBAR MMIO space whose location is determined by 889 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 890 * every way. It is not accessible from the CP register read instructions. 891 * 892 */ 893#define MCHBAR_MIRROR_BASE 0x10000 894 895/** 915-945 and GM965 MCH register controlling DRAM channel access */ 896#define DCC 0x10200 897#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 898#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 899#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 900#define DCC_ADDRESSING_MODE_MASK (3 << 0) 901#define DCC_CHANNEL_XOR_DISABLE (1 << 10) 902#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 903 904/** Pineview MCH register contains DDR3 setting */ 905#define CSHRDDR3CTL 0x101a8 906#define CSHRDDR3CTL_DDR3 (1 << 2) 907 908/** 965 MCH register controlling DRAM channel configuration */ 909#define C0DRB3 0x10206 910#define C1DRB3 0x10606 911 912/* Clocking configuration register */ 913#define CLKCFG 0x10c00 914#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 915#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 916#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 917#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 918#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 919#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 920/* Note, below two are guess */ 921#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 922#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 923#define CLKCFG_FSB_MASK (7 << 0) 924#define CLKCFG_MEM_533 (1 << 4) 925#define CLKCFG_MEM_667 (2 << 4) 926#define CLKCFG_MEM_800 (3 << 4) 927#define CLKCFG_MEM_MASK (7 << 4) 928 929#define TR1 0x11006 930#define TSFS 0x11020 931#define TSFS_SLOPE_MASK 0x0000ff00 932#define TSFS_SLOPE_SHIFT 8 933#define TSFS_INTR_MASK 0x000000ff 934 935#define CRSTANDVID 0x11100 936#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 937#define PXVFREQ_PX_MASK 0x7f000000 938#define PXVFREQ_PX_SHIFT 24 939#define VIDFREQ_BASE 0x11110 940#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 941#define VIDFREQ2 0x11114 942#define VIDFREQ3 0x11118 943#define VIDFREQ4 0x1111c 944#define VIDFREQ_P0_MASK 0x1f000000 945#define VIDFREQ_P0_SHIFT 24 946#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 947#define VIDFREQ_P0_CSCLK_SHIFT 20 948#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 949#define VIDFREQ_P0_CRCLK_SHIFT 16 950#define VIDFREQ_P1_MASK 0x00001f00 951#define VIDFREQ_P1_SHIFT 8 952#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 953#define VIDFREQ_P1_CSCLK_SHIFT 4 954#define VIDFREQ_P1_CRCLK_MASK 0x0000000f 955#define INTTOEXT_BASE_ILK 0x11300 956#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 957#define INTTOEXT_MAP3_SHIFT 24 958#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 959#define INTTOEXT_MAP2_SHIFT 16 960#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 961#define INTTOEXT_MAP1_SHIFT 8 962#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 963#define INTTOEXT_MAP0_SHIFT 0 964#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 965#define MEMSWCTL 0x11170 /* Ironlake only */ 966#define MEMCTL_CMD_MASK 0xe000 967#define MEMCTL_CMD_SHIFT 13 968#define MEMCTL_CMD_RCLK_OFF 0 969#define MEMCTL_CMD_RCLK_ON 1 970#define MEMCTL_CMD_CHFREQ 2 971#define MEMCTL_CMD_CHVID 3 972#define MEMCTL_CMD_VMMOFF 4 973#define MEMCTL_CMD_VMMON 5 974#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 975 when command complete */ 976#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 977#define MEMCTL_FREQ_SHIFT 8 978#define MEMCTL_SFCAVM (1<<7) 979#define MEMCTL_TGT_VID_MASK 0x007f 980#define MEMIHYST 0x1117c 981#define MEMINTREN 0x11180 /* 16 bits */ 982#define MEMINT_RSEXIT_EN (1<<8) 983#define MEMINT_CX_SUPR_EN (1<<7) 984#define MEMINT_CONT_BUSY_EN (1<<6) 985#define MEMINT_AVG_BUSY_EN (1<<5) 986#define MEMINT_EVAL_CHG_EN (1<<4) 987#define MEMINT_MON_IDLE_EN (1<<3) 988#define MEMINT_UP_EVAL_EN (1<<2) 989#define MEMINT_DOWN_EVAL_EN (1<<1) 990#define MEMINT_SW_CMD_EN (1<<0) 991#define MEMINTRSTR 0x11182 /* 16 bits */ 992#define MEM_RSEXIT_MASK 0xc000 993#define MEM_RSEXIT_SHIFT 14 994#define MEM_CONT_BUSY_MASK 0x3000 995#define MEM_CONT_BUSY_SHIFT 12 996#define MEM_AVG_BUSY_MASK 0x0c00 997#define MEM_AVG_BUSY_SHIFT 10 998#define MEM_EVAL_CHG_MASK 0x0300 999#define MEM_EVAL_BUSY_SHIFT 8 1000#define MEM_MON_IDLE_MASK 0x00c0 1001#define MEM_MON_IDLE_SHIFT 6 1002#define MEM_UP_EVAL_MASK 0x0030 1003#define MEM_UP_EVAL_SHIFT 4 1004#define MEM_DOWN_EVAL_MASK 0x000c 1005#define MEM_DOWN_EVAL_SHIFT 2 1006#define MEM_SW_CMD_MASK 0x0003 1007#define MEM_INT_STEER_GFX 0 1008#define MEM_INT_STEER_CMR 1 1009#define MEM_INT_STEER_SMI 2 1010#define MEM_INT_STEER_SCI 3 1011#define MEMINTRSTS 0x11184 1012#define MEMINT_RSEXIT (1<<7) 1013#define MEMINT_CONT_BUSY (1<<6) 1014#define MEMINT_AVG_BUSY (1<<5) 1015#define MEMINT_EVAL_CHG (1<<4) 1016#define MEMINT_MON_IDLE (1<<3) 1017#define MEMINT_UP_EVAL (1<<2) 1018#define MEMINT_DOWN_EVAL (1<<1) 1019#define MEMINT_SW_CMD (1<<0) 1020#define MEMMODECTL 0x11190 1021#define MEMMODE_BOOST_EN (1<<31) 1022#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1023#define MEMMODE_BOOST_FREQ_SHIFT 24 1024#define MEMMODE_IDLE_MODE_MASK 0x00030000 1025#define MEMMODE_IDLE_MODE_SHIFT 16 1026#define MEMMODE_IDLE_MODE_EVAL 0 1027#define MEMMODE_IDLE_MODE_CONT 1 1028#define MEMMODE_HWIDLE_EN (1<<15) 1029#define MEMMODE_SWMODE_EN (1<<14) 1030#define MEMMODE_RCLK_GATE (1<<13) 1031#define MEMMODE_HW_UPDATE (1<<12) 1032#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1033#define MEMMODE_FSTART_SHIFT 8 1034#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1035#define MEMMODE_FMAX_SHIFT 4 1036#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1037#define RCBMAXAVG 0x1119c 1038#define MEMSWCTL2 0x1119e /* Cantiga only */ 1039#define SWMEMCMD_RENDER_OFF (0 << 13) 1040#define SWMEMCMD_RENDER_ON (1 << 13) 1041#define SWMEMCMD_SWFREQ (2 << 13) 1042#define SWMEMCMD_TARVID (3 << 13) 1043#define SWMEMCMD_VRM_OFF (4 << 13) 1044#define SWMEMCMD_VRM_ON (5 << 13) 1045#define CMDSTS (1<<12) 1046#define SFCAVM (1<<11) 1047#define SWFREQ_MASK 0x0380 /* P0-7 */ 1048#define SWFREQ_SHIFT 7 1049#define TARVID_MASK 0x001f 1050#define MEMSTAT_CTG 0x111a0 1051#define RCBMINAVG 0x111a0 1052#define RCUPEI 0x111b0 1053#define RCDNEI 0x111b4 1054#define MCHBAR_RENDER_STANDBY 0x111b8 1055#define RCX_SW_EXIT (1<<23) 1056#define RSX_STATUS_MASK 0x00700000 1057#define VIDCTL 0x111c0 1058#define VIDSTS 0x111c8 1059#define VIDSTART 0x111cc /* 8 bits */ 1060#define MEMSTAT_ILK 0x111f8 1061#define MEMSTAT_VID_MASK 0x7f00 1062#define MEMSTAT_VID_SHIFT 8 1063#define MEMSTAT_PSTATE_MASK 0x00f8 1064#define MEMSTAT_PSTATE_SHIFT 3 1065#define MEMSTAT_MON_ACTV (1<<2) 1066#define MEMSTAT_SRC_CTL_MASK 0x0003 1067#define MEMSTAT_SRC_CTL_CORE 0 1068#define MEMSTAT_SRC_CTL_TRB 1 1069#define MEMSTAT_SRC_CTL_THM 2 1070#define MEMSTAT_SRC_CTL_STDBY 3 1071#define RCPREVBSYTUPAVG 0x113b8 1072#define RCPREVBSYTDNAVG 0x113bc 1073#define SDEW 0x1124c 1074#define CSIEW0 0x11250 1075#define CSIEW1 0x11254 1076#define CSIEW2 0x11258 1077#define PEW 0x1125c 1078#define DEW 0x11270 1079#define MCHAFE 0x112c0 1080#define CSIEC 0x112e0 1081#define DMIEC 0x112e4 1082#define DDREC 0x112e8 1083#define PEG0EC 0x112ec 1084#define PEG1EC 0x112f0 1085#define GFXEC 0x112f4 1086#define RPPREVBSYTUPAVG 0x113b8 1087#define RPPREVBSYTDNAVG 0x113bc 1088#define ECR 0x11600 1089#define ECR_GPFE (1<<31) 1090#define ECR_IMONE (1<<30) 1091#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1092#define OGW0 0x11608 1093#define OGW1 0x1160c 1094#define EG0 0x11610 1095#define EG1 0x11614 1096#define EG2 0x11618 1097#define EG3 0x1161c 1098#define EG4 0x11620 1099#define EG5 0x11624 1100#define EG6 0x11628 1101#define EG7 0x1162c 1102#define PXW 0x11664 1103#define PXWL 0x11680 1104#define LCFUSE02 0x116c0 1105#define LCFUSE_HIV_MASK 0x000000ff 1106#define CSIPLL0 0x12c10 1107#define DDRMPLL1 0X12c20 1108#define PEG_BAND_GAP_DATA 0x14d68 1109 1110/* 1111 * Logical Context regs 1112 */ 1113#define CCID 0x2180 1114#define CCID_EN (1<<0) 1115/* 1116 * Overlay regs 1117 */ 1118 1119#define OVADD 0x30000 1120#define DOVSTA 0x30008 1121#define OC_BUF (0x3<<20) 1122#define OGAMC5 0x30010 1123#define OGAMC4 0x30014 1124#define OGAMC3 0x30018 1125#define OGAMC2 0x3001c 1126#define OGAMC1 0x30020 1127#define OGAMC0 0x30024 1128 1129/* 1130 * Display engine regs 1131 */ 1132 1133/* Pipe A timing regs */ 1134#define HTOTAL_A 0x60000 1135#define HBLANK_A 0x60004 1136#define HSYNC_A 0x60008 1137#define VTOTAL_A 0x6000c 1138#define VBLANK_A 0x60010 1139#define VSYNC_A 0x60014 1140#define PIPEASRC 0x6001c 1141#define BCLRPAT_A 0x60020 1142 1143/* Pipe B timing regs */ 1144#define HTOTAL_B 0x61000 1145#define HBLANK_B 0x61004 1146#define HSYNC_B 0x61008 1147#define VTOTAL_B 0x6100c 1148#define VBLANK_B 0x61010 1149#define VSYNC_B 0x61014 1150#define PIPEBSRC 0x6101c 1151#define BCLRPAT_B 0x61020 1152 1153/* VGA port control */ 1154#define ADPA 0x61100 1155#define ADPA_DAC_ENABLE (1<<31) 1156#define ADPA_DAC_DISABLE 0 1157#define ADPA_PIPE_SELECT_MASK (1<<30) 1158#define ADPA_PIPE_A_SELECT 0 1159#define ADPA_PIPE_B_SELECT (1<<30) 1160#define ADPA_USE_VGA_HVPOLARITY (1<<15) 1161#define ADPA_SETS_HVPOLARITY 0 1162#define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1163#define ADPA_VSYNC_CNTL_ENABLE 0 1164#define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1165#define ADPA_HSYNC_CNTL_ENABLE 0 1166#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1167#define ADPA_VSYNC_ACTIVE_LOW 0 1168#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1169#define ADPA_HSYNC_ACTIVE_LOW 0 1170#define ADPA_DPMS_MASK (~(3<<10)) 1171#define ADPA_DPMS_ON (0<<10) 1172#define ADPA_DPMS_SUSPEND (1<<10) 1173#define ADPA_DPMS_STANDBY (2<<10) 1174#define ADPA_DPMS_OFF (3<<10) 1175 1176/* Hotplug control (945+ only) */ 1177#define PORT_HOTPLUG_EN 0x61110 1178#define HDMIB_HOTPLUG_INT_EN (1 << 29) 1179#define DPB_HOTPLUG_INT_EN (1 << 29) 1180#define HDMIC_HOTPLUG_INT_EN (1 << 28) 1181#define DPC_HOTPLUG_INT_EN (1 << 28) 1182#define HDMID_HOTPLUG_INT_EN (1 << 27) 1183#define DPD_HOTPLUG_INT_EN (1 << 27) 1184#define SDVOB_HOTPLUG_INT_EN (1 << 26) 1185#define SDVOC_HOTPLUG_INT_EN (1 << 25) 1186#define TV_HOTPLUG_INT_EN (1 << 18) 1187#define CRT_HOTPLUG_INT_EN (1 << 9) 1188#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1189#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1190/* must use period 64 on GM45 according to docs */ 1191#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1192#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1193#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1194#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1195#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1196#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1197#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1198#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1199#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1200#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1201#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1202#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1203 1204#define PORT_HOTPLUG_STAT 0x61114 1205#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 1206#define DPB_HOTPLUG_INT_STATUS (1 << 29) 1207#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 1208#define DPC_HOTPLUG_INT_STATUS (1 << 28) 1209#define HDMID_HOTPLUG_INT_STATUS (1 << 27) 1210#define DPD_HOTPLUG_INT_STATUS (1 << 27) 1211#define CRT_HOTPLUG_INT_STATUS (1 << 11) 1212#define TV_HOTPLUG_INT_STATUS (1 << 10) 1213#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1214#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1215#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1216#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1217#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1218#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1219 1220/* SDVO port control */ 1221#define SDVOB 0x61140 1222#define SDVOC 0x61160 1223#define SDVO_ENABLE (1 << 31) 1224#define SDVO_PIPE_B_SELECT (1 << 30) 1225#define SDVO_STALL_SELECT (1 << 29) 1226#define SDVO_INTERRUPT_ENABLE (1 << 26) 1227/** 1228 * 915G/GM SDVO pixel multiplier. 1229 * 1230 * Programmed value is multiplier - 1, up to 5x. 1231 * 1232 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1233 */ 1234#define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1235#define SDVO_PORT_MULTIPLY_SHIFT 23 1236#define SDVO_PHASE_SELECT_MASK (15 << 19) 1237#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1238#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1239#define SDVOC_GANG_MODE (1 << 16) 1240#define SDVO_ENCODING_SDVO (0x0 << 10) 1241#define SDVO_ENCODING_HDMI (0x2 << 10) 1242/** Requird for HDMI operation */ 1243#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1244#define SDVO_BORDER_ENABLE (1 << 7) 1245#define SDVO_AUDIO_ENABLE (1 << 6) 1246/** New with 965, default is to be set */ 1247#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1248/** New with 965, default is to be set */ 1249#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1250#define SDVOB_PCIE_CONCURRENCY (1 << 3) 1251#define SDVO_DETECTED (1 << 2) 1252/* Bits to be preserved when writing */ 1253#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1254#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1255 1256/* DVO port control */ 1257#define DVOA 0x61120 1258#define DVOB 0x61140 1259#define DVOC 0x61160 1260#define DVO_ENABLE (1 << 31) 1261#define DVO_PIPE_B_SELECT (1 << 30) 1262#define DVO_PIPE_STALL_UNUSED (0 << 28) 1263#define DVO_PIPE_STALL (1 << 28) 1264#define DVO_PIPE_STALL_TV (2 << 28) 1265#define DVO_PIPE_STALL_MASK (3 << 28) 1266#define DVO_USE_VGA_SYNC (1 << 15) 1267#define DVO_DATA_ORDER_I740 (0 << 14) 1268#define DVO_DATA_ORDER_FP (1 << 14) 1269#define DVO_VSYNC_DISABLE (1 << 11) 1270#define DVO_HSYNC_DISABLE (1 << 10) 1271#define DVO_VSYNC_TRISTATE (1 << 9) 1272#define DVO_HSYNC_TRISTATE (1 << 8) 1273#define DVO_BORDER_ENABLE (1 << 7) 1274#define DVO_DATA_ORDER_GBRG (1 << 6) 1275#define DVO_DATA_ORDER_RGGB (0 << 6) 1276#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1277#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1278#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1279#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1280#define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1281#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1282#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1283#define DVO_PRESERVE_MASK (0x7<<24) 1284#define DVOA_SRCDIM 0x61124 1285#define DVOB_SRCDIM 0x61144 1286#define DVOC_SRCDIM 0x61164 1287#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1288#define DVO_SRCDIM_VERTICAL_SHIFT 0 1289 1290/* LVDS port control */ 1291#define LVDS 0x61180 1292/* 1293 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1294 * the DPLL semantics change when the LVDS is assigned to that pipe. 1295 */ 1296#define LVDS_PORT_EN (1 << 31) 1297/* Selects pipe B for LVDS data. Must be set on pre-965. */ 1298#define LVDS_PIPEB_SELECT (1 << 30) 1299/* LVDS dithering flag on 965/g4x platform */ 1300#define LVDS_ENABLE_DITHER (1 << 25) 1301/* Enable border for unscaled (or aspect-scaled) display */ 1302#define LVDS_BORDER_ENABLE (1 << 15) 1303/* 1304 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1305 * pixel. 1306 */ 1307#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1308#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1309#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1310/* 1311 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1312 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1313 * on. 1314 */ 1315#define LVDS_A3_POWER_MASK (3 << 6) 1316#define LVDS_A3_POWER_DOWN (0 << 6) 1317#define LVDS_A3_POWER_UP (3 << 6) 1318/* 1319 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1320 * is set. 1321 */ 1322#define LVDS_CLKB_POWER_MASK (3 << 4) 1323#define LVDS_CLKB_POWER_DOWN (0 << 4) 1324#define LVDS_CLKB_POWER_UP (3 << 4) 1325/* 1326 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1327 * setting for whether we are in dual-channel mode. The B3 pair will 1328 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1329 */ 1330#define LVDS_B0B3_POWER_MASK (3 << 2) 1331#define LVDS_B0B3_POWER_DOWN (0 << 2) 1332#define LVDS_B0B3_POWER_UP (3 << 2) 1333 1334/* Panel power sequencing */ 1335#define PP_STATUS 0x61200 1336#define PP_ON (1 << 31) 1337/* 1338 * Indicates that all dependencies of the panel are on: 1339 * 1340 * - PLL enabled 1341 * - pipe enabled 1342 * - LVDS/DVOB/DVOC on 1343 */ 1344#define PP_READY (1 << 30) 1345#define PP_SEQUENCE_NONE (0 << 28) 1346#define PP_SEQUENCE_ON (1 << 28) 1347#define PP_SEQUENCE_OFF (2 << 28) 1348#define PP_SEQUENCE_MASK 0x30000000 1349#define PP_CONTROL 0x61204 1350#define POWER_TARGET_ON (1 << 0) 1351#define PP_ON_DELAYS 0x61208 1352#define PP_OFF_DELAYS 0x6120c 1353#define PP_DIVISOR 0x61210 1354 1355/* Panel fitting */ 1356#define PFIT_CONTROL 0x61230 1357#define PFIT_ENABLE (1 << 31) 1358#define PFIT_PIPE_MASK (3 << 29) 1359#define PFIT_PIPE_SHIFT 29 1360#define VERT_INTERP_DISABLE (0 << 10) 1361#define VERT_INTERP_BILINEAR (1 << 10) 1362#define VERT_INTERP_MASK (3 << 10) 1363#define VERT_AUTO_SCALE (1 << 9) 1364#define HORIZ_INTERP_DISABLE (0 << 6) 1365#define HORIZ_INTERP_BILINEAR (1 << 6) 1366#define HORIZ_INTERP_MASK (3 << 6) 1367#define HORIZ_AUTO_SCALE (1 << 5) 1368#define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1369#define PFIT_FILTER_FUZZY (0 << 24) 1370#define PFIT_SCALING_AUTO (0 << 26) 1371#define PFIT_SCALING_PROGRAMMED (1 << 26) 1372#define PFIT_SCALING_PILLAR (2 << 26) 1373#define PFIT_SCALING_LETTER (3 << 26) 1374#define PFIT_PGM_RATIOS 0x61234 1375#define PFIT_VERT_SCALE_MASK 0xfff00000 1376#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1377/* Pre-965 */ 1378#define PFIT_VERT_SCALE_SHIFT 20 1379#define PFIT_VERT_SCALE_MASK 0xfff00000 1380#define PFIT_HORIZ_SCALE_SHIFT 4 1381#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1382/* 965+ */ 1383#define PFIT_VERT_SCALE_SHIFT_965 16 1384#define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1385#define PFIT_HORIZ_SCALE_SHIFT_965 0 1386#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1387 1388#define PFIT_AUTO_RATIOS 0x61238 1389 1390/* Backlight control */ 1391#define BLC_PWM_CTL 0x61254 1392#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1393#define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1394#define BLM_COMBINATION_MODE (1 << 30) 1395/* 1396 * This is the most significant 15 bits of the number of backlight cycles in a 1397 * complete cycle of the modulated backlight control. 1398 * 1399 * The actual value is this field multiplied by two. 1400 */ 1401#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1402#define BLM_LEGACY_MODE (1 << 16) 1403/* 1404 * This is the number of cycles out of the backlight modulation cycle for which 1405 * the backlight is on. 1406 * 1407 * This field must be no greater than the number of cycles in the complete 1408 * backlight modulation cycle. 1409 */ 1410#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1411#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1412 1413#define BLC_HIST_CTL 0x61260 1414 1415/* TV port control */ 1416#define TV_CTL 0x68000 1417/** Enables the TV encoder */ 1418# define TV_ENC_ENABLE (1 << 31) 1419/** Sources the TV encoder input from pipe B instead of A. */ 1420# define TV_ENC_PIPEB_SELECT (1 << 30) 1421/** Outputs composite video (DAC A only) */ 1422# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1423/** Outputs SVideo video (DAC B/C) */ 1424# define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1425/** Outputs Component video (DAC A/B/C) */ 1426# define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1427/** Outputs Composite and SVideo (DAC A/B/C) */ 1428# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1429# define TV_TRILEVEL_SYNC (1 << 21) 1430/** Enables slow sync generation (945GM only) */ 1431# define TV_SLOW_SYNC (1 << 20) 1432/** Selects 4x oversampling for 480i and 576p */ 1433# define TV_OVERSAMPLE_4X (0 << 18) 1434/** Selects 2x oversampling for 720p and 1080i */ 1435# define TV_OVERSAMPLE_2X (1 << 18) 1436/** Selects no oversampling for 1080p */ 1437# define TV_OVERSAMPLE_NONE (2 << 18) 1438/** Selects 8x oversampling */ 1439# define TV_OVERSAMPLE_8X (3 << 18) 1440/** Selects progressive mode rather than interlaced */ 1441# define TV_PROGRESSIVE (1 << 17) 1442/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1443# define TV_PAL_BURST (1 << 16) 1444/** Field for setting delay of Y compared to C */ 1445# define TV_YC_SKEW_MASK (7 << 12) 1446/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1447# define TV_ENC_SDP_FIX (1 << 11) 1448/** 1449 * Enables a fix for the 915GM only. 1450 * 1451 * Not sure what it does. 1452 */ 1453# define TV_ENC_C0_FIX (1 << 10) 1454/** Bits that must be preserved by software */ 1455# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1456# define TV_FUSE_STATE_MASK (3 << 4) 1457/** Read-only state that reports all features enabled */ 1458# define TV_FUSE_STATE_ENABLED (0 << 4) 1459/** Read-only state that reports that Macrovision is disabled in hardware*/ 1460# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1461/** Read-only state that reports that TV-out is disabled in hardware. */ 1462# define TV_FUSE_STATE_DISABLED (2 << 4) 1463/** Normal operation */ 1464# define TV_TEST_MODE_NORMAL (0 << 0) 1465/** Encoder test pattern 1 - combo pattern */ 1466# define TV_TEST_MODE_PATTERN_1 (1 << 0) 1467/** Encoder test pattern 2 - full screen vertical 75% color bars */ 1468# define TV_TEST_MODE_PATTERN_2 (2 << 0) 1469/** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1470# define TV_TEST_MODE_PATTERN_3 (3 << 0) 1471/** Encoder test pattern 4 - random noise */ 1472# define TV_TEST_MODE_PATTERN_4 (4 << 0) 1473/** Encoder test pattern 5 - linear color ramps */ 1474# define TV_TEST_MODE_PATTERN_5 (5 << 0) 1475/** 1476 * This test mode forces the DACs to 50% of full output. 1477 * 1478 * This is used for load detection in combination with TVDAC_SENSE_MASK 1479 */ 1480# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1481# define TV_TEST_MODE_MASK (7 << 0) 1482 1483#define TV_DAC 0x68004 1484/** 1485 * Reports that DAC state change logic has reported change (RO). 1486 * 1487 * This gets cleared when TV_DAC_STATE_EN is cleared 1488*/ 1489# define TVDAC_STATE_CHG (1 << 31) 1490# define TVDAC_SENSE_MASK (7 << 28) 1491/** Reports that DAC A voltage is above the detect threshold */ 1492# define TVDAC_A_SENSE (1 << 30) 1493/** Reports that DAC B voltage is above the detect threshold */ 1494# define TVDAC_B_SENSE (1 << 29) 1495/** Reports that DAC C voltage is above the detect threshold */ 1496# define TVDAC_C_SENSE (1 << 28) 1497/** 1498 * Enables DAC state detection logic, for load-based TV detection. 1499 * 1500 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1501 * to off, for load detection to work. 1502 */ 1503# define TVDAC_STATE_CHG_EN (1 << 27) 1504/** Sets the DAC A sense value to high */ 1505# define TVDAC_A_SENSE_CTL (1 << 26) 1506/** Sets the DAC B sense value to high */ 1507# define TVDAC_B_SENSE_CTL (1 << 25) 1508/** Sets the DAC C sense value to high */ 1509# define TVDAC_C_SENSE_CTL (1 << 24) 1510/** Overrides the ENC_ENABLE and DAC voltage levels */ 1511# define DAC_CTL_OVERRIDE (1 << 7) 1512/** Sets the slew rate. Must be preserved in software */ 1513# define ENC_TVDAC_SLEW_FAST (1 << 6) 1514# define DAC_A_1_3_V (0 << 4) 1515# define DAC_A_1_1_V (1 << 4) 1516# define DAC_A_0_7_V (2 << 4) 1517# define DAC_A_MASK (3 << 4) 1518# define DAC_B_1_3_V (0 << 2) 1519# define DAC_B_1_1_V (1 << 2) 1520# define DAC_B_0_7_V (2 << 2) 1521# define DAC_B_MASK (3 << 2) 1522# define DAC_C_1_3_V (0 << 0) 1523# define DAC_C_1_1_V (1 << 0) 1524# define DAC_C_0_7_V (2 << 0) 1525# define DAC_C_MASK (3 << 0) 1526 1527/** 1528 * CSC coefficients are stored in a floating point format with 9 bits of 1529 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1530 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1531 * -1 (0x3) being the only legal negative value. 1532 */ 1533#define TV_CSC_Y 0x68010 1534# define TV_RY_MASK 0x07ff0000 1535# define TV_RY_SHIFT 16 1536# define TV_GY_MASK 0x00000fff 1537# define TV_GY_SHIFT 0 1538 1539#define TV_CSC_Y2 0x68014 1540# define TV_BY_MASK 0x07ff0000 1541# define TV_BY_SHIFT 16 1542/** 1543 * Y attenuation for component video. 1544 * 1545 * Stored in 1.9 fixed point. 1546 */ 1547# define TV_AY_MASK 0x000003ff 1548# define TV_AY_SHIFT 0 1549 1550#define TV_CSC_U 0x68018 1551# define TV_RU_MASK 0x07ff0000 1552# define TV_RU_SHIFT 16 1553# define TV_GU_MASK 0x000007ff 1554# define TV_GU_SHIFT 0 1555 1556#define TV_CSC_U2 0x6801c 1557# define TV_BU_MASK 0x07ff0000 1558# define TV_BU_SHIFT 16 1559/** 1560 * U attenuation for component video. 1561 * 1562 * Stored in 1.9 fixed point. 1563 */ 1564# define TV_AU_MASK 0x000003ff 1565# define TV_AU_SHIFT 0 1566 1567#define TV_CSC_V 0x68020 1568# define TV_RV_MASK 0x0fff0000 1569# define TV_RV_SHIFT 16 1570# define TV_GV_MASK 0x000007ff 1571# define TV_GV_SHIFT 0 1572 1573#define TV_CSC_V2 0x68024 1574# define TV_BV_MASK 0x07ff0000 1575# define TV_BV_SHIFT 16 1576/** 1577 * V attenuation for component video. 1578 * 1579 * Stored in 1.9 fixed point. 1580 */ 1581# define TV_AV_MASK 0x000007ff 1582# define TV_AV_SHIFT 0 1583 1584#define TV_CLR_KNOBS 0x68028 1585/** 2s-complement brightness adjustment */ 1586# define TV_BRIGHTNESS_MASK 0xff000000 1587# define TV_BRIGHTNESS_SHIFT 24 1588/** Contrast adjustment, as a 2.6 unsigned floating point number */ 1589# define TV_CONTRAST_MASK 0x00ff0000 1590# define TV_CONTRAST_SHIFT 16 1591/** Saturation adjustment, as a 2.6 unsigned floating point number */ 1592# define TV_SATURATION_MASK 0x0000ff00 1593# define TV_SATURATION_SHIFT 8 1594/** Hue adjustment, as an integer phase angle in degrees */ 1595# define TV_HUE_MASK 0x000000ff 1596# define TV_HUE_SHIFT 0 1597 1598#define TV_CLR_LEVEL 0x6802c 1599/** Controls the DAC level for black */ 1600# define TV_BLACK_LEVEL_MASK 0x01ff0000 1601# define TV_BLACK_LEVEL_SHIFT 16 1602/** Controls the DAC level for blanking */ 1603# define TV_BLANK_LEVEL_MASK 0x000001ff 1604# define TV_BLANK_LEVEL_SHIFT 0 1605 1606#define TV_H_CTL_1 0x68030 1607/** Number of pixels in the hsync. */ 1608# define TV_HSYNC_END_MASK 0x1fff0000 1609# define TV_HSYNC_END_SHIFT 16 1610/** Total number of pixels minus one in the line (display and blanking). */ 1611# define TV_HTOTAL_MASK 0x00001fff 1612# define TV_HTOTAL_SHIFT 0 1613 1614#define TV_H_CTL_2 0x68034 1615/** Enables the colorburst (needed for non-component color) */ 1616# define TV_BURST_ENA (1 << 31) 1617/** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1618# define TV_HBURST_START_SHIFT 16 1619# define TV_HBURST_START_MASK 0x1fff0000 1620/** Length of the colorburst */ 1621# define TV_HBURST_LEN_SHIFT 0 1622# define TV_HBURST_LEN_MASK 0x0001fff 1623 1624#define TV_H_CTL_3 0x68038 1625/** End of hblank, measured in pixels minus one from start of hsync */ 1626# define TV_HBLANK_END_SHIFT 16 1627# define TV_HBLANK_END_MASK 0x1fff0000 1628/** Start of hblank, measured in pixels minus one from start of hsync */ 1629# define TV_HBLANK_START_SHIFT 0 1630# define TV_HBLANK_START_MASK 0x0001fff 1631 1632#define TV_V_CTL_1 0x6803c 1633# define TV_NBR_END_SHIFT 16 1634# define TV_NBR_END_MASK 0x07ff0000 1635# define TV_VI_END_F1_SHIFT 8 1636# define TV_VI_END_F1_MASK 0x00003f00 1637# define TV_VI_END_F2_SHIFT 0 1638# define TV_VI_END_F2_MASK 0x0000003f 1639 1640#define TV_V_CTL_2 0x68040 1641/** Length of vsync, in half lines */ 1642# define TV_VSYNC_LEN_MASK 0x07ff0000 1643# define TV_VSYNC_LEN_SHIFT 16 1644/** Offset of the start of vsync in field 1, measured in one less than the 1645 * number of half lines. 1646 */ 1647# define TV_VSYNC_START_F1_MASK 0x00007f00 1648# define TV_VSYNC_START_F1_SHIFT 8 1649/** 1650 * Offset of the start of vsync in field 2, measured in one less than the 1651 * number of half lines. 1652 */ 1653# define TV_VSYNC_START_F2_MASK 0x0000007f 1654# define TV_VSYNC_START_F2_SHIFT 0 1655 1656#define TV_V_CTL_3 0x68044 1657/** Enables generation of the equalization signal */ 1658# define TV_EQUAL_ENA (1 << 31) 1659/** Length of vsync, in half lines */ 1660# define TV_VEQ_LEN_MASK 0x007f0000 1661# define TV_VEQ_LEN_SHIFT 16 1662/** Offset of the start of equalization in field 1, measured in one less than 1663 * the number of half lines. 1664 */ 1665# define TV_VEQ_START_F1_MASK 0x0007f00 1666# define TV_VEQ_START_F1_SHIFT 8 1667/** 1668 * Offset of the start of equalization in field 2, measured in one less than 1669 * the number of half lines. 1670 */ 1671# define TV_VEQ_START_F2_MASK 0x000007f 1672# define TV_VEQ_START_F2_SHIFT 0 1673 1674#define TV_V_CTL_4 0x68048 1675/** 1676 * Offset to start of vertical colorburst, measured in one less than the 1677 * number of lines from vertical start. 1678 */ 1679# define TV_VBURST_START_F1_MASK 0x003f0000 1680# define TV_VBURST_START_F1_SHIFT 16 1681/** 1682 * Offset to the end of vertical colorburst, measured in one less than the 1683 * number of lines from the start of NBR. 1684 */ 1685# define TV_VBURST_END_F1_MASK 0x000000ff 1686# define TV_VBURST_END_F1_SHIFT 0 1687 1688#define TV_V_CTL_5 0x6804c 1689/** 1690 * Offset to start of vertical colorburst, measured in one less than the 1691 * number of lines from vertical start. 1692 */ 1693# define TV_VBURST_START_F2_MASK 0x003f0000 1694# define TV_VBURST_START_F2_SHIFT 16 1695/** 1696 * Offset to the end of vertical colorburst, measured in one less than the 1697 * number of lines from the start of NBR. 1698 */ 1699# define TV_VBURST_END_F2_MASK 0x000000ff 1700# define TV_VBURST_END_F2_SHIFT 0 1701 1702#define TV_V_CTL_6 0x68050 1703/** 1704 * Offset to start of vertical colorburst, measured in one less than the 1705 * number of lines from vertical start. 1706 */ 1707# define TV_VBURST_START_F3_MASK 0x003f0000 1708# define TV_VBURST_START_F3_SHIFT 16 1709/** 1710 * Offset to the end of vertical colorburst, measured in one less than the 1711 * number of lines from the start of NBR. 1712 */ 1713# define TV_VBURST_END_F3_MASK 0x000000ff 1714# define TV_VBURST_END_F3_SHIFT 0 1715 1716#define TV_V_CTL_7 0x68054 1717/** 1718 * Offset to start of vertical colorburst, measured in one less than the 1719 * number of lines from vertical start. 1720 */ 1721# define TV_VBURST_START_F4_MASK 0x003f0000 1722# define TV_VBURST_START_F4_SHIFT 16 1723/** 1724 * Offset to the end of vertical colorburst, measured in one less than the 1725 * number of lines from the start of NBR. 1726 */ 1727# define TV_VBURST_END_F4_MASK 0x000000ff 1728# define TV_VBURST_END_F4_SHIFT 0 1729 1730#define TV_SC_CTL_1 0x68060 1731/** Turns on the first subcarrier phase generation DDA */ 1732# define TV_SC_DDA1_EN (1 << 31) 1733/** Turns on the first subcarrier phase generation DDA */ 1734# define TV_SC_DDA2_EN (1 << 30) 1735/** Turns on the first subcarrier phase generation DDA */ 1736# define TV_SC_DDA3_EN (1 << 29) 1737/** Sets the subcarrier DDA to reset frequency every other field */ 1738# define TV_SC_RESET_EVERY_2 (0 << 24) 1739/** Sets the subcarrier DDA to reset frequency every fourth field */ 1740# define TV_SC_RESET_EVERY_4 (1 << 24) 1741/** Sets the subcarrier DDA to reset frequency every eighth field */ 1742# define TV_SC_RESET_EVERY_8 (2 << 24) 1743/** Sets the subcarrier DDA to never reset the frequency */ 1744# define TV_SC_RESET_NEVER (3 << 24) 1745/** Sets the peak amplitude of the colorburst.*/ 1746# define TV_BURST_LEVEL_MASK 0x00ff0000 1747# define TV_BURST_LEVEL_SHIFT 16 1748/** Sets the increment of the first subcarrier phase generation DDA */ 1749# define TV_SCDDA1_INC_MASK 0x00000fff 1750# define TV_SCDDA1_INC_SHIFT 0 1751 1752#define TV_SC_CTL_2 0x68064 1753/** Sets the rollover for the second subcarrier phase generation DDA */ 1754# define TV_SCDDA2_SIZE_MASK 0x7fff0000 1755# define TV_SCDDA2_SIZE_SHIFT 16 1756/** Sets the increent of the second subcarrier phase generation DDA */ 1757# define TV_SCDDA2_INC_MASK 0x00007fff 1758# define TV_SCDDA2_INC_SHIFT 0 1759 1760#define TV_SC_CTL_3 0x68068 1761/** Sets the rollover for the third subcarrier phase generation DDA */ 1762# define TV_SCDDA3_SIZE_MASK 0x7fff0000 1763# define TV_SCDDA3_SIZE_SHIFT 16 1764/** Sets the increent of the third subcarrier phase generation DDA */ 1765# define TV_SCDDA3_INC_MASK 0x00007fff 1766# define TV_SCDDA3_INC_SHIFT 0 1767 1768#define TV_WIN_POS 0x68070 1769/** X coordinate of the display from the start of horizontal active */ 1770# define TV_XPOS_MASK 0x1fff0000 1771# define TV_XPOS_SHIFT 16 1772/** Y coordinate of the display from the start of vertical active (NBR) */ 1773# define TV_YPOS_MASK 0x00000fff 1774# define TV_YPOS_SHIFT 0 1775 1776#define TV_WIN_SIZE 0x68074 1777/** Horizontal size of the display window, measured in pixels*/ 1778# define TV_XSIZE_MASK 0x1fff0000 1779# define TV_XSIZE_SHIFT 16 1780/** 1781 * Vertical size of the display window, measured in pixels. 1782 * 1783 * Must be even for interlaced modes. 1784 */ 1785# define TV_YSIZE_MASK 0x00000fff 1786# define TV_YSIZE_SHIFT 0 1787 1788#define TV_FILTER_CTL_1 0x68080 1789/** 1790 * Enables automatic scaling calculation. 1791 * 1792 * If set, the rest of the registers are ignored, and the calculated values can 1793 * be read back from the register. 1794 */ 1795# define TV_AUTO_SCALE (1 << 31) 1796/** 1797 * Disables the vertical filter. 1798 * 1799 * This is required on modes more than 1024 pixels wide */ 1800# define TV_V_FILTER_BYPASS (1 << 29) 1801/** Enables adaptive vertical filtering */ 1802# define TV_VADAPT (1 << 28) 1803# define TV_VADAPT_MODE_MASK (3 << 26) 1804/** Selects the least adaptive vertical filtering mode */ 1805# define TV_VADAPT_MODE_LEAST (0 << 26) 1806/** Selects the moderately adaptive vertical filtering mode */ 1807# define TV_VADAPT_MODE_MODERATE (1 << 26) 1808/** Selects the most adaptive vertical filtering mode */ 1809# define TV_VADAPT_MODE_MOST (3 << 26) 1810/** 1811 * Sets the horizontal scaling factor. 1812 * 1813 * This should be the fractional part of the horizontal scaling factor divided 1814 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 1815 * 1816 * (src width - 1) / ((oversample * dest width) - 1) 1817 */ 1818# define TV_HSCALE_FRAC_MASK 0x00003fff 1819# define TV_HSCALE_FRAC_SHIFT 0 1820 1821#define TV_FILTER_CTL_2 0x68084 1822/** 1823 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1824 * 1825 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 1826 */ 1827# define TV_VSCALE_INT_MASK 0x00038000 1828# define TV_VSCALE_INT_SHIFT 15 1829/** 1830 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1831 * 1832 * \sa TV_VSCALE_INT_MASK 1833 */ 1834# define TV_VSCALE_FRAC_MASK 0x00007fff 1835# define TV_VSCALE_FRAC_SHIFT 0 1836 1837#define TV_FILTER_CTL_3 0x68088 1838/** 1839 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1840 * 1841 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 1842 * 1843 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1844 */ 1845# define TV_VSCALE_IP_INT_MASK 0x00038000 1846# define TV_VSCALE_IP_INT_SHIFT 15 1847/** 1848 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1849 * 1850 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1851 * 1852 * \sa TV_VSCALE_IP_INT_MASK 1853 */ 1854# define TV_VSCALE_IP_FRAC_MASK 0x00007fff 1855# define TV_VSCALE_IP_FRAC_SHIFT 0 1856 1857#define TV_CC_CONTROL 0x68090 1858# define TV_CC_ENABLE (1 << 31) 1859/** 1860 * Specifies which field to send the CC data in. 1861 * 1862 * CC data is usually sent in field 0. 1863 */ 1864# define TV_CC_FID_MASK (1 << 27) 1865# define TV_CC_FID_SHIFT 27 1866/** Sets the horizontal position of the CC data. Usually 135. */ 1867# define TV_CC_HOFF_MASK 0x03ff0000 1868# define TV_CC_HOFF_SHIFT 16 1869/** Sets the vertical position of the CC data. Usually 21 */ 1870# define TV_CC_LINE_MASK 0x0000003f 1871# define TV_CC_LINE_SHIFT 0 1872 1873#define TV_CC_DATA 0x68094 1874# define TV_CC_RDY (1 << 31) 1875/** Second word of CC data to be transmitted. */ 1876# define TV_CC_DATA_2_MASK 0x007f0000 1877# define TV_CC_DATA_2_SHIFT 16 1878/** First word of CC data to be transmitted. */ 1879# define TV_CC_DATA_1_MASK 0x0000007f 1880# define TV_CC_DATA_1_SHIFT 0 1881 1882#define TV_H_LUMA_0 0x68100 1883#define TV_H_LUMA_59 0x681ec 1884#define TV_H_CHROMA_0 0x68200 1885#define TV_H_CHROMA_59 0x682ec 1886#define TV_V_LUMA_0 0x68300 1887#define TV_V_LUMA_42 0x683a8 1888#define TV_V_CHROMA_0 0x68400 1889#define TV_V_CHROMA_42 0x684a8 1890 1891/* Display Port */ 1892#define DP_A 0x64000 /* eDP */ 1893#define DP_B 0x64100 1894#define DP_C 0x64200 1895#define DP_D 0x64300 1896 1897#define DP_PORT_EN (1 << 31) 1898#define DP_PIPEB_SELECT (1 << 30) 1899 1900/* Link training mode - select a suitable mode for each stage */ 1901#define DP_LINK_TRAIN_PAT_1 (0 << 28) 1902#define DP_LINK_TRAIN_PAT_2 (1 << 28) 1903#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 1904#define DP_LINK_TRAIN_OFF (3 << 28) 1905#define DP_LINK_TRAIN_MASK (3 << 28) 1906#define DP_LINK_TRAIN_SHIFT 28 1907 1908/* CPT Link training mode */ 1909#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 1910#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 1911#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 1912#define DP_LINK_TRAIN_OFF_CPT (3 << 8) 1913#define DP_LINK_TRAIN_MASK_CPT (7 << 8) 1914#define DP_LINK_TRAIN_SHIFT_CPT 8 1915 1916/* Signal voltages. These are mostly controlled by the other end */ 1917#define DP_VOLTAGE_0_4 (0 << 25) 1918#define DP_VOLTAGE_0_6 (1 << 25) 1919#define DP_VOLTAGE_0_8 (2 << 25) 1920#define DP_VOLTAGE_1_2 (3 << 25) 1921#define DP_VOLTAGE_MASK (7 << 25) 1922#define DP_VOLTAGE_SHIFT 25 1923 1924/* Signal pre-emphasis levels, like voltages, the other end tells us what 1925 * they want 1926 */ 1927#define DP_PRE_EMPHASIS_0 (0 << 22) 1928#define DP_PRE_EMPHASIS_3_5 (1 << 22) 1929#define DP_PRE_EMPHASIS_6 (2 << 22) 1930#define DP_PRE_EMPHASIS_9_5 (3 << 22) 1931#define DP_PRE_EMPHASIS_MASK (7 << 22) 1932#define DP_PRE_EMPHASIS_SHIFT 22 1933 1934/* How many wires to use. I guess 3 was too hard */ 1935#define DP_PORT_WIDTH_1 (0 << 19) 1936#define DP_PORT_WIDTH_2 (1 << 19) 1937#define DP_PORT_WIDTH_4 (3 << 19) 1938#define DP_PORT_WIDTH_MASK (7 << 19) 1939 1940/* Mystic DPCD version 1.1 special mode */ 1941#define DP_ENHANCED_FRAMING (1 << 18) 1942 1943/* eDP */ 1944#define DP_PLL_FREQ_270MHZ (0 << 16) 1945#define DP_PLL_FREQ_160MHZ (1 << 16) 1946#define DP_PLL_FREQ_MASK (3 << 16) 1947 1948/** locked once port is enabled */ 1949#define DP_PORT_REVERSAL (1 << 15) 1950 1951/* eDP */ 1952#define DP_PLL_ENABLE (1 << 14) 1953 1954/** sends the clock on lane 15 of the PEG for debug */ 1955#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 1956 1957#define DP_SCRAMBLING_DISABLE (1 << 12) 1958#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 1959 1960/** limit RGB values to avoid confusing TVs */ 1961#define DP_COLOR_RANGE_16_235 (1 << 8) 1962 1963/** Turn on the audio link */ 1964#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 1965 1966/** vs and hs sync polarity */ 1967#define DP_SYNC_VS_HIGH (1 << 4) 1968#define DP_SYNC_HS_HIGH (1 << 3) 1969 1970/** A fantasy */ 1971#define DP_DETECTED (1 << 2) 1972 1973/** The aux channel provides a way to talk to the 1974 * signal sink for DDC etc. Max packet size supported 1975 * is 20 bytes in each direction, hence the 5 fixed 1976 * data registers 1977 */ 1978#define DPA_AUX_CH_CTL 0x64010 1979#define DPA_AUX_CH_DATA1 0x64014 1980#define DPA_AUX_CH_DATA2 0x64018 1981#define DPA_AUX_CH_DATA3 0x6401c 1982#define DPA_AUX_CH_DATA4 0x64020 1983#define DPA_AUX_CH_DATA5 0x64024 1984 1985#define DPB_AUX_CH_CTL 0x64110 1986#define DPB_AUX_CH_DATA1 0x64114 1987#define DPB_AUX_CH_DATA2 0x64118 1988#define DPB_AUX_CH_DATA3 0x6411c 1989#define DPB_AUX_CH_DATA4 0x64120 1990#define DPB_AUX_CH_DATA5 0x64124 1991 1992#define DPC_AUX_CH_CTL 0x64210 1993#define DPC_AUX_CH_DATA1 0x64214 1994#define DPC_AUX_CH_DATA2 0x64218 1995#define DPC_AUX_CH_DATA3 0x6421c 1996#define DPC_AUX_CH_DATA4 0x64220 1997#define DPC_AUX_CH_DATA5 0x64224 1998 1999#define DPD_AUX_CH_CTL 0x64310 2000#define DPD_AUX_CH_DATA1 0x64314 2001#define DPD_AUX_CH_DATA2 0x64318 2002#define DPD_AUX_CH_DATA3 0x6431c 2003#define DPD_AUX_CH_DATA4 0x64320 2004#define DPD_AUX_CH_DATA5 0x64324 2005 2006#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 2007#define DP_AUX_CH_CTL_DONE (1 << 30) 2008#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2009#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2010#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2011#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2012#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2013#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2014#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2015#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2016#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2017#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2018#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2019#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2020#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2021#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2022#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2023#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2024#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2025#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2026#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2027 2028/* 2029 * Computing GMCH M and N values for the Display Port link 2030 * 2031 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2032 * 2033 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2034 * 2035 * The GMCH value is used internally 2036 * 2037 * bytes_per_pixel is the number of bytes coming out of the plane, 2038 * which is after the LUTs, so we want the bytes for our color format. 2039 * For our current usage, this is always 3, one byte for R, G and B. 2040 */ 2041#define PIPEA_GMCH_DATA_M 0x70050 2042#define PIPEB_GMCH_DATA_M 0x71050 2043 2044/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2045#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2046#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2047 2048#define PIPE_GMCH_DATA_M_MASK (0xffffff) 2049 2050#define PIPEA_GMCH_DATA_N 0x70054 2051#define PIPEB_GMCH_DATA_N 0x71054 2052#define PIPE_GMCH_DATA_N_MASK (0xffffff) 2053 2054/* 2055 * Computing Link M and N values for the Display Port link 2056 * 2057 * Link M / N = pixel_clock / ls_clk 2058 * 2059 * (the DP spec calls pixel_clock the 'strm_clk') 2060 * 2061 * The Link value is transmitted in the Main Stream 2062 * Attributes and VB-ID. 2063 */ 2064 2065#define PIPEA_DP_LINK_M 0x70060 2066#define PIPEB_DP_LINK_M 0x71060 2067#define PIPEA_DP_LINK_M_MASK (0xffffff) 2068 2069#define PIPEA_DP_LINK_N 0x70064 2070#define PIPEB_DP_LINK_N 0x71064 2071#define PIPEA_DP_LINK_N_MASK (0xffffff) 2072 2073/* Display & cursor control */ 2074 2075/* dithering flag on Ironlake */ 2076#define PIPE_ENABLE_DITHER (1 << 4) 2077#define PIPE_DITHER_TYPE_MASK (3 << 2) 2078#define PIPE_DITHER_TYPE_SPATIAL (0 << 2) 2079#define PIPE_DITHER_TYPE_ST01 (1 << 2) 2080/* Pipe A */ 2081#define PIPEADSL 0x70000 2082#define DSL_LINEMASK 0x00000fff 2083#define PIPEACONF 0x70008 2084#define PIPEACONF_ENABLE (1<<31) 2085#define PIPEACONF_DISABLE 0 2086#define PIPEACONF_DOUBLE_WIDE (1<<30) 2087#define I965_PIPECONF_ACTIVE (1<<30) 2088#define PIPEACONF_SINGLE_WIDE 0 2089#define PIPEACONF_PIPE_UNLOCKED 0 2090#define PIPEACONF_PIPE_LOCKED (1<<25) 2091#define PIPEACONF_PALETTE 0 2092#define PIPEACONF_GAMMA (1<<24) 2093#define PIPECONF_FORCE_BORDER (1<<25) 2094#define PIPECONF_PROGRESSIVE (0 << 21) 2095#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2096#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 2097#define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2098#define PIPEASTAT 0x70024 2099#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2100#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2101#define PIPE_CRC_DONE_ENABLE (1UL<<28) 2102#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 2103#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 2104#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 2105#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 2106#define PIPE_DPST_EVENT_ENABLE (1UL<<23) 2107#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 2108#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 2109#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 2110#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 2111#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 2112#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 2113#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 2114#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 2115#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 2116#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 2117#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 2118#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 2119#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 2120#define PIPE_DPST_EVENT_STATUS (1UL<<7) 2121#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 2122#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 2123#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 2124#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 2125#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2126#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2127#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2128#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2129#define PIPE_8BPC (0 << 5) 2130#define PIPE_10BPC (1 << 5) 2131#define PIPE_6BPC (2 << 5) 2132#define PIPE_12BPC (3 << 5) 2133 2134#define DSPARB 0x70030 2135#define DSPARB_CSTART_MASK (0x7f << 7) 2136#define DSPARB_CSTART_SHIFT 7 2137#define DSPARB_BSTART_MASK (0x7f) 2138#define DSPARB_BSTART_SHIFT 0 2139#define DSPARB_BEND_SHIFT 9 /* on 855 */ 2140#define DSPARB_AEND_SHIFT 0 2141 2142#define DSPFW1 0x70034 2143#define DSPFW_SR_SHIFT 23 2144#define DSPFW_SR_MASK (0x1ff<<23) 2145#define DSPFW_CURSORB_SHIFT 16 2146#define DSPFW_CURSORB_MASK (0x3f<<16) 2147#define DSPFW_PLANEB_SHIFT 8 2148#define DSPFW_PLANEB_MASK (0x7f<<8) 2149#define DSPFW_PLANEA_MASK (0x7f) 2150#define DSPFW2 0x70038 2151#define DSPFW_CURSORA_MASK 0x00003f00 2152#define DSPFW_CURSORA_SHIFT 8 2153#define DSPFW_PLANEC_MASK (0x7f) 2154#define DSPFW3 0x7003c 2155#define DSPFW_HPLL_SR_EN (1<<31) 2156#define DSPFW_CURSOR_SR_SHIFT 24 2157#define PINEVIEW_SELF_REFRESH_EN (1<<30) 2158#define DSPFW_CURSOR_SR_MASK (0x3f<<24) 2159#define DSPFW_HPLL_CURSOR_SHIFT 16 2160#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 2161#define DSPFW_HPLL_SR_MASK (0x1ff) 2162 2163/* FIFO watermark sizes etc */ 2164#define G4X_FIFO_LINE_SIZE 64 2165#define I915_FIFO_LINE_SIZE 64 2166#define I830_FIFO_LINE_SIZE 32 2167 2168#define G4X_FIFO_SIZE 127 2169#define I965_FIFO_SIZE 512 2170#define I945_FIFO_SIZE 127 2171#define I915_FIFO_SIZE 95 2172#define I855GM_FIFO_SIZE 127 /* In cachelines */ 2173#define I830_FIFO_SIZE 95 2174 2175#define G4X_MAX_WM 0x3f 2176#define I915_MAX_WM 0x3f 2177 2178#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2179#define PINEVIEW_FIFO_LINE_SIZE 64 2180#define PINEVIEW_MAX_WM 0x1ff 2181#define PINEVIEW_DFT_WM 0x3f 2182#define PINEVIEW_DFT_HPLLOFF_WM 0 2183#define PINEVIEW_GUARD_WM 10 2184#define PINEVIEW_CURSOR_FIFO 64 2185#define PINEVIEW_CURSOR_MAX_WM 0x3f 2186#define PINEVIEW_CURSOR_DFT_WM 0 2187#define PINEVIEW_CURSOR_GUARD_WM 5 2188 2189#define I965_CURSOR_FIFO 64 2190#define I965_CURSOR_MAX_WM 32 2191#define I965_CURSOR_DFT_WM 8 2192 2193/* define the Watermark register on Ironlake */ 2194#define WM0_PIPEA_ILK 0x45100 2195#define WM0_PIPE_PLANE_MASK (0x7f<<16) 2196#define WM0_PIPE_PLANE_SHIFT 16 2197#define WM0_PIPE_SPRITE_MASK (0x3f<<8) 2198#define WM0_PIPE_SPRITE_SHIFT 8 2199#define WM0_PIPE_CURSOR_MASK (0x1f) 2200 2201#define WM0_PIPEB_ILK 0x45104 2202#define WM1_LP_ILK 0x45108 2203#define WM1_LP_SR_EN (1<<31) 2204#define WM1_LP_LATENCY_SHIFT 24 2205#define WM1_LP_LATENCY_MASK (0x7f<<24) 2206#define WM1_LP_FBC_LP1_MASK (0xf<<20) 2207#define WM1_LP_FBC_LP1_SHIFT 20 2208#define WM1_LP_SR_MASK (0x1ff<<8) 2209#define WM1_LP_SR_SHIFT 8 2210#define WM1_LP_CURSOR_MASK (0x3f) 2211#define WM2_LP_ILK 0x4510c 2212#define WM2_LP_EN (1<<31) 2213#define WM3_LP_ILK 0x45110 2214#define WM3_LP_EN (1<<31) 2215#define WM1S_LP_ILK 0x45120 2216#define WM1S_LP_EN (1<<31) 2217 2218/* Memory latency timer register */ 2219#define MLTR_ILK 0x11222 2220/* the unit of memory self-refresh latency time is 0.5us */ 2221#define ILK_SRLT_MASK 0x3f 2222 2223/* define the fifo size on Ironlake */ 2224#define ILK_DISPLAY_FIFO 128 2225#define ILK_DISPLAY_MAXWM 64 2226#define ILK_DISPLAY_DFTWM 8 2227#define ILK_CURSOR_FIFO 32 2228#define ILK_CURSOR_MAXWM 16 2229#define ILK_CURSOR_DFTWM 8 2230 2231#define ILK_DISPLAY_SR_FIFO 512 2232#define ILK_DISPLAY_MAX_SRWM 0x1ff 2233#define ILK_DISPLAY_DFT_SRWM 0x3f 2234#define ILK_CURSOR_SR_FIFO 64 2235#define ILK_CURSOR_MAX_SRWM 0x3f 2236#define ILK_CURSOR_DFT_SRWM 8 2237 2238#define ILK_FIFO_LINE_SIZE 64 2239 2240/* 2241 * The two pipe frame counter registers are not synchronized, so 2242 * reading a stable value is somewhat tricky. The following code 2243 * should work: 2244 * 2245 * do { 2246 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2247 * PIPE_FRAME_HIGH_SHIFT; 2248 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2249 * PIPE_FRAME_LOW_SHIFT); 2250 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2251 * PIPE_FRAME_HIGH_SHIFT); 2252 * } while (high1 != high2); 2253 * frame = (high1 << 8) | low1; 2254 */ 2255#define PIPEAFRAMEHIGH 0x70040 2256#define PIPE_FRAME_HIGH_MASK 0x0000ffff 2257#define PIPE_FRAME_HIGH_SHIFT 0 2258#define PIPEAFRAMEPIXEL 0x70044 2259#define PIPE_FRAME_LOW_MASK 0xff000000 2260#define PIPE_FRAME_LOW_SHIFT 24 2261#define PIPE_PIXEL_MASK 0x00ffffff 2262#define PIPE_PIXEL_SHIFT 0 2263/* GM45+ just has to be different */ 2264#define PIPEA_FRMCOUNT_GM45 0x70040 2265#define PIPEA_FLIPCOUNT_GM45 0x70044 2266 2267/* Cursor A & B regs */ 2268#define CURACNTR 0x70080 2269/* Old style CUR*CNTR flags (desktop 8xx) */ 2270#define CURSOR_ENABLE 0x80000000 2271#define CURSOR_GAMMA_ENABLE 0x40000000 2272#define CURSOR_STRIDE_MASK 0x30000000 2273#define CURSOR_FORMAT_SHIFT 24 2274#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 2275#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 2276#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 2277#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 2278#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 2279#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 2280/* New style CUR*CNTR flags */ 2281#define CURSOR_MODE 0x27 2282#define CURSOR_MODE_DISABLE 0x00 2283#define CURSOR_MODE_64_32B_AX 0x07 2284#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 2285#define MCURSOR_PIPE_SELECT (1 << 28) 2286#define MCURSOR_PIPE_A 0x00 2287#define MCURSOR_PIPE_B (1 << 28) 2288#define MCURSOR_GAMMA_ENABLE (1 << 26) 2289#define CURABASE 0x70084 2290#define CURAPOS 0x70088 2291#define CURSOR_POS_MASK 0x007FF 2292#define CURSOR_POS_SIGN 0x8000 2293#define CURSOR_X_SHIFT 0 2294#define CURSOR_Y_SHIFT 16 2295#define CURSIZE 0x700a0 2296#define CURBCNTR 0x700c0 2297#define CURBBASE 0x700c4 2298#define CURBPOS 0x700c8 2299 2300/* Display A control */ 2301#define DSPACNTR 0x70180 2302#define DISPLAY_PLANE_ENABLE (1<<31) 2303#define DISPLAY_PLANE_DISABLE 0 2304#define DISPPLANE_GAMMA_ENABLE (1<<30) 2305#define DISPPLANE_GAMMA_DISABLE 0 2306#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2307#define DISPPLANE_8BPP (0x2<<26) 2308#define DISPPLANE_15_16BPP (0x4<<26) 2309#define DISPPLANE_16BPP (0x5<<26) 2310#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2311#define DISPPLANE_32BPP (0x7<<26) 2312#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2313#define DISPPLANE_STEREO_ENABLE (1<<25) 2314#define DISPPLANE_STEREO_DISABLE 0 2315#define DISPPLANE_SEL_PIPE_MASK (1<<24) 2316#define DISPPLANE_SEL_PIPE_A 0 2317#define DISPPLANE_SEL_PIPE_B (1<<24) 2318#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2319#define DISPPLANE_SRC_KEY_DISABLE 0 2320#define DISPPLANE_LINE_DOUBLE (1<<20) 2321#define DISPPLANE_NO_LINE_DOUBLE 0 2322#define DISPPLANE_STEREO_POLARITY_FIRST 0 2323#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2324#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2325#define DISPPLANE_TILED (1<<10) 2326#define DSPAADDR 0x70184 2327#define DSPASTRIDE 0x70188 2328#define DSPAPOS 0x7018C /* reserved */ 2329#define DSPASIZE 0x70190 2330#define DSPASURF 0x7019C /* 965+ only */ 2331#define DSPATILEOFF 0x701A4 /* 965+ only */ 2332 2333/* VBIOS flags */ 2334#define SWF00 0x71410 2335#define SWF01 0x71414 2336#define SWF02 0x71418 2337#define SWF03 0x7141c 2338#define SWF04 0x71420 2339#define SWF05 0x71424 2340#define SWF06 0x71428 2341#define SWF10 0x70410 2342#define SWF11 0x70414 2343#define SWF14 0x71420 2344#define SWF30 0x72414 2345#define SWF31 0x72418 2346#define SWF32 0x7241c 2347 2348/* Pipe B */ 2349#define PIPEBDSL 0x71000 2350#define PIPEBCONF 0x71008 2351#define PIPEBSTAT 0x71024 2352#define PIPEBFRAMEHIGH 0x71040 2353#define PIPEBFRAMEPIXEL 0x71044 2354#define PIPEB_FRMCOUNT_GM45 0x71040 2355#define PIPEB_FLIPCOUNT_GM45 0x71044 2356 2357 2358/* Display B control */ 2359#define DSPBCNTR 0x71180 2360#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2361#define DISPPLANE_ALPHA_TRANS_DISABLE 0 2362#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2363#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2364#define DSPBADDR 0x71184 2365#define DSPBSTRIDE 0x71188 2366#define DSPBPOS 0x7118C 2367#define DSPBSIZE 0x71190 2368#define DSPBSURF 0x7119C 2369#define DSPBTILEOFF 0x711A4 2370 2371/* VBIOS regs */ 2372#define VGACNTRL 0x71400 2373# define VGA_DISP_DISABLE (1 << 31) 2374# define VGA_2X_MODE (1 << 30) 2375# define VGA_PIPE_B_SELECT (1 << 29) 2376 2377/* Ironlake */ 2378 2379#define CPU_VGACNTRL 0x41000 2380 2381#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 2382#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2383#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 2384#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 2385#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 2386#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 2387#define DIGITAL_PORTA_NO_DETECT (0 << 0) 2388#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 2389#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 2390 2391/* refresh rate hardware control */ 2392#define RR_HW_CTL 0x45300 2393#define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2394#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2395 2396#define FDI_PLL_BIOS_0 0x46000 2397#define FDI_PLL_BIOS_1 0x46004 2398#define FDI_PLL_BIOS_2 0x46008 2399#define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2400#define DISPLAY_PORT_PLL_BIOS_1 0x46010 2401#define DISPLAY_PORT_PLL_BIOS_2 0x46014 2402 2403#define PCH_DSPCLK_GATE_D 0x42020 2404# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) 2405# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) 2406 2407#define PCH_3DCGDIS0 0x46020 2408# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2409# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2410 2411#define FDI_PLL_FREQ_CTL 0x46030 2412#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2413#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2414#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2415 2416 2417#define PIPEA_DATA_M1 0x60030 2418#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2419#define TU_SIZE_MASK 0x7e000000 2420#define PIPEA_DATA_M1_OFFSET 0 2421#define PIPEA_DATA_N1 0x60034 2422#define PIPEA_DATA_N1_OFFSET 0 2423 2424#define PIPEA_DATA_M2 0x60038 2425#define PIPEA_DATA_M2_OFFSET 0 2426#define PIPEA_DATA_N2 0x6003c 2427#define PIPEA_DATA_N2_OFFSET 0 2428 2429#define PIPEA_LINK_M1 0x60040 2430#define PIPEA_LINK_M1_OFFSET 0 2431#define PIPEA_LINK_N1 0x60044 2432#define PIPEA_LINK_N1_OFFSET 0 2433 2434#define PIPEA_LINK_M2 0x60048 2435#define PIPEA_LINK_M2_OFFSET 0 2436#define PIPEA_LINK_N2 0x6004c 2437#define PIPEA_LINK_N2_OFFSET 0 2438 2439/* PIPEB timing regs are same start from 0x61000 */ 2440 2441#define PIPEB_DATA_M1 0x61030 2442#define PIPEB_DATA_M1_OFFSET 0 2443#define PIPEB_DATA_N1 0x61034 2444#define PIPEB_DATA_N1_OFFSET 0 2445 2446#define PIPEB_DATA_M2 0x61038 2447#define PIPEB_DATA_M2_OFFSET 0 2448#define PIPEB_DATA_N2 0x6103c 2449#define PIPEB_DATA_N2_OFFSET 0 2450 2451#define PIPEB_LINK_M1 0x61040 2452#define PIPEB_LINK_M1_OFFSET 0 2453#define PIPEB_LINK_N1 0x61044 2454#define PIPEB_LINK_N1_OFFSET 0 2455 2456#define PIPEB_LINK_M2 0x61048 2457#define PIPEB_LINK_M2_OFFSET 0 2458#define PIPEB_LINK_N2 0x6104c 2459#define PIPEB_LINK_N2_OFFSET 0 2460 2461/* CPU panel fitter */ 2462#define PFA_CTL_1 0x68080 2463#define PFB_CTL_1 0x68880 2464#define PF_ENABLE (1<<31) 2465#define PF_FILTER_MASK (3<<23) 2466#define PF_FILTER_PROGRAMMED (0<<23) 2467#define PF_FILTER_MED_3x3 (1<<23) 2468#define PF_FILTER_EDGE_ENHANCE (2<<23) 2469#define PF_FILTER_EDGE_SOFTEN (3<<23) 2470#define PFA_WIN_SZ 0x68074 2471#define PFB_WIN_SZ 0x68874 2472#define PFA_WIN_POS 0x68070 2473#define PFB_WIN_POS 0x68870 2474 2475/* legacy palette */ 2476#define LGC_PALETTE_A 0x4a000 2477#define LGC_PALETTE_B 0x4a800 2478 2479/* interrupts */ 2480#define DE_MASTER_IRQ_CONTROL (1 << 31) 2481#define DE_SPRITEB_FLIP_DONE (1 << 29) 2482#define DE_SPRITEA_FLIP_DONE (1 << 28) 2483#define DE_PLANEB_FLIP_DONE (1 << 27) 2484#define DE_PLANEA_FLIP_DONE (1 << 26) 2485#define DE_PCU_EVENT (1 << 25) 2486#define DE_GTT_FAULT (1 << 24) 2487#define DE_POISON (1 << 23) 2488#define DE_PERFORM_COUNTER (1 << 22) 2489#define DE_PCH_EVENT (1 << 21) 2490#define DE_AUX_CHANNEL_A (1 << 20) 2491#define DE_DP_A_HOTPLUG (1 << 19) 2492#define DE_GSE (1 << 18) 2493#define DE_PIPEB_VBLANK (1 << 15) 2494#define DE_PIPEB_EVEN_FIELD (1 << 14) 2495#define DE_PIPEB_ODD_FIELD (1 << 13) 2496#define DE_PIPEB_LINE_COMPARE (1 << 12) 2497#define DE_PIPEB_VSYNC (1 << 11) 2498#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 2499#define DE_PIPEA_VBLANK (1 << 7) 2500#define DE_PIPEA_EVEN_FIELD (1 << 6) 2501#define DE_PIPEA_ODD_FIELD (1 << 5) 2502#define DE_PIPEA_LINE_COMPARE (1 << 4) 2503#define DE_PIPEA_VSYNC (1 << 3) 2504#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2505 2506#define DEISR 0x44000 2507#define DEIMR 0x44004 2508#define DEIIR 0x44008 2509#define DEIER 0x4400c 2510 2511/* GT interrupt */ 2512#define GT_PIPE_NOTIFY (1 << 4) 2513#define GT_SYNC_STATUS (1 << 2) 2514#define GT_USER_INTERRUPT (1 << 0) 2515#define GT_BSD_USER_INTERRUPT (1 << 5) 2516 2517 2518#define GTISR 0x44010 2519#define GTIMR 0x44014 2520#define GTIIR 0x44018 2521#define GTIER 0x4401c 2522 2523#define ILK_DISPLAY_CHICKEN2 0x42004 2524#define ILK_DPARB_GATE (1<<22) 2525#define ILK_VSDPFD_FULL (1<<21) 2526#define ILK_DSPCLK_GATE 0x42020 2527#define ILK_DPARB_CLK_GATE (1<<5) 2528/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ 2529#define ILK_CLK_FBC (1<<7) 2530#define ILK_DPFC_DIS1 (1<<8) 2531#define ILK_DPFC_DIS2 (1<<9) 2532 2533#define DISP_ARB_CTL 0x45000 2534#define DISP_TILE_SURFACE_SWIZZLING (1<<13) 2535#define DISP_FBC_WM_DIS (1<<15) 2536 2537/* PCH */ 2538 2539/* south display engine interrupt */ 2540#define SDE_CRT_HOTPLUG (1 << 11) 2541#define SDE_PORTD_HOTPLUG (1 << 10) 2542#define SDE_PORTC_HOTPLUG (1 << 9) 2543#define SDE_PORTB_HOTPLUG (1 << 8) 2544#define SDE_SDVOB_HOTPLUG (1 << 6) 2545#define SDE_HOTPLUG_MASK (0xf << 8) 2546/* CPT */ 2547#define SDE_CRT_HOTPLUG_CPT (1 << 19) 2548#define SDE_PORTD_HOTPLUG_CPT (1 << 23) 2549#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 2550#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 2551#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 2552 SDE_PORTD_HOTPLUG_CPT | \ 2553 SDE_PORTC_HOTPLUG_CPT | \ 2554 SDE_PORTB_HOTPLUG_CPT) 2555 2556#define SDEISR 0xc4000 2557#define SDEIMR 0xc4004 2558#define SDEIIR 0xc4008 2559#define SDEIER 0xc400c 2560 2561/* digital port hotplug */ 2562#define PCH_PORT_HOTPLUG 0xc4030 2563#define PORTD_HOTPLUG_ENABLE (1 << 20) 2564#define PORTD_PULSE_DURATION_2ms (0) 2565#define PORTD_PULSE_DURATION_4_5ms (1 << 18) 2566#define PORTD_PULSE_DURATION_6ms (2 << 18) 2567#define PORTD_PULSE_DURATION_100ms (3 << 18) 2568#define PORTD_HOTPLUG_NO_DETECT (0) 2569#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 2570#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 2571#define PORTC_HOTPLUG_ENABLE (1 << 12) 2572#define PORTC_PULSE_DURATION_2ms (0) 2573#define PORTC_PULSE_DURATION_4_5ms (1 << 10) 2574#define PORTC_PULSE_DURATION_6ms (2 << 10) 2575#define PORTC_PULSE_DURATION_100ms (3 << 10) 2576#define PORTC_HOTPLUG_NO_DETECT (0) 2577#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 2578#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 2579#define PORTB_HOTPLUG_ENABLE (1 << 4) 2580#define PORTB_PULSE_DURATION_2ms (0) 2581#define PORTB_PULSE_DURATION_4_5ms (1 << 2) 2582#define PORTB_PULSE_DURATION_6ms (2 << 2) 2583#define PORTB_PULSE_DURATION_100ms (3 << 2) 2584#define PORTB_HOTPLUG_NO_DETECT (0) 2585#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 2586#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 2587 2588#define PCH_GPIOA 0xc5010 2589#define PCH_GPIOB 0xc5014 2590#define PCH_GPIOC 0xc5018 2591#define PCH_GPIOD 0xc501c 2592#define PCH_GPIOE 0xc5020 2593#define PCH_GPIOF 0xc5024 2594 2595#define PCH_GMBUS0 0xc5100 2596#define PCH_GMBUS1 0xc5104 2597#define PCH_GMBUS2 0xc5108 2598#define PCH_GMBUS3 0xc510c 2599#define PCH_GMBUS4 0xc5110 2600#define PCH_GMBUS5 0xc5120 2601 2602#define PCH_DPLL_A 0xc6014 2603#define PCH_DPLL_B 0xc6018 2604 2605#define PCH_FPA0 0xc6040 2606#define PCH_FPA1 0xc6044 2607#define PCH_FPB0 0xc6048 2608#define PCH_FPB1 0xc604c 2609 2610#define PCH_DPLL_TEST 0xc606c 2611 2612#define PCH_DREF_CONTROL 0xC6200 2613#define DREF_CONTROL_MASK 0x7fc3 2614#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 2615#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 2616#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 2617#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 2618#define DREF_SSC_SOURCE_DISABLE (0<<11) 2619#define DREF_SSC_SOURCE_ENABLE (2<<11) 2620#define DREF_SSC_SOURCE_MASK (3<<11) 2621#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 2622#define DREF_NONSPREAD_CK505_ENABLE (1<<9) 2623#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 2624#define DREF_NONSPREAD_SOURCE_MASK (3<<9) 2625#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 2626#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 2627#define DREF_SSC4_DOWNSPREAD (0<<6) 2628#define DREF_SSC4_CENTERSPREAD (1<<6) 2629#define DREF_SSC1_DISABLE (0<<1) 2630#define DREF_SSC1_ENABLE (1<<1) 2631#define DREF_SSC4_DISABLE (0) 2632#define DREF_SSC4_ENABLE (1) 2633 2634#define PCH_RAWCLK_FREQ 0xc6204 2635#define FDL_TP1_TIMER_SHIFT 12 2636#define FDL_TP1_TIMER_MASK (3<<12) 2637#define FDL_TP2_TIMER_SHIFT 10 2638#define FDL_TP2_TIMER_MASK (3<<10) 2639#define RAWCLK_FREQ_MASK 0x3ff 2640 2641#define PCH_DPLL_TMR_CFG 0xc6208 2642 2643#define PCH_SSC4_PARMS 0xc6210 2644#define PCH_SSC4_AUX_PARMS 0xc6214 2645 2646#define PCH_DPLL_SEL 0xc7000 2647#define TRANSA_DPLL_ENABLE (1<<3) 2648#define TRANSA_DPLLB_SEL (1<<0) 2649#define TRANSA_DPLLA_SEL 0 2650#define TRANSB_DPLL_ENABLE (1<<7) 2651#define TRANSB_DPLLB_SEL (1<<4) 2652#define TRANSB_DPLLA_SEL (0) 2653#define TRANSC_DPLL_ENABLE (1<<11) 2654#define TRANSC_DPLLB_SEL (1<<8) 2655#define TRANSC_DPLLA_SEL (0) 2656 2657/* transcoder */ 2658 2659#define TRANS_HTOTAL_A 0xe0000 2660#define TRANS_HTOTAL_SHIFT 16 2661#define TRANS_HACTIVE_SHIFT 0 2662#define TRANS_HBLANK_A 0xe0004 2663#define TRANS_HBLANK_END_SHIFT 16 2664#define TRANS_HBLANK_START_SHIFT 0 2665#define TRANS_HSYNC_A 0xe0008 2666#define TRANS_HSYNC_END_SHIFT 16 2667#define TRANS_HSYNC_START_SHIFT 0 2668#define TRANS_VTOTAL_A 0xe000c 2669#define TRANS_VTOTAL_SHIFT 16 2670#define TRANS_VACTIVE_SHIFT 0 2671#define TRANS_VBLANK_A 0xe0010 2672#define TRANS_VBLANK_END_SHIFT 16 2673#define TRANS_VBLANK_START_SHIFT 0 2674#define TRANS_VSYNC_A 0xe0014 2675#define TRANS_VSYNC_END_SHIFT 16 2676#define TRANS_VSYNC_START_SHIFT 0 2677 2678#define TRANSA_DATA_M1 0xe0030 2679#define TRANSA_DATA_N1 0xe0034 2680#define TRANSA_DATA_M2 0xe0038 2681#define TRANSA_DATA_N2 0xe003c 2682#define TRANSA_DP_LINK_M1 0xe0040 2683#define TRANSA_DP_LINK_N1 0xe0044 2684#define TRANSA_DP_LINK_M2 0xe0048 2685#define TRANSA_DP_LINK_N2 0xe004c 2686 2687#define TRANS_HTOTAL_B 0xe1000 2688#define TRANS_HBLANK_B 0xe1004 2689#define TRANS_HSYNC_B 0xe1008 2690#define TRANS_VTOTAL_B 0xe100c 2691#define TRANS_VBLANK_B 0xe1010 2692#define TRANS_VSYNC_B 0xe1014 2693 2694#define TRANSB_DATA_M1 0xe1030 2695#define TRANSB_DATA_N1 0xe1034 2696#define TRANSB_DATA_M2 0xe1038 2697#define TRANSB_DATA_N2 0xe103c 2698#define TRANSB_DP_LINK_M1 0xe1040 2699#define TRANSB_DP_LINK_N1 0xe1044 2700#define TRANSB_DP_LINK_M2 0xe1048 2701#define TRANSB_DP_LINK_N2 0xe104c 2702 2703#define TRANSACONF 0xf0008 2704#define TRANSBCONF 0xf1008 2705#define TRANS_DISABLE (0<<31) 2706#define TRANS_ENABLE (1<<31) 2707#define TRANS_STATE_MASK (1<<30) 2708#define TRANS_STATE_DISABLE (0<<30) 2709#define TRANS_STATE_ENABLE (1<<30) 2710#define TRANS_FSYNC_DELAY_HB1 (0<<27) 2711#define TRANS_FSYNC_DELAY_HB2 (1<<27) 2712#define TRANS_FSYNC_DELAY_HB3 (2<<27) 2713#define TRANS_FSYNC_DELAY_HB4 (3<<27) 2714#define TRANS_DP_AUDIO_ONLY (1<<26) 2715#define TRANS_DP_VIDEO_AUDIO (0<<26) 2716#define TRANS_PROGRESSIVE (0<<21) 2717#define TRANS_8BPC (0<<5) 2718#define TRANS_10BPC (1<<5) 2719#define TRANS_6BPC (2<<5) 2720#define TRANS_12BPC (3<<5) 2721 2722#define FDI_RXA_CHICKEN 0xc200c 2723#define FDI_RXB_CHICKEN 0xc2010 2724#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) 2725 2726#define SOUTH_DSPCLK_GATE_D 0xc2020 2727#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 2728 2729/* CPU: FDI_TX */ 2730#define FDI_TXA_CTL 0x60100 2731#define FDI_TXB_CTL 0x61100 2732#define FDI_TX_DISABLE (0<<31) 2733#define FDI_TX_ENABLE (1<<31) 2734#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 2735#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 2736#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 2737#define FDI_LINK_TRAIN_NONE (3<<28) 2738#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 2739#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 2740#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 2741#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 2742#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 2743#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 2744#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 2745#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 2746/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 2747 SNB has different settings. */ 2748/* SNB A-stepping */ 2749#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 2750#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 2751#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 2752#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 2753/* SNB B-stepping */ 2754#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 2755#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 2756#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 2757#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 2758#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 2759#define FDI_DP_PORT_WIDTH_X1 (0<<19) 2760#define FDI_DP_PORT_WIDTH_X2 (1<<19) 2761#define FDI_DP_PORT_WIDTH_X3 (2<<19) 2762#define FDI_DP_PORT_WIDTH_X4 (3<<19) 2763#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 2764/* Ironlake: hardwired to 1 */ 2765#define FDI_TX_PLL_ENABLE (1<<14) 2766/* both Tx and Rx */ 2767#define FDI_SCRAMBLING_ENABLE (0<<7) 2768#define FDI_SCRAMBLING_DISABLE (1<<7) 2769 2770/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 2771#define FDI_RXA_CTL 0xf000c 2772#define FDI_RXB_CTL 0xf100c 2773#define FDI_RX_ENABLE (1<<31) 2774#define FDI_RX_DISABLE (0<<31) 2775/* train, dp width same as FDI_TX */ 2776#define FDI_DP_PORT_WIDTH_X8 (7<<19) 2777#define FDI_8BPC (0<<16) 2778#define FDI_10BPC (1<<16) 2779#define FDI_6BPC (2<<16) 2780#define FDI_12BPC (3<<16) 2781#define FDI_LINK_REVERSE_OVERWRITE (1<<15) 2782#define FDI_DMI_LINK_REVERSE_MASK (1<<14) 2783#define FDI_RX_PLL_ENABLE (1<<13) 2784#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 2785#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 2786#define FDI_FS_ERR_REPORT_ENABLE (1<<9) 2787#define FDI_FE_ERR_REPORT_ENABLE (1<<8) 2788#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 2789#define FDI_SEL_RAWCLK (0<<4) 2790#define FDI_SEL_PCDCLK (1<<4) 2791/* CPT */ 2792#define FDI_AUTO_TRAINING (1<<10) 2793#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 2794#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 2795#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 2796#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 2797#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 2798 2799#define FDI_RXA_MISC 0xf0010 2800#define FDI_RXB_MISC 0xf1010 2801#define FDI_RXA_TUSIZE1 0xf0030 2802#define FDI_RXA_TUSIZE2 0xf0038 2803#define FDI_RXB_TUSIZE1 0xf1030 2804#define FDI_RXB_TUSIZE2 0xf1038 2805 2806/* FDI_RX interrupt register format */ 2807#define FDI_RX_INTER_LANE_ALIGN (1<<10) 2808#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 2809#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 2810#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 2811#define FDI_RX_FS_CODE_ERR (1<<6) 2812#define FDI_RX_FE_CODE_ERR (1<<5) 2813#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 2814#define FDI_RX_HDCP_LINK_FAIL (1<<3) 2815#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 2816#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 2817#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 2818 2819#define FDI_RXA_IIR 0xf0014 2820#define FDI_RXA_IMR 0xf0018 2821#define FDI_RXB_IIR 0xf1014 2822#define FDI_RXB_IMR 0xf1018 2823 2824#define FDI_PLL_CTL_1 0xfe000 2825#define FDI_PLL_CTL_2 0xfe004 2826 2827/* CRT */ 2828#define PCH_ADPA 0xe1100 2829#define ADPA_TRANS_SELECT_MASK (1<<30) 2830#define ADPA_TRANS_A_SELECT 0 2831#define ADPA_TRANS_B_SELECT (1<<30) 2832#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2833#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 2834#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 2835#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 2836#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 2837#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 2838#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 2839#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 2840#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 2841#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 2842#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 2843#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 2844#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 2845#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 2846#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 2847#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 2848#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 2849#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 2850#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 2851 2852/* or SDVOB */ 2853#define HDMIB 0xe1140 2854#define PORT_ENABLE (1 << 31) 2855#define TRANSCODER_A (0) 2856#define TRANSCODER_B (1 << 30) 2857#define COLOR_FORMAT_8bpc (0) 2858#define COLOR_FORMAT_12bpc (3 << 26) 2859#define SDVOB_HOTPLUG_ENABLE (1 << 23) 2860#define SDVO_ENCODING (0) 2861#define TMDS_ENCODING (2 << 10) 2862#define NULL_PACKET_VSYNC_ENABLE (1 << 9) 2863/* CPT */ 2864#define HDMI_MODE_SELECT (1 << 9) 2865#define DVI_MODE_SELECT (0) 2866#define SDVOB_BORDER_ENABLE (1 << 7) 2867#define AUDIO_ENABLE (1 << 6) 2868#define VSYNC_ACTIVE_HIGH (1 << 4) 2869#define HSYNC_ACTIVE_HIGH (1 << 3) 2870#define PORT_DETECTED (1 << 2) 2871 2872/* PCH SDVOB multiplex with HDMIB */ 2873#define PCH_SDVOB HDMIB 2874 2875#define HDMIC 0xe1150 2876#define HDMID 0xe1160 2877 2878#define PCH_LVDS 0xe1180 2879#define LVDS_DETECTED (1 << 1) 2880 2881#define BLC_PWM_CPU_CTL2 0x48250 2882#define PWM_ENABLE (1 << 31) 2883#define PWM_PIPE_A (0 << 29) 2884#define PWM_PIPE_B (1 << 29) 2885#define BLC_PWM_CPU_CTL 0x48254 2886 2887#define BLC_PWM_PCH_CTL1 0xc8250 2888#define PWM_PCH_ENABLE (1 << 31) 2889#define PWM_POLARITY_ACTIVE_LOW (1 << 29) 2890#define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 2891#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 2892#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 2893 2894#define BLC_PWM_PCH_CTL2 0xc8254 2895 2896#define PCH_PP_STATUS 0xc7200 2897#define PCH_PP_CONTROL 0xc7204 2898#define PANEL_UNLOCK_REGS (0xabcd << 16) 2899#define EDP_FORCE_VDD (1 << 3) 2900#define EDP_BLC_ENABLE (1 << 2) 2901#define PANEL_POWER_RESET (1 << 1) 2902#define PANEL_POWER_OFF (0 << 0) 2903#define PANEL_POWER_ON (1 << 0) 2904#define PCH_PP_ON_DELAYS 0xc7208 2905#define EDP_PANEL (1 << 30) 2906#define PCH_PP_OFF_DELAYS 0xc720c 2907#define PCH_PP_DIVISOR 0xc7210 2908 2909#define PCH_DP_B 0xe4100 2910#define PCH_DPB_AUX_CH_CTL 0xe4110 2911#define PCH_DPB_AUX_CH_DATA1 0xe4114 2912#define PCH_DPB_AUX_CH_DATA2 0xe4118 2913#define PCH_DPB_AUX_CH_DATA3 0xe411c 2914#define PCH_DPB_AUX_CH_DATA4 0xe4120 2915#define PCH_DPB_AUX_CH_DATA5 0xe4124 2916 2917#define PCH_DP_C 0xe4200 2918#define PCH_DPC_AUX_CH_CTL 0xe4210 2919#define PCH_DPC_AUX_CH_DATA1 0xe4214 2920#define PCH_DPC_AUX_CH_DATA2 0xe4218 2921#define PCH_DPC_AUX_CH_DATA3 0xe421c 2922#define PCH_DPC_AUX_CH_DATA4 0xe4220 2923#define PCH_DPC_AUX_CH_DATA5 0xe4224 2924 2925#define PCH_DP_D 0xe4300 2926#define PCH_DPD_AUX_CH_CTL 0xe4310 2927#define PCH_DPD_AUX_CH_DATA1 0xe4314 2928#define PCH_DPD_AUX_CH_DATA2 0xe4318 2929#define PCH_DPD_AUX_CH_DATA3 0xe431c 2930#define PCH_DPD_AUX_CH_DATA4 0xe4320 2931#define PCH_DPD_AUX_CH_DATA5 0xe4324 2932 2933/* CPT */ 2934#define PORT_TRANS_A_SEL_CPT 0 2935#define PORT_TRANS_B_SEL_CPT (1<<29) 2936#define PORT_TRANS_C_SEL_CPT (2<<29) 2937#define PORT_TRANS_SEL_MASK (3<<29) 2938 2939#define TRANS_DP_CTL_A 0xe0300 2940#define TRANS_DP_CTL_B 0xe1300 2941#define TRANS_DP_CTL_C 0xe2300 2942#define TRANS_DP_OUTPUT_ENABLE (1<<31) 2943#define TRANS_DP_PORT_SEL_B (0<<29) 2944#define TRANS_DP_PORT_SEL_C (1<<29) 2945#define TRANS_DP_PORT_SEL_D (2<<29) 2946#define TRANS_DP_PORT_SEL_MASK (3<<29) 2947#define TRANS_DP_AUDIO_ONLY (1<<26) 2948#define TRANS_DP_ENH_FRAMING (1<<18) 2949#define TRANS_DP_8BPC (0<<9) 2950#define TRANS_DP_10BPC (1<<9) 2951#define TRANS_DP_6BPC (2<<9) 2952#define TRANS_DP_12BPC (3<<9) 2953#define TRANS_DP_BPC_MASK (3<<9) 2954#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 2955#define TRANS_DP_VSYNC_ACTIVE_LOW 0 2956#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 2957#define TRANS_DP_HSYNC_ACTIVE_LOW 0 2958#define TRANS_DP_SYNC_MASK (3<<3) 2959 2960/* SNB eDP training params */ 2961/* SNB A-stepping */ 2962#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 2963#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 2964#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 2965#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 2966/* SNB B-stepping */ 2967#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 2968#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 2969#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 2970#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 2971#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 2972#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 2973 2974#endif /* _I915_REG_H_ */ 2975